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/linux-6.14.4/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/
Dmemory.json8 …ECC or parity) in protected CPUs RAMs. On the core, this event counts errors in the caches (includ…
/linux-6.14.4/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/
Dmemory.json8 …ECC or parity) in protected CPUs RAMs. On the core, this event counts errors in the caches (includ…
/linux-6.14.4/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/
Dmemory.json8 …ECC or parity) in protected CPUs RAMs. On the core, this event counts errors in the caches (includ…
/linux-6.14.4/tools/perf/pmu-events/arch/arm64/ampere/emag/
Dmemory.json21 …t counts any correctable or uncorrectable memory error (ECC or parity) in the protected core RAMs",
/linux-6.14.4/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/
Dexception.json6 …t counts any correctable or uncorrectable memory error (ECC or parity) in the protected core RAMs",
/linux-6.14.4/Documentation/devicetree/bindings/soc/ti/
Dti,pruss.yaml19 instruction RAMs, some internal peripheral modules to facilitate industrial
35 acts on a primary Data RAM (there are usually 2 Data RAMs) at its address
109 The various Data RAMs within a single PRU-ICSS unit are represented as a
/linux-6.14.4/arch/xtensa/variants/fsf/include/variant/
Dcore.h165 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
167 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
168 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
/linux-6.14.4/arch/arc/
DKconfig242 Single Cycle RAMS to store Fast Path Code
252 Single Cycle RAMS to store Fast Path Data
/linux-6.14.4/kernel/
Dresource.c454 struct resource res, *rams; in walk_system_ram_res_rev() local
460 rams = kvcalloc(rams_size, sizeof(struct resource), GFP_KERNEL); in walk_system_ram_res_rev()
461 if (!rams) in walk_system_ram_res_rev()
472 rams_new = kvrealloc(rams, (rams_size + 16) * sizeof(struct resource), in walk_system_ram_res_rev()
477 rams = rams_new; in walk_system_ram_res_rev()
481 rams[i++] = res; in walk_system_ram_res_rev()
487 ret = (*func)(&rams[i], arg); in walk_system_ram_res_rev()
493 kvfree(rams); in walk_system_ram_res_rev()
/linux-6.14.4/drivers/misc/eeprom/
DKconfig5 tristate "I2C EEPROMs / RAMs / ROMs from most vendors"
/linux-6.14.4/arch/xtensa/variants/test_mmuhifi_c3/include/variant/
Dcore.h185 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
187 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
188 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
/linux-6.14.4/arch/xtensa/variants/dc232b/include/variant/
Dcore.h172 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
174 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
175 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
/linux-6.14.4/arch/powerpc/platforms/8xx/
DKconfig155 This microcode relocates SMC1 and SMC2 parameter RAMs at
/linux-6.14.4/arch/xtensa/variants/dc233c/include/variant/
Dcore.h218 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
220 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
221 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
/linux-6.14.4/drivers/remoteproc/
Dti_k3_m4_remoteproc.c175 * internal RAMs. The .prepare() ops is invoked by remoteproc core before any
278 * RAMs only) to a kernel virtual address. The remote processors can access
279 * their RAMs at either an internal address visible only from a remote
Dkeystone_remoteproc.c242 * Custom function to translate a DSP device address (internal RAMs only) to a
243 * kernel virtual address. The DSPs can access their RAMs at either an internal
Dti_k3_dsp_remoteproc.c266 * internal RAMs. The .prepare() ops is invoked by remoteproc core before any
410 * Custom function to translate a DSP device address (internal RAMs only) to a
411 * kernel virtual address. The DSPs can access their RAMs at either an internal
Dpru_rproc.c62 /* PRU device addresses for various type of PRU RAMs */
647 * RAMs as well as any shared Data RAM to convert a PRU device address to
727 * Provide address translations for only PRU Data RAMs through the remoteproc
/linux-6.14.4/arch/xtensa/variants/test_kc705_be/include/variant/
Dcore.h285 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
287 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
288 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
/linux-6.14.4/arch/xtensa/variants/csp/include/variant/
Dcore.h284 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
286 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
287 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
/linux-6.14.4/arch/xtensa/variants/test_kc705_hifi/include/variant/
Dcore.h242 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
244 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
245 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
/linux-6.14.4/arch/xtensa/variants/de212/include/variant/
Dcore.h284 #define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */
286 #define XCHAL_NUM_DATARAM 1 /* number of core data RAMs */
287 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
/linux-6.14.4/Documentation/devicetree/bindings/cache/
Dl2c2x0.yaml93 description: Cycles of latency for Dirty RAMs. This is a single cell.
/linux-6.14.4/Documentation/arch/arm/stm32/
Dstm32-dma-mdma-chaining.rst29 the system SRAM) for different peripheral. It can access external RAMs but
111 three fast access static internal RAMs of various size, used for data storage.
/linux-6.14.4/Documentation/devicetree/bindings/remoteproc/
Dti,pru-rproc.yaml17 use the Data RAMs present within the PRU-ICSS for code execution.

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