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/linux-6.14.4/tools/power/x86/intel-speed-select/
Disst-core-mbox.c1 // SPDX-License-Identifier: GPL-2.0
3 * Intel Speed Select -- Enumerate and control features for Mailbox Interface
34 snprintf(level_str, sizeof(level_str), "level-%d", level); in mbox_get_trl_level_name()
66 if (id->cpu < 0) in mbox_is_punit_valid()
69 if (id->pkg < 0 || id->die < 0 || id->punit) in mbox_is_punit_valid()
75 static int _send_mmio_command(unsigned int cpu, unsigned int reg, int write, in _send_mmio_command() argument
84 debug_printf("mmio_cmd cpu:%d reg:%d write:%d\n", cpu, reg, write); in _send_mmio_command()
88 err(-1, "%s open failed", pathname); in _send_mmio_command()
91 io_regs.io_reg[0].logical_cpu = cpu; in _send_mmio_command()
101 if (ioctl(fd, cmd, &io_regs) == -1) { in _send_mmio_command()
[all …]
/linux-6.14.4/arch/mips/kernel/
Dsmp-bmips.c20 #include <linux/cpu.h>
40 #include <asm/cpu-features.h>
53 static void bmips_set_reset_vec(int cpu, u32 val);
59 /* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
63 static void bmips43xx_send_ipi_single(int cpu, unsigned int action);
64 static void bmips5000_send_ipi_single(int cpu, unsigned int action);
72 #define CPUNUM(cpu, shift) (((cpu) + bmips_cpu_offset) << (shift)) argument
73 #define ACTION_CLR_IPI(cpu, ipi) (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8)) argument
74 #define ACTION_SET_IPI(cpu, ipi) (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8)) argument
75 #define ACTION_BOOT_THREAD(cpu) (0x08 | CPUNUM(cpu, 0)) argument
[all …]
/linux-6.14.4/Documentation/ABI/stable/
Dsysfs-devices-system-cpu1 What: /sys/devices/system/cpu/dscr_default
2 Date: 13-May-2014
6 /sys/devices/system/cpu/cpuN/dscr on all CPUs.
9 all per-CPU defaults at the same time.
12 What: /sys/devices/system/cpu/cpu[0-9]+/dscr
13 Date: 13-May-2014
17 a CPU.
22 on any CPU where it executes (overriding the value described
27 What: /sys/devices/system/cpu/cpuX/topology/physical_package_id
33 What: /sys/devices/system/cpu/cpuX/topology/die_id
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/linux-6.14.4/tools/perf/util/
Dsvghelper.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * svghelper.c - helper functions for outputting svg
44 static double cpu2slot(int cpu) in cpu2slot() argument
46 return 2 * cpu + 1; in cpu2slot()
51 static double cpu2y(int cpu) in cpu2y() argument
54 return cpu2slot(topology_map[cpu]) * SLOT_MULT; in cpu2y()
56 return cpu2slot(cpu) * SLOT_MULT; in cpu2y()
63 X = 1.0 * svg_page_width * (__time - first_time) / (last_time - first_time); in time2pixels()
78 while (loop--) { in round_text_size()
103 new_width = (last_time - first_time) / 5000000; in open_svg()
[all …]
Daffinity.c1 // SPDX-License-Identifier: GPL-2.0
14 int sz = cpu__max_cpu().cpu + 8 - 1; in get_cpu_set_size()
21 return sz / 8; in get_cpu_set_size()
28 a->orig_cpus = bitmap_zalloc(cpu_set_size * 8); in affinity__setup()
29 if (!a->orig_cpus) in affinity__setup()
30 return -1; in affinity__setup()
31 sched_getaffinity(0, cpu_set_size, (cpu_set_t *)a->orig_cpus); in affinity__setup()
32 a->sched_cpus = bitmap_zalloc(cpu_set_size * 8); in affinity__setup()
33 if (!a->sched_cpus) { in affinity__setup()
34 zfree(&a->orig_cpus); in affinity__setup()
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/linux-6.14.4/arch/arm/boot/dts/samsung/
Dexynos5422-odroidhc1.dts1 // SPDX-License-Identifier: GPL-2.0
10 /dts-v1/;
11 #include <dt-bindings/leds/common.h>
12 #include "exynos5422-odroid-core.dtsi"
16 compatible = "hardkernel,odroid-hc1", "samsung,exynos5800", \
19 led-controller {
20 compatible = "pwm-leds";
22 led-1 {
26 pwm-names = "pwm2";
27 max-brightness = <255>;
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Dexynos5422-odroidxu3-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Hardkernel Odroid XU3/XU3-Lite/XU4 boards common device tree source
12 #include <dt-bindings/input/input.h>
13 #include "exynos5422-odroid-core.dtsi"
20 gpio-keys {
21 compatible = "gpio-keys";
22 pinctrl-names = "default";
23 pinctrl-0 = <&power_key>;
25 power-key {
36 debounce-interval = <0>;
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/linux-6.14.4/arch/x86/kernel/
Dmsr.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* ----------------------------------------------------------------------- *
4 * Copyright 2000-2008 H. Peter Anvin - All Rights Reserved
7 * ----------------------------------------------------------------------- */
13 * and then read/write in chunks of 8 bytes. A larger size means multiple
16 * This driver uses /dev/cpu/%d/msr where %d is the minor number, and on
17 * an SMP box will direct the access to CPU %d.
33 #include <linux/cpu.h>
58 int cpu = iminor(file_inode(file)); in msr_read() local
62 if (count % 8) in msr_read()
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Dhead_64.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit
21 #include <asm/processor-flags.h>
25 #include <asm/nospec-branch.h>
33 * because we need identity-mapped pages.
41 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
86 * be done now, since this also includes setup of the SEV-SNP CPUID table,
94 /* Sanitize CPU configuration */
98 * Derive the kernel's physical-to-virtual offset from the physical and
121 * For SEV guests: Verify that the C-bit is correct. A malicious
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/linux-6.14.4/arch/arm64/boot/dts/amlogic/
Damlogic-t7.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/power/amlogic,t7-pwrc.h>
8 #include "amlogic-t7-reset.h"
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <0x2>;
17 #size-cells = <0x0>;
19 cpu-map {
[all …]
/linux-6.14.4/drivers/clk/mvebu/
Ddove.c1 // SPDX-License-Identifier: GPL-2.0
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
14 #include <linux/clk-provider.h>
18 #include "dove-divider.h"
23 * Dove PLL sample-at-reset configuration
25 * SAR0[8:5] : CPU frequency
29 * 8 = 800 MHz
39 * SAR0[11:9] : CPU to L2 Clock divider ratio
40 * 0 = (1/1) * CPU
41 * 2 = (1/2) * CPU
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/linux-6.14.4/arch/arm64/boot/dts/hisilicon/
Dhi6220.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/reset/hisi,hi6220-resets.h>
10 #include <dt-bindings/clock/hi6220-clock.h>
11 #include <dt-bindings/pinctrl/hisi.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 compatible = "arm,psci-0.2";
[all …]
/linux-6.14.4/tools/perf/tests/
Dcpumap.c1 // SPDX-License-Identifier: GPL-2.0
6 #include "util/synthetic-events.h"
19 struct perf_record_cpu_map *map_event = &event->cpu_map; in process_event_mask()
24 data = &map_event->data; in process_event_mask()
26 TEST_ASSERT_VAL("wrong type", data->type == PERF_CPU_MAP__MASK); in process_event_mask()
28 long_size = data->mask32_data.long_size; in process_event_mask()
30 TEST_ASSERT_VAL("wrong long_size", long_size == 4 || long_size == 8); in process_event_mask()
32 TEST_ASSERT_VAL("wrong nr", data->mask32_data.nr == 1); in process_event_mask()
34 TEST_ASSERT_VAL("wrong cpu", perf_record_cpu_map_data__test_bit(0, data)); in process_event_mask()
35 TEST_ASSERT_VAL("wrong cpu", !perf_record_cpu_map_data__test_bit(1, data)); in process_event_mask()
[all …]
/linux-6.14.4/arch/arc/include/asm/
Dmmu_context.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 * -Refactored get_new_mmu_context( ) to only handle live-mm.
7 * retiring-mm handled in other hooks
10 * -Major rewrite of Core ASID allocation routine get_new_mmu_context
21 #include <asm-generic/mm_hooks.h>
25 * MMU tags TLBs with an 8-bit ASID, avoiding need to flush the TLB on
26 * context-switch.
28 * ASID is managed per cpu, so task threads across CPUs can have different
32 * Each task is assigned unique ASID, with a simple round-robin allocator
[all …]
/linux-6.14.4/tools/power/x86/x86_energy_perf_policy/
Dx86_energy_perf_policy.81 .\" This page Copyright (C) 2010 - 2015 Len Brown <[email protected]>
3 .TH X86_ENERGY_PERF_POLICY 8
5 x86_energy_perf_policy \- Manage Energy vs. Performance Policy via x86 Model Specific Registers
10 .RB "scope: \-\-cpu\ cpu-list | \-\-pkg\ pkg-list"
12 .RB "cpu-list, pkg-list: # | #,# | #-# | all"
14 .RB "field: \-\-all | \-\-epb | \-\-hwp-epp | \-\-hwp-min | \-\-hwp-max | \-\-hwp-desired"
16 .RB "other: (\-\-force | \-\-hwp-enable | \-\-turbo-enable) value)"
18 .RB "value: # | default | performance | balance-performance | balance-power | power"
21 displays and updates energy-performance policy settings specific to
23 updates, no matter if the Linux cpufreq sub-system is enabled or not.
[all …]
/linux-6.14.4/arch/alpha/kernel/
Dcore_mcpcia.c1 // SPDX-License-Identifier: GPL-2.0
7 * Code common to all MCbus-PCI Adaptor core logic chipsets
27 * NOTE: Herein lie back-to-back mb instructions. They are magic.
33 * BIOS32-style PCI interface:
54 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
55 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
57 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
60 * 10:8 Function number
66 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
67 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
[all …]
Dcore_t2.c1 // SPDX-License-Identifier: GPL-2.0
37 * By default, we direct-map starting at 2GB, in order to allow the
38 * maximum size direct-map window (2GB) to match the maximum amount of
40 * floppy to DMA only via the scatter/gather window set up for 8MB
41 * ISA DMA, since the maximum ISA DMA address is 2GB-1.
43 * For now, this seems a reasonable trade-off: even though most SABLEs
62 * NOTE: Herein lie back-to-back mb instructions. They are magic.
68 * BIOS32-style PCI interface:
108 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
109 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
[all …]
/linux-6.14.4/tools/power/cpupower/utils/helpers/
Damd.c1 // SPDX-License-Identifier: GPL-2.0
14 /* ACPI P-States Helper Functions for AMD Processors ***************/
29 unsigned iddval:8;
36 unsigned fid:8;
38 unsigned vid:8;
39 unsigned iddval:8;
48 unsigned vid:8;
49 unsigned iddval:8;
101 * cpu -> the cpu that gets evaluated
102 * boost_states -> how much boost states the machines support
[all …]
/linux-6.14.4/arch/x86/include/asm/
Dsegment.h1 /* SPDX-License-Identifier: GPL-2.0 */
14 ((((base) & _AC(0xff000000,ULL)) << (56-24)) | \
16 (((limit) & _AC(0x000f0000,ULL)) << (48-16)) | \
25 #define __BOOT_CS (GDT_ENTRY_BOOT_CS*8)
26 #define __BOOT_DS (GDT_ENTRY_BOOT_DS*8)
27 #define __BOOT_TSS (GDT_ENTRY_BOOT_TSS*8)
61 * The layout of the per-CPU GDT under Linux:
63 * 0 - null <=== cacheline #1
64 * 1 - reserved
65 * 2 - reserved
[all …]
/linux-6.14.4/arch/arm64/boot/dts/exynos/
Dexynos9810.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <2>;
14 #size-cells = <1>;
16 interrupt-parent = <&gic>;
31 #address-cells = <1>;
32 #size-cells = <0>;
34 cpu-map {
37 cpu = <&cpu0>;
40 cpu = <&cpu1>;
[all …]
/linux-6.14.4/arch/arm64/boot/dts/mediatek/
Dmt6755.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&sysirq>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu0: cpu@0 {
[all …]
/linux-6.14.4/net/netfilter/
Dnf_flow_table_procfs.c1 // SPDX-License-Identifier: GPL-2.0-only
9 int cpu; in nf_flow_table_cpu_seq_start() local
14 for (cpu = *pos - 1; cpu < nr_cpu_ids; ++cpu) { in nf_flow_table_cpu_seq_start()
15 if (!cpu_possible(cpu)) in nf_flow_table_cpu_seq_start()
17 *pos = cpu + 1; in nf_flow_table_cpu_seq_start()
18 return per_cpu_ptr(net->ft.stat, cpu); in nf_flow_table_cpu_seq_start()
27 int cpu; in nf_flow_table_cpu_seq_next() local
29 for (cpu = *pos; cpu < nr_cpu_ids; ++cpu) { in nf_flow_table_cpu_seq_next()
30 if (!cpu_possible(cpu)) in nf_flow_table_cpu_seq_next()
32 *pos = cpu + 1; in nf_flow_table_cpu_seq_next()
[all …]
/linux-6.14.4/arch/powerpc/include/asm/
Dcputhreads.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 * as the CPU numbers are still allocated, just not brought online).
41 int cpu_core_index_of_thread(int cpu);
44 static inline int cpu_core_index_of_thread(int cpu) { return cpu; } in cpu_core_index_of_thread() argument
48 static inline int cpu_thread_in_core(int cpu) in cpu_thread_in_core() argument
50 return cpu & (threads_per_core - 1); in cpu_thread_in_core()
53 static inline int cpu_thread_in_subcore(int cpu) in cpu_thread_in_subcore() argument
55 return cpu & (threads_per_subcore - 1); in cpu_thread_in_subcore()
58 static inline int cpu_first_thread_sibling(int cpu) in cpu_first_thread_sibling() argument
60 return cpu & ~(threads_per_core - 1); in cpu_first_thread_sibling()
[all …]
/linux-6.14.4/tools/power/cpupower/debug/i386/
Dcentrino-decode.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * (C) 2003 - 2004 Dominik Brodowski <[email protected]>
6 * linux/arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c
9 * USAGE: simply run it to decode the current settings on CPU 0,
10 * or pass the CPU number as argument, or pass the MSR content
28 static int rdmsr(unsigned int cpu, unsigned int msr, in rdmsr() argument
34 int retval = -1; in rdmsr()
38 if (cpu > MCPU) in rdmsr()
41 sprintf(file, "/dev/cpu/%d/msr", cpu); in rdmsr()
47 if (lseek(fd, msr, SEEK_CUR) == -1) in rdmsr()
[all …]
/linux-6.14.4/Documentation/translations/zh_CN/core-api/
Dworkqueue.rst1 .. SPDX-License-Identifier: GPL-2.0
2 .. include:: ../disclaimer-zh_CN.rst
4 :Original: Documentation/core-api/workqueue.rst
109 每个与实际CPU绑定的worker-pool通过钩住调度器来实现并发管理。每当
139 参数 - ``@name`` , ``@flags`` 和 ``@max_active`` 。
148 ---------
202 --------------
234 0 w0 starts and burns CPU
236 15 w0 wakes up and burns CPU
238 20 w1 starts and burns CPU
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