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/linux-6.14.4/drivers/clk/renesas/
Dr9a09g057-cpg.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
15 #include "rzv2h-cpg.h"
118 DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5,
121 BUS_MSTOP(3, BIT(5))),
123 BUS_MSTOP(5, BIT(10))),
125 BUS_MSTOP(5, BIT(11))),
126 DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5,
127 BUS_MSTOP(2, BIT(13))),
[all …]
/linux-6.14.4/sound/soc/codecs/
Dsma1307.h1 /* SPDX-License-Identifier: GPL-2.0-or-later
2 * sma1307.h -- sma1307 ALSA SoC Audio driver
55 int *mode_set[5];
232 /* SMA1307 Registers Bit Fields */
234 #define SMA1307_POWER_MASK BIT(0)
236 #define SMA1307_POWER_ON BIT(0)
239 #define SMA1307_RESET_MASK BIT(1)
240 #define SMA1307_RESET_ON BIT(1)
243 #define SMA1307_LEFTPOL_MASK BIT(3)
245 #define SMA1307_HIGH_FIRST_CH BIT(3)
[all …]
Drk3328_codec.h1 /* SPDX-License-Identifier: GPL-2.0 */
37 #define PIN_DIRECTION_MASK BIT(5)
38 #define PIN_DIRECTION_IN (0x0 << 5)
39 #define PIN_DIRECTION_OUT (0x1 << 5)
40 #define DAC_I2S_MODE_MASK BIT(4)
45 #define DAC_I2S_LRP_MASK BIT(7)
48 #define DAC_VDL_MASK GENMASK(6, 5)
49 #define DAC_VDL_16BITS (0x0 << 5)
50 #define DAC_VDL_20BITS (0x1 << 5)
51 #define DAC_VDL_24BITS (0x2 << 5)
[all …]
/linux-6.14.4/include/linux/mfd/da9062/
Dregisters.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2015-2017 Dialog Semiconductor
151 * Bit fields
158 #define DA9062AA_WRITE_MODE_MASK BIT(6)
160 #define DA9062AA_REVERT_MASK BIT(7)
166 #define DA9062AA_DVC_BUSY_MASK BIT(2)
172 #define DA9062AA_GPI1_MASK BIT(1)
174 #define DA9062AA_GPI2_MASK BIT(2)
176 #define DA9062AA_GPI3_MASK BIT(3)
178 #define DA9062AA_GPI4_MASK BIT(4)
[all …]
/linux-6.14.4/drivers/usb/typec/tcpm/
Dfusb302_reg.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2016-2017 Google, Inc
5 * Fairchild FUSB302 Type-C Chip Driver
13 #define FUSB_REG_SWITCHES0_CC2_PU_EN BIT(7)
14 #define FUSB_REG_SWITCHES0_CC1_PU_EN BIT(6)
15 #define FUSB_REG_SWITCHES0_VCONN_CC2 BIT(5)
16 #define FUSB_REG_SWITCHES0_VCONN_CC1 BIT(4)
17 #define FUSB_REG_SWITCHES0_MEAS_CC2 BIT(3)
18 #define FUSB_REG_SWITCHES0_MEAS_CC1 BIT(2)
19 #define FUSB_REG_SWITCHES0_CC2_PD_EN BIT(1)
[all …]
/linux-6.14.4/include/linux/mfd/
Dtps6594.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2023 BayLibre Incorporated - https://www.baylibre.com/
248 #define TPS6594_BIT_BUCK_EN BIT(0)
249 #define TPS6594_BIT_BUCK_FPWM BIT(1)
250 #define TPS6594_BIT_BUCK_FPWM_MP BIT(2)
251 #define TPS6594_BIT_BUCK_VSEL BIT(3)
252 #define TPS6594_BIT_BUCK_VMON_EN BIT(4)
253 #define TPS6594_BIT_BUCK_PLDN BIT(5)
254 #define TPS6594_BIT_BUCK_RV_SEL BIT(7)
258 #define TPS6594_MASK_BUCK_ILIM GENMASK(5, 3)
[all …]
Dtps65219.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2022 BayLibre Incorporated - https://www.baylibre.com/
85 #define TPS65219_REG_INT_RV_POS 5
97 #define TPS65219_BUCKS_LDOS_VOUT_VSET_MASK GENMASK(5, 0)
98 #define TPS65219_BUCKS_UV_THR_SEL_MASK BIT(6)
99 #define TPS65219_BUCKS_BW_SEL_MASK BIT(7)
101 #define TPS65219_LDOS_BYP_CONFIG_MASK BIT(LDO_BYP_SHIFT)
102 #define TPS65219_LDOS_LSW_CONFIG_MASK BIT(7)
104 #define TPS65219_ENABLE_BUCK1_EN_MASK BIT(0)
105 #define TPS65219_ENABLE_BUCK2_EN_MASK BIT(1)
[all …]
Drohm-bd71815.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 * Author: yanglsh@embest-tech.com
32 /* LDO for Low-Power State Retention */
236 #define BD71815_BUCK_PWM_FIXED BIT(4)
237 #define BD71815_BUCK_SNVS_ON BIT(3)
238 #define BD71815_BUCK_RUN_ON BIT(2)
239 #define BD71815_BUCK_LPSR_ON BIT(1)
240 #define BD71815_BUCK_SUSP_ON BIT(0)
243 #define BD71815_BUCK_DVSSEL BIT(7)
244 #define BD71815_BUCK_STBY_DVS BIT(6)
[all …]
Dtps65218.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
63 #define TPS65218_INT1_VPRG BIT(5)
64 #define TPS65218_INT1_AC BIT(4)
65 #define TPS65218_INT1_PB BIT(3)
66 #define TPS65218_INT1_HOT BIT(2)
67 #define TPS65218_INT1_CC_AQC BIT(1)
68 #define TPS65218_INT1_PRGC BIT(0)
70 #define TPS65218_INT2_LS3_F BIT(5)
71 #define TPS65218_INT2_LS2_F BIT(4)
[all …]
/linux-6.14.4/Documentation/input/devices/
Delantech.rst4 Copyright (C) 2007-2008 Arjan Opmeer <[email protected]>
22 5. Hardware version 2
25 5.2.1 Parity checking and packet re-synchronization
58 4 allows tracking up to 5 fingers.
114 non-zero value will turn it ON. For hardware version 1 the default is ON.
118 calculating a parity bit for the last 3 bytes of each packet. The driver
145 4 bytes version: (after the arrow is the name given in the Dell-provided driver)
173 ---------
179 echo -n 0x16 > reg_10
183 bit 7 6 5 4 3 2 1 0
[all …]
/linux-6.14.4/drivers/net/dsa/microchip/
Dksz8_reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
27 #define KSZ8863_GLOBAL_SOFTWARE_RESET BIT(4)
28 #define KSZ8863_PCS_RESET BIT(0)
31 #define KSZ88X3_PORT3_RMII_CLK_INTERNAL BIT(3)
35 #define SW_NEW_BACKOFF BIT(7)
36 #define SW_GLOBAL_RESET BIT(6)
37 #define SW_FLUSH_DYN_MAC_TABLE BIT(5)
38 #define SW_FLUSH_STA_MAC_TABLE BIT(4)
39 #define SW_LINK_AUTO_AGING BIT(0)
43 #define SW_HUGE_PACKET BIT(6)
[all …]
Dksz9477_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2017-2024 Microchip Technology Inc.
14 /* 0 - Operation */
43 #define SW_GIGABIT_ABLE BIT(6)
44 #define SW_REDUNDANCY_ABLE BIT(5)
45 #define SW_AVB_ABLE BIT(4)
63 #define SW_QW_ABLE BIT(5)
69 #define LUE_INT BIT(31)
70 #define TRIG_TS_INT BIT(30)
71 #define APB_TIMEOUT_INT BIT(29)
[all …]
/linux-6.14.4/drivers/gpu/drm/bridge/analogix/
Danalogix-i2c-txcommon.h1 /* SPDX-License-Identifier: GPL-2.0-only */
27 #define SP_REGISTER_PD BIT(7)
28 #define SP_HDCP_PD BIT(5)
29 #define SP_AUDIO_PD BIT(4)
30 #define SP_VIDEO_PD BIT(3)
31 #define SP_LINK_PD BIT(2)
32 #define SP_TOTAL_PD BIT(1)
36 #define SP_MISC_RST BIT(7)
37 #define SP_VIDCAP_RST BIT(6)
38 #define SP_VIDFIF_RST BIT(5)
[all …]
/linux-6.14.4/include/linux/soundwire/
Dsdw_registers.h1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
39 #define SDW_DP0_INT_TEST_FAIL BIT(0)
40 #define SDW_DP0_INT_PORT_READY BIT(1)
41 #define SDW_DP0_INT_BRA_FAILURE BIT(2)
42 #define SDW_DP0_SDCA_CASCADE BIT(3)
43 /* BIT(4) not allocated in SoundWire specification 1.2 */
44 #define SDW_DP0_INT_IMPDEF1 BIT(5)
45 #define SDW_DP0_INT_IMPDEF2 BIT(6)
46 #define SDW_DP0_INT_IMPDEF3 BIT(7)
[all …]
/linux-6.14.4/drivers/platform/x86/intel/pmc/
Dmtl.c1 // SPDX-License-Identifier: GPL-2.0
20 static const u8 MTL_LPM_REG_INDEX[] = {0, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 20};
25 * MTL-M SOC-M IOE-M None
26 * MTL-P SOC-M IOE-P None
27 * MTL-S SOC-S IOE-P PCH-S
31 {"PMC", BIT(0)},
32 {"OPI", BIT(1)},
33 {"SPI", BIT(2)},
34 {"XHCI", BIT(3)},
35 {"SPA", BIT(4)},
[all …]
/linux-6.14.4/drivers/gpu/drm/mcde/
Dmcde_dsi_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 #define DSI_MCTL_MAIN_DATA_CTL_LINK_EN BIT(0)
9 #define DSI_MCTL_MAIN_DATA_CTL_IF1_MODE BIT(1)
10 #define DSI_MCTL_MAIN_DATA_CTL_VID_EN BIT(2)
11 #define DSI_MCTL_MAIN_DATA_CTL_TVG_SEL BIT(3)
12 #define DSI_MCTL_MAIN_DATA_CTL_TBG_SEL BIT(4)
13 #define DSI_MCTL_MAIN_DATA_CTL_IF1_TE_EN BIT(5)
14 #define DSI_MCTL_MAIN_DATA_CTL_IF2_TE_EN BIT(6)
15 #define DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN BIT(7)
16 #define DSI_MCTL_MAIN_DATA_CTL_READ_EN BIT(8)
[all …]
/linux-6.14.4/include/linux/mfd/da9150/
Dregisters.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * DA9150 MFD Driver - Registers
160 #define DA9150_WRITE_MODE_MASK BIT(6)
162 #define DA9150_REVERT_MASK BIT(7)
172 #define DA9150_VFAULT_STAT_MASK BIT(0)
174 #define DA9150_TFAULT_STAT_MASK BIT(1)
178 #define DA9150_VDD33_STAT_MASK BIT(0)
180 #define DA9150_VDD33_SLEEP_MASK BIT(1)
182 #define DA9150_LFOSC_STAT_MASK BIT(7)
186 #define DA9150_GPIOA_STAT_MASK BIT(0)
[all …]
/linux-6.14.4/drivers/net/ethernet/freescale/dpaa2/
Ddpkg.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /* Copyright 2013-2015 Freescale Semiconductor Inc.
16 * DPKG_NUM_OF_MASKS - Number of masks per key extraction
21 * DPKG_MAX_NUM_OF_EXTRACTS - Number of extractions per key profile
26 * enum dpkg_extract_from_hdr_type - Selecting extraction by header types
38 * enum dpkg_extract_type - Enumeration for selecting extraction type
41 * @DPKG_EXTRACT_FROM_PARSE: Extract from parser-result;
52 * struct dpkg_mask - A structure for defining a single extraction mask
64 #define NH_FLD_ETH_DA BIT(0)
65 #define NH_FLD_ETH_SA BIT(1)
[all …]
/linux-6.14.4/drivers/iio/dac/
Dad3552r.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * AD3552R Digital <-> Analog converters common header
5 * Copyright 2021-2024 Analog Devices Inc.
15 #define AD3552R_MASK_SOFTWARE_RESET (BIT(7) | BIT(0))
16 #define AD3552R_MASK_ADDR_ASCENSION BIT(5)
17 #define AD3552R_MASK_SDO_ACTIVE BIT(4)
19 #define AD3552R_MASK_SINGLE_INST BIT(7)
20 #define AD3552R_MASK_SHORT_INSTRUCTION BIT(3)
22 #define AD3552R_MASK_DEVICE_STATUS(n) BIT(4 + (n))
40 #define AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE BIT(2)
[all …]
/linux-6.14.4/sound/soc/mediatek/mt8186/
Dmt8186-reg.h1 /* SPDX-License-Identifier: GPL-2.0
3 * mt8186-reg.h -- Mediatek 8186 audio driver reg definition
12 /* reg bit enum */
26 #define RESERVED_MASK_SFT BIT(31)
28 #define AHB_IDLE_EN_INT_MASK_SFT BIT(30)
30 #define AHB_IDLE_EN_EXT_MASK_SFT BIT(29)
32 #define PDN_NLE_MASK_SFT BIT(28)
34 #define PDN_TML_MASK_SFT BIT(27)
36 #define PDN_DAC_PREDIS_MASK_SFT BIT(26)
38 #define PDN_DAC_MASK_SFT BIT(25)
[all …]
/linux-6.14.4/drivers/clk/stm32/
Dstm32mp13_rcc.h1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
3 * Copyright (C) 2020, STMicroelectronics - All Rights Reserved
238 #define RCC_MP_SREQSETR_STPREQ_P0 BIT(0)
241 #define RCC_MP_SREQCLRR_STPREQ_P0 BIT(0)
244 #define RCC_MP_APRSTCR_RDCTLEN BIT(0)
257 #define RCC_MP_GRSTCSETR_MPSYSRST BIT(0)
258 #define RCC_MP_GRSTCSETR_MPUP0RST BIT(4)
261 #define RCC_BR_RSTSCLRR_PORRSTF BIT(0)
262 #define RCC_BR_RSTSCLRR_BORRSTF BIT(1)
263 #define RCC_BR_RSTSCLRR_PADRSTF BIT(2)
[all …]
/linux-6.14.4/include/soc/mscc/
Docelot_hsio.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
85 #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
86 #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
87 #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
88 #define HSIO_PLL5G_CFG0_DIV4 BIT(28)
89 #define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
99 #define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
100 #define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14)
101 #define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13)
102 #define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12)
[all …]
/linux-6.14.4/drivers/gpu/drm/vc4/
Dvc4_packet.h34 VC4_PACKET_FLUSH_ALL = 5,
78 /* Not an actual hardware packet -- this is what we use to put
93 #define VC4_PACKET_BRANCH_SIZE 5
94 #define VC4_PACKET_BRANCH_TO_SUB_LIST_SIZE 5
97 #define VC4_PACKET_STORE_FULL_RES_TILE_BUFFER_SIZE 5
98 #define VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER_SIZE 5
106 #define VC4_PACKET_GL_SHADER_STATE_SIZE 5
107 #define VC4_PACKET_NV_SHADER_STATE_SIZE 5
108 #define VC4_PACKET_VG_SHADER_STATE_SIZE 5
110 #define VC4_PACKET_FLAT_SHADE_FLAGS_SIZE 5
[all …]
/linux-6.14.4/drivers/media/i2c/
Dmax9271.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2017-2020 Jacopo Mondi
4 * Copyright (C) 2017-2020 Kieran Bingham
5 * Copyright (C) 2017-2020 Laurent Pinchart
6 * Copyright (C) 2017-2020 Niklas Söderlund
19 #define MAX9271_SPREAD_SPECT_0 (0 << 5)
20 #define MAX9271_SPREAD_SPECT_05 (1 << 5)
21 #define MAX9271_SPREAD_SPECT_15 (2 << 5)
22 #define MAX9271_SPREAD_SPECT_1 (5 << 5)
23 #define MAX9271_SPREAD_SPECT_2 (3 << 5)
[all …]
/linux-6.14.4/drivers/crypto/intel/qat/qat_common/
Dadf_gen4_ras.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #define ADF_GEN4_ERRSOU0_BIT BIT(0)
18 #define ADF_GEN4_ERRSOU1_HIAEUNCERRLOG_CPP0_BIT BIT(0)
19 #define ADF_GEN4_ERRSOU1_HICPPAGENTCMDPARERRLOG_BIT BIT(1)
20 #define ADF_GEN4_ERRSOU1_RIMEM_PARERR_STS_BIT BIT(2)
21 #define ADF_GEN4_ERRSOU1_TIMEM_PARERR_STS_BIT BIT(3)
22 #define ADF_GEN4_ERRSOU1_RIMISCSTS_BIT BIT(4)
51 * BIT(0) - BIT(3) - ri_iosf_pdata_rxq[0:3] parity error
52 * BIT(4) - ri_tlq_phdr parity error
53 * BIT(5) - ri_tlq_pdata parity error
[all …]

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