Searched +full:0 +full:x80f00000 (Results 1 – 4 of 4) sorted by relevance
15 #size-cells = <0>;17 cpu@0 {19 reg = <0>;26 pll: clock-0 {28 #clock-cells = <0>;34 #clock-cells = <0>;50 reg = <0xb0040000 0x1000>;59 ranges = <0x0 0xc0000000 0x30000000>;64 reg = <0xeff0000 0x1000>;71 reg = <0x80f00000 0x1000>;[all …]
161 mailbox0_cluster3: mailbox-0 {173 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */174 <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71_0 */175 <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */176 <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>; /* C66_1 */181 reg = <0x4d 0x80800000 0x00 0x00048000>,182 <0x4d 0x80e00000 0x00 0x00008000>,183 <0x4d 0x80f00000 0x00 0x00008000>;187 ti,sci-proc-ids = <0x03 0xFF>;198 reg = <0x00 0x64800000 0x00 0x00080000>,[all …]
15 #clock-cells = <0>;17 clock-frequency = <0>;21 #clock-cells = <0>;23 clock-frequency = <0>;30 reg = <0x0 0x70000000 0x0 0x800000>;33 ranges = <0x0 0x0 0x70000000 0x800000>;35 atf-sram@0 {36 reg = <0x0 0x20000>;42 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */45 ranges = <0x0 0x0 0x00100000 0x1c000>;[all …]
17 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e23 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF24 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 025 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF000031 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF32 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 033 #define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF000042 #define PIN_CFG_NA 0x0000000043 #define PIN_CFG_GPIO0_P0 0x0000000144 #define PIN_CFG_GPIO1_P0 0x00000002[all …]