1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 #include <device/mmio.h>
4 #include <console/console.h>
5 #include <delay.h>
6 #include <soc/dp.h>
7 #include <soc/fimd.h>
8 #include <soc/i2c.h>
9 #include <soc/power.h>
10 #include <soc/sysreg.h>
11
12 /* FIXME: I think the DP controller shouldn't be hardcoded here... */
13 static struct exynos_dp * const dp_regs = (void *)EXYNOS5_DP1_BASE;
14
15 /* for debugging, it's nice to get control on a per-file basis.
16 * I had a bit of a discussion with myself (boring!) about
17 * how to do this and for the moment this is the easiest way.
18 * These debugging statements allowed me to find the final bugs.
19 */
20
21 #if 0
22 static inline void fwadl(unsigned long l,void *v) {
23 writel(l, v);
24 printk(BIOS_SPEW, "W %p %p\n", v, (void *)l);
25 }
26 #define lwrite32(a,b) fwadl((unsigned long)(a), (void *)(b))
27
28 static inline unsigned long fradl(void *v) {
29 unsigned long l = readl(v);
30 printk(BIOS_SPEW, "R %p %p\n", v, (void *)l);
31 return l;
32 }
33
34 #define lread32(a) fradl((void *)(a))
35 #else
36 #define lwrite32(a,b) write32((void *)(b), (unsigned long)(a))
37 #define lread32(a) read32((void *)(a))
38 #endif
39
exynos_dp_enable_video_input(u32 enable)40 static void exynos_dp_enable_video_input(u32 enable)
41 {
42 u32 reg;
43
44 reg = lread32(&dp_regs->video_ctl1);
45 reg &= ~VIDEO_EN_MASK;
46
47 /* enable video input*/
48 if (enable)
49 reg |= VIDEO_EN_MASK;
50
51 lwrite32(reg, &dp_regs->video_ctl1);
52 }
53
exynos_dp_disable_video_bist(void)54 void exynos_dp_disable_video_bist(void)
55 {
56 u32 reg;
57 reg = lread32(&dp_regs->video_ctl4);
58 reg &= ~VIDEO_BIST_MASK;
59 lwrite32(reg, &dp_regs->video_ctl4);
60 }
61
exynos_dp_enable_video_mute(unsigned int enable)62 void exynos_dp_enable_video_mute(unsigned int enable)
63 {
64 u32 reg;
65
66 reg = lread32(&dp_regs->video_ctl1);
67 reg &= ~(VIDEO_MUTE_MASK);
68 if (enable)
69 reg |= VIDEO_MUTE_MASK;
70
71 lwrite32(reg, &dp_regs->video_ctl1);
72 }
73
exynos_dp_init_analog_param(void)74 static void exynos_dp_init_analog_param(void)
75 {
76 u32 reg;
77
78 /*
79 * Set termination
80 * Normal bandgap, Normal swing, Tx terminal resistor 61 ohm
81 * 24M Phy clock, TX digital logic power is 100:1.0625V
82 */
83 reg = SEL_BG_NEW_BANDGAP | TX_TERMINAL_CTRL_61_OHM |
84 SWING_A_30PER_G_NORMAL;
85 lwrite32(reg, &dp_regs->analog_ctl1);
86
87 reg = SEL_24M | TX_DVDD_BIT_1_0625V;
88 lwrite32(reg, &dp_regs->analog_ctl2);
89
90 /*
91 * Set power source for internal clk driver to 1.0625v.
92 * Select current reference of TX driver current to 00:Ipp/2+Ic/2.
93 * Set VCO range of PLL +- 0uA
94 */
95 reg = DRIVE_DVDD_BIT_1_0625V | SEL_CURRENT_DEFAULT | VCO_BIT_000_MICRO;
96 lwrite32(reg, &dp_regs->analog_ctl3);
97
98 /*
99 * Set AUX TX terminal resistor to 102 ohm
100 * Set AUX channel amplitude control
101 */
102 reg = PD_RING_OSC | AUX_TERMINAL_CTRL_52_OHM | TX_CUR1_2X | TX_CUR_4_MA;
103 lwrite32(reg, &dp_regs->pll_filter_ctl1);
104
105 /*
106 * PLL loop filter bandwidth
107 * For 2.7Gbps: 175KHz, For 1.62Gbps: 234KHz
108 * PLL digital power select: 1.2500V
109 */
110 reg = CH3_AMP_0_MV | CH2_AMP_0_MV | CH1_AMP_0_MV | CH0_AMP_0_MV;
111
112 lwrite32(reg, &dp_regs->amp_tuning_ctl);
113
114 /*
115 * PLL loop filter bandwidth
116 * For 2.7Gbps: 175KHz, For 1.62Gbps: 234KHz
117 * PLL digital power select: 1.1250V
118 */
119 reg = DP_PLL_LOOP_BIT_DEFAULT | DP_PLL_REF_BIT_1_1250V;
120 lwrite32(reg, &dp_regs->pll_ctl);
121 }
122
exynos_dp_init_interrupt(void)123 static void exynos_dp_init_interrupt(void)
124 {
125 /* Set interrupt registers to initial states */
126
127 /*
128 * Disable interrupt
129 * INT pin assertion polarity. It must be configured
130 * correctly according to ICU setting.
131 * 1 = assert high, 0 = assert low
132 */
133 lwrite32(INT_POL, &dp_regs->int_ctl);
134
135 /* Clear pending registers */
136 lwrite32(0xff, &dp_regs->common_int_sta1);
137 lwrite32(0xff, &dp_regs->common_int_sta2);
138 lwrite32(0xff, &dp_regs->common_int_sta3);
139 lwrite32(0xff, &dp_regs->common_int_sta4);
140 lwrite32(0xff, &dp_regs->int_sta);
141
142 /* 0:mask,1: unmask */
143 lwrite32(0x00, &dp_regs->int_sta_mask1);
144 lwrite32(0x00, &dp_regs->int_sta_mask2);
145 lwrite32(0x00, &dp_regs->int_sta_mask3);
146 lwrite32(0x00, &dp_regs->int_sta_mask4);
147 lwrite32(0x00, &dp_regs->int_sta_mask);
148 }
149
exynos_dp_reset(void)150 void exynos_dp_reset(void)
151 {
152 u32 reg_func_1;
153
154 /*dp tx sw reset*/
155 lwrite32(RESET_DP_TX, &dp_regs->tx_sw_reset);
156
157 exynos_dp_enable_video_input(DP_DISABLE);
158 exynos_dp_disable_video_bist();
159 exynos_dp_enable_video_mute(DP_DISABLE);
160
161 /* software reset */
162 reg_func_1 = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
163 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
164 HDCP_FUNC_EN_N | SW_FUNC_EN_N;
165
166 lwrite32(reg_func_1, &dp_regs->func_en1);
167 lwrite32(reg_func_1, &dp_regs->func_en2);
168
169 mdelay(1);
170
171 exynos_dp_init_analog_param();
172 exynos_dp_init_interrupt();
173 }
174
exynos_dp_enable_sw_func(unsigned int enable)175 void exynos_dp_enable_sw_func(unsigned int enable)
176 {
177 u32 reg;
178
179 reg = lread32(&dp_regs->func_en1);
180 reg &= ~(SW_FUNC_EN_N);
181
182 if (!enable)
183 reg |= SW_FUNC_EN_N;
184
185 lwrite32(reg, &dp_regs->func_en1);
186 }
187
exynos_dp_set_analog_power_down(unsigned int block,u32 enable)188 unsigned int exynos_dp_set_analog_power_down(unsigned int block, u32 enable)
189 {
190 u32 reg;
191
192 reg = lread32(&dp_regs->phy_pd);
193 switch (block) {
194 case AUX_BLOCK:
195 reg &= ~(AUX_PD);
196 if (enable)
197 reg |= AUX_PD;
198 break;
199 case CH0_BLOCK:
200 reg &= ~(CH0_PD);
201 if (enable)
202 reg |= CH0_PD;
203 break;
204 case CH1_BLOCK:
205 reg &= ~(CH1_PD);
206 if (enable)
207 reg |= CH1_PD;
208 break;
209 case CH2_BLOCK:
210 reg &= ~(CH2_PD);
211 if (enable)
212 reg |= CH2_PD;
213 break;
214 case CH3_BLOCK:
215 reg &= ~(CH3_PD);
216 if (enable)
217 reg |= CH3_PD;
218 break;
219 case ANALOG_TOTAL:
220 reg &= ~PHY_PD;
221 if (enable)
222 reg |= PHY_PD;
223 break;
224 case POWER_ALL:
225 reg &= ~(PHY_PD | AUX_PD | CH0_PD | CH1_PD | CH2_PD |
226 CH3_PD);
227 if (enable)
228 reg |= (PHY_PD | AUX_PD | CH0_PD | CH1_PD |
229 CH2_PD | CH3_PD);
230 break;
231 default:
232 printk(BIOS_ERR, "DP undefined block number : %d\n", block);
233 return -1;
234 }
235
236 lwrite32(reg, &dp_regs->phy_pd);
237
238 return 0;
239 }
240
exynos_dp_get_pll_lock_status(void)241 unsigned int exynos_dp_get_pll_lock_status(void)
242 {
243 u32 reg;
244
245 reg = lread32(&dp_regs->debug_ctl);
246
247 if (reg & PLL_LOCK)
248 return PLL_LOCKED;
249 else
250 return PLL_UNLOCKED;
251 }
252
exynos_dp_set_pll_power(unsigned int enable)253 static void exynos_dp_set_pll_power(unsigned int enable)
254 {
255 u32 reg;
256
257 reg = lread32(&dp_regs->pll_ctl);
258 reg &= ~(DP_PLL_PD);
259
260 if (!enable)
261 reg |= DP_PLL_PD;
262
263 lwrite32(reg, &dp_regs->pll_ctl);
264 }
265
exynos_dp_init_analog_func(void)266 int exynos_dp_init_analog_func(void)
267 {
268 int ret = EXYNOS_DP_SUCCESS;
269 unsigned int retry_cnt = 10;
270 u32 reg;
271
272 /*Power On All Analog block */
273 exynos_dp_set_analog_power_down(POWER_ALL, DP_DISABLE);
274
275 reg = PLL_LOCK_CHG;
276 lwrite32(reg, &dp_regs->common_int_sta1);
277
278 reg = lread32(&dp_regs->debug_ctl);
279 reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
280 lwrite32(reg, &dp_regs->debug_ctl);
281
282 /*Assert DP PLL Reset*/
283 reg = lread32(&dp_regs->pll_ctl);
284 reg |= DP_PLL_RESET;
285 lwrite32(reg, &dp_regs->pll_ctl);
286
287 mdelay(1);
288
289 /*Deassert DP PLL Reset*/
290 reg = lread32(&dp_regs->pll_ctl);
291 reg &= ~(DP_PLL_RESET);
292 lwrite32(reg, &dp_regs->pll_ctl);
293
294 exynos_dp_set_pll_power(DP_ENABLE);
295
296 while (exynos_dp_get_pll_lock_status() == PLL_UNLOCKED) {
297 mdelay(1);
298 retry_cnt--;
299 if (retry_cnt == 0) {
300 printk(BIOS_ERR, "DP dp's pll lock failed : retry : %d\n",
301 retry_cnt);
302 return -1;
303 }
304 }
305
306 printk(BIOS_DEBUG, "dp's pll lock success(%d)\n", retry_cnt);
307
308 /* Enable Serdes FIFO function and Link symbol clock domain module */
309 reg = lread32(&dp_regs->func_en2);
310 reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
311 | AUX_FUNC_EN_N);
312 lwrite32(reg, &dp_regs->func_en2);
313
314 return ret;
315 }
316
exynos_dp_init_hpd(void)317 void exynos_dp_init_hpd(void)
318 {
319 u32 reg;
320
321 /* Clear interrupts related to Hot Plug Detect */
322 reg = HOTPLUG_CHG | HPD_LOST | PLUG;
323 lwrite32(reg, &dp_regs->common_int_sta4);
324
325 reg = INT_HPD;
326 lwrite32(reg, &dp_regs->int_sta);
327
328 reg = lread32(&dp_regs->sys_ctl3);
329 reg &= ~(F_HPD | HPD_CTRL);
330 lwrite32(reg, &dp_regs->sys_ctl3);
331 }
332
exynos_dp_reset_aux(void)333 static inline void exynos_dp_reset_aux(void)
334 {
335 u32 reg;
336
337 /* Disable AUX channel module */
338 reg = lread32(&dp_regs->func_en2);
339 reg |= AUX_FUNC_EN_N;
340 lwrite32(reg, &dp_regs->func_en2);
341 }
342
exynos_dp_init_aux(void)343 void exynos_dp_init_aux(void)
344 {
345 u32 reg;
346
347 /* Clear interrupts related to AUX channel */
348 reg = RPLY_RECEIV | AUX_ERR;
349 lwrite32(reg, &dp_regs->int_sta);
350
351 exynos_dp_reset_aux();
352
353 /* Disable AUX transaction H/W retry */
354 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(3)|
355 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
356 lwrite32(reg, &dp_regs->aux_hw_retry_ctl);
357
358 /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
359 reg = DEFER_CTRL_EN | DEFER_COUNT(1);
360 lwrite32(reg, &dp_regs->aux_ch_defer_ctl);
361
362 /* Enable AUX channel module */
363 reg = lread32(&dp_regs->func_en2);
364 reg &= ~AUX_FUNC_EN_N;
365 lwrite32(reg, &dp_regs->func_en2);
366 }
367
exynos_dp_config_interrupt(void)368 void exynos_dp_config_interrupt(void)
369 {
370 u32 reg;
371
372 /* 0: mask, 1: unmask */
373 reg = COMMON_INT_MASK_1;
374 lwrite32(reg, &dp_regs->common_int_mask1);
375
376 reg = COMMON_INT_MASK_2;
377 lwrite32(reg, &dp_regs->common_int_mask2);
378
379 reg = COMMON_INT_MASK_3;
380 lwrite32(reg, &dp_regs->common_int_mask3);
381
382 reg = COMMON_INT_MASK_4;
383 lwrite32(reg, &dp_regs->common_int_mask4);
384
385 reg = INT_STA_MASK;
386 lwrite32(reg, &dp_regs->int_sta_mask);
387 }
388
exynos_dp_get_plug_in_status(void)389 unsigned int exynos_dp_get_plug_in_status(void)
390 {
391 u32 reg;
392
393 reg = lread32(&dp_regs->sys_ctl3);
394 if (reg & HPD_STATUS)
395 return 0;
396
397 return -1;
398 }
399
exynos_dp_detect_hpd(void)400 unsigned int exynos_dp_detect_hpd(void)
401 {
402 int timeout_loop = DP_TIMEOUT_LOOP_COUNT;
403
404 mdelay(2);
405
406 while (exynos_dp_get_plug_in_status() != 0) {
407 if (timeout_loop == 0)
408 return -1;
409 mdelay(1);
410 timeout_loop--;
411 }
412
413 return EXYNOS_DP_SUCCESS;
414 }
415
exynos_dp_start_aux_transaction(void)416 unsigned int exynos_dp_start_aux_transaction(void)
417 {
418 u32 reg;
419 unsigned int ret = 0;
420 unsigned int retry_cnt;
421
422 /* Enable AUX CH operation */
423 reg = lread32(&dp_regs->aux_ch_ctl2);
424 reg |= AUX_EN;
425 lwrite32(reg, &dp_regs->aux_ch_ctl2);
426
427 retry_cnt = 10;
428 while (retry_cnt) {
429 reg = lread32(&dp_regs->int_sta);
430 if (!(reg & RPLY_RECEIV)) {
431 if (retry_cnt == 0) {
432 printk(BIOS_ERR, "DP Reply Timeout!!\n");
433 ret = -1;
434 return ret;
435 }
436 mdelay(1);
437 retry_cnt--;
438 } else
439 break;
440 }
441
442 /* Clear interrupt source for AUX CH command reply */
443 lwrite32(reg, &dp_regs->int_sta);
444
445 /* Clear interrupt source for AUX CH access error */
446 reg = lread32(&dp_regs->int_sta);
447 if (reg & AUX_ERR) {
448 printk(BIOS_ERR, "DP Aux Access Error\n");
449 lwrite32(AUX_ERR, &dp_regs->int_sta);
450 ret = -1;
451 return ret;
452 }
453
454 /* Check AUX CH error access status */
455 reg = lread32(&dp_regs->aux_ch_sta);
456 if ((reg & AUX_STATUS_MASK) != 0) {
457 printk(BIOS_DEBUG, "DP AUX CH error happens: %x\n", reg & AUX_STATUS_MASK);
458 ret = -1;
459 return ret;
460 }
461 return EXYNOS_DP_SUCCESS;
462 }
463
exynos_dp_write_byte_to_dpcd(u32 reg_addr,u8 data)464 unsigned int exynos_dp_write_byte_to_dpcd(u32 reg_addr, u8 data)
465 {
466 u32 reg;
467 unsigned int ret;
468
469 /* Clear AUX CH data buffer */
470 reg = BUF_CLR;
471 lwrite32(reg, &dp_regs->buffer_data_ctl);
472
473 /* Select DPCD device address */
474 reg = AUX_ADDR_7_0(reg_addr);
475 lwrite32(reg, &dp_regs->aux_addr_7_0);
476 reg = AUX_ADDR_15_8(reg_addr);
477 lwrite32(reg, &dp_regs->aux_addr_15_8);
478 reg = AUX_ADDR_19_16(reg_addr);
479 lwrite32(reg, &dp_regs->aux_addr_19_16);
480
481 /* Write data buffer */
482 reg = data;
483 lwrite32(reg, &dp_regs->buf_data0);
484
485 /*
486 * Set DisplayPort transaction and write 1 byte
487 * If bit 3 is 1, DisplayPort transaction.
488 * If Bit 3 is 0, I2C transaction.
489 */
490 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
491 lwrite32(reg, &dp_regs->aux_ch_ctl1);
492
493 /* Start AUX transaction */
494 ret = exynos_dp_start_aux_transaction();
495 if (ret != EXYNOS_DP_SUCCESS) {
496 printk(BIOS_ERR, "DP Aux transaction failed\n");
497 }
498
499 return ret;
500 }
501
exynos_dp_read_byte_from_dpcd(u32 reg_addr,unsigned char * data)502 unsigned int exynos_dp_read_byte_from_dpcd(u32 reg_addr,
503 unsigned char *data)
504 {
505 u32 reg;
506 int retval;
507
508 /* Clear AUX CH data buffer */
509 reg = BUF_CLR;
510 lwrite32(reg, &dp_regs->buffer_data_ctl);
511
512 /* Select DPCD device address */
513 reg = AUX_ADDR_7_0(reg_addr);
514 lwrite32(reg, &dp_regs->aux_addr_7_0);
515 reg = AUX_ADDR_15_8(reg_addr);
516 lwrite32(reg, &dp_regs->aux_addr_15_8);
517 reg = AUX_ADDR_19_16(reg_addr);
518 lwrite32(reg, &dp_regs->aux_addr_19_16);
519
520 /*
521 * Set DisplayPort transaction and read 1 byte
522 * If bit 3 is 1, DisplayPort transaction.
523 * If Bit 3 is 0, I2C transaction.
524 */
525 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
526 lwrite32(reg, &dp_regs->aux_ch_ctl1);
527
528 /* Start AUX transaction */
529 retval = exynos_dp_start_aux_transaction();
530 if (retval != EXYNOS_DP_SUCCESS)
531 printk(BIOS_DEBUG, "DP Aux Transaction fail!\n");
532
533 /* Read data buffer */
534 reg = lread32(&dp_regs->buf_data0);
535 *data = (unsigned char)(reg & 0xff);
536
537 return retval;
538 }
539
exynos_dp_write_bytes_to_dpcd(u32 reg_addr,unsigned int count,unsigned char data[])540 unsigned int exynos_dp_write_bytes_to_dpcd(u32 reg_addr,
541 unsigned int count,
542 unsigned char data[])
543 {
544 u32 reg;
545 unsigned int start_offset;
546 unsigned int cur_data_count;
547 unsigned int cur_data_idx;
548 unsigned int retry_cnt;
549 unsigned int ret = 0;
550
551 /* Clear AUX CH data buffer */
552 reg = BUF_CLR;
553 lwrite32(reg, &dp_regs->buffer_data_ctl);
554
555 start_offset = 0;
556 while (start_offset < count) {
557 /* Buffer size of AUX CH is 16 * 4bytes */
558 if ((count - start_offset) > 16)
559 cur_data_count = 16;
560 else
561 cur_data_count = count - start_offset;
562
563 retry_cnt = 5;
564 while (retry_cnt) {
565 /* Select DPCD device address */
566 reg = AUX_ADDR_7_0(reg_addr + start_offset);
567 lwrite32(reg, &dp_regs->aux_addr_7_0);
568 reg = AUX_ADDR_15_8(reg_addr + start_offset);
569 lwrite32(reg, &dp_regs->aux_addr_15_8);
570 reg = AUX_ADDR_19_16(reg_addr + start_offset);
571 lwrite32(reg, &dp_regs->aux_addr_19_16);
572
573 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
574 cur_data_idx++) {
575 reg = data[start_offset + cur_data_idx];
576 lwrite32(reg, (void *)((unsigned int)&dp_regs->buf_data0 +
577 (4 * cur_data_idx)));
578 }
579 /*
580 * Set DisplayPort transaction and write
581 * If bit 3 is 1, DisplayPort transaction.
582 * If Bit 3 is 0, I2C transaction.
583 */
584 reg = AUX_LENGTH(cur_data_count) |
585 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
586 lwrite32(reg, &dp_regs->aux_ch_ctl1);
587
588 /* Start AUX transaction */
589 ret = exynos_dp_start_aux_transaction();
590 if (ret != EXYNOS_DP_SUCCESS) {
591 if (retry_cnt == 0) {
592 printk(BIOS_ERR, "DP Aux Transaction failed\n");
593 return ret;
594 }
595 retry_cnt--;
596 } else
597 break;
598 }
599 start_offset += cur_data_count;
600 }
601
602 return ret;
603 }
604
exynos_dp_read_bytes_from_dpcd(u32 reg_addr,unsigned int count,unsigned char data[])605 unsigned int exynos_dp_read_bytes_from_dpcd(u32 reg_addr,
606 unsigned int count,
607 unsigned char data[])
608 {
609 u32 reg;
610 unsigned int start_offset;
611 unsigned int cur_data_count;
612 unsigned int cur_data_idx;
613 unsigned int retry_cnt;
614 unsigned int ret = 0;
615
616 /* Clear AUX CH data buffer */
617 reg = BUF_CLR;
618 lwrite32(reg, &dp_regs->buffer_data_ctl);
619
620 start_offset = 0;
621 while (start_offset < count) {
622 /* Buffer size of AUX CH is 16 * 4bytes */
623 if ((count - start_offset) > 16)
624 cur_data_count = 16;
625 else
626 cur_data_count = count - start_offset;
627
628 retry_cnt = 5;
629 while (retry_cnt) {
630 /* Select DPCD device address */
631 reg = AUX_ADDR_7_0(reg_addr + start_offset);
632 lwrite32(reg, &dp_regs->aux_addr_7_0);
633 reg = AUX_ADDR_15_8(reg_addr + start_offset);
634 lwrite32(reg, &dp_regs->aux_addr_15_8);
635 reg = AUX_ADDR_19_16(reg_addr + start_offset);
636 lwrite32(reg, &dp_regs->aux_addr_19_16);
637 /*
638 * Set DisplayPort transaction and read
639 * If bit 3 is 1, DisplayPort transaction.
640 * If Bit 3 is 0, I2C transaction.
641 */
642 reg = AUX_LENGTH(cur_data_count) |
643 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
644 lwrite32(reg, &dp_regs->aux_ch_ctl1);
645
646 /* Start AUX transaction */
647 ret = exynos_dp_start_aux_transaction();
648 if (ret != EXYNOS_DP_SUCCESS) {
649 if (retry_cnt == 0) {
650 printk(BIOS_ERR, "DP Aux Transaction failed\n");
651 return ret;
652 }
653 retry_cnt--;
654 } else
655 break;
656 }
657
658 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
659 cur_data_idx++) {
660 reg = lread32((void *)((u32)&dp_regs->buf_data0 +
661 4 * cur_data_idx));
662 data[start_offset + cur_data_idx] = (unsigned char)reg;
663 }
664
665 start_offset += cur_data_count;
666 }
667
668 return ret;
669 }
670
exynos_dp_select_i2c_device(u32 device_addr,u32 reg_addr)671 int exynos_dp_select_i2c_device(u32 device_addr,
672 u32 reg_addr)
673 {
674 u32 reg;
675 int retval;
676
677 /* Set EDID device address */
678 reg = device_addr;
679 lwrite32(reg, &dp_regs->aux_addr_7_0);
680 lwrite32(0x0, &dp_regs->aux_addr_15_8);
681 lwrite32(0x0, &dp_regs->aux_addr_19_16);
682
683 /* Set offset from base address of EDID device */
684 lwrite32(reg_addr, &dp_regs->buf_data0);
685
686 /*
687 * Set I2C transaction and write address
688 * If bit 3 is 1, DisplayPort transaction.
689 * If Bit 3 is 0, I2C transaction.
690 */
691 reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
692 AUX_TX_COMM_WRITE;
693 lwrite32(reg, &dp_regs->aux_ch_ctl1);
694
695 /* Start AUX transaction */
696 retval = exynos_dp_start_aux_transaction();
697 if (retval != 0)
698 printk(BIOS_DEBUG, "%s: DP Aux Transaction fail!\n", __func__);
699
700 return retval;
701 }
702
exynos_dp_read_byte_from_i2c(u32 device_addr,u32 reg_addr,unsigned int * data)703 int exynos_dp_read_byte_from_i2c(u32 device_addr,
704 u32 reg_addr,
705 unsigned int *data)
706 {
707 u32 reg;
708 int i;
709 int retval;
710
711 for (i = 0; i < 10; i++) {
712 /* Clear AUX CH data buffer */
713 reg = BUF_CLR;
714 lwrite32(reg, &dp_regs->buffer_data_ctl);
715
716 /* Select EDID device */
717 retval = exynos_dp_select_i2c_device(device_addr, reg_addr);
718 if (retval != 0) {
719 printk(BIOS_DEBUG, "DP Select EDID device fail. retry !\n");
720 continue;
721 }
722
723 /*
724 * Set I2C transaction and read data
725 * If bit 3 is 1, DisplayPort transaction.
726 * If Bit 3 is 0, I2C transaction.
727 */
728 reg = AUX_TX_COMM_I2C_TRANSACTION |
729 AUX_TX_COMM_READ;
730 lwrite32(reg, &dp_regs->aux_ch_ctl1);
731
732 /* Start AUX transaction */
733 retval = exynos_dp_start_aux_transaction();
734 if (retval != EXYNOS_DP_SUCCESS)
735 printk(BIOS_DEBUG, "%s: DP Aux Transaction fail!\n", __func__);
736 }
737
738 /* Read data */
739 if (retval == 0)
740 *data = lread32(&dp_regs->buf_data0);
741
742 return retval;
743 }
744
exynos_dp_read_bytes_from_i2c(u32 device_addr,u32 reg_addr,unsigned int count,unsigned char edid[])745 int exynos_dp_read_bytes_from_i2c(u32 device_addr,
746 u32 reg_addr, unsigned int count, unsigned char edid[])
747 {
748 u32 reg;
749 unsigned int i, j;
750 unsigned int cur_data_idx;
751 unsigned int defer = 0;
752 int retval = 0;
753
754 for (i = 0; i < count; i += 16) { /* use 16 burst */
755 for (j = 0; j < 100; j++) {
756 /* Clear AUX CH data buffer */
757 reg = BUF_CLR;
758 lwrite32(reg, &dp_regs->buffer_data_ctl);
759
760 /* Set normal AUX CH command */
761 reg = lread32(&dp_regs->aux_ch_ctl2);
762 reg &= ~ADDR_ONLY;
763 lwrite32(reg, &dp_regs->aux_ch_ctl2);
764
765 /*
766 * If Rx sends defer, Tx sends only reads
767 * request without sending address
768 */
769 if (!defer)
770 retval =
771 exynos_dp_select_i2c_device(device_addr,
772 reg_addr + i);
773 else
774 defer = 0;
775
776 if (retval == EXYNOS_DP_SUCCESS) {
777 /*
778 * Set I2C transaction and write data
779 * If bit 3 is 1, DisplayPort transaction.
780 * If Bit 3 is 0, I2C transaction.
781 */
782 reg = AUX_LENGTH(16) |
783 AUX_TX_COMM_I2C_TRANSACTION |
784 AUX_TX_COMM_READ;
785 lwrite32(reg, &dp_regs->aux_ch_ctl1);
786
787 /* Start AUX transaction */
788 retval = exynos_dp_start_aux_transaction();
789 if (retval == 0)
790 break;
791 else
792 printk(BIOS_ERR, "DP Aux Transaction fail!\n");
793 }
794 /* Check if Rx sends defer */
795 reg = lread32(&dp_regs->aux_rx_comm);
796 if (reg == AUX_RX_COMM_AUX_DEFER ||
797 reg == AUX_RX_COMM_I2C_DEFER) {
798 printk(BIOS_ERR, "DP Defer: %d\n\n", reg);
799 defer = 1;
800 }
801 }
802
803 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
804 reg = lread32((void *)((u32)&dp_regs->buf_data0
805 + 4 * cur_data_idx));
806 edid[i + cur_data_idx] = (unsigned char)reg;
807 }
808 }
809
810 return retval;
811 }
812
exynos_dp_reset_macro(void)813 void exynos_dp_reset_macro(void)
814 {
815 u32 reg;
816
817 reg = lread32(&dp_regs->phy_test);
818 reg |= MACRO_RST;
819 lwrite32(reg, &dp_regs->phy_test);
820
821 /* 10 us is the minimum Macro reset time. */
822 udelay(50);
823
824 reg &= ~MACRO_RST;
825 lwrite32(reg, &dp_regs->phy_test);
826 }
827
exynos_dp_set_link_bandwidth(unsigned char bwtype)828 void exynos_dp_set_link_bandwidth(unsigned char bwtype)
829 {
830 u32 reg;
831
832 reg = (u32)bwtype;
833
834 /* Set bandwidth to 2.7G or 1.62G */
835 if ((bwtype == DP_LANE_BW_1_62) || (bwtype == DP_LANE_BW_2_70))
836 lwrite32(reg, &dp_regs->link_bw_set);
837 }
838
exynos_dp_get_link_bandwidth(void)839 unsigned char exynos_dp_get_link_bandwidth(void)
840 {
841 unsigned char ret;
842 u32 reg;
843
844 reg = lread32(&dp_regs->link_bw_set);
845 ret = (unsigned char)reg;
846
847 return ret;
848 }
849
exynos_dp_set_lane_count(unsigned char count)850 void exynos_dp_set_lane_count(unsigned char count)
851 {
852 u32 reg;
853
854 reg = (u32)count;
855
856 if ((count == DP_LANE_CNT_1) || (count == DP_LANE_CNT_2) ||
857 (count == DP_LANE_CNT_4))
858 lwrite32(reg, &dp_regs->lane_count_set);
859 }
860
exynos_dp_get_lane_count(void)861 unsigned int exynos_dp_get_lane_count(void)
862 {
863 u32 reg;
864
865 reg = lread32(&dp_regs->lane_count_set);
866
867 return reg;
868 }
869
exynos_dp_get_lanex_pre_emphasis(unsigned char lanecnt)870 unsigned char exynos_dp_get_lanex_pre_emphasis(unsigned char lanecnt)
871 {
872 void *reg_list[DP_LANE_CNT_4] = {
873 &dp_regs->ln0_link_training_ctl,
874 &dp_regs->ln1_link_training_ctl,
875 &dp_regs->ln2_link_training_ctl,
876 &dp_regs->ln3_link_training_ctl,
877 };
878
879 return lread32(reg_list[lanecnt]);
880 }
881
exynos_dp_set_lanex_pre_emphasis(unsigned char request_val,unsigned char lanecnt)882 void exynos_dp_set_lanex_pre_emphasis(unsigned char request_val,
883 unsigned char lanecnt)
884 {
885 void *reg_list[DP_LANE_CNT_4] = {
886 &dp_regs->ln0_link_training_ctl,
887 &dp_regs->ln1_link_training_ctl,
888 &dp_regs->ln2_link_training_ctl,
889 &dp_regs->ln3_link_training_ctl,
890 };
891
892 lwrite32(request_val, reg_list[lanecnt]);
893 }
894
exynos_dp_set_lane_pre_emphasis(unsigned int level,unsigned char lanecnt)895 void exynos_dp_set_lane_pre_emphasis(unsigned int level, unsigned char lanecnt)
896 {
897 unsigned int i;
898 u32 reg;
899 void *reg_list[DP_LANE_CNT_4] = {
900 &dp_regs->ln0_link_training_ctl,
901 &dp_regs->ln1_link_training_ctl,
902 &dp_regs->ln2_link_training_ctl,
903 &dp_regs->ln3_link_training_ctl,
904 };
905 u32 reg_shift[DP_LANE_CNT_4] = {
906 PRE_EMPHASIS_SET_0_SHIFT,
907 PRE_EMPHASIS_SET_1_SHIFT,
908 PRE_EMPHASIS_SET_2_SHIFT,
909 PRE_EMPHASIS_SET_3_SHIFT
910 };
911
912 for (i = 0; i < lanecnt; i++) {
913 reg = level << reg_shift[i];
914 lwrite32(reg, reg_list[i]);
915 }
916 }
917
exynos_dp_set_training_pattern(unsigned int pattern)918 void exynos_dp_set_training_pattern(unsigned int pattern)
919 {
920 u32 reg = 0;
921
922 switch (pattern) {
923 case PRBS7:
924 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
925 break;
926 case D10_2:
927 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
928 break;
929 case TRAINING_PTN1:
930 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
931 break;
932 case TRAINING_PTN2:
933 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
934 break;
935 case DP_NONE:
936 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_DISABLE |
937 SW_TRAINING_PATTERN_SET_NORMAL;
938 break;
939 default:
940 break;
941 }
942
943 lwrite32(reg, &dp_regs->training_ptn_set);
944 }
945
exynos_dp_enable_enhanced_mode(unsigned char enable)946 void exynos_dp_enable_enhanced_mode(unsigned char enable)
947 {
948 u32 reg;
949
950 reg = lread32(&dp_regs->sys_ctl4);
951 reg &= ~ENHANCED;
952
953 if (enable)
954 reg |= ENHANCED;
955
956 lwrite32(reg, &dp_regs->sys_ctl4);
957 }
958
exynos_dp_enable_scrambling(unsigned int enable)959 void exynos_dp_enable_scrambling(unsigned int enable)
960 {
961 u32 reg;
962
963 reg = lread32(&dp_regs->training_ptn_set);
964 reg &= ~(SCRAMBLING_DISABLE);
965
966 if (!enable)
967 reg |= SCRAMBLING_DISABLE;
968
969 lwrite32(reg, &dp_regs->training_ptn_set);
970 }
exynos_dp_init_video(void)971 int exynos_dp_init_video(void)
972 {
973 unsigned int reg;
974
975 /* Clear VID_CLK_CHG[1] and VID_FORMAT_CHG[3] and VSYNC_DET[7] */
976 reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
977 lwrite32(reg, &dp_regs->common_int_sta1);
978
979 /* I_STRM__CLK detect : DE_CTL : Auto detect */
980 reg &= ~DET_CTRL;
981 lwrite32(reg, &dp_regs->sys_ctl1);
982 return 0;
983 }
984
exynos_dp_config_video_slave_mode(struct edp_video_info * video_info)985 void exynos_dp_config_video_slave_mode(struct edp_video_info *video_info)
986 {
987 u32 reg;
988
989 /* Video Slave mode setting */
990 reg = lread32(&dp_regs->func_en1);
991 reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
992 reg |= MASTER_VID_FUNC_EN_N;
993 lwrite32(reg, &dp_regs->func_en1);
994
995 /* Configure Interlaced for slave mode video */
996 reg = lread32(&dp_regs->video_ctl10);
997 reg &= ~INTERACE_SCAN_CFG;
998 reg |= (video_info->interlaced << INTERACE_SCAN_CFG_SHIFT);
999 printk(BIOS_SPEW, "interlaced %d\n", video_info->interlaced);
1000 lwrite32(reg, &dp_regs->video_ctl10);
1001
1002 /* Configure V sync polarity for slave mode video */
1003 reg = lread32(&dp_regs->video_ctl10);
1004 reg &= ~VSYNC_POLARITY_CFG;
1005 reg |= (video_info->v_sync_polarity << V_S_POLARITY_CFG_SHIFT);
1006 lwrite32(reg, &dp_regs->video_ctl10);
1007
1008 /* Configure H sync polarity for slave mode video */
1009 reg = lread32(&dp_regs->video_ctl10);
1010 reg &= ~HSYNC_POLARITY_CFG;
1011 reg |= (video_info->h_sync_polarity << H_S_POLARITY_CFG_SHIFT);
1012 lwrite32(reg, &dp_regs->video_ctl10);
1013
1014 /*Set video mode to slave mode */
1015 reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
1016 lwrite32(reg, &dp_regs->soc_general_ctl);
1017 }
1018
exynos_dp_set_video_color_format(struct edp_video_info * video_info)1019 void exynos_dp_set_video_color_format(struct edp_video_info *video_info)
1020 {
1021 u32 reg;
1022
1023 /* Configure the input color depth, color space, dynamic range */
1024 reg = (video_info->dynamic_range << IN_D_RANGE_SHIFT) |
1025 (video_info->color_depth << IN_BPC_SHIFT) |
1026 (video_info->color_space << IN_COLOR_F_SHIFT);
1027 lwrite32(reg, &dp_regs->video_ctl2);
1028
1029 /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
1030 reg = lread32(&dp_regs->video_ctl3);
1031 reg &= ~IN_YC_COEFFI_MASK;
1032 if (video_info->ycbcr_coeff)
1033 reg |= IN_YC_COEFFI_ITU709;
1034 else
1035 reg |= IN_YC_COEFFI_ITU601;
1036 lwrite32(reg, &dp_regs->video_ctl3);
1037 }
1038
exynos_dp_is_slave_video_stream_clock_on(void)1039 unsigned int exynos_dp_is_slave_video_stream_clock_on(void)
1040 {
1041 u32 reg;
1042
1043 /* Update Video stream clk detect status */
1044 reg = lread32(&dp_regs->sys_ctl1);
1045 lwrite32(reg, &dp_regs->sys_ctl1);
1046
1047 reg = lread32(&dp_regs->sys_ctl1);
1048
1049 if (!(reg & DET_STA)) {
1050 printk(BIOS_DEBUG, "DP Input stream clock not detected.\n");
1051 return -1;
1052 }
1053
1054 return EXYNOS_DP_SUCCESS;
1055 }
1056
exynos_dp_set_video_cr_mn(unsigned int type,unsigned int m_value,unsigned int n_value)1057 void exynos_dp_set_video_cr_mn(unsigned int type, unsigned int m_value,
1058 unsigned int n_value)
1059 {
1060 u32 reg;
1061
1062 if (type == REGISTER_M) {
1063 reg = lread32(&dp_regs->sys_ctl4);
1064 reg |= FIX_M_VID;
1065 lwrite32(reg, &dp_regs->sys_ctl4);
1066 reg = M_VID0_CFG(m_value);
1067 lwrite32(reg, &dp_regs->m_vid0);
1068 reg = M_VID1_CFG(m_value);
1069 lwrite32(reg, &dp_regs->m_vid1);
1070 reg = M_VID2_CFG(m_value);
1071 lwrite32(reg, &dp_regs->m_vid2);
1072
1073 reg = N_VID0_CFG(n_value);
1074 lwrite32(reg, &dp_regs->n_vid0);
1075 reg = N_VID1_CFG(n_value);
1076 lwrite32(reg, &dp_regs->n_vid1);
1077 reg = N_VID2_CFG(n_value);
1078 lwrite32(reg, &dp_regs->n_vid2);
1079 } else {
1080 reg = lread32(&dp_regs->sys_ctl4);
1081 reg &= ~FIX_M_VID;
1082 lwrite32(reg, &dp_regs->sys_ctl4);
1083 }
1084 }
1085
exynos_dp_set_video_timing_mode(unsigned int type)1086 void exynos_dp_set_video_timing_mode(unsigned int type)
1087 {
1088 u32 reg;
1089
1090 reg = lread32(&dp_regs->video_ctl10);
1091 reg &= ~FORMAT_SEL;
1092
1093 if (type != VIDEO_TIMING_FROM_CAPTURE)
1094 reg |= FORMAT_SEL;
1095
1096 lwrite32(reg, &dp_regs->video_ctl10);
1097 }
1098
exynos_dp_enable_video_master(unsigned int enable)1099 void exynos_dp_enable_video_master(unsigned int enable)
1100 {
1101 u32 reg;
1102
1103 reg = lread32(&dp_regs->soc_general_ctl);
1104 if (enable) {
1105 reg &= ~VIDEO_MODE_MASK;
1106 reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
1107 } else {
1108 reg &= ~VIDEO_MODE_MASK;
1109 reg |= VIDEO_MODE_SLAVE_MODE;
1110 }
1111
1112 lwrite32(reg, &dp_regs->soc_general_ctl);
1113 }
1114
exynos_dp_start_video(void)1115 void exynos_dp_start_video(void)
1116 {
1117 u32 reg;
1118
1119 /* Enable Video input and disable Mute */
1120 reg = lread32(&dp_regs->video_ctl1);
1121 reg |= VIDEO_EN;
1122 lwrite32(reg, &dp_regs->video_ctl1);
1123 }
1124
exynos_dp_is_video_stream_on(void)1125 unsigned int exynos_dp_is_video_stream_on(void)
1126 {
1127 u32 reg;
1128
1129 /* Update STRM_VALID */
1130 reg = lread32(&dp_regs->sys_ctl3);
1131 lwrite32(reg, &dp_regs->sys_ctl3);
1132
1133 reg = lread32(&dp_regs->sys_ctl3);
1134
1135 if (!(reg & STRM_VALID))
1136 return -1;
1137
1138 return EXYNOS_DP_SUCCESS;
1139 }
1140
dp_phy_control(unsigned int enable)1141 void dp_phy_control(unsigned int enable)
1142 {
1143 u32 cfg;
1144
1145 cfg = lread32(&exynos_power->dptx_phy_control);
1146 if (enable)
1147 cfg |= EXYNOS_DP_PHY_ENABLE;
1148 else
1149 cfg &= ~EXYNOS_DP_PHY_ENABLE;
1150 lwrite32(cfg, &exynos_power->dptx_phy_control);
1151 }
1152