xref: /aosp_15_r20/external/coreboot/src/mainboard/google/rambi/romstage.c (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <cbfs.h>
4 #include <console/console.h>
5 #include <device/dram/ddr3.h>
6 #include <soc/gpio.h>
7 #include <soc/mrc_wrapper.h>
8 #include <soc/romstage.h>
9 #include <variant/variant.h>
10 
get_spd_pointer(char * spd_file_content,int total_spds,int * dual)11 static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual)
12 {
13 	int ram_id = 0;
14 
15 	/* The ram_id[2:0] pullups are too large for the default 20K
16 	 * pulldown on the pad. Therefore, disable the internal pull resistor to
17 	 * read high values correctly. */
18 	ssus_disable_internal_pull(GPIO_SSUS_37_PAD);
19 	ssus_disable_internal_pull(GPIO_SSUS_38_PAD);
20 	ssus_disable_internal_pull(GPIO_SSUS_39_PAD);
21 #ifdef GPIO_SSUS_40_PAD_USE_PULLDOWN
22 	/* To prevent floating pin on shipped systems. */
23 	ssus_enable_internal_pull(GPIO_SSUS_40_PAD, PAD_PULL_DOWN | PAD_PU_20K);
24 #elif defined(GPIO_SSUS_40_PAD)
25 	ssus_disable_internal_pull(GPIO_SSUS_40_PAD);
26 #endif
27 	ram_id |= (ssus_get_gpio(GPIO_SSUS_37_PAD) << 0);
28 	ram_id |= (ssus_get_gpio(GPIO_SSUS_38_PAD) << 1);
29 	ram_id |= (ssus_get_gpio(GPIO_SSUS_39_PAD) << 2);
30 #ifdef GPIO_SSUS_40_PAD
31 	ram_id |= (ssus_get_gpio(GPIO_SSUS_40_PAD) << 3);
32 #endif
33 	printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds);
34 
35 	if (ram_id >= total_spds)
36 		return NULL;
37 
38 	/* Single channel configs */
39 	if (dual_channel_config & (1 << ram_id))
40 		*dual = 1;
41 
42 	return &spd_file_content[SPD_SIZE_MAX_DDR3 * ram_id];
43 }
44 
mainboard_fill_mrc_params(struct mrc_params * mp)45 void mainboard_fill_mrc_params(struct mrc_params *mp)
46 {
47 	void *spd_content;
48 	int dual_channel = 0;
49 	void *spd_file;
50 	size_t spd_fsize;
51 
52 	spd_file = cbfs_map("spd.bin", &spd_fsize);
53 	if (!spd_file)
54 		die("SPD data not found.");
55 
56 	spd_content = get_spd_pointer(spd_file, spd_fsize / SPD_SIZE_MAX_DDR3,
57 	                              &dual_channel);
58 
59 	mp->mainboard.dram_type = DRAM_DDR3L;
60 	mp->mainboard.dram_info_location = DRAM_INFO_SPD_MEM,
61 	mp->mainboard.weaker_odt_settings = 1,
62 
63 	mp->mainboard.dram_data[0] = spd_content;
64 	if (dual_channel)
65 		mp->mainboard.dram_data[1] = spd_content;
66 }
67