1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 #include <console/console.h>
4 #include <delay.h>
5 #include <stddef.h>
6 #include <superio/hwm5_conf.h>
7
8 #include "env_ctrl.h"
9 #include "env_ctrl_chip.h"
10
extemp_force_idle_status(const u16 base)11 static void extemp_force_idle_status(const u16 base)
12 {
13 u8 reg;
14 int retries = 10;
15
16 /* Wait up to 10ms for non-busy state. */
17 while (retries > 0) {
18 reg = pnp_read_hwm5_index(base, ITE_EC_EXTEMP_STATUS);
19
20 if ((reg & ITE_EC_EXTEMP_STATUS_HOST_BUSY) == 0x0)
21 break;
22
23 retries--;
24
25 mdelay(1);
26 }
27
28 if (retries == 0 && (reg & ITE_EC_EXTEMP_STATUS_HOST_BUSY) == 0x1) {
29 /*
30 * SIO is busy due to unfinished peci transaction.
31 * Re-configure Register 0x8E to terminate processes.
32 */
33 pnp_write_hwm5_index(base, ITE_EC_EXTEMP_CONTROL,
34 ITE_EC_EXTEMP_CTRL_AUTO_4HZ | ITE_EC_EXTEMP_CTRL_AUTO_START);
35 }
36 }
37
38 /*
39 * Setup PECI interface
40 */
enable_peci(const u16 base)41 static void enable_peci(const u16 base)
42 {
43 /* Enable PECI interface */
44 pnp_write_hwm5_index(base, ITE_EC_INTERFACE_SELECT,
45 ITE_EC_INTERFACE_SEL_PECI | ITE_EC_INTERFACE_SPEED_TOLERANCE);
46
47 /* Setup External Temperature using PECI GetTemp */
48 pnp_write_hwm5_index(base, ITE_EC_EXTEMP_ADDRESS, PECI_CLIENT_ADDRESS);
49 pnp_write_hwm5_index(base, ITE_EC_EXTEMP_COMMAND, PECI_GETTEMP_COMMAND);
50 pnp_write_hwm5_index(base, ITE_EC_EXTEMP_WRITE_LENGTH, PECI_GETTEMP_WRITE_LENGTH);
51 pnp_write_hwm5_index(base, ITE_EC_EXTEMP_READ_LENGTH, PECI_GETTEMP_READ_LENGTH);
52 pnp_write_hwm5_index(base, ITE_EC_EXTEMP_CONTROL,
53 ITE_EC_EXTEMP_CTRL_AUTO_4HZ | ITE_EC_EXTEMP_CTRL_AUTO_START);
54 }
55
56 /*
57 * Set up External Temperature to read via PECI or thermal diode/resistor
58 * into TMPINx register
59 */
enable_tmpin(const u16 base,const u8 tmpin,const struct ite_ec_thermal_config * const conf)60 static void enable_tmpin(const u16 base, const u8 tmpin,
61 const struct ite_ec_thermal_config *const conf)
62 {
63 u8 reg;
64 u8 reg_extra;
65
66 reg = pnp_read_hwm5_index(base, ITE_EC_ADC_TEMP_CHANNEL_ENABLE);
67 reg_extra = pnp_read_hwm5_index(base, ITE_EC_ADC_TEMP_EXTRA_CHANNEL_ENABLE);
68
69 switch (conf->mode) {
70 case THERMAL_MODE_DISABLED:
71 return;
72 case THERMAL_PECI:
73 /* Some chips can set any TMPIN as the target for PECI readings
74 while others can only read to TMPIN3. In the latter case a
75 different register is used for enabling it. */
76 if (CONFIG(SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN)) {
77 /* IT8721F is an exception, it cannot use TMPIN2 for PECI. */
78 if (CONFIG(SUPERIO_ITE_IT8721F) && tmpin == 2) {
79 printk(BIOS_WARNING,
80 "PECI to TMPIN2 not supported on IT8721F\n");
81 return;
82 }
83 u8 reg_new = (reg & ~ITE_EC_ADC_TEMP_EXT_REPORTS_TO_MASK)
84 | ITE_EC_ADC_TEMP_EXT_REPORTS_TO(tmpin);
85 /* Registers stick on reboot and resume,
86 don't warn for correct reg values */
87 if (reg & ITE_EC_ADC_TEMP_EXT_REPORTS_TO_MASK && reg != reg_new) {
88 printk(BIOS_WARNING,
89 "PECI specified for another TMPIN, overwriting\n");
90 }
91 reg = reg_new;
92 } else if (tmpin == 3) {
93 reg_extra |= ITE_EC_ADC_TEMP_EXTRA_TMPIN3_EXT;
94 pnp_write_hwm5_index(base, ITE_EC_ADC_TEMP_EXTRA_CHANNEL_ENABLE,
95 reg_extra);
96 } else {
97 printk(BIOS_WARNING, "PECI to TMPIN%d not supported on this Super I/O",
98 tmpin);
99 return;
100 }
101 enable_peci(base);
102
103 break;
104 case THERMAL_DIODE:
105 reg |= ITE_EC_ADC_TEMP_DIODE_MODE(tmpin);
106 break;
107 case THERMAL_RESISTOR:
108 reg |= ITE_EC_ADC_TEMP_RESISTOR_MODE(tmpin);
109 break;
110 default:
111 printk(BIOS_WARNING, "Unsupported thermal mode 0x%x on TMPIN%d\n",
112 conf->mode, tmpin);
113 return;
114 }
115
116 pnp_write_hwm5_index(base, ITE_EC_ADC_TEMP_CHANNEL_ENABLE, reg);
117
118 /* Set temperature offsets */
119 if (conf->mode != THERMAL_RESISTOR) {
120 reg = pnp_read_hwm5_index(base, ITE_EC_BEEP_ENABLE);
121 reg |= ITE_EC_TEMP_ADJUST_WRITE_ENABLE;
122 pnp_write_hwm5_index(base, ITE_EC_BEEP_ENABLE, reg);
123 pnp_write_hwm5_index(base, ITE_EC_TEMP_ADJUST[tmpin-1], conf->offset);
124 }
125
126 /* Set temperature limits */
127 u8 max = conf->max;
128 pnp_write_hwm5_index(base, ITE_EC_HIGH_TEMP_LIMIT(tmpin), max ? max : 127);
129 pnp_write_hwm5_index(base, ITE_EC_LOW_TEMP_LIMIT(tmpin), conf->min);
130
131 /* Enable the startup of monitoring operation */
132 reg = pnp_read_hwm5_index(base, ITE_EC_CONFIGURATION);
133 reg |= ITE_EC_CONFIGURATION_START;
134 pnp_write_hwm5_index(base, ITE_EC_CONFIGURATION, reg);
135 }
136
fan_smartconfig(const u16 base,const u8 fan,const enum ite_ec_fan_mode mode,const struct ite_ec_fan_smartconfig * const conf)137 static void fan_smartconfig(const u16 base, const u8 fan,
138 const enum ite_ec_fan_mode mode,
139 const struct ite_ec_fan_smartconfig *const conf)
140 {
141 u8 pwm_ctrl;
142 u8 pwm_start = 0;
143 u8 pwm_auto = 0;
144 u8 delta_temp;
145
146 if (mode == FAN_SMART_SOFTWARE) {
147 pwm_ctrl = ITE_EC_FAN_CTL_PWM_MODE_SOFTWARE;
148
149 /* 50% duty cycle by default */
150 const u8 duty = conf->pwm_start ? conf->pwm_start : 50;
151 if (CONFIG(SUPERIO_ITE_ENV_CTRL_8BIT_PWM))
152 pwm_start = ITE_EC_FAN_CTL_PWM_DUTY(duty);
153 else
154 pwm_ctrl |= ITE_EC_FAN_CTL_PWM_DUTY(duty);
155 } else {
156 pwm_ctrl = ITE_EC_FAN_CTL_PWM_MODE_AUTOMATIC;
157 pwm_ctrl |= ITE_EC_FAN_CTL_TEMPIN(conf->tmpin);
158
159 if (conf->clsd_loop) {
160 pwm_ctrl |= ITE_EC_FAN_PWM_CLSD_LOOP;
161 pwm_start = ITE_EC_FAN_CTL_PWM_START_RPM(conf->rpm_start);
162 pwm_auto = ITE_EC_FAN_CTL_PWM_SLOPE_LOWER(conf->slope);
163 } else {
164 pwm_start = ITE_EC_FAN_CTL_PWM_START_DUTY(conf->pwm_start);
165
166 if (CONFIG(SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG)) {
167 pwm_auto = conf->slope & 0x7f;
168 } else {
169 pwm_start |= ITE_EC_FAN_CTL_PWM_SLOPE_BIT6(conf->slope);
170 pwm_auto = ITE_EC_FAN_CTL_PWM_SLOPE_LOWER(conf->slope);
171 }
172 }
173
174 if (conf->smoothing)
175 pwm_auto |= ITE_EC_FAN_CTL_AUTO_SMOOTHING_EN;
176
177 pnp_write_hwm5_index(base, ITE_EC_FAN_CTL_TEMP_LIMIT_OFF(fan), conf->tmp_off);
178 pnp_write_hwm5_index(base, ITE_EC_FAN_CTL_TEMP_LIMIT_START(fan),
179 conf->tmp_start);
180 /* Full speed above 127°C by default */
181 pnp_write_hwm5_index(base, ITE_EC_FAN_CTL_TEMP_LIMIT_FULL(fan),
182 conf->tmp_full ? conf->tmp_full : 127);
183
184 delta_temp = ITE_EC_FAN_CTL_DELTA_TEMP_INTRVL(conf->tmp_delta);
185 if (!CONFIG(SUPERIO_ITE_ENV_CTRL_NO_FULLSPEED_SETTING))
186 delta_temp |= ITE_EC_FAN_CTL_FULL_AT_THRML_LMT(conf->full_lmt);
187 pnp_write_hwm5_index(base, ITE_EC_FAN_CTL_DELTA_TEMP(fan),
188 delta_temp);
189 }
190
191 pnp_write_hwm5_index(base, ITE_EC_FAN_CTL_PWM_CONTROL(fan), pwm_ctrl);
192 pnp_write_hwm5_index(base, ITE_EC_FAN_CTL_PWM_START(fan), pwm_start);
193 pnp_write_hwm5_index(base, ITE_EC_FAN_CTL_PWM_AUTO(fan), pwm_auto);
194 }
195
enable_fan(const u16 base,const u8 fan,const struct ite_ec_fan_config * const conf)196 static void enable_fan(const u16 base, const u8 fan,
197 const struct ite_ec_fan_config *const conf)
198 {
199 u8 reg;
200
201 if (conf->mode == FAN_IGNORE ||
202 (CONFIG(SUPERIO_ITE_ENV_CTRL_NO_ONOFF) &&
203 conf->mode <= FAN_MODE_OFF))
204 return;
205
206 /* FAN_CTL2 might have its own frequency setting */
207 if (CONFIG(SUPERIO_ITE_ENV_CTRL_PWM_FREQ2) && fan == 2) {
208 reg = pnp_read_hwm5_index(base, ITE_EC_ADC_TEMP_EXTRA_CHANNEL_ENABLE);
209 reg &= ~ITE_EC_FAN_PWM_CLOCK_MASK;
210 reg |= ITE_EC_FAN_PWM_DEFAULT_CLOCK;
211 pnp_write_hwm5_index(base, ITE_EC_ADC_TEMP_EXTRA_CHANNEL_ENABLE, reg);
212 }
213
214 if (conf->mode >= FAN_SMART_SOFTWARE) {
215 fan_smartconfig(base, fan, conf->mode, &conf->smart);
216 } else {
217 reg = pnp_read_hwm5_index(base, ITE_EC_FAN_CTL_MODE);
218 if (conf->mode == FAN_MODE_ON)
219 reg |= ITE_EC_FAN_CTL_ON(fan);
220 else
221 reg &= ~ITE_EC_FAN_CTL_ON(fan);
222 pnp_write_hwm5_index(base, ITE_EC_FAN_CTL_MODE, reg);
223 }
224
225 if (CONFIG(SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG) && conf->mode >= FAN_MODE_ON) {
226 reg = pnp_read_hwm5_index(base, ITE_EC_FAN_TAC_COUNTER_ENABLE);
227 reg |= ITE_EC_FAN_TAC_16BIT_ENABLE(fan);
228 pnp_write_hwm5_index(base, ITE_EC_FAN_TAC_COUNTER_ENABLE, reg);
229 }
230
231 if (CONFIG(SUPERIO_ITE_ENV_CTRL_5FANS) && fan > 3) {
232 reg = pnp_read_hwm5_index(base, ITE_EC_FAN_SEC_CTL);
233 if (conf->mode >= FAN_MODE_ON)
234 reg |= ITE_EC_FAN_SEC_CTL_TAC_EN(fan);
235 else
236 reg &= ~ITE_EC_FAN_SEC_CTL_TAC_EN(fan);
237 pnp_write_hwm5_index(base, ITE_EC_FAN_SEC_CTL, reg);
238 } else {
239 reg = pnp_read_hwm5_index(base, ITE_EC_FAN_MAIN_CTL);
240 if (conf->mode >= FAN_MODE_ON)
241 reg |= ITE_EC_FAN_MAIN_CTL_TAC_EN(fan);
242 else
243 reg &= ~ITE_EC_FAN_MAIN_CTL_TAC_EN(fan);
244
245 /* Some ITEs have SmartGuardian always enabled */
246 if (!CONFIG(SUPERIO_ITE_ENV_CTRL_NO_ONOFF)) {
247 if (conf->mode >= FAN_SMART_SOFTWARE)
248 reg |= ITE_EC_FAN_MAIN_CTL_SMART(fan);
249 else
250 reg &= ~ITE_EC_FAN_MAIN_CTL_SMART(fan);
251 }
252 pnp_write_hwm5_index(base, ITE_EC_FAN_MAIN_CTL, reg);
253 }
254 }
255
enable_fan_vector(const u16 base,const u8 fan_vector,const struct ite_ec_fan_vector_config * const conf)256 static void enable_fan_vector(const u16 base, const u8 fan_vector,
257 const struct ite_ec_fan_vector_config *const conf)
258 {
259 u8 reg;
260
261 u8 start = conf->tmp_start;
262 if (!start) {
263 /* When tmp_start is not configured we would set the
264 * register to it's default of 0xFF here, which would
265 * effectively disable the vector functionality of the
266 * SuperIO altogether since that temperature will never
267 * be reached. We can therefore return here and don't
268 * need to set any other registers.
269 */
270 return;
271 }
272 pnp_write_hwm5_index(base, ITE_EC_FAN_VEC_CTL_LIMIT_START(fan_vector), start);
273
274 const s8 slope = conf->slope;
275 const bool slope_neg = slope < 0;
276 if (slope <= -128)
277 reg = 127;
278 else if (slope_neg)
279 reg = -slope;
280 else
281 reg = slope;
282 reg |= ITE_EC_FAN_VEC_CTL_SLOPE_TMPIN0(conf->tmpin);
283 pnp_write_hwm5_index(base, ITE_EC_FAN_VEC_CTL_SLOPE(fan_vector), reg);
284
285 reg = ITE_EC_FAN_VEC_CTL_DELTA_TEMP_INTRVL(conf->tmp_delta);
286 reg |= ITE_EC_FAN_VEC_CTL_DELTA_FANOUT(conf->fanout);
287 reg |= ITE_EC_FAN_VEC_CTL_DELTA_TMPIN1(conf->tmpin);
288 pnp_write_hwm5_index(base, ITE_EC_FAN_VEC_CTL_DELTA(fan_vector), reg);
289
290 if (CONFIG(SUPERIO_ITE_ENV_CTRL_FAN_VECTOR_RANGED)) {
291 reg = conf->tmp_range & 0x7f;
292 reg |= ITE_EC_FAN_VEC_CTL_RANGE_SLOPESIGN(slope_neg);
293 pnp_write_hwm5_index(base, ITE_EC_FAN_VEC_CTL_RANGE(fan_vector), reg);
294 } else if (slope_neg) {
295 printk(BIOS_WARNING, "Unsupported negative slope on fan vector control\n");
296 }
297 }
298
enable_beeps(const u16 base,const struct ite_ec_config * const conf)299 static void enable_beeps(const u16 base, const struct ite_ec_config *const conf)
300 {
301 u8 reg = 0;
302 u8 freq = ITE_EC_BEEP_TONE_DIVISOR(10) | ITE_EC_BEEP_FREQ_DIVISOR(10);
303
304 if (conf->tmpin_beep) {
305 reg |= ITE_EC_BEEP_ON_TMP_LIMIT;
306 pnp_write_hwm5_index(base, ITE_EC_BEEP_FREQ_DIV_OF_TMPIN, freq);
307 }
308 if (conf->fan_beep) {
309 reg |= ITE_EC_BEEP_ON_FAN_LIMIT;
310 pnp_write_hwm5_index(base, ITE_EC_BEEP_FREQ_DIV_OF_FAN, freq);
311 }
312 if (conf->vin_beep) {
313 reg |= ITE_EC_BEEP_ON_VIN_LIMIT;
314 pnp_write_hwm5_index(base, ITE_EC_BEEP_FREQ_DIV_OF_VIN, freq);
315 }
316
317 if (reg) {
318 reg |= pnp_read_hwm5_index(base, ITE_EC_BEEP_ENABLE);
319 pnp_write_hwm5_index(base, ITE_EC_BEEP_ENABLE, reg);
320 }
321 }
322
ite_ec_init(const u16 base,const struct ite_ec_config * const conf)323 void ite_ec_init(const u16 base, const struct ite_ec_config *const conf)
324 {
325 size_t i;
326
327 /* Configure 23.43kHz PWM active high output */
328 u8 fan_ctl = pnp_read_hwm5_index(base, ITE_EC_FAN_CTL_MODE);
329 fan_ctl &= ~ITE_EC_FAN_PWM_CLOCK_MASK;
330 fan_ctl |= ITE_EC_FAN_PWM_DEFAULT_CLOCK;
331 fan_ctl |= ITE_EC_FAN_CTL_POLARITY_HIGH;
332 pnp_write_hwm5_index(base, ITE_EC_FAN_CTL_MODE, fan_ctl);
333
334 /* Enable HWM if configured */
335 for (i = 0; i < ITE_EC_TMPIN_CNT; ++i)
336 enable_tmpin(base, i + 1, &conf->tmpin[i]);
337
338 /* Enable External Sensor SMBus Host if configured */
339 if (conf->smbus_en) {
340 pnp_write_hwm5_index(base, ITE_EC_INTERFACE_SELECT,
341 pnp_read_hwm5_index(base, ITE_EC_INTERFACE_SELECT) |
342 ITE_EC_INTERFACE_SMB_ENABLE);
343 }
344
345 /* Set SST/PECI Host Controller Clock to either 24 MHz or internal 32 MHz */
346 if (conf->smbus_24mhz) {
347 pnp_write_hwm5_index(base, ITE_EC_INTERFACE_SELECT,
348 pnp_read_hwm5_index(base, ITE_EC_INTERFACE_SELECT) |
349 ITE_EC_INTERFACE_CLOCK_24MHZ);
350 }
351
352 /* Enable reading of voltage pins */
353 pnp_write_hwm5_index(base, ITE_EC_ADC_VOLTAGE_CHANNEL_ENABLE, conf->vin_mask);
354
355 /* Enable FANx if configured */
356 for (i = 0; i < ITE_EC_FAN_CNT; ++i)
357 enable_fan(base, i + 1, &conf->fan[i]);
358
359 if (CONFIG(SUPERIO_ITE_ENV_CTRL_FAN_VECTOR)) {
360 /* Enable Special FAN Vector X if configured */
361 for (i = 0; i < ITE_EC_FAN_VECTOR_CNT; ++i)
362 enable_fan_vector(base, i, &conf->fan_vector[i]);
363 }
364
365 /* Enable beeps if configured */
366 enable_beeps(base, conf);
367
368 /*
369 * System may get wrong temperature data when SIO is in
370 * busy state. Therefore, check the status and terminate
371 * processes if needed.
372 */
373 for (i = 0; i < ITE_EC_TMPIN_CNT; ++i)
374 if (conf->tmpin[i].mode == THERMAL_PECI)
375 extemp_force_idle_status(base);
376 }
377