1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 #include <arch/romstage.h>
4 #include <device/pci_ops.h>
5 #include <arch/symbols.h>
6 #include <assert.h>
7 #include <cf9_reset.h>
8 #include <console/console.h>
9 #include <device/device.h>
10 #include <delay.h>
11 #include <device/pci_def.h>
12 #include <fsp/api.h>
13 #include <fsp/util.h>
14 #include <intelblocks/cpulib.h>
15 #include <intelblocks/cse.h>
16 #include <intelblocks/lpc_lib.h>
17 #include <intelblocks/msr.h>
18 #include <intelblocks/pmclib.h>
19 #include <intelblocks/systemagent.h>
20 #include <mrc_cache.h>
21 #include <soc/cpu.h>
22 #include <soc/iomap.h>
23 #include <soc/meminit.h>
24 #include <soc/pci_devs.h>
25 #include <soc/pm.h>
26 #include <soc/romstage.h>
27 #include <soc/systemagent.h>
28 #include <spi_flash.h>
29 #include <timer.h>
30 #include "chip.h"
31
32 static const uint8_t hob_variable_guid[16] = {
33 0x7d, 0x14, 0x34, 0xa0, 0x0c, 0x69, 0x54, 0x41,
34 0x8d, 0xe6, 0xc0, 0x44, 0x64, 0x1d, 0xe9, 0x42,
35 };
36
37 static uint32_t fsp_version;
38
39 /* High Performance Event Timer Configuration */
40 #define P2SB_HPTC 0x60
41 #define P2SB_HPTC_ADDRESS_ENABLE (1 << 7)
42 /*
43 * ADDRESS_SELECT ENCODING_RANGE
44 * 0 0xFED0 0000 - 0xFED0 03FF
45 * 1 0xFED0 1000 - 0xFED0 13FF
46 * 2 0xFED0 2000 - 0xFED0 23FF
47 * 3 0xFED0 3000 - 0xFED0 33FF
48 */
49 #define P2SB_HPTC_ADDRESS_SELECT_0 (0 << 0)
50 #define P2SB_HPTC_ADDRESS_SELECT_1 (1 << 0)
51 #define P2SB_HPTC_ADDRESS_SELECT_2 (2 << 0)
52 #define P2SB_HPTC_ADDRESS_SELECT_3 (3 << 0)
53
54 /*
55 * Enables several BARs and devices which are needed for memory init
56 * - MCH_BASE_ADDR is needed in order to talk to the memory controller
57 * - HPET is enabled because FSP wants to store a pointer to global data in the
58 * HPET comparator register
59 */
soc_early_romstage_init(void)60 static void soc_early_romstage_init(void)
61 {
62 static const struct sa_mmio_descriptor soc_fixed_pci_resources[] = {
63 { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
64 };
65
66 /* Set Fixed MMIO address into PCI configuration space */
67 sa_set_pci_bar(soc_fixed_pci_resources,
68 ARRAY_SIZE(soc_fixed_pci_resources));
69
70 /* Enable decoding for HPET. Needed for FSP global pointer storage */
71 pci_write_config8(PCH_DEV_P2SB, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 |
72 P2SB_HPTC_ADDRESS_ENABLE);
73 }
74
75 /*
76 * Punit Initialization code. This all isn't documented, but
77 * this is the recipe.
78 */
punit_init(void)79 static bool punit_init(void)
80 {
81 uint32_t reg;
82 uint32_t data;
83 struct stopwatch sw;
84
85 /* Thermal throttle activation offset */
86 configure_tcc_thermal_target();
87
88 /*
89 * Software Core Disable Mask (P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR).
90 * Enable all cores here.
91 */
92 MCHBAR32(CORE_DISABLE_MASK) = 0x0;
93
94 /* P-Unit bring up */
95 reg = MCHBAR32(BIOS_RESET_CPL);
96 if (reg == 0xffffffff) {
97 /* P-unit not found */
98 printk(BIOS_DEBUG, "Punit MMIO not available\n");
99 return false;
100 }
101 /* Set Punit interrupt pin IPIN offset 3D */
102 pci_write_config8(SA_DEV_PUNIT, PCI_INTERRUPT_PIN, 0x2);
103
104 /* Set PUINT IRQ to 24 and INTPIN LOCK */
105 MCHBAR32(PUNIT_THERMAL_DEVICE_IRQ) =
106 PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER |
107 PUINT_THERMAL_DEVICE_IRQ_LOCK;
108
109 if (!CONFIG(SOC_INTEL_GEMINILAKE)) {
110 data = MCHBAR32(0x7818);
111 data &= 0xFFFFE01F;
112 data |= 0x20 | 0x200;
113 MCHBAR32(0x7818) = data;
114 }
115
116 /* Stage0 BIOS Reset Complete (RST_CPL) */
117 enable_bios_reset_cpl();
118
119 /*
120 * Poll for bit 8 to check if PCODE has completed its action
121 * in response to BIOS Reset complete.
122 * We wait here till 1 ms for the bit to get set.
123 */
124 stopwatch_init_msecs_expire(&sw, 1);
125 while (!(MCHBAR32(BIOS_RESET_CPL) & PCODE_INIT_DONE)) {
126 if (stopwatch_expired(&sw)) {
127 printk(BIOS_DEBUG, "PCODE Init Done Failure\n");
128 return false;
129 }
130 udelay(100);
131 }
132
133 return true;
134 }
135
set_max_freq(void)136 void set_max_freq(void)
137 {
138 if (cpu_get_burst_mode_state() == BURST_MODE_UNAVAILABLE) {
139 /* Burst Mode has been factory configured as disabled
140 * and is not available in this physical processor
141 * package.
142 */
143 printk(BIOS_DEBUG, "Burst Mode is factory disabled\n");
144 return;
145 }
146
147 /* Enable burst mode */
148 cpu_burst_mode(true);
149
150 /* Enable speed step. */
151 cpu_set_eist(true);
152
153 /* Set P-State ratio */
154 cpu_set_p_state_to_turbo_ratio();
155 }
156
mainboard_romstage_entry(void)157 void mainboard_romstage_entry(void)
158 {
159 bool s3wake;
160 size_t var_size;
161 struct chipset_power_state *ps = pmc_get_power_state();
162 const void *new_var_data;
163
164 soc_early_romstage_init();
165 report_platform_info();
166
167 /* Initialize Heci interfaces */
168 heci_init();
169
170 s3wake = pmc_fill_power_state(ps) == ACPI_S3;
171 fsp_memory_init(s3wake);
172
173 if (punit_init())
174 set_max_freq();
175 else
176 printk(BIOS_DEBUG, "Punit failed to initialize properly\n");
177
178 /* Stash variable MRC data and let cache system update it later */
179 new_var_data = fsp_find_extension_hob_by_guid(hob_variable_guid,
180 &var_size);
181 if (new_var_data)
182 mrc_cache_stash_data(MRC_VARIABLE_DATA,
183 fsp_version, new_var_data,
184 var_size);
185 else
186 printk(BIOS_ERR, "Failed to determine variable data\n");
187
188 mainboard_save_dimm_info();
189 }
190
fill_console_params(FSPM_UPD * mupd)191 static void fill_console_params(FSPM_UPD *mupd)
192 {
193 if (CONFIG(CONSOLE_SERIAL)) {
194 if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) {
195 mupd->FspmConfig.SerialDebugPortDevice =
196 CONFIG_UART_FOR_CONSOLE;
197 /* use MMIO port type */
198 mupd->FspmConfig.SerialDebugPortType = 2;
199 /* use 4 byte register stride */
200 mupd->FspmConfig.SerialDebugPortStrideSize = 2;
201 /* used only for port type set to external */
202 mupd->FspmConfig.SerialDebugPortAddress = 0;
203 } else if (CONFIG(DRIVERS_UART_8250IO)) {
204 /* use external UART for debug */
205 mupd->FspmConfig.SerialDebugPortDevice = 3;
206 /* use I/O port type */
207 mupd->FspmConfig.SerialDebugPortType = 1;
208 /* use 1 byte register stride */
209 mupd->FspmConfig.SerialDebugPortStrideSize = 0;
210 /* used only for port type set to external */
211 mupd->FspmConfig.SerialDebugPortAddress =
212 CONFIG_TTYS0_BASE;
213 }
214 } else {
215 mupd->FspmConfig.SerialDebugPortType = 0;
216 }
217 }
218
check_full_retrain(const FSPM_UPD * mupd)219 static void check_full_retrain(const FSPM_UPD *mupd)
220 {
221 struct chipset_power_state *ps;
222
223 if (mupd->FspmArchUpd.BootMode != FSP_BOOT_WITH_FULL_CONFIGURATION)
224 return;
225
226 ps = pmc_get_power_state();
227
228 if (ps->gen_pmcon1 & WARM_RESET_STS) {
229 printk(BIOS_INFO, "Full retrain unsupported on warm reboot.\n");
230 full_reset();
231 }
232 }
233
soc_gpu_init_params(FSPM_UPD * mupd)234 static void soc_gpu_init_params(FSPM_UPD *mupd)
235 {
236 enum {
237 GPU_PRIMARY_IGD = 0,
238 GPU_PRIMARY_PCI = 1,
239 };
240 /* Select primary GPU device */
241 if (CONFIG(ONBOARD_VGA_IS_PRIMARY) && is_devfn_enabled(SA_DEVFN_IGD))
242 mupd->FspmConfig.PrimaryVideoAdaptor = GPU_PRIMARY_IGD;
243 else
244 mupd->FspmConfig.PrimaryVideoAdaptor = GPU_PRIMARY_PCI;
245 }
246
soc_memory_init_params(FSPM_UPD * mupd)247 static void soc_memory_init_params(FSPM_UPD *mupd)
248 {
249 #if CONFIG(SOC_INTEL_GEMINILAKE)
250 /* Only for GLK */
251 FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
252
253 m_cfg->PrmrrSize = get_valid_prmrr_size();
254
255 /*
256 * CpuMemoryTest in FSP tests 0 to 1M of the RAM after MRC init.
257 * With PAGING_IN_CACHE_AS_RAM enabled for GLK, there was no page
258 * table entry for this range which caused a page fault. Since this
259 * test is anyway not exhaustive, skipping the memory test in FSP.
260 */
261 m_cfg->SkipMemoryTestUpd = 1;
262
263 /*
264 * PCIe power sequence can be done from within FSP when provided
265 * with the GPIOs used for PERST to FSP. Since this is done in
266 * coreboot, skipping the PCIe power sequence done by FSP.
267 */
268 m_cfg->SkipPciePowerSequence = 1;
269 #endif
270 }
271
parse_devicetree_setting(FSPM_UPD * m_upd)272 static void parse_devicetree_setting(FSPM_UPD *m_upd)
273 {
274 #if CONFIG(SOC_INTEL_GEMINILAKE)
275 m_upd->FspmConfig.TraceHubEn = is_devfn_enabled(PCH_DEVFN_NPK);
276 #else
277 m_upd->FspmConfig.NpkEn = is_devfn_enabled(PCH_DEVFN_NPK);
278 #endif
279 }
280
platform_fsp_memory_init_params_cb(FSPM_UPD * mupd,uint32_t version)281 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
282 {
283 check_full_retrain(mupd);
284
285 fill_console_params(mupd);
286 soc_gpu_init_params(mupd);
287
288 if (CONFIG(SOC_INTEL_GEMINILAKE))
289 soc_memory_init_params(mupd);
290
291 mainboard_memory_init_params(mupd);
292
293 parse_devicetree_setting(mupd);
294
295 /* Do NOT let FSP do any GPIO pad configuration */
296 mupd->FspmConfig.PreMemGpioTablePtr = (uintptr_t)NULL;
297
298 mupd->FspmConfig.SkipCseRbp = CONFIG(SKIP_CSE_RBP);
299
300 /*
301 * Converged Security Engine (CSE) has secure storage functionality.
302 * HECI2 device can be used to access that functionality. However, part
303 * of S3 resume flow involves resetting HECI2 which takes 136ms. Since
304 * coreboot does not use secure storage functionality, instruct FSP to
305 * skip HECI2 reset.
306 */
307 mupd->FspmConfig.EnableS3Heci2 = 0;
308
309 /*
310 * Apollolake splits MRC cache into two parts: constant and variable.
311 * The constant part is not expected to change often and variable is.
312 * Currently variable part consists of parameters that change on cold
313 * boots such as scrambler seed and some memory controller registers.
314 * Scrambler seed is vital for S3 resume case because attempt to use
315 * wrong/missing key renders DRAM contents useless.
316 */
317
318 mupd->FspmConfig.VariableNvsBufferPtr =
319 mrc_cache_current_mmap_leak(MRC_VARIABLE_DATA, version,
320 NULL);
321
322 assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
323
324 fsp_version = version;
325 }
326
327 __weak
mainboard_memory_init_params(FSPM_UPD * mupd)328 void mainboard_memory_init_params(FSPM_UPD *mupd)
329 {
330 printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
331 }
332
333 __weak
mainboard_save_dimm_info(void)334 void mainboard_save_dimm_info(void)
335 {
336 printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
337 }
338