1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 2 /* 3 * Wave5 series multi-standard codec IP - helper definitions 4 * 5 * Copyright (C) 2021-2023 CHIPS&MEDIA INC 6 */ 7 8 #ifndef VPUAPI_H_INCLUDED 9 #define VPUAPI_H_INCLUDED 10 11 #include <linux/idr.h> 12 #include <linux/genalloc.h> 13 #include <media/v4l2-device.h> 14 #include <media/v4l2-mem2mem.h> 15 #include <media/v4l2-ctrls.h> 16 #include "wave5-vpuerror.h" 17 #include "wave5-vpuconfig.h" 18 #include "wave5-vdi.h" 19 20 enum product_id { 21 PRODUCT_ID_515, 22 PRODUCT_ID_521, 23 PRODUCT_ID_511, 24 PRODUCT_ID_517, 25 PRODUCT_ID_NONE, 26 }; 27 28 struct vpu_attr; 29 30 enum vpu_instance_type { 31 VPU_INST_TYPE_DEC = 0, 32 VPU_INST_TYPE_ENC = 1 33 }; 34 35 enum vpu_instance_state { 36 VPU_INST_STATE_NONE = 0, 37 VPU_INST_STATE_OPEN = 1, 38 VPU_INST_STATE_INIT_SEQ = 2, 39 VPU_INST_STATE_PIC_RUN = 3, 40 VPU_INST_STATE_STOP = 4 41 }; 42 43 /* Maximum available on hardware. */ 44 #define WAVE5_MAX_FBS 32 45 46 #define MAX_REG_FRAME (WAVE5_MAX_FBS * 2) 47 48 #define WAVE5_DEC_HEVC_BUF_SIZE(_w, _h) (DIV_ROUND_UP(_w, 64) * DIV_ROUND_UP(_h, 64) * 256 + 64) 49 #define WAVE5_DEC_AVC_BUF_SIZE(_w, _h) ((((ALIGN(_w, 256) / 16) * (ALIGN(_h, 16) / 16)) + 16) * 80) 50 51 #define WAVE5_FBC_LUMA_TABLE_SIZE(_w, _h) (ALIGN(_h, 64) * ALIGN(_w, 256) / 32) 52 #define WAVE5_FBC_CHROMA_TABLE_SIZE(_w, _h) (ALIGN((_h), 64) * ALIGN((_w) / 2, 256) / 32) 53 #define WAVE5_ENC_AVC_BUF_SIZE(_w, _h) (ALIGN(_w, 64) * ALIGN(_h, 64) / 32) 54 #define WAVE5_ENC_HEVC_BUF_SIZE(_w, _h) (ALIGN(_w, 64) / 64 * ALIGN(_h, 64) / 64 * 128) 55 56 /* 57 * common struct and definition 58 */ 59 enum cod_std { 60 STD_AVC = 0, 61 STD_HEVC = 12, 62 STD_MAX 63 }; 64 65 enum wave_std { 66 W_HEVC_DEC = 0x00, 67 W_HEVC_ENC = 0x01, 68 W_AVC_DEC = 0x02, 69 W_AVC_ENC = 0x03, 70 STD_UNKNOWN = 0xFF 71 }; 72 73 enum set_param_option { 74 OPT_COMMON = 0, /* SET_PARAM command option for encoding sequence */ 75 OPT_CUSTOM_GOP = 1, /* SET_PARAM command option for setting custom GOP */ 76 OPT_CUSTOM_HEADER = 2, /* SET_PARAM command option for setting custom VPS/SPS/PPS */ 77 OPT_VUI = 3, /* SET_PARAM command option for encoding VUI */ 78 OPT_CHANGE_PARAM = 0x10, 79 }; 80 81 /************************************************************************/ 82 /* PROFILE & LEVEL */ 83 /************************************************************************/ 84 /* HEVC */ 85 #define HEVC_PROFILE_MAIN 1 86 #define HEVC_PROFILE_MAIN10 2 87 #define HEVC_PROFILE_STILLPICTURE 3 88 #define HEVC_PROFILE_MAIN10_STILLPICTURE 2 89 90 /* H.264 profile for encoder*/ 91 #define H264_PROFILE_BP 1 92 #define H264_PROFILE_MP 2 93 #define H264_PROFILE_EXTENDED 3 94 #define H264_PROFILE_HP 4 95 #define H264_PROFILE_HIGH10 5 96 #define H264_PROFILE_HIGH422 6 97 #define H264_PROFILE_HIGH444 7 98 99 /************************************************************************/ 100 /* error codes */ 101 /************************************************************************/ 102 103 /************************************************************************/ 104 /* utility macros */ 105 /************************************************************************/ 106 107 /* Initialize sequence firmware command mode */ 108 #define INIT_SEQ_NORMAL 1 109 110 /* Decode firmware command mode */ 111 #define DEC_PIC_NORMAL 0 112 113 /* bit_alloc_mode */ 114 #define BIT_ALLOC_MODE_FIXED_RATIO 2 115 116 /* bit_rate */ 117 #define MAX_BIT_RATE 700000000 118 119 /* decoding_refresh_type */ 120 #define DEC_REFRESH_TYPE_NON_IRAP 0 121 #define DEC_REFRESH_TYPE_CRA 1 122 #define DEC_REFRESH_TYPE_IDR 2 123 124 /* depend_slice_mode */ 125 #define DEPEND_SLICE_MODE_RECOMMENDED 1 126 #define DEPEND_SLICE_MODE_BOOST 2 127 #define DEPEND_SLICE_MODE_FAST 3 128 129 /* hvs_max_delta_qp */ 130 #define MAX_HVS_MAX_DELTA_QP 51 131 132 /* intra_refresh_mode */ 133 #define REFRESH_MODE_CTU_ROWS 1 134 #define REFRESH_MODE_CTU_COLUMNS 2 135 #define REFRESH_MODE_CTU_STEP_SIZE 3 136 #define REFRESH_MODE_CTUS 4 137 138 /* intra_mb_refresh_mode */ 139 #define REFRESH_MB_MODE_NONE 0 140 #define REFRESH_MB_MODE_CTU_ROWS 1 141 #define REFRESH_MB_MODE_CTU_COLUMNS 2 142 #define REFRESH_MB_MODE_CTU_STEP_SIZE 3 143 144 /* intra_qp */ 145 #define MAX_INTRA_QP 63 146 147 /* nr_inter_weight_* */ 148 #define MAX_INTER_WEIGHT 31 149 150 /* nr_intra_weight_* */ 151 #define MAX_INTRA_WEIGHT 31 152 153 /* nr_noise_sigma_* */ 154 #define MAX_NOISE_SIGMA 255 155 156 /* bitstream_buffer_size */ 157 #define MIN_BITSTREAM_BUFFER_SIZE 1024 158 #define MIN_BITSTREAM_BUFFER_SIZE_WAVE521 (1024 * 64) 159 160 /* vbv_buffer_size */ 161 #define MIN_VBV_BUFFER_SIZE 10 162 #define MAX_VBV_BUFFER_SIZE 3000 163 164 #define BUFFER_MARGIN 4096 165 166 #define MAX_FIRMWARE_CALL_RETRY 10 167 168 #define VDI_LITTLE_ENDIAN 0x0 169 170 /* 171 * Parameters of DEC_SET_SEQ_CHANGE_MASK 172 */ 173 #define SEQ_CHANGE_ENABLE_PROFILE BIT(5) 174 #define SEQ_CHANGE_ENABLE_SIZE BIT(16) 175 #define SEQ_CHANGE_ENABLE_BITDEPTH BIT(18) 176 #define SEQ_CHANGE_ENABLE_DPB_COUNT BIT(19) 177 #define SEQ_CHANGE_ENABLE_ASPECT_RATIO BIT(21) 178 #define SEQ_CHANGE_ENABLE_VIDEO_SIGNAL BIT(23) 179 #define SEQ_CHANGE_ENABLE_VUI_TIMING_INFO BIT(29) 180 181 #define SEQ_CHANGE_ENABLE_ALL_HEVC (SEQ_CHANGE_ENABLE_PROFILE | \ 182 SEQ_CHANGE_ENABLE_SIZE | \ 183 SEQ_CHANGE_ENABLE_BITDEPTH | \ 184 SEQ_CHANGE_ENABLE_DPB_COUNT) 185 186 #define SEQ_CHANGE_ENABLE_ALL_AVC (SEQ_CHANGE_ENABLE_SIZE | \ 187 SEQ_CHANGE_ENABLE_BITDEPTH | \ 188 SEQ_CHANGE_ENABLE_DPB_COUNT | \ 189 SEQ_CHANGE_ENABLE_ASPECT_RATIO | \ 190 SEQ_CHANGE_ENABLE_VIDEO_SIGNAL | \ 191 SEQ_CHANGE_ENABLE_VUI_TIMING_INFO) 192 193 #define DISPLAY_IDX_FLAG_SEQ_END -1 194 #define DISPLAY_IDX_FLAG_NO_FB -3 195 #define DECODED_IDX_FLAG_NO_FB -1 196 #define DECODED_IDX_FLAG_SKIP -2 197 198 #define RECON_IDX_FLAG_ENC_END -1 199 #define RECON_IDX_FLAG_ENC_DELAY -2 200 #define RECON_IDX_FLAG_HEADER_ONLY -3 201 #define RECON_IDX_FLAG_CHANGE_PARAM -4 202 203 enum codec_command { 204 ENABLE_ROTATION, 205 ENABLE_MIRRORING, 206 SET_MIRROR_DIRECTION, 207 SET_ROTATION_ANGLE, 208 DEC_GET_QUEUE_STATUS, 209 ENC_GET_QUEUE_STATUS, 210 DEC_RESET_FRAMEBUF_INFO, 211 DEC_GET_SEQ_INFO, 212 }; 213 214 enum mirror_direction { 215 MIRDIR_NONE, /* no mirroring */ 216 MIRDIR_VER, /* vertical mirroring */ 217 MIRDIR_HOR, /* horizontal mirroring */ 218 MIRDIR_HOR_VER /* horizontal and vertical mirroring */ 219 }; 220 221 enum frame_buffer_format { 222 FORMAT_ERR = -1, 223 FORMAT_420 = 0, /* 8bit */ 224 FORMAT_422, /* 8bit */ 225 FORMAT_224, /* 8bit */ 226 FORMAT_444, /* 8bit */ 227 FORMAT_400, /* 8bit */ 228 229 /* little endian perspective */ 230 /* | addr 0 | addr 1 | */ 231 FORMAT_420_P10_16BIT_MSB = 5, /* lsb |000000xx|xxxxxxxx | msb */ 232 FORMAT_420_P10_16BIT_LSB, /* lsb |xxxxxxx |xx000000 | msb */ 233 FORMAT_420_P10_32BIT_MSB, /* lsb |00xxxxxxxxxxxxxxxxxxxxxxxxxxx| msb */ 234 FORMAT_420_P10_32BIT_LSB, /* lsb |xxxxxxxxxxxxxxxxxxxxxxxxxxx00| msb */ 235 236 /* 4:2:2 packed format */ 237 /* little endian perspective */ 238 /* | addr 0 | addr 1 | */ 239 FORMAT_422_P10_16BIT_MSB, /* lsb |000000xx |xxxxxxxx | msb */ 240 FORMAT_422_P10_16BIT_LSB, /* lsb |xxxxxxxx |xx000000 | msb */ 241 FORMAT_422_P10_32BIT_MSB, /* lsb |00xxxxxxxxxxxxxxxxxxxxxxxxxxx| msb */ 242 FORMAT_422_P10_32BIT_LSB, /* lsb |xxxxxxxxxxxxxxxxxxxxxxxxxxx00| msb */ 243 244 FORMAT_YUYV, /* 8bit packed format : Y0U0Y1V0 Y2U1Y3V1 ... */ 245 FORMAT_YUYV_P10_16BIT_MSB, 246 FORMAT_YUYV_P10_16BIT_LSB, 247 FORMAT_YUYV_P10_32BIT_MSB, 248 FORMAT_YUYV_P10_32BIT_LSB, 249 250 FORMAT_YVYU, /* 8bit packed format : Y0V0Y1U0 Y2V1Y3U1 ... */ 251 FORMAT_YVYU_P10_16BIT_MSB, 252 FORMAT_YVYU_P10_16BIT_LSB, 253 FORMAT_YVYU_P10_32BIT_MSB, 254 FORMAT_YVYU_P10_32BIT_LSB, 255 256 FORMAT_UYVY, /* 8bit packed format : U0Y0V0Y1 U1Y2V1Y3 ... */ 257 FORMAT_UYVY_P10_16BIT_MSB, 258 FORMAT_UYVY_P10_16BIT_LSB, 259 FORMAT_UYVY_P10_32BIT_MSB, 260 FORMAT_UYVY_P10_32BIT_LSB, 261 262 FORMAT_VYUY, /* 8bit packed format : V0Y0U0Y1 V1Y2U1Y3 ... */ 263 FORMAT_VYUY_P10_16BIT_MSB, 264 FORMAT_VYUY_P10_16BIT_LSB, 265 FORMAT_VYUY_P10_32BIT_MSB, 266 FORMAT_VYUY_P10_32BIT_LSB, 267 268 FORMAT_MAX, 269 }; 270 271 enum packed_format_num { 272 NOT_PACKED = 0, 273 PACKED_YUYV, 274 PACKED_YVYU, 275 PACKED_UYVY, 276 PACKED_VYUY, 277 }; 278 279 enum wave5_interrupt_bit { 280 INT_WAVE5_INIT_VPU = 0, 281 INT_WAVE5_WAKEUP_VPU = 1, 282 INT_WAVE5_SLEEP_VPU = 2, 283 INT_WAVE5_CREATE_INSTANCE = 3, 284 INT_WAVE5_FLUSH_INSTANCE = 4, 285 INT_WAVE5_DESTROY_INSTANCE = 5, 286 INT_WAVE5_INIT_SEQ = 6, 287 INT_WAVE5_SET_FRAMEBUF = 7, 288 INT_WAVE5_DEC_PIC = 8, 289 INT_WAVE5_ENC_PIC = 8, 290 INT_WAVE5_ENC_SET_PARAM = 9, 291 INT_WAVE5_DEC_QUERY = 14, 292 INT_WAVE5_BSBUF_EMPTY = 15, 293 INT_WAVE5_BSBUF_FULL = 15, 294 }; 295 296 enum pic_type { 297 PIC_TYPE_I = 0, 298 PIC_TYPE_P = 1, 299 PIC_TYPE_B = 2, 300 PIC_TYPE_IDR = 5, /* H.264/H.265 IDR (Instantaneous Decoder Refresh) picture */ 301 PIC_TYPE_MAX /* no meaning */ 302 }; 303 304 enum sw_reset_mode { 305 SW_RESET_SAFETY, 306 SW_RESET_FORCE, 307 SW_RESET_ON_BOOT 308 }; 309 310 enum tiled_map_type { 311 LINEAR_FRAME_MAP = 0, /* linear frame map type */ 312 COMPRESSED_FRAME_MAP = 17, /* compressed frame map type*/ 313 }; 314 315 enum temporal_id_mode { 316 TEMPORAL_ID_MODE_ABSOLUTE, 317 TEMPORAL_ID_MODE_RELATIVE, 318 }; 319 320 struct vpu_attr { 321 u32 product_id; 322 char product_name[8]; /* product name in ascii code */ 323 u32 product_version; 324 u32 fw_version; 325 u32 customer_id; 326 u32 support_decoders; /* bitmask */ 327 u32 support_encoders; /* bitmask */ 328 u32 support_backbone: 1; 329 u32 support_avc10bit_enc: 1; 330 u32 support_hevc10bit_enc: 1; 331 u32 support_hevc10bit_dec: 1; 332 u32 support_vcore_backbone: 1; 333 u32 support_vcpu_backbone: 1; 334 }; 335 336 struct frame_buffer { 337 dma_addr_t buf_y; 338 dma_addr_t buf_cb; 339 dma_addr_t buf_cr; 340 unsigned int buf_y_size; 341 unsigned int buf_cb_size; 342 unsigned int buf_cr_size; 343 enum tiled_map_type map_type; 344 unsigned int stride; /* horizontal stride for the given frame buffer */ 345 unsigned int width; /* width of the given frame buffer */ 346 unsigned int height; /* height of the given frame buffer */ 347 size_t size; /* size of the given frame buffer */ 348 unsigned int sequence_no; 349 bool update_fb_info; 350 }; 351 352 struct vpu_rect { 353 unsigned int left; /* horizontal pixel offset from left edge */ 354 unsigned int top; /* vertical pixel offset from top edge */ 355 unsigned int right; /* horizontal pixel offset from right edge */ 356 unsigned int bottom; /* vertical pixel offset from bottom edge */ 357 }; 358 359 /* 360 * decode struct and definition 361 */ 362 363 struct dec_open_param { 364 dma_addr_t bitstream_buffer; 365 size_t bitstream_buffer_size; 366 }; 367 368 struct dec_initial_info { 369 u32 pic_width; 370 u32 pic_height; 371 struct vpu_rect pic_crop_rect; 372 u32 min_frame_buffer_count; /* between 1 to 16 */ 373 374 u32 profile; 375 u32 luma_bitdepth; /* bit-depth of the luma sample */ 376 u32 chroma_bitdepth; /* bit-depth of the chroma sample */ 377 u32 seq_init_err_reason; 378 dma_addr_t rd_ptr; /* read pointer of bitstream buffer */ 379 dma_addr_t wr_ptr; /* write pointer of bitstream buffer */ 380 u32 sequence_no; 381 u32 vlc_buf_size; 382 u32 param_buf_size; 383 }; 384 385 struct dec_output_info { 386 /** 387 * This is a frame buffer index for the picture to be displayed at the moment 388 * among frame buffers which are registered using vpu_dec_register_frame_buffer(). 389 * Frame data that will be displayed is stored in the frame buffer with this index 390 * When there is no display delay, this index is always the equal to 391 * index_frame_decoded, however, if displaying is delayed (for display 392 * reordering in AVC or B-frames in VC1), this index might be different to 393 * index_frame_decoded. By checking this index, HOST applications can easily figure 394 * out whether sequence decoding has been finished or not. 395 * 396 * -3(0xFFFD) or -2(0xFFFE) : when a display output cannot be given due to picture 397 * reordering or skip option 398 * -1(0xFFFF) : when there is no more output for display at the end of sequence 399 * decoding 400 */ 401 s32 index_frame_display; 402 /** 403 * This is the frame buffer index of the decoded picture among the frame buffers which were 404 * registered using vpu_dec_register_frame_buffer(). The currently decoded frame is stored 405 * into the frame buffer specified by this index. 406 * 407 * -2 : indicates that no decoded output is generated because decoder meets EOS 408 * (end of sequence) or skip 409 * -1 : indicates that the decoder fails to decode a picture because there is no available 410 * frame buffer 411 */ 412 s32 index_frame_decoded; 413 s32 index_frame_decoded_for_tiled; 414 u32 nal_type; 415 unsigned int pic_type; 416 struct vpu_rect rc_display; 417 unsigned int disp_pic_width; 418 unsigned int disp_pic_height; 419 struct vpu_rect rc_decoded; 420 u32 dec_pic_width; 421 u32 dec_pic_height; 422 s32 decoded_poc; 423 int temporal_id; /* temporal ID of the picture */ 424 dma_addr_t rd_ptr; /* stream buffer read pointer for the current decoder instance */ 425 dma_addr_t wr_ptr; /* stream buffer write pointer for the current decoder instance */ 426 struct frame_buffer disp_frame; 427 u32 frame_display_flag; /* it reports a frame buffer flag to be displayed */ 428 /** 429 * this variable reports that sequence has been changed while H.264/AVC stream decoding. 430 * if it is 1, HOST application can get the new sequence information by calling 431 * vpu_dec_get_initial_info() or wave5_vpu_dec_issue_seq_init(). 432 * 433 * for H.265/HEVC decoder, each bit has a different meaning as follows. 434 * 435 * sequence_changed[5] : it indicates that the profile_idc has been changed 436 * sequence_changed[16] : it indicates that the resolution has been changed 437 * sequence_changed[19] : it indicates that the required number of frame buffer has 438 * been changed. 439 */ 440 unsigned int frame_cycle; /* reports the number of cycles for processing a frame */ 441 u32 sequence_no; 442 443 u32 dec_host_cmd_tick; /* tick of DEC_PIC command for the picture */ 444 u32 dec_decode_end_tick; /* end tick of decoding slices of the picture */ 445 446 u32 sequence_changed; 447 }; 448 449 struct queue_status_info { 450 u32 instance_queue_count; 451 u32 report_queue_count; 452 }; 453 454 /* 455 * encode struct and definition 456 */ 457 458 #define MAX_NUM_TEMPORAL_LAYER 7 459 #define MAX_NUM_SPATIAL_LAYER 3 460 #define MAX_GOP_NUM 8 461 462 struct custom_gop_pic_param { 463 u32 pic_type; /* picture type of nth picture in the custom GOP */ 464 u32 poc_offset; /* POC of nth picture in the custom GOP */ 465 u32 pic_qp; /* quantization parameter of nth picture in the custom GOP */ 466 u32 use_multi_ref_p; /* use multiref pic for P picture. valid only if PIC_TYPE is P */ 467 u32 ref_poc_l0; /* POC of reference L0 of nth picture in the custom GOP */ 468 u32 ref_poc_l1; /* POC of reference L1 of nth picture in the custom GOP */ 469 s32 temporal_id; /* temporal ID of nth picture in the custom GOP */ 470 }; 471 472 struct enc_wave_param { 473 /* 474 * profile indicator (HEVC only) 475 * 476 * 0 : the firmware determines a profile according to the internal_bit_depth 477 * 1 : main profile 478 * 2 : main10 profile 479 * 3 : main still picture profile 480 * In the AVC encoder, a profile cannot be set by the host application. 481 * The firmware decides it based on internal_bit_depth. 482 * profile = HIGH (bitdepth 8) profile = HIGH10 (bitdepth 10) 483 */ 484 u32 profile; 485 u32 level; /* level indicator (level * 10) */ 486 u32 internal_bit_depth: 4; /* 8/10 */ 487 u32 gop_preset_idx: 4; /* 0 - 9 */ 488 u32 decoding_refresh_type: 2; /* 0=non-IRAP, 1=CRA, 2=IDR */ 489 u32 intra_qp; /* quantization parameter of intra picture */ 490 u32 intra_period; /* period of intra picture in GOP size */ 491 u32 conf_win_top; /* top offset of conformance window */ 492 u32 conf_win_bot; /* bottom offset of conformance window */ 493 u32 conf_win_left; /* left offset of conformance window */ 494 u32 conf_win_right; /* right offset of conformance window */ 495 u32 intra_refresh_mode: 3; 496 /* 497 * Argument for intra_ctu_refresh_mode. 498 * 499 * Depending on intra_refresh_mode, it can mean one of the following: 500 * - intra_ctu_refresh_mode (1) -> number of consecutive CTU rows 501 * - intra_ctu_refresh_mode (2) -> the number of consecutive CTU columns 502 * - intra_ctu_refresh_mode (3) -> step size in CTU 503 * - intra_ctu_refresh_mode (4) -> number of intra ct_us to be encoded in a picture 504 */ 505 u32 intra_refresh_arg; 506 /* 507 * 0 : custom setting 508 * 1 : recommended encoder parameters (slow encoding speed, highest picture quality) 509 * 2 : boost mode (normal encoding speed, moderate picture quality) 510 * 3 : fast mode (fast encoding speed, low picture quality) 511 */ 512 u32 depend_slice_mode : 2; 513 u32 depend_slice_mode_arg; 514 u32 independ_slice_mode : 1; /* 0=no-multi-slice, 1=slice-in-ctu-number*/ 515 u32 independ_slice_mode_arg; 516 u32 max_num_merge: 2; 517 s32 beta_offset_div2: 4; /* sets beta_offset_div2 for deblocking filter */ 518 s32 tc_offset_div2: 4; /* sets tc_offset_div3 for deblocking filter */ 519 u32 hvs_qp_scale: 4; /* QP scaling factor for CU QP adjust if hvs_qp_scale_enable is 1 */ 520 u32 hvs_max_delta_qp; /* maximum delta QP for HVS */ 521 s32 chroma_cb_qp_offset; /* the value of chroma(cb) QP offset */ 522 s32 chroma_cr_qp_offset; /* the value of chroma(cr) QP offset */ 523 s32 initial_rc_qp; 524 u32 nr_intra_weight_y; 525 u32 nr_intra_weight_cb; /* weight to cb noise level for intra picture (0 ~ 31) */ 526 u32 nr_intra_weight_cr; /* weight to cr noise level for intra picture (0 ~ 31) */ 527 u32 nr_inter_weight_y; 528 u32 nr_inter_weight_cb; /* weight to cb noise level for inter picture (0 ~ 31) */ 529 u32 nr_inter_weight_cr; /* weight to cr noise level for inter picture (0 ~ 31) */ 530 u32 min_qp_i; /* minimum QP of I picture for rate control */ 531 u32 max_qp_i; /* maximum QP of I picture for rate control */ 532 u32 min_qp_p; /* minimum QP of P picture for rate control */ 533 u32 max_qp_p; /* maximum QP of P picture for rate control */ 534 u32 min_qp_b; /* minimum QP of B picture for rate control */ 535 u32 max_qp_b; /* maximum QP of B picture for rate control */ 536 u32 avc_idr_period; /* period of IDR picture (0 ~ 1024). 0 - implies an infinite period */ 537 u32 avc_slice_arg; /* the number of MB for a slice when avc_slice_mode is set with 1 */ 538 u32 intra_mb_refresh_mode: 2; /* 0=none, 1=row, 2=column, 3=step-size-in-mb */ 539 /** 540 * Argument for intra_mb_refresh_mode. 541 * 542 * intra_mb_refresh_mode (1) -> number of consecutive MB rows 543 * intra_mb_refresh_mode (2) ->the number of consecutive MB columns 544 * intra_mb_refresh_mode (3) -> step size in MB 545 */ 546 u32 intra_mb_refresh_arg; 547 u32 rc_weight_param; 548 u32 rc_weight_buf; 549 550 /* flags */ 551 u32 en_still_picture: 1; /* still picture profile */ 552 u32 tier: 1; /* 0=main, 1=high */ 553 u32 avc_slice_mode: 1; /* 0=none, 1=slice-in-mb-number */ 554 u32 entropy_coding_mode: 1; /* 0=CAVLC, 1=CABAC */ 555 u32 lossless_enable: 1; /* enable lossless encoding */ 556 u32 const_intra_pred_flag: 1; /* enable constrained intra prediction */ 557 u32 tmvp_enable: 1; /* enable temporal motion vector prediction */ 558 u32 wpp_enable: 1; 559 u32 disable_deblk: 1; /* disable in-loop deblocking filtering */ 560 u32 lf_cross_slice_boundary_enable: 1; 561 u32 skip_intra_trans: 1; 562 u32 sao_enable: 1; /* enable SAO (sample adaptive offset) */ 563 u32 intra_nx_n_enable: 1; /* enables intra nx_n p_us */ 564 u32 cu_level_rc_enable: 1; /* enable CU level rate control */ 565 u32 hvs_qp_enable: 1; /* enable CU QP adjustment for subjective quality enhancement */ 566 u32 strong_intra_smooth_enable: 1; /* enable strong intra smoothing */ 567 u32 rdo_skip: 1; /* skip RDO (rate distortion optimization) */ 568 u32 lambda_scaling_enable: 1; /* enable lambda scaling using custom GOP */ 569 u32 transform8x8_enable: 1; /* enable 8x8 intra prediction and 8x8 transform */ 570 u32 mb_level_rc_enable: 1; /* enable MB-level rate control */ 571 u32 forced_idr_header_enable: 1; /* enable header encoding before IDR frame */ 572 }; 573 574 struct enc_open_param { 575 dma_addr_t bitstream_buffer; 576 unsigned int bitstream_buffer_size; 577 u32 pic_width; /* width of a picture to be encoded in unit of sample */ 578 u32 pic_height; /* height of a picture to be encoded in unit of sample */ 579 u32 frame_rate_info;/* desired fps */ 580 u32 vbv_buffer_size; 581 u32 bit_rate; /* target bitrate in bps */ 582 struct enc_wave_param wave_param; 583 enum packed_format_num packed_format; /* <<vpuapi_h_packed_format_num>> */ 584 enum frame_buffer_format src_format; 585 bool line_buf_int_en; 586 u32 rc_enable : 1; /* rate control */ 587 }; 588 589 struct enc_initial_info { 590 u32 min_frame_buffer_count; /* minimum number of frame buffers */ 591 u32 min_src_frame_count; /* minimum number of source buffers */ 592 u32 seq_init_err_reason; 593 u32 warn_info; 594 u32 vlc_buf_size; /* size of task buffer */ 595 u32 param_buf_size; /* size of task buffer */ 596 }; 597 598 /* 599 * Flags to encode NAL units explicitly 600 */ 601 struct enc_code_opt { 602 u32 implicit_header_encode: 1; 603 u32 encode_vcl: 1; 604 u32 encode_vps: 1; 605 u32 encode_sps: 1; 606 u32 encode_pps: 1; 607 u32 encode_aud: 1; 608 u32 encode_eos: 1; 609 u32 encode_eob: 1; 610 u32 encode_vui: 1; 611 }; 612 613 struct enc_param { 614 struct frame_buffer *source_frame; 615 u32 pic_stream_buffer_addr; 616 u64 pic_stream_buffer_size; 617 u32 src_idx; /* source frame buffer index */ 618 struct enc_code_opt code_option; 619 u64 pts; /* presentation timestamp (PTS) of the input source */ 620 bool src_end_flag; 621 }; 622 623 struct enc_output_info { 624 u32 bitstream_buffer; 625 u32 bitstream_size; /* byte size of encoded bitstream */ 626 u32 pic_type: 2; /* <<vpuapi_h_pic_type>> */ 627 s32 recon_frame_index; 628 dma_addr_t rd_ptr; 629 dma_addr_t wr_ptr; 630 u32 enc_pic_byte; /* number of encoded picture bytes */ 631 s32 enc_src_idx; /* source buffer index of the currently encoded picture */ 632 u32 enc_vcl_nut; 633 u32 error_reason; /* error reason of the currently encoded picture */ 634 u32 warn_info; /* warning information on the currently encoded picture */ 635 unsigned int frame_cycle; /* param for reporting the cycle number of encoding one frame*/ 636 u64 pts; 637 u32 enc_host_cmd_tick; /* tick of ENC_PIC command for the picture */ 638 u32 enc_encode_end_tick; /* end tick of encoding slices of the picture */ 639 }; 640 641 enum enc_pic_code_option { 642 CODEOPT_ENC_HEADER_IMPLICIT = BIT(0), 643 CODEOPT_ENC_VCL = BIT(1), /* flag to encode VCL nal unit explicitly */ 644 }; 645 646 enum gop_preset_idx { 647 PRESET_IDX_CUSTOM_GOP = 0, /* user defined GOP structure */ 648 PRESET_IDX_ALL_I = 1, /* all intra, gopsize = 1 */ 649 PRESET_IDX_IPP = 2, /* consecutive P, cyclic gopsize = 1 */ 650 PRESET_IDX_IBBB = 3, /* consecutive B, cyclic gopsize = 1 */ 651 PRESET_IDX_IBPBP = 4, /* gopsize = 2 */ 652 PRESET_IDX_IBBBP = 5, /* gopsize = 4 */ 653 PRESET_IDX_IPPPP = 6, /* consecutive P, cyclic gopsize = 4 */ 654 PRESET_IDX_IBBBB = 7, /* consecutive B, cyclic gopsize = 4 */ 655 PRESET_IDX_RA_IB = 8, /* random access, cyclic gopsize = 8 */ 656 PRESET_IDX_IPP_SINGLE = 9, /* consecutive P, cyclic gopsize = 1, with single ref */ 657 }; 658 659 struct sec_axi_info { 660 u32 use_ip_enable; 661 u32 use_bit_enable; 662 u32 use_lf_row_enable: 1; 663 u32 use_enc_rdo_enable: 1; 664 u32 use_enc_lf_enable: 1; 665 }; 666 667 struct dec_info { 668 struct dec_open_param open_param; 669 struct dec_initial_info initial_info; 670 struct dec_initial_info new_seq_info; /* temporal new sequence information */ 671 u32 stream_wr_ptr; 672 u32 stream_rd_ptr; 673 u32 frame_display_flag; 674 dma_addr_t stream_buf_start_addr; 675 dma_addr_t stream_buf_end_addr; 676 u32 stream_buf_size; 677 struct vpu_buf vb_mv[MAX_REG_FRAME]; 678 struct vpu_buf vb_fbc_y_tbl[MAX_REG_FRAME]; 679 struct vpu_buf vb_fbc_c_tbl[MAX_REG_FRAME]; 680 unsigned int num_of_decoding_fbs: 7; 681 unsigned int num_of_display_fbs: 7; 682 unsigned int stride; 683 struct sec_axi_info sec_axi_info; 684 dma_addr_t user_data_buf_addr; 685 u32 user_data_enable; 686 u32 user_data_buf_size; 687 struct vpu_buf vb_work; 688 struct vpu_buf vb_task; 689 struct dec_output_info dec_out_info[WAVE5_MAX_FBS]; 690 u32 seq_change_mask; 691 enum temporal_id_mode temp_id_select_mode; 692 u32 target_temp_id; 693 u32 target_spatial_id; 694 u32 instance_queue_count; 695 u32 report_queue_count; 696 u32 cycle_per_tick; 697 u32 product_code; 698 u32 vlc_buf_size; 699 u32 param_buf_size; 700 bool initial_info_obtained; 701 bool reorder_enable; 702 bool first_cycle_check; 703 u32 stream_endflag: 1; 704 }; 705 706 struct enc_info { 707 struct enc_open_param open_param; 708 struct enc_initial_info initial_info; 709 u32 stream_rd_ptr; 710 u32 stream_wr_ptr; 711 dma_addr_t stream_buf_start_addr; 712 dma_addr_t stream_buf_end_addr; 713 u32 stream_buf_size; 714 unsigned int num_frame_buffers; 715 unsigned int stride; 716 bool rotation_enable; 717 bool mirror_enable; 718 enum mirror_direction mirror_direction; 719 unsigned int rotation_angle; 720 bool initial_info_obtained; 721 struct sec_axi_info sec_axi_info; 722 bool line_buf_int_en; 723 struct vpu_buf vb_work; 724 struct vpu_buf vb_mv; /* col_mv buffer */ 725 struct vpu_buf vb_fbc_y_tbl; /* FBC luma table buffer */ 726 struct vpu_buf vb_fbc_c_tbl; /* FBC chroma table buffer */ 727 struct vpu_buf vb_sub_sam_buf; /* sub-sampled buffer for ME */ 728 struct vpu_buf vb_task; 729 u64 cur_pts; /* current timestamp in 90_k_hz */ 730 u64 pts_map[32]; /* PTS mapped with source frame index */ 731 u32 instance_queue_count; 732 u32 report_queue_count; 733 bool first_cycle_check; 734 u32 cycle_per_tick; 735 u32 product_code; 736 u32 vlc_buf_size; 737 u32 param_buf_size; 738 }; 739 740 struct vpu_device { 741 struct device *dev; 742 struct v4l2_device v4l2_dev; 743 struct v4l2_m2m_dev *v4l2_m2m_dec_dev; 744 struct v4l2_m2m_dev *v4l2_m2m_enc_dev; 745 struct list_head instances; 746 struct video_device *video_dev_dec; 747 struct video_device *video_dev_enc; 748 struct mutex dev_lock; /* lock for the src, dst v4l2 queues */ 749 struct mutex hw_lock; /* lock hw configurations */ 750 int irq; 751 enum product_id product; 752 struct vpu_attr attr; 753 struct vpu_buf common_mem; 754 u32 last_performance_cycles; 755 u32 sram_size; 756 struct gen_pool *sram_pool; 757 struct vpu_buf sram_buf; 758 void __iomem *vdb_register; 759 u32 product_code; 760 struct ida inst_ida; 761 struct clk_bulk_data *clks; 762 struct hrtimer hrtimer; 763 struct kthread_work work; 764 struct kthread_worker *worker; 765 int vpu_poll_interval; 766 int num_clks; 767 struct reset_control *resets; 768 }; 769 770 struct vpu_instance; 771 772 struct vpu_instance_ops { 773 void (*finish_process)(struct vpu_instance *inst); 774 }; 775 776 struct vpu_instance { 777 struct list_head list; 778 struct v4l2_fh v4l2_fh; 779 struct v4l2_m2m_dev *v4l2_m2m_dev; 780 struct v4l2_ctrl_handler v4l2_ctrl_hdl; 781 struct vpu_device *dev; 782 struct completion irq_done; 783 784 struct v4l2_pix_format_mplane src_fmt; 785 struct v4l2_pix_format_mplane dst_fmt; 786 enum v4l2_colorspace colorspace; 787 enum v4l2_xfer_func xfer_func; 788 enum v4l2_ycbcr_encoding ycbcr_enc; 789 enum v4l2_quantization quantization; 790 791 enum vpu_instance_state state; 792 enum vpu_instance_type type; 793 const struct vpu_instance_ops *ops; 794 spinlock_t state_spinlock; /* This protects the instance state */ 795 796 enum wave_std std; 797 s32 id; 798 union { 799 struct enc_info enc_info; 800 struct dec_info dec_info; 801 } *codec_info; 802 struct frame_buffer frame_buf[MAX_REG_FRAME]; 803 struct vpu_buf frame_vbuf[MAX_REG_FRAME]; 804 u32 fbc_buf_count; 805 u32 queued_src_buf_num; 806 u32 queued_dst_buf_num; 807 struct list_head avail_src_bufs; 808 struct list_head avail_dst_bufs; 809 struct v4l2_rect conf_win; 810 u64 timestamp; 811 enum frame_buffer_format output_format; 812 bool cbcr_interleave; 813 bool nv21; 814 bool eos; 815 struct vpu_buf bitstream_vbuf; 816 dma_addr_t last_rd_ptr; 817 size_t remaining_consumed_bytes; 818 bool needs_reallocation; 819 820 unsigned int min_src_buf_count; 821 unsigned int rot_angle; 822 unsigned int mirror_direction; 823 unsigned int bit_depth; 824 unsigned int frame_rate; 825 unsigned int vbv_buf_size; 826 unsigned int rc_mode; 827 unsigned int rc_enable; 828 unsigned int bit_rate; 829 unsigned int encode_aud; 830 struct enc_wave_param enc_param; 831 }; 832 833 void wave5_vdi_write_register(struct vpu_device *vpu_dev, u32 addr, u32 data); 834 u32 wave5_vdi_read_register(struct vpu_device *vpu_dev, u32 addr); 835 int wave5_vdi_clear_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb); 836 int wave5_vdi_allocate_dma_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb); 837 int wave5_vdi_allocate_array(struct vpu_device *vpu_dev, struct vpu_buf *array, unsigned int count, 838 size_t size); 839 int wave5_vdi_write_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb, size_t offset, 840 u8 *data, size_t len); 841 int wave5_vdi_free_dma_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb); 842 void wave5_vdi_allocate_sram(struct vpu_device *vpu_dev); 843 void wave5_vdi_free_sram(struct vpu_device *vpu_dev); 844 845 int wave5_vpu_init_with_bitcode(struct device *dev, u8 *bitcode, size_t size); 846 int wave5_vpu_flush_instance(struct vpu_instance *inst); 847 int wave5_vpu_get_version_info(struct device *dev, u32 *revision, unsigned int *product_id); 848 int wave5_vpu_dec_open(struct vpu_instance *inst, struct dec_open_param *open_param); 849 int wave5_vpu_dec_close(struct vpu_instance *inst, u32 *fail_res); 850 int wave5_vpu_dec_issue_seq_init(struct vpu_instance *inst); 851 int wave5_vpu_dec_complete_seq_init(struct vpu_instance *inst, struct dec_initial_info *info); 852 int wave5_vpu_dec_register_frame_buffer_ex(struct vpu_instance *inst, int num_of_decoding_fbs, 853 int num_of_display_fbs, int stride, int height); 854 int wave5_vpu_dec_start_one_frame(struct vpu_instance *inst, u32 *res_fail); 855 int wave5_vpu_dec_get_output_info(struct vpu_instance *inst, struct dec_output_info *info); 856 int wave5_vpu_dec_set_rd_ptr(struct vpu_instance *inst, dma_addr_t addr, int update_wr_ptr); 857 dma_addr_t wave5_vpu_dec_get_rd_ptr(struct vpu_instance *inst); 858 int wave5_vpu_dec_reset_framebuffer(struct vpu_instance *inst, unsigned int index); 859 int wave5_vpu_dec_give_command(struct vpu_instance *inst, enum codec_command cmd, void *parameter); 860 int wave5_vpu_dec_get_bitstream_buffer(struct vpu_instance *inst, dma_addr_t *prd_ptr, 861 dma_addr_t *pwr_ptr, size_t *size); 862 int wave5_vpu_dec_update_bitstream_buffer(struct vpu_instance *inst, size_t size); 863 int wave5_vpu_dec_clr_disp_flag(struct vpu_instance *inst, int index); 864 int wave5_vpu_dec_set_disp_flag(struct vpu_instance *inst, int index); 865 866 int wave5_vpu_enc_open(struct vpu_instance *inst, struct enc_open_param *open_param); 867 int wave5_vpu_enc_close(struct vpu_instance *inst, u32 *fail_res); 868 int wave5_vpu_enc_issue_seq_init(struct vpu_instance *inst); 869 int wave5_vpu_enc_complete_seq_init(struct vpu_instance *inst, struct enc_initial_info *info); 870 int wave5_vpu_enc_register_frame_buffer(struct vpu_instance *inst, unsigned int num, 871 unsigned int stride, int height, 872 enum tiled_map_type map_type); 873 int wave5_vpu_enc_start_one_frame(struct vpu_instance *inst, struct enc_param *param, 874 u32 *fail_res); 875 int wave5_vpu_enc_get_output_info(struct vpu_instance *inst, struct enc_output_info *info); 876 int wave5_vpu_enc_give_command(struct vpu_instance *inst, enum codec_command cmd, void *parameter); 877 878 #endif 879