1/*
2 * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <common/bl_common.h>
10#include <cortex_a78.h>
11#include <cpu_macros.S>
12#include <plat_macros.S>
13#include "wa_cve_2022_23960_bhb_vector.S"
14
15/* Hardware handled coherency */
16#if HW_ASSISTED_COHERENCY == 0
17#error "cortex_a78 must be compiled with HW_ASSISTED_COHERENCY enabled"
18#endif
19
20.globl cortex_a78_reset_func
21.globl cortex_a78_core_pwr_dwn
22
23#if WORKAROUND_CVE_2022_23960
24	wa_cve_2022_23960_bhb_vector_table CORTEX_A78_BHB_LOOP_COUNT, cortex_a78
25#endif /* WORKAROUND_CVE_2022_23960 */
26
27workaround_reset_start cortex_a78, ERRATUM(1688305), ERRATA_A78_1688305
28	sysreg_bit_set CORTEX_A78_ACTLR2_EL1, CORTEX_A78_ACTLR2_EL1_BIT_1
29workaround_reset_end cortex_a78, ERRATUM(1688305)
30
31check_erratum_ls cortex_a78, ERRATUM(1688305), CPU_REV(1, 0)
32
33workaround_reset_start cortex_a78, ERRATUM(1821534), ERRATA_A78_1821534
34	sysreg_bit_set CORTEX_A78_ACTLR2_EL1, CORTEX_A78_ACTLR2_EL1_BIT_2
35workaround_reset_end cortex_a78, ERRATUM(1821534)
36
37check_erratum_ls cortex_a78, ERRATUM(1821534), CPU_REV(1, 0)
38
39workaround_reset_start cortex_a78, ERRATUM(1941498), ERRATA_A78_1941498
40	sysreg_bit_set CORTEX_A78_CPUECTLR_EL1, CORTEX_A78_CPUECTLR_EL1_BIT_8
41workaround_reset_end cortex_a78, ERRATUM(1941498)
42
43check_erratum_ls cortex_a78, ERRATUM(1941498), CPU_REV(1, 1)
44
45workaround_reset_start cortex_a78, ERRATUM(1951500), ERRATA_A78_1951500
46	msr	S3_6_c15_c8_0, xzr
47	ldr	x0, =0x10E3900002
48	msr	S3_6_c15_c8_2, x0
49	ldr	x0, =0x10FFF00083
50	msr	S3_6_c15_c8_3, x0
51	ldr	x0, =0x2001003FF
52	msr	S3_6_c15_c8_1, x0
53
54	mov	x0, #1
55	msr	S3_6_c15_c8_0, x0
56	ldr	x0, =0x10E3800082
57	msr	S3_6_c15_c8_2, x0
58	ldr	x0, =0x10FFF00083
59	msr	S3_6_c15_c8_3, x0
60	ldr	x0, =0x2001003FF
61	msr	S3_6_c15_c8_1, x0
62
63	mov	x0, #2
64	msr	S3_6_c15_c8_0, x0
65	ldr	x0, =0x10E3800200
66	msr	S3_6_c15_c8_2, x0
67	ldr	x0, =0x10FFF003E0
68	msr	S3_6_c15_c8_3, x0
69	ldr	x0, =0x2001003FF
70	msr	S3_6_c15_c8_1, x0
71workaround_reset_end cortex_a78, ERRATUM(1951500)
72
73check_erratum_range cortex_a78, ERRATUM(1951500), CPU_REV(1, 0), CPU_REV(1, 1)
74
75workaround_reset_start cortex_a78, ERRATUM(1952683), ERRATA_A78_1952683
76	ldr	x0,=0x5
77	msr	S3_6_c15_c8_0,x0
78	ldr	x0,=0xEEE10A10
79	msr	S3_6_c15_c8_2,x0
80	ldr	x0,=0xFFEF0FFF
81	msr	S3_6_c15_c8_3,x0
82	ldr	x0,=0x0010F000
83	msr	S3_6_c15_c8_4,x0
84	ldr	x0,=0x0010F000
85	msr	S3_6_c15_c8_5,x0
86	ldr	x0,=0x40000080023ff
87	msr	S3_6_c15_c8_1,x0
88	ldr	x0,=0x6
89	msr	S3_6_c15_c8_0,x0
90	ldr	x0,=0xEE640F34
91	msr	S3_6_c15_c8_2,x0
92	ldr	x0,=0xFFEF0FFF
93	msr	S3_6_c15_c8_3,x0
94	ldr	x0,=0x40000080023ff
95	msr	S3_6_c15_c8_1,x0
96workaround_reset_end cortex_a78, ERRATUM(1952683)
97
98check_erratum_ls cortex_a78, ERRATUM(1952683), CPU_REV(0, 0)
99
100workaround_reset_start cortex_a78, ERRATUM(2132060), ERRATA_A78_2132060
101	/* Apply the workaround. */
102	mrs	x1, CORTEX_A78_CPUECTLR_EL1
103	mov	x0, #CORTEX_A78_CPUECTLR_EL1_PF_MODE_CNSRV
104	bfi	x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH
105	msr	CORTEX_A78_CPUECTLR_EL1, x1
106workaround_reset_end cortex_a78, ERRATUM(2132060)
107
108check_erratum_ls cortex_a78, ERRATUM(2132060), CPU_REV(1, 2)
109
110workaround_reset_start cortex_a78, ERRATUM(2242635), ERRATA_A78_2242635
111	ldr	x0, =0x5
112	msr	S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */
113	ldr	x0, =0x10F600E000
114	msr	S3_6_c15_c8_2, x0 /* CPUPOR_EL3 */
115	ldr	x0, =0x10FF80E000
116	msr	S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */
117	ldr	x0, =0x80000000003FF
118	msr	S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */
119workaround_reset_end cortex_a78, ERRATUM(2242635)
120
121check_erratum_range cortex_a78, ERRATUM(2242635), CPU_REV(1, 0), CPU_REV(1, 2)
122
123workaround_reset_start cortex_a78, ERRATUM(2376745), ERRATA_A78_2376745
124	sysreg_bit_set CORTEX_A78_ACTLR2_EL1, BIT(0)
125workaround_reset_end cortex_a78, ERRATUM(2376745)
126
127check_erratum_ls cortex_a78, ERRATUM(2376745), CPU_REV(1, 2)
128
129workaround_reset_start cortex_a78, ERRATUM(2395406), ERRATA_A78_2395406
130	sysreg_bit_set CORTEX_A78_ACTLR2_EL1, BIT(40)
131workaround_reset_end cortex_a78, ERRATUM(2395406)
132
133check_erratum_ls cortex_a78, ERRATUM(2395406), CPU_REV(1, 2)
134
135workaround_reset_start cortex_a78, ERRATUM(2742426), ERRATA_A78_2742426
136	/* Apply the workaround */
137	mrs	x1, CORTEX_A78_ACTLR5_EL1
138	bic	x1, x1, #BIT(56)
139	orr	x1, x1, #BIT(55)
140	msr	CORTEX_A78_ACTLR5_EL1, x1
141workaround_reset_end cortex_a78, ERRATUM(2742426)
142
143check_erratum_ls cortex_a78, ERRATUM(2742426), CPU_REV(1, 2)
144
145workaround_runtime_start cortex_a78, ERRATUM(2772019), ERRATA_A78_2772019
146	/* dsb before isb of power down sequence */
147	dsb	sy
148workaround_runtime_end cortex_a78, ERRATUM(2772019)
149
150check_erratum_ls cortex_a78, ERRATUM(2772019), CPU_REV(1, 2)
151
152workaround_reset_start cortex_a78, ERRATUM(2779479), ERRATA_A78_2779479
153	sysreg_bit_set CORTEX_A78_ACTLR3_EL1, BIT(47)
154workaround_reset_end cortex_a78, ERRATUM(2779479)
155
156check_erratum_ls cortex_a78, ERRATUM(2779479), CPU_REV(1, 2)
157
158workaround_reset_start cortex_a78, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
159#if IMAGE_BL31
160	/*
161	 * The Cortex-X1 generic vectors are overridden to apply errata
162	 * mitigation on exception entry from lower ELs.
163	 */
164	override_vector_table wa_cve_vbar_cortex_a78
165#endif /* IMAGE_BL31 */
166workaround_reset_end cortex_a78, CVE(2022, 23960)
167
168check_erratum_chosen cortex_a78, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
169
170cpu_reset_func_start cortex_a78
171#if ENABLE_FEAT_AMU
172	/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
173	sysreg_bit_clear actlr_el3, CORTEX_A78_ACTLR_TAM_BIT
174
175	/* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */
176	sysreg_bit_clear actlr_el2, CORTEX_A78_ACTLR_TAM_BIT
177
178	/* Enable group0 counters */
179	mov	x0, #CORTEX_A78_AMU_GROUP0_MASK
180	msr	CPUAMCNTENSET0_EL0, x0
181
182	/* Enable group1 counters */
183	mov	x0, #CORTEX_A78_AMU_GROUP1_MASK
184	msr	CPUAMCNTENSET1_EL0, x0
185#endif
186cpu_reset_func_end cortex_a78
187
188	/* ---------------------------------------------
189	 * HW will do the cache maintenance while powering down
190	 * ---------------------------------------------
191	 */
192func cortex_a78_core_pwr_dwn
193	sysreg_bit_set CORTEX_A78_CPUPWRCTLR_EL1, CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
194
195	apply_erratum cortex_a78, ERRATUM(2772019), ERRATA_A78_2772019
196
197	isb
198	ret
199endfunc cortex_a78_core_pwr_dwn
200
201errata_report_shim cortex_a78
202
203	/* ---------------------------------------------
204	 * This function provides cortex_a78 specific
205	 * register information for crash reporting.
206	 * It needs to return with x6 pointing to
207	 * a list of register names in ascii and
208	 * x8 - x15 having values of registers to be
209	 * reported.
210	 * ---------------------------------------------
211	 */
212.section .rodata.cortex_a78_regs, "aS"
213cortex_a78_regs:  /* The ascii list of register names to be reported */
214	.asciz	"cpuectlr_el1", ""
215
216func cortex_a78_cpu_reg_dump
217	adr	x6, cortex_a78_regs
218	mrs	x8, CORTEX_A78_CPUECTLR_EL1
219	ret
220endfunc cortex_a78_cpu_reg_dump
221
222declare_cpu_ops cortex_a78, CORTEX_A78_MIDR, \
223	cortex_a78_reset_func, \
224	cortex_a78_core_pwr_dwn
225