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Searched refs:regMPCC2_MPCC_SM_CONTROL_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux-6.14.4/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_1_5_offset.h6289 #define regMPCC2_MPCC_SM_CONTROL_BASE_IDX … macro
Ddcn_3_5_1_offset.h12199 #define regMPCC2_MPCC_SM_CONTROL_BASE_IDX … macro
Ddcn_3_1_2_offset.h6530 #define regMPCC2_MPCC_SM_CONTROL_BASE_IDX … macro
Ddcn_3_2_0_offset.h4852 #define regMPCC2_MPCC_SM_CONTROL_BASE_IDX … macro
Ddcn_3_1_4_offset.h13291 #define regMPCC2_MPCC_SM_CONTROL_BASE_IDX … macro
Ddcn_3_5_0_offset.h12220 #define regMPCC2_MPCC_SM_CONTROL_BASE_IDX … macro
Ddcn_3_2_1_offset.h4851 #define regMPCC2_MPCC_SM_CONTROL_BASE_IDX … macro
Ddcn_4_1_0_offset.h5375 #define regMPCC2_MPCC_SM_CONTROL_BASE_IDX … macro
Ddcn_3_1_6_offset.h6750 #define regMPCC2_MPCC_SM_CONTROL_BASE_IDX … macro