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Searched refs:regDC_GPU_TIMER_READ_CNTL_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux-6.14.4/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_1_5_offset.h461 #define regDC_GPU_TIMER_READ_CNTL_BASE_IDX … macro
Ddcn_3_5_1_offset.h1675 #define regDC_GPU_TIMER_READ_CNTL_BASE_IDX … macro
Ddcn_3_1_2_offset.h692 #define regDC_GPU_TIMER_READ_CNTL_BASE_IDX … macro
Ddcn_3_2_0_offset.h277 #define regDC_GPU_TIMER_READ_CNTL_BASE_IDX … macro
Ddcn_3_1_4_offset.h1953 #define regDC_GPU_TIMER_READ_CNTL_BASE_IDX … macro
Ddcn_3_5_0_offset.h1696 #define regDC_GPU_TIMER_READ_CNTL_BASE_IDX … macro
Ddcn_3_2_1_offset.h277 #define regDC_GPU_TIMER_READ_CNTL_BASE_IDX … macro
Ddcn_4_1_0_offset.h298 #define regDC_GPU_TIMER_READ_CNTL_BASE_IDX … macro
Ddcn_3_1_6_offset.h896 #define regDC_GPU_TIMER_READ_CNTL_BASE_IDX … macro