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Searched refs:regCNVC_CFG1_FORMAT_CONTROL_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux-6.14.4/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_1_5_offset.h4143 #define regCNVC_CFG1_FORMAT_CONTROL_BASE_IDX macro
Ddcn_3_5_1_offset.h4833 #define regCNVC_CFG1_FORMAT_CONTROL_BASE_IDX macro
Ddcn_3_1_2_offset.h4384 #define regCNVC_CFG1_FORMAT_CONTROL_BASE_IDX macro
Ddcn_3_2_0_offset.h3608 #define regCNVC_CFG1_FORMAT_CONTROL_BASE_IDX macro
Ddcn_3_1_4_offset.h5293 #define regCNVC_CFG1_FORMAT_CONTROL_BASE_IDX macro
Ddcn_3_5_0_offset.h4854 #define regCNVC_CFG1_FORMAT_CONTROL_BASE_IDX macro
Ddcn_3_2_1_offset.h3607 #define regCNVC_CFG1_FORMAT_CONTROL_BASE_IDX macro
Ddcn_4_1_0_offset.h3772 #define regCNVC_CFG1_FORMAT_CONTROL_BASE_IDX macro
Ddcn_3_1_6_offset.h4604 #define regCNVC_CFG1_FORMAT_CONTROL_BASE_IDX macro