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Searched refs:regCM1_CM_POST_CSC_C31_C32_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux-6.14.4/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_1_5_offset.h4303 #define regCM1_CM_POST_CSC_C31_C32_BASE_IDX … macro
Ddcn_3_5_1_offset.h4993 #define regCM1_CM_POST_CSC_C31_C32_BASE_IDX … macro
Ddcn_3_1_2_offset.h4544 #define regCM1_CM_POST_CSC_C31_C32_BASE_IDX … macro
Ddcn_3_2_0_offset.h3768 #define regCM1_CM_POST_CSC_C31_C32_BASE_IDX … macro
Ddcn_3_1_4_offset.h5453 #define regCM1_CM_POST_CSC_C31_C32_BASE_IDX … macro
Ddcn_3_5_0_offset.h5014 #define regCM1_CM_POST_CSC_C31_C32_BASE_IDX … macro
Ddcn_3_2_1_offset.h3767 #define regCM1_CM_POST_CSC_C31_C32_BASE_IDX … macro
Ddcn_4_1_0_offset.h4078 #define regCM1_CM_POST_CSC_C31_C32_BASE_IDX … macro
Ddcn_3_1_6_offset.h4764 #define regCM1_CM_POST_CSC_C31_C32_BASE_IDX … macro