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Searched refs:regCM0_CM_POST_CSC_CONTROL_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux-6.14.4/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_1_5_offset.h3601 #define regCM0_CM_POST_CSC_CONTROL_BASE_IDX … macro
Ddcn_3_5_1_offset.h4571 #define regCM0_CM_POST_CSC_CONTROL_BASE_IDX … macro
Ddcn_3_1_2_offset.h3842 #define regCM0_CM_POST_CSC_CONTROL_BASE_IDX … macro
Ddcn_3_2_0_offset.h3368 #define regCM0_CM_POST_CSC_CONTROL_BASE_IDX … macro
Ddcn_3_1_4_offset.h4751 #define regCM0_CM_POST_CSC_CONTROL_BASE_IDX … macro
Ddcn_3_5_0_offset.h4592 #define regCM0_CM_POST_CSC_CONTROL_BASE_IDX … macro
Ddcn_3_2_1_offset.h3367 #define regCM0_CM_POST_CSC_CONTROL_BASE_IDX … macro
Ddcn_4_1_0_offset.h3559 #define regCM0_CM_POST_CSC_CONTROL_BASE_IDX … macro
Ddcn_3_1_6_offset.h4062 #define regCM0_CM_POST_CSC_CONTROL_BASE_IDX … macro