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Searched refs:mtk_phy_update_bits (Results 1 – 7 of 7) sorted by relevance

/linux-6.14.4/drivers/phy/mediatek/
Dphy-mtk-xfi-tphy.c118 mtk_phy_update_bits(xfi_tphy->base + 0x9024, 0x100000, is_10g ? 0x0 : 0x100000); in mtk_xfi_tphy_setup()
119 mtk_phy_update_bits(xfi_tphy->base + 0x2020, 0x202000, is_5g ? 0x202000 : 0x0); in mtk_xfi_tphy_setup()
120 mtk_phy_update_bits(xfi_tphy->base + 0x2030, 0x500, is_1g ? 0x0 : 0x500); in mtk_xfi_tphy_setup()
121 mtk_phy_update_bits(xfi_tphy->base + 0x2034, 0xa00, is_1g ? 0x0 : 0xa00); in mtk_xfi_tphy_setup()
122 mtk_phy_update_bits(xfi_tphy->base + 0x2040, 0x340000, is_1g ? 0x200000 : 0x140000); in mtk_xfi_tphy_setup()
125 mtk_phy_update_bits(xfi_tphy->base + 0x50f0, 0xc10, is_1g ? 0x410 : is_5g ? 0x800 : 0x400); in mtk_xfi_tphy_setup()
126 mtk_phy_update_bits(xfi_tphy->base + 0x50e0, 0x4000, is_5g ? 0x0 : 0x4000); in mtk_xfi_tphy_setup()
129 mtk_phy_update_bits(xfi_tphy->base + 0x506c, 0x30000, is_5g ? 0x0 : 0x30000); in mtk_xfi_tphy_setup()
130 mtk_phy_update_bits(xfi_tphy->base + 0x5070, 0x670000, is_5g ? 0x620000 : 0x50000); in mtk_xfi_tphy_setup()
131 mtk_phy_update_bits(xfi_tphy->base + 0x5074, 0x180000, is_5g ? 0x180000 : 0x0); in mtk_xfi_tphy_setup()
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Dphy-mtk-hdmi-mt8173.c162 mtk_phy_update_bits(base + HDMI_CON0, in mtk_hdmi_pll_set_rate()
167 mtk_phy_update_bits(base + HDMI_CON0, in mtk_hdmi_pll_set_rate()
172 mtk_phy_update_bits(base + HDMI_CON0, in mtk_hdmi_pll_set_rate()
189 mtk_phy_update_bits(base + HDMI_CON4, in mtk_hdmi_pll_set_rate()
197 mtk_phy_update_bits(base + HDMI_CON6, in mtk_hdmi_pll_set_rate()
204 mtk_phy_update_bits(base + HDMI_CON5, in mtk_hdmi_pll_set_rate()
Dphy-mtk-mipi-dsi-mt8173.c155 mtk_phy_update_bits(base + MIPITX_DSI_BG_CON, in mtk_mipi_tx_pll_prepare()
168 mtk_phy_update_bits(base + MIPITX_DSI_TOP_CON, in mtk_mipi_tx_pll_prepare()
176 mtk_phy_update_bits(base + MIPITX_DSI_PLL_PWR, in mtk_mipi_tx_pll_prepare()
182 mtk_phy_update_bits(base + MIPITX_DSI_PLL_CON0, in mtk_mipi_tx_pll_prepare()
225 mtk_phy_update_bits(base + MIPITX_DSI_PLL_PWR, in mtk_mipi_tx_pll_unprepare()
Dphy-mtk-io.h30 static inline void mtk_phy_update_bits(void __iomem *reg, u32 mask, u32 val) in mtk_phy_update_bits() function
43 mtk_phy_update_bits(reg, mask, FIELD_PREP(mask, val)); \
Dphy-mtk-tphy.c784 mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_CDR1, in u3_phy_instance_init()
956 mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG0, in pcie_phy_instance_init()
972 mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG5, in pcie_phy_instance_init()
977 mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG4, in pcie_phy_instance_init()
1029 mtk_phy_update_bits(phyd + ANA_RG_CTRL_SIGNAL6, in sata_phy_instance_init()
1038 mtk_phy_update_bits(phyd + ANA_RG_CTRL_SIGNAL4, in sata_phy_instance_init()
1043 mtk_phy_update_bits(phyd + PHYD_CTRL_SIGNAL_MODE4, in sata_phy_instance_init()
1050 mtk_phy_update_bits(phyd + PHYD_DESIGN_OPTION9, in sata_phy_instance_init()
1055 mtk_phy_update_bits(phyd + PHYD_DESIGN_OPTION9, in sata_phy_instance_init()
Dphy-mtk-xsphy.c186 mtk_phy_update_bits(pbase + XSP_U2PHYDTM1, in u2_phy_instance_power_on()
201 mtk_phy_update_bits(pbase + XSP_U2PHYDTM1, in u2_phy_instance_power_off()
Dphy-mtk-mipi-dsi-mt8183.c126 mtk_phy_update_bits(mipi_tx->regs + in mtk_mipi_tx_config_calibration_data()