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Searched refs:mmDP5_DP_MSA_TIMING_PARAM1_BASE_IDX (Results 1 – 4 of 4) sorted by relevance

/linux-6.14.4/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_1_0_offset.h10008 #define mmDP5_DP_MSA_TIMING_PARAM1_BASE_IDX … macro
Ddcn_3_0_2_offset.h11370 #define mmDP5_DP_MSA_TIMING_PARAM1_BASE_IDX … macro
Ddcn_2_0_0_offset.h12695 #define mmDP5_DP_MSA_TIMING_PARAM1_BASE_IDX … macro
Ddcn_3_0_0_offset.h12522 #define mmDP5_DP_MSA_TIMING_PARAM1_BASE_IDX … macro