Searched refs:macrotile_mode_array (Results 1 – 10 of 10) sorted by relevance
218 uint32_t macrotile_mode_array[16]; member
3200 adev->gfx.config.macrotile_mode_array; in amdgpu_amdkfd_get_tile_config()3202 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); in amdgpu_amdkfd_get_tile_config()
1211 return adev->gfx.config.macrotile_mode_array[idx]; in cik_get_register_value()
827 return adev->gfx.config.macrotile_mode_array[idx]; in vi_get_register_value()
995 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); in gfx_v7_0_tiling_mode_table_init()1000 macrotile = adev->gfx.config.macrotile_mode_array; in gfx_v7_0_tiling_mode_table_init()
2090 const u32 num_secondary_tile_mode_states = ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); in gfx_v8_0_tiling_mode_table_init()2094 mod2array = adev->gfx.config.macrotile_mode_array; in gfx_v8_0_tiling_mode_table_init()
506 value = rdev->config.cik.macrotile_mode_array; in radeon_info_ioctl()
1290 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3; in dce4_crtc_do_set_base()
2181 uint32_t macrotile_mode_array[16]; member
2323 u32 *macrotile = rdev->config.cik.macrotile_mode_array; in cik_tiling_mode_table_init()2327 ARRAY_SIZE(rdev->config.cik.macrotile_mode_array); in cik_tiling_mode_table_init()