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Searched refs:block_sequence (Results 1 – 7 of 7) sorted by relevance

/linux-6.14.4/drivers/gpu/drm/amd/display/dc/core/
Ddc_hw_sequencer.c635 struct block_sequence block_sequence[], in hwss_build_fast_sequence() argument
654 block_sequence[*num_steps].params.wait_for_dcc_meta_propagation_params.dc = dc; in hwss_build_fast_sequence()
655block_sequence[*num_steps].params.wait_for_dcc_meta_propagation_params.top_pipe_to_program = pipe_… in hwss_build_fast_sequence()
656 block_sequence[*num_steps].func = HUBP_WAIT_FOR_DCC_META_PROP; in hwss_build_fast_sequence()
660 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.dc = dc; in hwss_build_fast_sequence()
661 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.lock = true; in hwss_build_fast_sequence()
662 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.subvp_immediate_flip = in hwss_build_fast_sequence()
664 block_sequence[*num_steps].func = DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST; in hwss_build_fast_sequence()
668 block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.dc = dc; in hwss_build_fast_sequence()
669 block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.lock = true; in hwss_build_fast_sequence()
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Ddc_state.c342 memset(state->block_sequence, 0, sizeof(state->block_sequence)); in dc_state_destruct()
Ddc.c3877 context->block_sequence, in commit_planes_for_stream_fast()
3883 context->block_sequence, in commit_planes_for_stream_fast()
/linux-6.14.4/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
Ddcn401_clk_mgr.c641 params = &clk_mgr401->block_sequence[i].params; in dcn401_execute_block_sequence()
643 switch (clk_mgr401->block_sequence[i].func) { in dcn401_execute_block_sequence()
761 struct dcn401_clk_mgr_block_sequence *block_sequence = clk_mgr401->block_sequence; in dcn401_build_update_bandwidth_clocks_sequence() local
796 block_sequence[num_steps].params.update_num_displays_params.num_displays = display_count; in dcn401_build_update_bandwidth_clocks_sequence()
797 block_sequence[num_steps].func = CLK_MGR401_UPDATE_NUM_DISPLAYS; in dcn401_build_update_bandwidth_clocks_sequence()
836 block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_DCFCLK; in dcn401_build_update_bandwidth_clocks_sequence()
837block_sequence[num_steps].params.update_hardmin_params.freq_mhz = khz_to_mhz_ceil(clk_mgr_base->cl… in dcn401_build_update_bandwidth_clocks_sequence()
838 block_sequence[num_steps].params.update_hardmin_params.response = NULL; in dcn401_build_update_bandwidth_clocks_sequence()
839 block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK; in dcn401_build_update_bandwidth_clocks_sequence()
848block_sequence[num_steps].params.update_deep_sleep_dcfclk_params.freq_mhz = khz_to_mhz_ceil(clk_mg… in dcn401_build_update_bandwidth_clocks_sequence()
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Ddcn401_clk_mgr.h104 struct dcn401_clk_mgr_block_sequence block_sequence[DCN401_CLK_MGR_MAX_SEQUENCE_SIZE]; member
/linux-6.14.4/drivers/gpu/drm/amd/display/dc/hwss/
Dhw_sequencer.h199 struct block_sequence { struct
525 struct block_sequence block_sequence[],
531 struct block_sequence block_sequence[],
/linux-6.14.4/drivers/gpu/drm/amd/display/dc/inc/
Dcore_types.h630 struct block_sequence block_sequence[50]; member