Searched refs:amdgpu_vcn4_fw_shared (Results 1 – 6 of 6) sorted by relevance
145 volatile struct amdgpu_vcn4_fw_shared *fw_shared; in vcn_v5_0_1_sw_fini()316 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); in vcn_v5_0_1_mc_resume()424 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()466 volatile struct amdgpu_vcn4_fw_shared *fw_shared = in vcn_v5_0_1_start_dpg_mode()573 volatile struct amdgpu_vcn4_fw_shared *fw_shared; in vcn_v5_0_1_start()757 volatile struct amdgpu_vcn4_fw_shared *fw_shared; in vcn_v5_0_1_stop()
128 struct amdgpu_vcn4_fw_shared *fw_shared; in vcn_v4_0_3_fw_shared_init()248 volatile struct amdgpu_vcn4_fw_shared *fw_shared; in vcn_v4_0_3_sw_fini()299 struct amdgpu_vcn4_fw_shared *fw_shared; in vcn_v4_0_3_hw_init()468 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); in vcn_v4_0_3_mc_resume()576 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()791 volatile struct amdgpu_vcn4_fw_shared *fw_shared = in vcn_v4_0_3_start_dpg_mode()948 volatile struct amdgpu_vcn4_fw_shared *fw_shared; in vcn_v4_0_3_start_sriov()1051 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); in vcn_v4_0_3_start_sriov()1121 volatile struct amdgpu_vcn4_fw_shared *fw_shared; in vcn_v4_0_3_start()1331 volatile struct amdgpu_vcn4_fw_shared *fw_shared; in vcn_v4_0_3_stop()
150 volatile struct amdgpu_vcn4_fw_shared *fw_shared; in vcn_v4_0_5_sw_init()234 volatile struct amdgpu_vcn4_fw_shared *fw_shared; in vcn_v4_0_5_sw_fini()417 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); in vcn_v4_0_5_mc_resume()526 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()873 volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; in vcn_v4_0_5_start_dpg_mode()998 volatile struct amdgpu_vcn4_fw_shared *fw_shared; in vcn_v4_0_5_start()1211 volatile struct amdgpu_vcn4_fw_shared *fw_shared; in vcn_v4_0_5_stop()
141 volatile struct amdgpu_vcn4_fw_shared *fw_shared; in vcn_v4_0_fw_shared_init()275 volatile struct amdgpu_vcn4_fw_shared *fw_shared; in vcn_v4_0_sw_fini()478 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); in vcn_v4_0_mc_resume()581 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()968 volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; in vcn_v4_0_start_dpg_mode()1095 volatile struct amdgpu_vcn4_fw_shared *fw_shared; in vcn_v4_0_start()1313 volatile struct amdgpu_vcn4_fw_shared *fw_shared; in vcn_v4_0_start_sriov()1445 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); in vcn_v4_0_start_sriov()1557 volatile struct amdgpu_vcn4_fw_shared *fw_shared; in vcn_v4_0_stop()
435 struct amdgpu_vcn4_fw_shared { struct
198 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)); in amdgpu_vcn_sw_init()199 log_offset = offsetof(struct amdgpu_vcn4_fw_shared, fw_log); in amdgpu_vcn_sw_init()