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Searched refs:SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK (Results 1 – 19 of 19) sorted by relevance

/linux-6.14.4/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_8_0_sh_mask.h1485 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK 0xffff0000 macro
Ddce_10_0_sh_mask.h1515 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK 0xffff0000 macro
Ddce_11_0_sh_mask.h1423 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK 0xffff0000 macro
Ddce_11_2_sh_mask.h1551 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK 0xffff0000 macro
Ddce_12_0_sh_mask.h2609 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK … macro
/linux-6.14.4/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_3_sh_mask.h1311 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK … macro
Ddcn_2_1_0_sh_mask.h2109 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK … macro
Ddcn_1_0_sh_mask.h3608 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK … macro
Ddcn_3_2_1_sh_mask.h2765 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK … macro
Ddcn_3_5_0_sh_mask.h8138 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK … macro
Ddcn_3_5_1_sh_mask.h8117 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK … macro
Ddcn_3_1_2_sh_mask.h5600 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK … macro
Ddcn_3_1_6_sh_mask.h6195 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK … macro
Ddcn_3_0_2_sh_mask.h2180 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK … macro
Ddcn_3_1_4_sh_mask.h10347 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK … macro
Ddcn_2_0_0_sh_mask.h2377 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK … macro
Ddcn_3_0_0_sh_mask.h2252 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK … macro
Ddcn_4_1_0_sh_mask.h3097 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK … macro
Ddcn_3_2_0_sh_mask.h2766 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK … macro