1 /* 2 * Copyright (C) 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 #ifndef _mmhub_9_4_1_SH_MASK_HEADER 22 #define _mmhub_9_4_1_SH_MASK_HEADER 23 24 25 // addressBlock: mmhub_dagb_dagbdec0 26 //DAGB0_RDCLI0 27 #define DAGB0_RDCLI0__VIRT_CHAN__SHIFT 0x0 28 #define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 29 #define DAGB0_RDCLI0__URG_HIGH__SHIFT 0x4 30 #define DAGB0_RDCLI0__URG_LOW__SHIFT 0x8 31 #define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 32 #define DAGB0_RDCLI0__MAX_BW__SHIFT 0xd 33 #define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 34 #define DAGB0_RDCLI0__MIN_BW__SHIFT 0x16 35 #define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 36 #define DAGB0_RDCLI0__MAX_OSD__SHIFT 0x1a 37 #define DAGB0_RDCLI0__VIRT_CHAN_MASK 0x00000007L 38 #define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 39 #define DAGB0_RDCLI0__URG_HIGH_MASK 0x000000F0L 40 #define DAGB0_RDCLI0__URG_LOW_MASK 0x00000F00L 41 #define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L 42 #define DAGB0_RDCLI0__MAX_BW_MASK 0x001FE000L 43 #define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L 44 #define DAGB0_RDCLI0__MIN_BW_MASK 0x01C00000L 45 #define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 46 #define DAGB0_RDCLI0__MAX_OSD_MASK 0xFC000000L 47 //DAGB0_RDCLI1 48 #define DAGB0_RDCLI1__VIRT_CHAN__SHIFT 0x0 49 #define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 50 #define DAGB0_RDCLI1__URG_HIGH__SHIFT 0x4 51 #define DAGB0_RDCLI1__URG_LOW__SHIFT 0x8 52 #define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc 53 #define DAGB0_RDCLI1__MAX_BW__SHIFT 0xd 54 #define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 55 #define DAGB0_RDCLI1__MIN_BW__SHIFT 0x16 56 #define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 57 #define DAGB0_RDCLI1__MAX_OSD__SHIFT 0x1a 58 #define DAGB0_RDCLI1__VIRT_CHAN_MASK 0x00000007L 59 #define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 60 #define DAGB0_RDCLI1__URG_HIGH_MASK 0x000000F0L 61 #define DAGB0_RDCLI1__URG_LOW_MASK 0x00000F00L 62 #define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L 63 #define DAGB0_RDCLI1__MAX_BW_MASK 0x001FE000L 64 #define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L 65 #define DAGB0_RDCLI1__MIN_BW_MASK 0x01C00000L 66 #define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 67 #define DAGB0_RDCLI1__MAX_OSD_MASK 0xFC000000L 68 //DAGB0_RDCLI2 69 #define DAGB0_RDCLI2__VIRT_CHAN__SHIFT 0x0 70 #define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 71 #define DAGB0_RDCLI2__URG_HIGH__SHIFT 0x4 72 #define DAGB0_RDCLI2__URG_LOW__SHIFT 0x8 73 #define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc 74 #define DAGB0_RDCLI2__MAX_BW__SHIFT 0xd 75 #define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 76 #define DAGB0_RDCLI2__MIN_BW__SHIFT 0x16 77 #define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 78 #define DAGB0_RDCLI2__MAX_OSD__SHIFT 0x1a 79 #define DAGB0_RDCLI2__VIRT_CHAN_MASK 0x00000007L 80 #define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 81 #define DAGB0_RDCLI2__URG_HIGH_MASK 0x000000F0L 82 #define DAGB0_RDCLI2__URG_LOW_MASK 0x00000F00L 83 #define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L 84 #define DAGB0_RDCLI2__MAX_BW_MASK 0x001FE000L 85 #define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L 86 #define DAGB0_RDCLI2__MIN_BW_MASK 0x01C00000L 87 #define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 88 #define DAGB0_RDCLI2__MAX_OSD_MASK 0xFC000000L 89 //DAGB0_RDCLI3 90 #define DAGB0_RDCLI3__VIRT_CHAN__SHIFT 0x0 91 #define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 92 #define DAGB0_RDCLI3__URG_HIGH__SHIFT 0x4 93 #define DAGB0_RDCLI3__URG_LOW__SHIFT 0x8 94 #define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc 95 #define DAGB0_RDCLI3__MAX_BW__SHIFT 0xd 96 #define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 97 #define DAGB0_RDCLI3__MIN_BW__SHIFT 0x16 98 #define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 99 #define DAGB0_RDCLI3__MAX_OSD__SHIFT 0x1a 100 #define DAGB0_RDCLI3__VIRT_CHAN_MASK 0x00000007L 101 #define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 102 #define DAGB0_RDCLI3__URG_HIGH_MASK 0x000000F0L 103 #define DAGB0_RDCLI3__URG_LOW_MASK 0x00000F00L 104 #define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L 105 #define DAGB0_RDCLI3__MAX_BW_MASK 0x001FE000L 106 #define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L 107 #define DAGB0_RDCLI3__MIN_BW_MASK 0x01C00000L 108 #define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 109 #define DAGB0_RDCLI3__MAX_OSD_MASK 0xFC000000L 110 //DAGB0_RDCLI4 111 #define DAGB0_RDCLI4__VIRT_CHAN__SHIFT 0x0 112 #define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 113 #define DAGB0_RDCLI4__URG_HIGH__SHIFT 0x4 114 #define DAGB0_RDCLI4__URG_LOW__SHIFT 0x8 115 #define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc 116 #define DAGB0_RDCLI4__MAX_BW__SHIFT 0xd 117 #define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 118 #define DAGB0_RDCLI4__MIN_BW__SHIFT 0x16 119 #define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 120 #define DAGB0_RDCLI4__MAX_OSD__SHIFT 0x1a 121 #define DAGB0_RDCLI4__VIRT_CHAN_MASK 0x00000007L 122 #define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 123 #define DAGB0_RDCLI4__URG_HIGH_MASK 0x000000F0L 124 #define DAGB0_RDCLI4__URG_LOW_MASK 0x00000F00L 125 #define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L 126 #define DAGB0_RDCLI4__MAX_BW_MASK 0x001FE000L 127 #define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L 128 #define DAGB0_RDCLI4__MIN_BW_MASK 0x01C00000L 129 #define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 130 #define DAGB0_RDCLI4__MAX_OSD_MASK 0xFC000000L 131 //DAGB0_RDCLI5 132 #define DAGB0_RDCLI5__VIRT_CHAN__SHIFT 0x0 133 #define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 134 #define DAGB0_RDCLI5__URG_HIGH__SHIFT 0x4 135 #define DAGB0_RDCLI5__URG_LOW__SHIFT 0x8 136 #define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc 137 #define DAGB0_RDCLI5__MAX_BW__SHIFT 0xd 138 #define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 139 #define DAGB0_RDCLI5__MIN_BW__SHIFT 0x16 140 #define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 141 #define DAGB0_RDCLI5__MAX_OSD__SHIFT 0x1a 142 #define DAGB0_RDCLI5__VIRT_CHAN_MASK 0x00000007L 143 #define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 144 #define DAGB0_RDCLI5__URG_HIGH_MASK 0x000000F0L 145 #define DAGB0_RDCLI5__URG_LOW_MASK 0x00000F00L 146 #define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L 147 #define DAGB0_RDCLI5__MAX_BW_MASK 0x001FE000L 148 #define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L 149 #define DAGB0_RDCLI5__MIN_BW_MASK 0x01C00000L 150 #define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 151 #define DAGB0_RDCLI5__MAX_OSD_MASK 0xFC000000L 152 //DAGB0_RDCLI6 153 #define DAGB0_RDCLI6__VIRT_CHAN__SHIFT 0x0 154 #define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 155 #define DAGB0_RDCLI6__URG_HIGH__SHIFT 0x4 156 #define DAGB0_RDCLI6__URG_LOW__SHIFT 0x8 157 #define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc 158 #define DAGB0_RDCLI6__MAX_BW__SHIFT 0xd 159 #define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 160 #define DAGB0_RDCLI6__MIN_BW__SHIFT 0x16 161 #define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 162 #define DAGB0_RDCLI6__MAX_OSD__SHIFT 0x1a 163 #define DAGB0_RDCLI6__VIRT_CHAN_MASK 0x00000007L 164 #define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 165 #define DAGB0_RDCLI6__URG_HIGH_MASK 0x000000F0L 166 #define DAGB0_RDCLI6__URG_LOW_MASK 0x00000F00L 167 #define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L 168 #define DAGB0_RDCLI6__MAX_BW_MASK 0x001FE000L 169 #define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L 170 #define DAGB0_RDCLI6__MIN_BW_MASK 0x01C00000L 171 #define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 172 #define DAGB0_RDCLI6__MAX_OSD_MASK 0xFC000000L 173 //DAGB0_RDCLI7 174 #define DAGB0_RDCLI7__VIRT_CHAN__SHIFT 0x0 175 #define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 176 #define DAGB0_RDCLI7__URG_HIGH__SHIFT 0x4 177 #define DAGB0_RDCLI7__URG_LOW__SHIFT 0x8 178 #define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc 179 #define DAGB0_RDCLI7__MAX_BW__SHIFT 0xd 180 #define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 181 #define DAGB0_RDCLI7__MIN_BW__SHIFT 0x16 182 #define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 183 #define DAGB0_RDCLI7__MAX_OSD__SHIFT 0x1a 184 #define DAGB0_RDCLI7__VIRT_CHAN_MASK 0x00000007L 185 #define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 186 #define DAGB0_RDCLI7__URG_HIGH_MASK 0x000000F0L 187 #define DAGB0_RDCLI7__URG_LOW_MASK 0x00000F00L 188 #define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L 189 #define DAGB0_RDCLI7__MAX_BW_MASK 0x001FE000L 190 #define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L 191 #define DAGB0_RDCLI7__MIN_BW_MASK 0x01C00000L 192 #define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 193 #define DAGB0_RDCLI7__MAX_OSD_MASK 0xFC000000L 194 //DAGB0_RDCLI8 195 #define DAGB0_RDCLI8__VIRT_CHAN__SHIFT 0x0 196 #define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 197 #define DAGB0_RDCLI8__URG_HIGH__SHIFT 0x4 198 #define DAGB0_RDCLI8__URG_LOW__SHIFT 0x8 199 #define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc 200 #define DAGB0_RDCLI8__MAX_BW__SHIFT 0xd 201 #define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 202 #define DAGB0_RDCLI8__MIN_BW__SHIFT 0x16 203 #define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 204 #define DAGB0_RDCLI8__MAX_OSD__SHIFT 0x1a 205 #define DAGB0_RDCLI8__VIRT_CHAN_MASK 0x00000007L 206 #define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 207 #define DAGB0_RDCLI8__URG_HIGH_MASK 0x000000F0L 208 #define DAGB0_RDCLI8__URG_LOW_MASK 0x00000F00L 209 #define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L 210 #define DAGB0_RDCLI8__MAX_BW_MASK 0x001FE000L 211 #define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L 212 #define DAGB0_RDCLI8__MIN_BW_MASK 0x01C00000L 213 #define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 214 #define DAGB0_RDCLI8__MAX_OSD_MASK 0xFC000000L 215 //DAGB0_RDCLI9 216 #define DAGB0_RDCLI9__VIRT_CHAN__SHIFT 0x0 217 #define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 218 #define DAGB0_RDCLI9__URG_HIGH__SHIFT 0x4 219 #define DAGB0_RDCLI9__URG_LOW__SHIFT 0x8 220 #define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc 221 #define DAGB0_RDCLI9__MAX_BW__SHIFT 0xd 222 #define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 223 #define DAGB0_RDCLI9__MIN_BW__SHIFT 0x16 224 #define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 225 #define DAGB0_RDCLI9__MAX_OSD__SHIFT 0x1a 226 #define DAGB0_RDCLI9__VIRT_CHAN_MASK 0x00000007L 227 #define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 228 #define DAGB0_RDCLI9__URG_HIGH_MASK 0x000000F0L 229 #define DAGB0_RDCLI9__URG_LOW_MASK 0x00000F00L 230 #define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L 231 #define DAGB0_RDCLI9__MAX_BW_MASK 0x001FE000L 232 #define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L 233 #define DAGB0_RDCLI9__MIN_BW_MASK 0x01C00000L 234 #define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 235 #define DAGB0_RDCLI9__MAX_OSD_MASK 0xFC000000L 236 //DAGB0_RDCLI10 237 #define DAGB0_RDCLI10__VIRT_CHAN__SHIFT 0x0 238 #define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 239 #define DAGB0_RDCLI10__URG_HIGH__SHIFT 0x4 240 #define DAGB0_RDCLI10__URG_LOW__SHIFT 0x8 241 #define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc 242 #define DAGB0_RDCLI10__MAX_BW__SHIFT 0xd 243 #define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 244 #define DAGB0_RDCLI10__MIN_BW__SHIFT 0x16 245 #define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 246 #define DAGB0_RDCLI10__MAX_OSD__SHIFT 0x1a 247 #define DAGB0_RDCLI10__VIRT_CHAN_MASK 0x00000007L 248 #define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 249 #define DAGB0_RDCLI10__URG_HIGH_MASK 0x000000F0L 250 #define DAGB0_RDCLI10__URG_LOW_MASK 0x00000F00L 251 #define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L 252 #define DAGB0_RDCLI10__MAX_BW_MASK 0x001FE000L 253 #define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L 254 #define DAGB0_RDCLI10__MIN_BW_MASK 0x01C00000L 255 #define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 256 #define DAGB0_RDCLI10__MAX_OSD_MASK 0xFC000000L 257 //DAGB0_RDCLI11 258 #define DAGB0_RDCLI11__VIRT_CHAN__SHIFT 0x0 259 #define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 260 #define DAGB0_RDCLI11__URG_HIGH__SHIFT 0x4 261 #define DAGB0_RDCLI11__URG_LOW__SHIFT 0x8 262 #define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc 263 #define DAGB0_RDCLI11__MAX_BW__SHIFT 0xd 264 #define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 265 #define DAGB0_RDCLI11__MIN_BW__SHIFT 0x16 266 #define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 267 #define DAGB0_RDCLI11__MAX_OSD__SHIFT 0x1a 268 #define DAGB0_RDCLI11__VIRT_CHAN_MASK 0x00000007L 269 #define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 270 #define DAGB0_RDCLI11__URG_HIGH_MASK 0x000000F0L 271 #define DAGB0_RDCLI11__URG_LOW_MASK 0x00000F00L 272 #define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L 273 #define DAGB0_RDCLI11__MAX_BW_MASK 0x001FE000L 274 #define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L 275 #define DAGB0_RDCLI11__MIN_BW_MASK 0x01C00000L 276 #define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 277 #define DAGB0_RDCLI11__MAX_OSD_MASK 0xFC000000L 278 //DAGB0_RDCLI12 279 #define DAGB0_RDCLI12__VIRT_CHAN__SHIFT 0x0 280 #define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 281 #define DAGB0_RDCLI12__URG_HIGH__SHIFT 0x4 282 #define DAGB0_RDCLI12__URG_LOW__SHIFT 0x8 283 #define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc 284 #define DAGB0_RDCLI12__MAX_BW__SHIFT 0xd 285 #define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 286 #define DAGB0_RDCLI12__MIN_BW__SHIFT 0x16 287 #define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 288 #define DAGB0_RDCLI12__MAX_OSD__SHIFT 0x1a 289 #define DAGB0_RDCLI12__VIRT_CHAN_MASK 0x00000007L 290 #define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 291 #define DAGB0_RDCLI12__URG_HIGH_MASK 0x000000F0L 292 #define DAGB0_RDCLI12__URG_LOW_MASK 0x00000F00L 293 #define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L 294 #define DAGB0_RDCLI12__MAX_BW_MASK 0x001FE000L 295 #define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L 296 #define DAGB0_RDCLI12__MIN_BW_MASK 0x01C00000L 297 #define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 298 #define DAGB0_RDCLI12__MAX_OSD_MASK 0xFC000000L 299 //DAGB0_RDCLI13 300 #define DAGB0_RDCLI13__VIRT_CHAN__SHIFT 0x0 301 #define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 302 #define DAGB0_RDCLI13__URG_HIGH__SHIFT 0x4 303 #define DAGB0_RDCLI13__URG_LOW__SHIFT 0x8 304 #define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc 305 #define DAGB0_RDCLI13__MAX_BW__SHIFT 0xd 306 #define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 307 #define DAGB0_RDCLI13__MIN_BW__SHIFT 0x16 308 #define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 309 #define DAGB0_RDCLI13__MAX_OSD__SHIFT 0x1a 310 #define DAGB0_RDCLI13__VIRT_CHAN_MASK 0x00000007L 311 #define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 312 #define DAGB0_RDCLI13__URG_HIGH_MASK 0x000000F0L 313 #define DAGB0_RDCLI13__URG_LOW_MASK 0x00000F00L 314 #define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L 315 #define DAGB0_RDCLI13__MAX_BW_MASK 0x001FE000L 316 #define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L 317 #define DAGB0_RDCLI13__MIN_BW_MASK 0x01C00000L 318 #define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 319 #define DAGB0_RDCLI13__MAX_OSD_MASK 0xFC000000L 320 //DAGB0_RDCLI14 321 #define DAGB0_RDCLI14__VIRT_CHAN__SHIFT 0x0 322 #define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 323 #define DAGB0_RDCLI14__URG_HIGH__SHIFT 0x4 324 #define DAGB0_RDCLI14__URG_LOW__SHIFT 0x8 325 #define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc 326 #define DAGB0_RDCLI14__MAX_BW__SHIFT 0xd 327 #define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 328 #define DAGB0_RDCLI14__MIN_BW__SHIFT 0x16 329 #define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 330 #define DAGB0_RDCLI14__MAX_OSD__SHIFT 0x1a 331 #define DAGB0_RDCLI14__VIRT_CHAN_MASK 0x00000007L 332 #define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 333 #define DAGB0_RDCLI14__URG_HIGH_MASK 0x000000F0L 334 #define DAGB0_RDCLI14__URG_LOW_MASK 0x00000F00L 335 #define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L 336 #define DAGB0_RDCLI14__MAX_BW_MASK 0x001FE000L 337 #define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L 338 #define DAGB0_RDCLI14__MIN_BW_MASK 0x01C00000L 339 #define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 340 #define DAGB0_RDCLI14__MAX_OSD_MASK 0xFC000000L 341 //DAGB0_RDCLI15 342 #define DAGB0_RDCLI15__VIRT_CHAN__SHIFT 0x0 343 #define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 344 #define DAGB0_RDCLI15__URG_HIGH__SHIFT 0x4 345 #define DAGB0_RDCLI15__URG_LOW__SHIFT 0x8 346 #define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc 347 #define DAGB0_RDCLI15__MAX_BW__SHIFT 0xd 348 #define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 349 #define DAGB0_RDCLI15__MIN_BW__SHIFT 0x16 350 #define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 351 #define DAGB0_RDCLI15__MAX_OSD__SHIFT 0x1a 352 #define DAGB0_RDCLI15__VIRT_CHAN_MASK 0x00000007L 353 #define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 354 #define DAGB0_RDCLI15__URG_HIGH_MASK 0x000000F0L 355 #define DAGB0_RDCLI15__URG_LOW_MASK 0x00000F00L 356 #define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L 357 #define DAGB0_RDCLI15__MAX_BW_MASK 0x001FE000L 358 #define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L 359 #define DAGB0_RDCLI15__MIN_BW_MASK 0x01C00000L 360 #define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 361 #define DAGB0_RDCLI15__MAX_OSD_MASK 0xFC000000L 362 //DAGB0_RD_CNTL 363 #define DAGB0_RD_CNTL__SCLK_FREQ__SHIFT 0x0 364 #define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 365 #define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 366 #define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 367 #define DAGB0_RD_CNTL__IO_LEVEL__SHIFT 0x11 368 #define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 369 #define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 370 #define DAGB0_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL 371 #define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 372 #define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 373 #define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 374 #define DAGB0_RD_CNTL__IO_LEVEL_MASK 0x000E0000L 375 #define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 376 #define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L 377 //DAGB0_RD_GMI_CNTL 378 #define DAGB0_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 379 #define DAGB0_RD_GMI_CNTL__LEVEL__SHIFT 0x6 380 #define DAGB0_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 381 #define DAGB0_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 382 #define DAGB0_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 383 #define DAGB0_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L 384 #define DAGB0_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 385 #define DAGB0_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 386 //DAGB0_RD_ADDR_DAGB 387 #define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 388 #define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 389 #define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 390 #define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 391 #define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 392 #define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 393 #define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 394 #define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 395 //DAGB0_RD_OUTPUT_DAGB_MAX_BURST 396 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 397 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 398 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 399 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 400 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 401 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 402 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 403 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 404 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 405 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 406 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 407 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 408 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 409 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 410 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 411 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 412 //DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER 413 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 414 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 415 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 416 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 417 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 418 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 419 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 420 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 421 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 422 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 423 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 424 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 425 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 426 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 427 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 428 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 429 //DAGB0_RD_CGTT_CLK_CTRL 430 #define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 431 #define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 432 #define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 433 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 434 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 435 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 436 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 437 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 438 #define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 439 #define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 440 #define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 441 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 442 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 443 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 444 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 445 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 446 //DAGB0_L1TLB_RD_CGTT_CLK_CTRL 447 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 448 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 449 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 450 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 451 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 452 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 453 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 454 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 455 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 456 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 457 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 458 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 459 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 460 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 461 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 462 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 463 //DAGB0_ATCVM_RD_CGTT_CLK_CTRL 464 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 465 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 466 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 467 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 468 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 469 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 470 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 471 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 472 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 473 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 474 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 475 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 476 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 477 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 478 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 479 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 480 //DAGB0_RD_ADDR_DAGB_MAX_BURST0 481 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 482 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 483 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 484 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 485 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 486 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 487 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 488 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 489 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 490 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 491 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 492 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 493 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 494 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 495 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 496 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 497 //DAGB0_RD_ADDR_DAGB_LAZY_TIMER0 498 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 499 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 500 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 501 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 502 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 503 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 504 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 505 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 506 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 507 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 508 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 509 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 510 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 511 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 512 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 513 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 514 //DAGB0_RD_ADDR_DAGB_MAX_BURST1 515 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 516 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 517 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 518 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 519 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 520 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 521 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 522 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 523 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 524 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 525 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 526 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 527 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 528 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 529 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 530 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 531 //DAGB0_RD_ADDR_DAGB_LAZY_TIMER1 532 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 533 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 534 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 535 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 536 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 537 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 538 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 539 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 540 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 541 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 542 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 543 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 544 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 545 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 546 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 547 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 548 //DAGB0_RD_VC0_CNTL 549 #define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 550 #define DAGB0_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 551 #define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 552 #define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT 0xc 553 #define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 554 #define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 555 #define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 556 #define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 557 #define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 558 #define DAGB0_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 559 #define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 560 #define DAGB0_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L 561 #define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 562 #define DAGB0_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L 563 #define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 564 #define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 565 //DAGB0_RD_VC1_CNTL 566 #define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 567 #define DAGB0_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 568 #define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 569 #define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT 0xc 570 #define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 571 #define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 572 #define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 573 #define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 574 #define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 575 #define DAGB0_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 576 #define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 577 #define DAGB0_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L 578 #define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 579 #define DAGB0_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L 580 #define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 581 #define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 582 //DAGB0_RD_VC2_CNTL 583 #define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 584 #define DAGB0_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 585 #define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 586 #define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT 0xc 587 #define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 588 #define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 589 #define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 590 #define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 591 #define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 592 #define DAGB0_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 593 #define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 594 #define DAGB0_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L 595 #define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 596 #define DAGB0_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L 597 #define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 598 #define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 599 //DAGB0_RD_VC3_CNTL 600 #define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 601 #define DAGB0_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 602 #define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 603 #define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT 0xc 604 #define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 605 #define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 606 #define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 607 #define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 608 #define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 609 #define DAGB0_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 610 #define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 611 #define DAGB0_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L 612 #define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 613 #define DAGB0_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L 614 #define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 615 #define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 616 //DAGB0_RD_VC4_CNTL 617 #define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 618 #define DAGB0_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 619 #define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 620 #define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT 0xc 621 #define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 622 #define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 623 #define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 624 #define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 625 #define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 626 #define DAGB0_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 627 #define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 628 #define DAGB0_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L 629 #define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 630 #define DAGB0_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L 631 #define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 632 #define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 633 //DAGB0_RD_VC5_CNTL 634 #define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 635 #define DAGB0_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 636 #define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 637 #define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT 0xc 638 #define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 639 #define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 640 #define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 641 #define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 642 #define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 643 #define DAGB0_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 644 #define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 645 #define DAGB0_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L 646 #define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 647 #define DAGB0_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L 648 #define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 649 #define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 650 //DAGB0_RD_VC6_CNTL 651 #define DAGB0_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 652 #define DAGB0_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 653 #define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 654 #define DAGB0_RD_VC6_CNTL__MAX_BW__SHIFT 0xc 655 #define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 656 #define DAGB0_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 657 #define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 658 #define DAGB0_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 659 #define DAGB0_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 660 #define DAGB0_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 661 #define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 662 #define DAGB0_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L 663 #define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 664 #define DAGB0_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L 665 #define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 666 #define DAGB0_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 667 //DAGB0_RD_VC7_CNTL 668 #define DAGB0_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 669 #define DAGB0_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 670 #define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 671 #define DAGB0_RD_VC7_CNTL__MAX_BW__SHIFT 0xc 672 #define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 673 #define DAGB0_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 674 #define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 675 #define DAGB0_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 676 #define DAGB0_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 677 #define DAGB0_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 678 #define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 679 #define DAGB0_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L 680 #define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 681 #define DAGB0_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L 682 #define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 683 #define DAGB0_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 684 //DAGB0_RD_CNTL_MISC 685 #define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 686 #define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 687 #define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 688 #define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 689 #define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 690 #define DAGB0_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 691 #define DAGB0_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a 692 #define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 693 #define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 694 #define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 695 #define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 696 #define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 697 #define DAGB0_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 698 #define DAGB0_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L 699 //DAGB0_RD_TLB_CREDIT 700 #define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT 0x0 701 #define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT 0x5 702 #define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT 0xa 703 #define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT 0xf 704 #define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT 0x14 705 #define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT 0x19 706 #define DAGB0_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL 707 #define DAGB0_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L 708 #define DAGB0_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L 709 #define DAGB0_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L 710 #define DAGB0_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L 711 #define DAGB0_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L 712 //DAGB0_RDCLI_ASK_PENDING 713 #define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 714 #define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 715 //DAGB0_RDCLI_GO_PENDING 716 #define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 717 #define DAGB0_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 718 //DAGB0_RDCLI_GBLSEND_PENDING 719 #define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 720 #define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 721 //DAGB0_RDCLI_TLB_PENDING 722 #define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 723 #define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 724 //DAGB0_RDCLI_OARB_PENDING 725 #define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 726 #define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 727 //DAGB0_RDCLI_OSD_PENDING 728 #define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 729 #define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 730 //DAGB0_WRCLI0 731 #define DAGB0_WRCLI0__VIRT_CHAN__SHIFT 0x0 732 #define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 733 #define DAGB0_WRCLI0__URG_HIGH__SHIFT 0x4 734 #define DAGB0_WRCLI0__URG_LOW__SHIFT 0x8 735 #define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc 736 #define DAGB0_WRCLI0__MAX_BW__SHIFT 0xd 737 #define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 738 #define DAGB0_WRCLI0__MIN_BW__SHIFT 0x16 739 #define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 740 #define DAGB0_WRCLI0__MAX_OSD__SHIFT 0x1a 741 #define DAGB0_WRCLI0__VIRT_CHAN_MASK 0x00000007L 742 #define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 743 #define DAGB0_WRCLI0__URG_HIGH_MASK 0x000000F0L 744 #define DAGB0_WRCLI0__URG_LOW_MASK 0x00000F00L 745 #define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L 746 #define DAGB0_WRCLI0__MAX_BW_MASK 0x001FE000L 747 #define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L 748 #define DAGB0_WRCLI0__MIN_BW_MASK 0x01C00000L 749 #define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 750 #define DAGB0_WRCLI0__MAX_OSD_MASK 0xFC000000L 751 //DAGB0_WRCLI1 752 #define DAGB0_WRCLI1__VIRT_CHAN__SHIFT 0x0 753 #define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 754 #define DAGB0_WRCLI1__URG_HIGH__SHIFT 0x4 755 #define DAGB0_WRCLI1__URG_LOW__SHIFT 0x8 756 #define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc 757 #define DAGB0_WRCLI1__MAX_BW__SHIFT 0xd 758 #define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 759 #define DAGB0_WRCLI1__MIN_BW__SHIFT 0x16 760 #define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 761 #define DAGB0_WRCLI1__MAX_OSD__SHIFT 0x1a 762 #define DAGB0_WRCLI1__VIRT_CHAN_MASK 0x00000007L 763 #define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 764 #define DAGB0_WRCLI1__URG_HIGH_MASK 0x000000F0L 765 #define DAGB0_WRCLI1__URG_LOW_MASK 0x00000F00L 766 #define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L 767 #define DAGB0_WRCLI1__MAX_BW_MASK 0x001FE000L 768 #define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L 769 #define DAGB0_WRCLI1__MIN_BW_MASK 0x01C00000L 770 #define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 771 #define DAGB0_WRCLI1__MAX_OSD_MASK 0xFC000000L 772 //DAGB0_WRCLI2 773 #define DAGB0_WRCLI2__VIRT_CHAN__SHIFT 0x0 774 #define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 775 #define DAGB0_WRCLI2__URG_HIGH__SHIFT 0x4 776 #define DAGB0_WRCLI2__URG_LOW__SHIFT 0x8 777 #define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc 778 #define DAGB0_WRCLI2__MAX_BW__SHIFT 0xd 779 #define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 780 #define DAGB0_WRCLI2__MIN_BW__SHIFT 0x16 781 #define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 782 #define DAGB0_WRCLI2__MAX_OSD__SHIFT 0x1a 783 #define DAGB0_WRCLI2__VIRT_CHAN_MASK 0x00000007L 784 #define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 785 #define DAGB0_WRCLI2__URG_HIGH_MASK 0x000000F0L 786 #define DAGB0_WRCLI2__URG_LOW_MASK 0x00000F00L 787 #define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L 788 #define DAGB0_WRCLI2__MAX_BW_MASK 0x001FE000L 789 #define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L 790 #define DAGB0_WRCLI2__MIN_BW_MASK 0x01C00000L 791 #define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 792 #define DAGB0_WRCLI2__MAX_OSD_MASK 0xFC000000L 793 //DAGB0_WRCLI3 794 #define DAGB0_WRCLI3__VIRT_CHAN__SHIFT 0x0 795 #define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 796 #define DAGB0_WRCLI3__URG_HIGH__SHIFT 0x4 797 #define DAGB0_WRCLI3__URG_LOW__SHIFT 0x8 798 #define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc 799 #define DAGB0_WRCLI3__MAX_BW__SHIFT 0xd 800 #define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 801 #define DAGB0_WRCLI3__MIN_BW__SHIFT 0x16 802 #define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 803 #define DAGB0_WRCLI3__MAX_OSD__SHIFT 0x1a 804 #define DAGB0_WRCLI3__VIRT_CHAN_MASK 0x00000007L 805 #define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 806 #define DAGB0_WRCLI3__URG_HIGH_MASK 0x000000F0L 807 #define DAGB0_WRCLI3__URG_LOW_MASK 0x00000F00L 808 #define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L 809 #define DAGB0_WRCLI3__MAX_BW_MASK 0x001FE000L 810 #define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L 811 #define DAGB0_WRCLI3__MIN_BW_MASK 0x01C00000L 812 #define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 813 #define DAGB0_WRCLI3__MAX_OSD_MASK 0xFC000000L 814 //DAGB0_WRCLI4 815 #define DAGB0_WRCLI4__VIRT_CHAN__SHIFT 0x0 816 #define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 817 #define DAGB0_WRCLI4__URG_HIGH__SHIFT 0x4 818 #define DAGB0_WRCLI4__URG_LOW__SHIFT 0x8 819 #define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc 820 #define DAGB0_WRCLI4__MAX_BW__SHIFT 0xd 821 #define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 822 #define DAGB0_WRCLI4__MIN_BW__SHIFT 0x16 823 #define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 824 #define DAGB0_WRCLI4__MAX_OSD__SHIFT 0x1a 825 #define DAGB0_WRCLI4__VIRT_CHAN_MASK 0x00000007L 826 #define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 827 #define DAGB0_WRCLI4__URG_HIGH_MASK 0x000000F0L 828 #define DAGB0_WRCLI4__URG_LOW_MASK 0x00000F00L 829 #define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L 830 #define DAGB0_WRCLI4__MAX_BW_MASK 0x001FE000L 831 #define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L 832 #define DAGB0_WRCLI4__MIN_BW_MASK 0x01C00000L 833 #define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 834 #define DAGB0_WRCLI4__MAX_OSD_MASK 0xFC000000L 835 //DAGB0_WRCLI5 836 #define DAGB0_WRCLI5__VIRT_CHAN__SHIFT 0x0 837 #define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 838 #define DAGB0_WRCLI5__URG_HIGH__SHIFT 0x4 839 #define DAGB0_WRCLI5__URG_LOW__SHIFT 0x8 840 #define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc 841 #define DAGB0_WRCLI5__MAX_BW__SHIFT 0xd 842 #define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 843 #define DAGB0_WRCLI5__MIN_BW__SHIFT 0x16 844 #define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 845 #define DAGB0_WRCLI5__MAX_OSD__SHIFT 0x1a 846 #define DAGB0_WRCLI5__VIRT_CHAN_MASK 0x00000007L 847 #define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 848 #define DAGB0_WRCLI5__URG_HIGH_MASK 0x000000F0L 849 #define DAGB0_WRCLI5__URG_LOW_MASK 0x00000F00L 850 #define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L 851 #define DAGB0_WRCLI5__MAX_BW_MASK 0x001FE000L 852 #define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L 853 #define DAGB0_WRCLI5__MIN_BW_MASK 0x01C00000L 854 #define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 855 #define DAGB0_WRCLI5__MAX_OSD_MASK 0xFC000000L 856 //DAGB0_WRCLI6 857 #define DAGB0_WRCLI6__VIRT_CHAN__SHIFT 0x0 858 #define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 859 #define DAGB0_WRCLI6__URG_HIGH__SHIFT 0x4 860 #define DAGB0_WRCLI6__URG_LOW__SHIFT 0x8 861 #define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc 862 #define DAGB0_WRCLI6__MAX_BW__SHIFT 0xd 863 #define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 864 #define DAGB0_WRCLI6__MIN_BW__SHIFT 0x16 865 #define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 866 #define DAGB0_WRCLI6__MAX_OSD__SHIFT 0x1a 867 #define DAGB0_WRCLI6__VIRT_CHAN_MASK 0x00000007L 868 #define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 869 #define DAGB0_WRCLI6__URG_HIGH_MASK 0x000000F0L 870 #define DAGB0_WRCLI6__URG_LOW_MASK 0x00000F00L 871 #define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L 872 #define DAGB0_WRCLI6__MAX_BW_MASK 0x001FE000L 873 #define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L 874 #define DAGB0_WRCLI6__MIN_BW_MASK 0x01C00000L 875 #define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 876 #define DAGB0_WRCLI6__MAX_OSD_MASK 0xFC000000L 877 //DAGB0_WRCLI7 878 #define DAGB0_WRCLI7__VIRT_CHAN__SHIFT 0x0 879 #define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 880 #define DAGB0_WRCLI7__URG_HIGH__SHIFT 0x4 881 #define DAGB0_WRCLI7__URG_LOW__SHIFT 0x8 882 #define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc 883 #define DAGB0_WRCLI7__MAX_BW__SHIFT 0xd 884 #define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 885 #define DAGB0_WRCLI7__MIN_BW__SHIFT 0x16 886 #define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 887 #define DAGB0_WRCLI7__MAX_OSD__SHIFT 0x1a 888 #define DAGB0_WRCLI7__VIRT_CHAN_MASK 0x00000007L 889 #define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 890 #define DAGB0_WRCLI7__URG_HIGH_MASK 0x000000F0L 891 #define DAGB0_WRCLI7__URG_LOW_MASK 0x00000F00L 892 #define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L 893 #define DAGB0_WRCLI7__MAX_BW_MASK 0x001FE000L 894 #define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L 895 #define DAGB0_WRCLI7__MIN_BW_MASK 0x01C00000L 896 #define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 897 #define DAGB0_WRCLI7__MAX_OSD_MASK 0xFC000000L 898 //DAGB0_WRCLI8 899 #define DAGB0_WRCLI8__VIRT_CHAN__SHIFT 0x0 900 #define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 901 #define DAGB0_WRCLI8__URG_HIGH__SHIFT 0x4 902 #define DAGB0_WRCLI8__URG_LOW__SHIFT 0x8 903 #define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc 904 #define DAGB0_WRCLI8__MAX_BW__SHIFT 0xd 905 #define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 906 #define DAGB0_WRCLI8__MIN_BW__SHIFT 0x16 907 #define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 908 #define DAGB0_WRCLI8__MAX_OSD__SHIFT 0x1a 909 #define DAGB0_WRCLI8__VIRT_CHAN_MASK 0x00000007L 910 #define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 911 #define DAGB0_WRCLI8__URG_HIGH_MASK 0x000000F0L 912 #define DAGB0_WRCLI8__URG_LOW_MASK 0x00000F00L 913 #define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L 914 #define DAGB0_WRCLI8__MAX_BW_MASK 0x001FE000L 915 #define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L 916 #define DAGB0_WRCLI8__MIN_BW_MASK 0x01C00000L 917 #define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 918 #define DAGB0_WRCLI8__MAX_OSD_MASK 0xFC000000L 919 //DAGB0_WRCLI9 920 #define DAGB0_WRCLI9__VIRT_CHAN__SHIFT 0x0 921 #define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 922 #define DAGB0_WRCLI9__URG_HIGH__SHIFT 0x4 923 #define DAGB0_WRCLI9__URG_LOW__SHIFT 0x8 924 #define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc 925 #define DAGB0_WRCLI9__MAX_BW__SHIFT 0xd 926 #define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 927 #define DAGB0_WRCLI9__MIN_BW__SHIFT 0x16 928 #define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 929 #define DAGB0_WRCLI9__MAX_OSD__SHIFT 0x1a 930 #define DAGB0_WRCLI9__VIRT_CHAN_MASK 0x00000007L 931 #define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 932 #define DAGB0_WRCLI9__URG_HIGH_MASK 0x000000F0L 933 #define DAGB0_WRCLI9__URG_LOW_MASK 0x00000F00L 934 #define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L 935 #define DAGB0_WRCLI9__MAX_BW_MASK 0x001FE000L 936 #define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L 937 #define DAGB0_WRCLI9__MIN_BW_MASK 0x01C00000L 938 #define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 939 #define DAGB0_WRCLI9__MAX_OSD_MASK 0xFC000000L 940 //DAGB0_WRCLI10 941 #define DAGB0_WRCLI10__VIRT_CHAN__SHIFT 0x0 942 #define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 943 #define DAGB0_WRCLI10__URG_HIGH__SHIFT 0x4 944 #define DAGB0_WRCLI10__URG_LOW__SHIFT 0x8 945 #define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc 946 #define DAGB0_WRCLI10__MAX_BW__SHIFT 0xd 947 #define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 948 #define DAGB0_WRCLI10__MIN_BW__SHIFT 0x16 949 #define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 950 #define DAGB0_WRCLI10__MAX_OSD__SHIFT 0x1a 951 #define DAGB0_WRCLI10__VIRT_CHAN_MASK 0x00000007L 952 #define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 953 #define DAGB0_WRCLI10__URG_HIGH_MASK 0x000000F0L 954 #define DAGB0_WRCLI10__URG_LOW_MASK 0x00000F00L 955 #define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L 956 #define DAGB0_WRCLI10__MAX_BW_MASK 0x001FE000L 957 #define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L 958 #define DAGB0_WRCLI10__MIN_BW_MASK 0x01C00000L 959 #define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 960 #define DAGB0_WRCLI10__MAX_OSD_MASK 0xFC000000L 961 //DAGB0_WRCLI11 962 #define DAGB0_WRCLI11__VIRT_CHAN__SHIFT 0x0 963 #define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 964 #define DAGB0_WRCLI11__URG_HIGH__SHIFT 0x4 965 #define DAGB0_WRCLI11__URG_LOW__SHIFT 0x8 966 #define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc 967 #define DAGB0_WRCLI11__MAX_BW__SHIFT 0xd 968 #define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 969 #define DAGB0_WRCLI11__MIN_BW__SHIFT 0x16 970 #define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 971 #define DAGB0_WRCLI11__MAX_OSD__SHIFT 0x1a 972 #define DAGB0_WRCLI11__VIRT_CHAN_MASK 0x00000007L 973 #define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 974 #define DAGB0_WRCLI11__URG_HIGH_MASK 0x000000F0L 975 #define DAGB0_WRCLI11__URG_LOW_MASK 0x00000F00L 976 #define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L 977 #define DAGB0_WRCLI11__MAX_BW_MASK 0x001FE000L 978 #define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L 979 #define DAGB0_WRCLI11__MIN_BW_MASK 0x01C00000L 980 #define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 981 #define DAGB0_WRCLI11__MAX_OSD_MASK 0xFC000000L 982 //DAGB0_WRCLI12 983 #define DAGB0_WRCLI12__VIRT_CHAN__SHIFT 0x0 984 #define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 985 #define DAGB0_WRCLI12__URG_HIGH__SHIFT 0x4 986 #define DAGB0_WRCLI12__URG_LOW__SHIFT 0x8 987 #define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc 988 #define DAGB0_WRCLI12__MAX_BW__SHIFT 0xd 989 #define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 990 #define DAGB0_WRCLI12__MIN_BW__SHIFT 0x16 991 #define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 992 #define DAGB0_WRCLI12__MAX_OSD__SHIFT 0x1a 993 #define DAGB0_WRCLI12__VIRT_CHAN_MASK 0x00000007L 994 #define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 995 #define DAGB0_WRCLI12__URG_HIGH_MASK 0x000000F0L 996 #define DAGB0_WRCLI12__URG_LOW_MASK 0x00000F00L 997 #define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L 998 #define DAGB0_WRCLI12__MAX_BW_MASK 0x001FE000L 999 #define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L 1000 #define DAGB0_WRCLI12__MIN_BW_MASK 0x01C00000L 1001 #define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 1002 #define DAGB0_WRCLI12__MAX_OSD_MASK 0xFC000000L 1003 //DAGB0_WRCLI13 1004 #define DAGB0_WRCLI13__VIRT_CHAN__SHIFT 0x0 1005 #define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 1006 #define DAGB0_WRCLI13__URG_HIGH__SHIFT 0x4 1007 #define DAGB0_WRCLI13__URG_LOW__SHIFT 0x8 1008 #define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc 1009 #define DAGB0_WRCLI13__MAX_BW__SHIFT 0xd 1010 #define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 1011 #define DAGB0_WRCLI13__MIN_BW__SHIFT 0x16 1012 #define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 1013 #define DAGB0_WRCLI13__MAX_OSD__SHIFT 0x1a 1014 #define DAGB0_WRCLI13__VIRT_CHAN_MASK 0x00000007L 1015 #define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 1016 #define DAGB0_WRCLI13__URG_HIGH_MASK 0x000000F0L 1017 #define DAGB0_WRCLI13__URG_LOW_MASK 0x00000F00L 1018 #define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L 1019 #define DAGB0_WRCLI13__MAX_BW_MASK 0x001FE000L 1020 #define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L 1021 #define DAGB0_WRCLI13__MIN_BW_MASK 0x01C00000L 1022 #define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 1023 #define DAGB0_WRCLI13__MAX_OSD_MASK 0xFC000000L 1024 //DAGB0_WRCLI14 1025 #define DAGB0_WRCLI14__VIRT_CHAN__SHIFT 0x0 1026 #define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 1027 #define DAGB0_WRCLI14__URG_HIGH__SHIFT 0x4 1028 #define DAGB0_WRCLI14__URG_LOW__SHIFT 0x8 1029 #define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc 1030 #define DAGB0_WRCLI14__MAX_BW__SHIFT 0xd 1031 #define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 1032 #define DAGB0_WRCLI14__MIN_BW__SHIFT 0x16 1033 #define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 1034 #define DAGB0_WRCLI14__MAX_OSD__SHIFT 0x1a 1035 #define DAGB0_WRCLI14__VIRT_CHAN_MASK 0x00000007L 1036 #define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 1037 #define DAGB0_WRCLI14__URG_HIGH_MASK 0x000000F0L 1038 #define DAGB0_WRCLI14__URG_LOW_MASK 0x00000F00L 1039 #define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L 1040 #define DAGB0_WRCLI14__MAX_BW_MASK 0x001FE000L 1041 #define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L 1042 #define DAGB0_WRCLI14__MIN_BW_MASK 0x01C00000L 1043 #define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 1044 #define DAGB0_WRCLI14__MAX_OSD_MASK 0xFC000000L 1045 //DAGB0_WRCLI15 1046 #define DAGB0_WRCLI15__VIRT_CHAN__SHIFT 0x0 1047 #define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 1048 #define DAGB0_WRCLI15__URG_HIGH__SHIFT 0x4 1049 #define DAGB0_WRCLI15__URG_LOW__SHIFT 0x8 1050 #define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc 1051 #define DAGB0_WRCLI15__MAX_BW__SHIFT 0xd 1052 #define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 1053 #define DAGB0_WRCLI15__MIN_BW__SHIFT 0x16 1054 #define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 1055 #define DAGB0_WRCLI15__MAX_OSD__SHIFT 0x1a 1056 #define DAGB0_WRCLI15__VIRT_CHAN_MASK 0x00000007L 1057 #define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 1058 #define DAGB0_WRCLI15__URG_HIGH_MASK 0x000000F0L 1059 #define DAGB0_WRCLI15__URG_LOW_MASK 0x00000F00L 1060 #define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L 1061 #define DAGB0_WRCLI15__MAX_BW_MASK 0x001FE000L 1062 #define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L 1063 #define DAGB0_WRCLI15__MIN_BW_MASK 0x01C00000L 1064 #define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 1065 #define DAGB0_WRCLI15__MAX_OSD_MASK 0xFC000000L 1066 //DAGB0_WR_CNTL 1067 #define DAGB0_WR_CNTL__SCLK_FREQ__SHIFT 0x0 1068 #define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 1069 #define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 1070 #define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 1071 #define DAGB0_WR_CNTL__IO_LEVEL__SHIFT 0x11 1072 #define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 1073 #define DAGB0_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 1074 #define DAGB0_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL 1075 #define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 1076 #define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 1077 #define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 1078 #define DAGB0_WR_CNTL__IO_LEVEL_MASK 0x000E0000L 1079 #define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 1080 #define DAGB0_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L 1081 //DAGB0_WR_GMI_CNTL 1082 #define DAGB0_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 1083 #define DAGB0_WR_GMI_CNTL__LEVEL__SHIFT 0x6 1084 #define DAGB0_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 1085 #define DAGB0_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 1086 #define DAGB0_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 1087 #define DAGB0_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L 1088 #define DAGB0_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 1089 #define DAGB0_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 1090 //DAGB0_WR_ADDR_DAGB 1091 #define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 1092 #define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 1093 #define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 1094 #define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 1095 #define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 1096 #define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 1097 #define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 1098 #define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 1099 //DAGB0_WR_OUTPUT_DAGB_MAX_BURST 1100 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 1101 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 1102 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 1103 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 1104 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 1105 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 1106 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 1107 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 1108 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 1109 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 1110 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 1111 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 1112 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 1113 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 1114 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 1115 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 1116 //DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER 1117 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 1118 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 1119 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 1120 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 1121 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 1122 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 1123 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 1124 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 1125 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 1126 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 1127 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 1128 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 1129 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 1130 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 1131 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 1132 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 1133 //DAGB0_WR_CGTT_CLK_CTRL 1134 #define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 1135 #define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 1136 #define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 1137 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 1138 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 1139 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 1140 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 1141 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 1142 #define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 1143 #define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 1144 #define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 1145 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 1146 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 1147 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 1148 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 1149 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 1150 //DAGB0_L1TLB_WR_CGTT_CLK_CTRL 1151 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 1152 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 1153 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 1154 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 1155 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 1156 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 1157 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 1158 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 1159 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 1160 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 1161 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 1162 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 1163 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 1164 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 1165 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 1166 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 1167 //DAGB0_ATCVM_WR_CGTT_CLK_CTRL 1168 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 1169 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 1170 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 1171 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 1172 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 1173 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 1174 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 1175 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 1176 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 1177 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 1178 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 1179 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 1180 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 1181 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 1182 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 1183 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 1184 //DAGB0_WR_ADDR_DAGB_MAX_BURST0 1185 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 1186 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 1187 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 1188 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 1189 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 1190 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 1191 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 1192 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 1193 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 1194 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 1195 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 1196 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 1197 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 1198 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 1199 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 1200 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 1201 //DAGB0_WR_ADDR_DAGB_LAZY_TIMER0 1202 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 1203 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 1204 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 1205 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 1206 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 1207 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 1208 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 1209 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 1210 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 1211 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 1212 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 1213 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 1214 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 1215 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 1216 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 1217 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 1218 //DAGB0_WR_ADDR_DAGB_MAX_BURST1 1219 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 1220 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 1221 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 1222 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 1223 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 1224 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 1225 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 1226 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 1227 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 1228 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 1229 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 1230 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 1231 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 1232 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 1233 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 1234 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 1235 //DAGB0_WR_ADDR_DAGB_LAZY_TIMER1 1236 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 1237 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 1238 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 1239 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 1240 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 1241 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 1242 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 1243 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 1244 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 1245 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 1246 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 1247 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 1248 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 1249 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 1250 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 1251 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 1252 //DAGB0_WR_DATA_DAGB 1253 #define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 1254 #define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 1255 #define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 1256 #define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 1257 #define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L 1258 #define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 1259 #define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 1260 #define DAGB0_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L 1261 //DAGB0_WR_DATA_DAGB_MAX_BURST0 1262 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 1263 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 1264 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 1265 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 1266 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 1267 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 1268 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 1269 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 1270 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 1271 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 1272 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 1273 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 1274 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 1275 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 1276 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 1277 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 1278 //DAGB0_WR_DATA_DAGB_LAZY_TIMER0 1279 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 1280 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 1281 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 1282 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 1283 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 1284 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 1285 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 1286 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 1287 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 1288 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 1289 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 1290 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 1291 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 1292 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 1293 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 1294 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 1295 //DAGB0_WR_DATA_DAGB_MAX_BURST1 1296 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 1297 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 1298 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 1299 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 1300 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 1301 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 1302 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 1303 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 1304 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 1305 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 1306 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 1307 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 1308 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 1309 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 1310 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 1311 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 1312 //DAGB0_WR_DATA_DAGB_LAZY_TIMER1 1313 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 1314 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 1315 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 1316 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 1317 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 1318 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 1319 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 1320 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 1321 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 1322 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 1323 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 1324 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 1325 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 1326 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 1327 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 1328 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 1329 //DAGB0_WR_VC0_CNTL 1330 #define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 1331 #define DAGB0_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 1332 #define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1333 #define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT 0xc 1334 #define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1335 #define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 1336 #define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1337 #define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 1338 #define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 1339 #define DAGB0_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 1340 #define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1341 #define DAGB0_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L 1342 #define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1343 #define DAGB0_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L 1344 #define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1345 #define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 1346 //DAGB0_WR_VC1_CNTL 1347 #define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 1348 #define DAGB0_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 1349 #define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1350 #define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT 0xc 1351 #define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1352 #define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 1353 #define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1354 #define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 1355 #define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 1356 #define DAGB0_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 1357 #define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1358 #define DAGB0_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L 1359 #define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1360 #define DAGB0_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L 1361 #define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1362 #define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 1363 //DAGB0_WR_VC2_CNTL 1364 #define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 1365 #define DAGB0_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 1366 #define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1367 #define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT 0xc 1368 #define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1369 #define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 1370 #define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1371 #define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 1372 #define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 1373 #define DAGB0_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 1374 #define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1375 #define DAGB0_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L 1376 #define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1377 #define DAGB0_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L 1378 #define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1379 #define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 1380 //DAGB0_WR_VC3_CNTL 1381 #define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 1382 #define DAGB0_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 1383 #define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1384 #define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT 0xc 1385 #define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1386 #define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 1387 #define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1388 #define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 1389 #define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 1390 #define DAGB0_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 1391 #define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1392 #define DAGB0_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L 1393 #define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1394 #define DAGB0_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L 1395 #define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1396 #define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 1397 //DAGB0_WR_VC4_CNTL 1398 #define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 1399 #define DAGB0_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 1400 #define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1401 #define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT 0xc 1402 #define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1403 #define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 1404 #define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1405 #define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 1406 #define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 1407 #define DAGB0_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 1408 #define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1409 #define DAGB0_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L 1410 #define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1411 #define DAGB0_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L 1412 #define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1413 #define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 1414 //DAGB0_WR_VC5_CNTL 1415 #define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 1416 #define DAGB0_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 1417 #define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1418 #define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT 0xc 1419 #define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1420 #define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 1421 #define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1422 #define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 1423 #define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 1424 #define DAGB0_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 1425 #define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1426 #define DAGB0_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L 1427 #define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1428 #define DAGB0_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L 1429 #define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1430 #define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 1431 //DAGB0_WR_VC6_CNTL 1432 #define DAGB0_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 1433 #define DAGB0_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 1434 #define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1435 #define DAGB0_WR_VC6_CNTL__MAX_BW__SHIFT 0xc 1436 #define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1437 #define DAGB0_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 1438 #define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1439 #define DAGB0_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 1440 #define DAGB0_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 1441 #define DAGB0_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 1442 #define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1443 #define DAGB0_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L 1444 #define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1445 #define DAGB0_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L 1446 #define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1447 #define DAGB0_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 1448 //DAGB0_WR_VC7_CNTL 1449 #define DAGB0_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 1450 #define DAGB0_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 1451 #define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1452 #define DAGB0_WR_VC7_CNTL__MAX_BW__SHIFT 0xc 1453 #define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1454 #define DAGB0_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 1455 #define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1456 #define DAGB0_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 1457 #define DAGB0_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 1458 #define DAGB0_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 1459 #define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1460 #define DAGB0_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L 1461 #define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1462 #define DAGB0_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L 1463 #define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1464 #define DAGB0_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 1465 //DAGB0_WR_CNTL_MISC 1466 #define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 1467 #define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 1468 #define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 1469 #define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 1470 #define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 1471 #define DAGB0_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 1472 #define DAGB0_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a 1473 #define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 1474 #define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 1475 #define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 1476 #define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 1477 #define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 1478 #define DAGB0_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 1479 #define DAGB0_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L 1480 //DAGB0_WR_TLB_CREDIT 1481 #define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT 0x0 1482 #define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT 0x5 1483 #define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT 0xa 1484 #define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT 0xf 1485 #define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT 0x14 1486 #define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT 0x19 1487 #define DAGB0_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL 1488 #define DAGB0_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L 1489 #define DAGB0_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L 1490 #define DAGB0_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L 1491 #define DAGB0_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L 1492 #define DAGB0_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L 1493 //DAGB0_WR_DATA_CREDIT 1494 #define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 1495 #define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 1496 #define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 1497 #define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 1498 #define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL 1499 #define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L 1500 #define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L 1501 #define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L 1502 //DAGB0_WR_MISC_CREDIT 1503 #define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 1504 #define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 1505 #define DAGB0_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 1506 #define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 1507 #define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL 1508 #define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L 1509 #define DAGB0_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L 1510 #define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L 1511 //DAGB0_WRCLI_ASK_PENDING 1512 #define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 1513 #define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 1514 //DAGB0_WRCLI_GO_PENDING 1515 #define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 1516 #define DAGB0_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 1517 //DAGB0_WRCLI_GBLSEND_PENDING 1518 #define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 1519 #define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 1520 //DAGB0_WRCLI_TLB_PENDING 1521 #define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 1522 #define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 1523 //DAGB0_WRCLI_OARB_PENDING 1524 #define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 1525 #define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 1526 //DAGB0_WRCLI_OSD_PENDING 1527 #define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 1528 #define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 1529 //DAGB0_WRCLI_DBUS_ASK_PENDING 1530 #define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 1531 #define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 1532 //DAGB0_WRCLI_DBUS_GO_PENDING 1533 #define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 1534 #define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 1535 //DAGB0_DAGB_DLY 1536 #define DAGB0_DAGB_DLY__DLY__SHIFT 0x0 1537 #define DAGB0_DAGB_DLY__CLI__SHIFT 0x8 1538 #define DAGB0_DAGB_DLY__POS__SHIFT 0x10 1539 #define DAGB0_DAGB_DLY__DLY_MASK 0x000000FFL 1540 #define DAGB0_DAGB_DLY__CLI_MASK 0x0000FF00L 1541 #define DAGB0_DAGB_DLY__POS_MASK 0x000F0000L 1542 //DAGB0_CNTL_MISC 1543 #define DAGB0_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 1544 #define DAGB0_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 1545 #define DAGB0_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 1546 #define DAGB0_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 1547 #define DAGB0_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc 1548 #define DAGB0_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf 1549 #define DAGB0_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 1550 #define DAGB0_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 1551 #define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 1552 #define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e 1553 #define DAGB0_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L 1554 #define DAGB0_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L 1555 #define DAGB0_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L 1556 #define DAGB0_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L 1557 #define DAGB0_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L 1558 #define DAGB0_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L 1559 #define DAGB0_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L 1560 #define DAGB0_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L 1561 #define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L 1562 #define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L 1563 //DAGB0_CNTL_MISC2 1564 #define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 1565 #define DAGB0_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 1566 #define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 1567 #define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 1568 #define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 1569 #define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 1570 #define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 1571 #define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 1572 #define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 1573 #define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 1574 #define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT 0xa 1575 #define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xb 1576 #define DAGB0_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x11 1577 #define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L 1578 #define DAGB0_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L 1579 #define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L 1580 #define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L 1581 #define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L 1582 #define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L 1583 #define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L 1584 #define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L 1585 #define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L 1586 #define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L 1587 #define DAGB0_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L 1588 #define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000800L 1589 #define DAGB0_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x007E0000L 1590 //DAGB0_FIFO_EMPTY 1591 #define DAGB0_FIFO_EMPTY__EMPTY__SHIFT 0x0 1592 #define DAGB0_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL 1593 //DAGB0_FIFO_FULL 1594 #define DAGB0_FIFO_FULL__FULL__SHIFT 0x0 1595 #define DAGB0_FIFO_FULL__FULL_MASK 0x007FFFFFL 1596 //DAGB0_WR_CREDITS_FULL 1597 #define DAGB0_WR_CREDITS_FULL__FULL__SHIFT 0x0 1598 #define DAGB0_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL 1599 //DAGB0_RD_CREDITS_FULL 1600 #define DAGB0_RD_CREDITS_FULL__FULL__SHIFT 0x0 1601 #define DAGB0_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL 1602 //DAGB0_PERFCOUNTER_LO 1603 #define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 1604 #define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 1605 //DAGB0_PERFCOUNTER_HI 1606 #define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 1607 #define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 1608 #define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 1609 #define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 1610 //DAGB0_PERFCOUNTER0_CFG 1611 #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 1612 #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 1613 #define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 1614 #define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 1615 #define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 1616 #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 1617 #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 1618 #define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 1619 #define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 1620 #define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 1621 //DAGB0_PERFCOUNTER1_CFG 1622 #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 1623 #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 1624 #define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 1625 #define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 1626 #define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 1627 #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 1628 #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 1629 #define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 1630 #define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 1631 #define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 1632 //DAGB0_PERFCOUNTER2_CFG 1633 #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 1634 #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 1635 #define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 1636 #define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 1637 #define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 1638 #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 1639 #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 1640 #define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 1641 #define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 1642 #define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 1643 //DAGB0_PERFCOUNTER_RSLT_CNTL 1644 #define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 1645 #define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 1646 #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 1647 #define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 1648 #define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 1649 #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 1650 #define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 1651 #define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 1652 #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 1653 #define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 1654 #define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 1655 #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 1656 //DAGB0_RESERVE0 1657 #define DAGB0_RESERVE0__RESERVE__SHIFT 0x0 1658 #define DAGB0_RESERVE0__RESERVE_MASK 0xFFFFFFFFL 1659 //DAGB0_RESERVE1 1660 #define DAGB0_RESERVE1__RESERVE__SHIFT 0x0 1661 #define DAGB0_RESERVE1__RESERVE_MASK 0xFFFFFFFFL 1662 //DAGB0_RESERVE2 1663 #define DAGB0_RESERVE2__RESERVE__SHIFT 0x0 1664 #define DAGB0_RESERVE2__RESERVE_MASK 0xFFFFFFFFL 1665 //DAGB0_RESERVE3 1666 #define DAGB0_RESERVE3__RESERVE__SHIFT 0x0 1667 #define DAGB0_RESERVE3__RESERVE_MASK 0xFFFFFFFFL 1668 //DAGB0_RESERVE4 1669 #define DAGB0_RESERVE4__RESERVE__SHIFT 0x0 1670 #define DAGB0_RESERVE4__RESERVE_MASK 0xFFFFFFFFL 1671 //DAGB0_RESERVE5 1672 #define DAGB0_RESERVE5__RESERVE__SHIFT 0x0 1673 #define DAGB0_RESERVE5__RESERVE_MASK 0xFFFFFFFFL 1674 //DAGB0_RESERVE6 1675 #define DAGB0_RESERVE6__RESERVE__SHIFT 0x0 1676 #define DAGB0_RESERVE6__RESERVE_MASK 0xFFFFFFFFL 1677 //DAGB0_RESERVE7 1678 #define DAGB0_RESERVE7__RESERVE__SHIFT 0x0 1679 #define DAGB0_RESERVE7__RESERVE_MASK 0xFFFFFFFFL 1680 //DAGB0_RESERVE8 1681 #define DAGB0_RESERVE8__RESERVE__SHIFT 0x0 1682 #define DAGB0_RESERVE8__RESERVE_MASK 0xFFFFFFFFL 1683 //DAGB0_RESERVE9 1684 #define DAGB0_RESERVE9__RESERVE__SHIFT 0x0 1685 #define DAGB0_RESERVE9__RESERVE_MASK 0xFFFFFFFFL 1686 //DAGB0_RESERVE10 1687 #define DAGB0_RESERVE10__RESERVE__SHIFT 0x0 1688 #define DAGB0_RESERVE10__RESERVE_MASK 0xFFFFFFFFL 1689 //DAGB0_RESERVE11 1690 #define DAGB0_RESERVE11__RESERVE__SHIFT 0x0 1691 #define DAGB0_RESERVE11__RESERVE_MASK 0xFFFFFFFFL 1692 //DAGB0_RESERVE12 1693 #define DAGB0_RESERVE12__RESERVE__SHIFT 0x0 1694 #define DAGB0_RESERVE12__RESERVE_MASK 0xFFFFFFFFL 1695 //DAGB0_RESERVE13 1696 #define DAGB0_RESERVE13__RESERVE__SHIFT 0x0 1697 #define DAGB0_RESERVE13__RESERVE_MASK 0xFFFFFFFFL 1698 1699 1700 // addressBlock: mmhub_dagb_dagbdec1 1701 //DAGB1_RDCLI0 1702 #define DAGB1_RDCLI0__VIRT_CHAN__SHIFT 0x0 1703 #define DAGB1_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 1704 #define DAGB1_RDCLI0__URG_HIGH__SHIFT 0x4 1705 #define DAGB1_RDCLI0__URG_LOW__SHIFT 0x8 1706 #define DAGB1_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 1707 #define DAGB1_RDCLI0__MAX_BW__SHIFT 0xd 1708 #define DAGB1_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 1709 #define DAGB1_RDCLI0__MIN_BW__SHIFT 0x16 1710 #define DAGB1_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 1711 #define DAGB1_RDCLI0__MAX_OSD__SHIFT 0x1a 1712 #define DAGB1_RDCLI0__VIRT_CHAN_MASK 0x00000007L 1713 #define DAGB1_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 1714 #define DAGB1_RDCLI0__URG_HIGH_MASK 0x000000F0L 1715 #define DAGB1_RDCLI0__URG_LOW_MASK 0x00000F00L 1716 #define DAGB1_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L 1717 #define DAGB1_RDCLI0__MAX_BW_MASK 0x001FE000L 1718 #define DAGB1_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L 1719 #define DAGB1_RDCLI0__MIN_BW_MASK 0x01C00000L 1720 #define DAGB1_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 1721 #define DAGB1_RDCLI0__MAX_OSD_MASK 0xFC000000L 1722 //DAGB1_RDCLI1 1723 #define DAGB1_RDCLI1__VIRT_CHAN__SHIFT 0x0 1724 #define DAGB1_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 1725 #define DAGB1_RDCLI1__URG_HIGH__SHIFT 0x4 1726 #define DAGB1_RDCLI1__URG_LOW__SHIFT 0x8 1727 #define DAGB1_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc 1728 #define DAGB1_RDCLI1__MAX_BW__SHIFT 0xd 1729 #define DAGB1_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 1730 #define DAGB1_RDCLI1__MIN_BW__SHIFT 0x16 1731 #define DAGB1_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 1732 #define DAGB1_RDCLI1__MAX_OSD__SHIFT 0x1a 1733 #define DAGB1_RDCLI1__VIRT_CHAN_MASK 0x00000007L 1734 #define DAGB1_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 1735 #define DAGB1_RDCLI1__URG_HIGH_MASK 0x000000F0L 1736 #define DAGB1_RDCLI1__URG_LOW_MASK 0x00000F00L 1737 #define DAGB1_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L 1738 #define DAGB1_RDCLI1__MAX_BW_MASK 0x001FE000L 1739 #define DAGB1_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L 1740 #define DAGB1_RDCLI1__MIN_BW_MASK 0x01C00000L 1741 #define DAGB1_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 1742 #define DAGB1_RDCLI1__MAX_OSD_MASK 0xFC000000L 1743 //DAGB1_RDCLI2 1744 #define DAGB1_RDCLI2__VIRT_CHAN__SHIFT 0x0 1745 #define DAGB1_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 1746 #define DAGB1_RDCLI2__URG_HIGH__SHIFT 0x4 1747 #define DAGB1_RDCLI2__URG_LOW__SHIFT 0x8 1748 #define DAGB1_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc 1749 #define DAGB1_RDCLI2__MAX_BW__SHIFT 0xd 1750 #define DAGB1_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 1751 #define DAGB1_RDCLI2__MIN_BW__SHIFT 0x16 1752 #define DAGB1_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 1753 #define DAGB1_RDCLI2__MAX_OSD__SHIFT 0x1a 1754 #define DAGB1_RDCLI2__VIRT_CHAN_MASK 0x00000007L 1755 #define DAGB1_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 1756 #define DAGB1_RDCLI2__URG_HIGH_MASK 0x000000F0L 1757 #define DAGB1_RDCLI2__URG_LOW_MASK 0x00000F00L 1758 #define DAGB1_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L 1759 #define DAGB1_RDCLI2__MAX_BW_MASK 0x001FE000L 1760 #define DAGB1_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L 1761 #define DAGB1_RDCLI2__MIN_BW_MASK 0x01C00000L 1762 #define DAGB1_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 1763 #define DAGB1_RDCLI2__MAX_OSD_MASK 0xFC000000L 1764 //DAGB1_RDCLI3 1765 #define DAGB1_RDCLI3__VIRT_CHAN__SHIFT 0x0 1766 #define DAGB1_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 1767 #define DAGB1_RDCLI3__URG_HIGH__SHIFT 0x4 1768 #define DAGB1_RDCLI3__URG_LOW__SHIFT 0x8 1769 #define DAGB1_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc 1770 #define DAGB1_RDCLI3__MAX_BW__SHIFT 0xd 1771 #define DAGB1_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 1772 #define DAGB1_RDCLI3__MIN_BW__SHIFT 0x16 1773 #define DAGB1_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 1774 #define DAGB1_RDCLI3__MAX_OSD__SHIFT 0x1a 1775 #define DAGB1_RDCLI3__VIRT_CHAN_MASK 0x00000007L 1776 #define DAGB1_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 1777 #define DAGB1_RDCLI3__URG_HIGH_MASK 0x000000F0L 1778 #define DAGB1_RDCLI3__URG_LOW_MASK 0x00000F00L 1779 #define DAGB1_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L 1780 #define DAGB1_RDCLI3__MAX_BW_MASK 0x001FE000L 1781 #define DAGB1_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L 1782 #define DAGB1_RDCLI3__MIN_BW_MASK 0x01C00000L 1783 #define DAGB1_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 1784 #define DAGB1_RDCLI3__MAX_OSD_MASK 0xFC000000L 1785 //DAGB1_RDCLI4 1786 #define DAGB1_RDCLI4__VIRT_CHAN__SHIFT 0x0 1787 #define DAGB1_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 1788 #define DAGB1_RDCLI4__URG_HIGH__SHIFT 0x4 1789 #define DAGB1_RDCLI4__URG_LOW__SHIFT 0x8 1790 #define DAGB1_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc 1791 #define DAGB1_RDCLI4__MAX_BW__SHIFT 0xd 1792 #define DAGB1_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 1793 #define DAGB1_RDCLI4__MIN_BW__SHIFT 0x16 1794 #define DAGB1_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 1795 #define DAGB1_RDCLI4__MAX_OSD__SHIFT 0x1a 1796 #define DAGB1_RDCLI4__VIRT_CHAN_MASK 0x00000007L 1797 #define DAGB1_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 1798 #define DAGB1_RDCLI4__URG_HIGH_MASK 0x000000F0L 1799 #define DAGB1_RDCLI4__URG_LOW_MASK 0x00000F00L 1800 #define DAGB1_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L 1801 #define DAGB1_RDCLI4__MAX_BW_MASK 0x001FE000L 1802 #define DAGB1_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L 1803 #define DAGB1_RDCLI4__MIN_BW_MASK 0x01C00000L 1804 #define DAGB1_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 1805 #define DAGB1_RDCLI4__MAX_OSD_MASK 0xFC000000L 1806 //DAGB1_RDCLI5 1807 #define DAGB1_RDCLI5__VIRT_CHAN__SHIFT 0x0 1808 #define DAGB1_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 1809 #define DAGB1_RDCLI5__URG_HIGH__SHIFT 0x4 1810 #define DAGB1_RDCLI5__URG_LOW__SHIFT 0x8 1811 #define DAGB1_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc 1812 #define DAGB1_RDCLI5__MAX_BW__SHIFT 0xd 1813 #define DAGB1_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 1814 #define DAGB1_RDCLI5__MIN_BW__SHIFT 0x16 1815 #define DAGB1_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 1816 #define DAGB1_RDCLI5__MAX_OSD__SHIFT 0x1a 1817 #define DAGB1_RDCLI5__VIRT_CHAN_MASK 0x00000007L 1818 #define DAGB1_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 1819 #define DAGB1_RDCLI5__URG_HIGH_MASK 0x000000F0L 1820 #define DAGB1_RDCLI5__URG_LOW_MASK 0x00000F00L 1821 #define DAGB1_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L 1822 #define DAGB1_RDCLI5__MAX_BW_MASK 0x001FE000L 1823 #define DAGB1_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L 1824 #define DAGB1_RDCLI5__MIN_BW_MASK 0x01C00000L 1825 #define DAGB1_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 1826 #define DAGB1_RDCLI5__MAX_OSD_MASK 0xFC000000L 1827 //DAGB1_RDCLI6 1828 #define DAGB1_RDCLI6__VIRT_CHAN__SHIFT 0x0 1829 #define DAGB1_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 1830 #define DAGB1_RDCLI6__URG_HIGH__SHIFT 0x4 1831 #define DAGB1_RDCLI6__URG_LOW__SHIFT 0x8 1832 #define DAGB1_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc 1833 #define DAGB1_RDCLI6__MAX_BW__SHIFT 0xd 1834 #define DAGB1_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 1835 #define DAGB1_RDCLI6__MIN_BW__SHIFT 0x16 1836 #define DAGB1_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 1837 #define DAGB1_RDCLI6__MAX_OSD__SHIFT 0x1a 1838 #define DAGB1_RDCLI6__VIRT_CHAN_MASK 0x00000007L 1839 #define DAGB1_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 1840 #define DAGB1_RDCLI6__URG_HIGH_MASK 0x000000F0L 1841 #define DAGB1_RDCLI6__URG_LOW_MASK 0x00000F00L 1842 #define DAGB1_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L 1843 #define DAGB1_RDCLI6__MAX_BW_MASK 0x001FE000L 1844 #define DAGB1_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L 1845 #define DAGB1_RDCLI6__MIN_BW_MASK 0x01C00000L 1846 #define DAGB1_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 1847 #define DAGB1_RDCLI6__MAX_OSD_MASK 0xFC000000L 1848 //DAGB1_RDCLI7 1849 #define DAGB1_RDCLI7__VIRT_CHAN__SHIFT 0x0 1850 #define DAGB1_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 1851 #define DAGB1_RDCLI7__URG_HIGH__SHIFT 0x4 1852 #define DAGB1_RDCLI7__URG_LOW__SHIFT 0x8 1853 #define DAGB1_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc 1854 #define DAGB1_RDCLI7__MAX_BW__SHIFT 0xd 1855 #define DAGB1_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 1856 #define DAGB1_RDCLI7__MIN_BW__SHIFT 0x16 1857 #define DAGB1_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 1858 #define DAGB1_RDCLI7__MAX_OSD__SHIFT 0x1a 1859 #define DAGB1_RDCLI7__VIRT_CHAN_MASK 0x00000007L 1860 #define DAGB1_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 1861 #define DAGB1_RDCLI7__URG_HIGH_MASK 0x000000F0L 1862 #define DAGB1_RDCLI7__URG_LOW_MASK 0x00000F00L 1863 #define DAGB1_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L 1864 #define DAGB1_RDCLI7__MAX_BW_MASK 0x001FE000L 1865 #define DAGB1_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L 1866 #define DAGB1_RDCLI7__MIN_BW_MASK 0x01C00000L 1867 #define DAGB1_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 1868 #define DAGB1_RDCLI7__MAX_OSD_MASK 0xFC000000L 1869 //DAGB1_RDCLI8 1870 #define DAGB1_RDCLI8__VIRT_CHAN__SHIFT 0x0 1871 #define DAGB1_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 1872 #define DAGB1_RDCLI8__URG_HIGH__SHIFT 0x4 1873 #define DAGB1_RDCLI8__URG_LOW__SHIFT 0x8 1874 #define DAGB1_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc 1875 #define DAGB1_RDCLI8__MAX_BW__SHIFT 0xd 1876 #define DAGB1_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 1877 #define DAGB1_RDCLI8__MIN_BW__SHIFT 0x16 1878 #define DAGB1_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 1879 #define DAGB1_RDCLI8__MAX_OSD__SHIFT 0x1a 1880 #define DAGB1_RDCLI8__VIRT_CHAN_MASK 0x00000007L 1881 #define DAGB1_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 1882 #define DAGB1_RDCLI8__URG_HIGH_MASK 0x000000F0L 1883 #define DAGB1_RDCLI8__URG_LOW_MASK 0x00000F00L 1884 #define DAGB1_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L 1885 #define DAGB1_RDCLI8__MAX_BW_MASK 0x001FE000L 1886 #define DAGB1_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L 1887 #define DAGB1_RDCLI8__MIN_BW_MASK 0x01C00000L 1888 #define DAGB1_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 1889 #define DAGB1_RDCLI8__MAX_OSD_MASK 0xFC000000L 1890 //DAGB1_RDCLI9 1891 #define DAGB1_RDCLI9__VIRT_CHAN__SHIFT 0x0 1892 #define DAGB1_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 1893 #define DAGB1_RDCLI9__URG_HIGH__SHIFT 0x4 1894 #define DAGB1_RDCLI9__URG_LOW__SHIFT 0x8 1895 #define DAGB1_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc 1896 #define DAGB1_RDCLI9__MAX_BW__SHIFT 0xd 1897 #define DAGB1_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 1898 #define DAGB1_RDCLI9__MIN_BW__SHIFT 0x16 1899 #define DAGB1_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 1900 #define DAGB1_RDCLI9__MAX_OSD__SHIFT 0x1a 1901 #define DAGB1_RDCLI9__VIRT_CHAN_MASK 0x00000007L 1902 #define DAGB1_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 1903 #define DAGB1_RDCLI9__URG_HIGH_MASK 0x000000F0L 1904 #define DAGB1_RDCLI9__URG_LOW_MASK 0x00000F00L 1905 #define DAGB1_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L 1906 #define DAGB1_RDCLI9__MAX_BW_MASK 0x001FE000L 1907 #define DAGB1_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L 1908 #define DAGB1_RDCLI9__MIN_BW_MASK 0x01C00000L 1909 #define DAGB1_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 1910 #define DAGB1_RDCLI9__MAX_OSD_MASK 0xFC000000L 1911 //DAGB1_RDCLI10 1912 #define DAGB1_RDCLI10__VIRT_CHAN__SHIFT 0x0 1913 #define DAGB1_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 1914 #define DAGB1_RDCLI10__URG_HIGH__SHIFT 0x4 1915 #define DAGB1_RDCLI10__URG_LOW__SHIFT 0x8 1916 #define DAGB1_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc 1917 #define DAGB1_RDCLI10__MAX_BW__SHIFT 0xd 1918 #define DAGB1_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 1919 #define DAGB1_RDCLI10__MIN_BW__SHIFT 0x16 1920 #define DAGB1_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 1921 #define DAGB1_RDCLI10__MAX_OSD__SHIFT 0x1a 1922 #define DAGB1_RDCLI10__VIRT_CHAN_MASK 0x00000007L 1923 #define DAGB1_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 1924 #define DAGB1_RDCLI10__URG_HIGH_MASK 0x000000F0L 1925 #define DAGB1_RDCLI10__URG_LOW_MASK 0x00000F00L 1926 #define DAGB1_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L 1927 #define DAGB1_RDCLI10__MAX_BW_MASK 0x001FE000L 1928 #define DAGB1_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L 1929 #define DAGB1_RDCLI10__MIN_BW_MASK 0x01C00000L 1930 #define DAGB1_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 1931 #define DAGB1_RDCLI10__MAX_OSD_MASK 0xFC000000L 1932 //DAGB1_RDCLI11 1933 #define DAGB1_RDCLI11__VIRT_CHAN__SHIFT 0x0 1934 #define DAGB1_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 1935 #define DAGB1_RDCLI11__URG_HIGH__SHIFT 0x4 1936 #define DAGB1_RDCLI11__URG_LOW__SHIFT 0x8 1937 #define DAGB1_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc 1938 #define DAGB1_RDCLI11__MAX_BW__SHIFT 0xd 1939 #define DAGB1_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 1940 #define DAGB1_RDCLI11__MIN_BW__SHIFT 0x16 1941 #define DAGB1_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 1942 #define DAGB1_RDCLI11__MAX_OSD__SHIFT 0x1a 1943 #define DAGB1_RDCLI11__VIRT_CHAN_MASK 0x00000007L 1944 #define DAGB1_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 1945 #define DAGB1_RDCLI11__URG_HIGH_MASK 0x000000F0L 1946 #define DAGB1_RDCLI11__URG_LOW_MASK 0x00000F00L 1947 #define DAGB1_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L 1948 #define DAGB1_RDCLI11__MAX_BW_MASK 0x001FE000L 1949 #define DAGB1_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L 1950 #define DAGB1_RDCLI11__MIN_BW_MASK 0x01C00000L 1951 #define DAGB1_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 1952 #define DAGB1_RDCLI11__MAX_OSD_MASK 0xFC000000L 1953 //DAGB1_RDCLI12 1954 #define DAGB1_RDCLI12__VIRT_CHAN__SHIFT 0x0 1955 #define DAGB1_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 1956 #define DAGB1_RDCLI12__URG_HIGH__SHIFT 0x4 1957 #define DAGB1_RDCLI12__URG_LOW__SHIFT 0x8 1958 #define DAGB1_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc 1959 #define DAGB1_RDCLI12__MAX_BW__SHIFT 0xd 1960 #define DAGB1_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 1961 #define DAGB1_RDCLI12__MIN_BW__SHIFT 0x16 1962 #define DAGB1_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 1963 #define DAGB1_RDCLI12__MAX_OSD__SHIFT 0x1a 1964 #define DAGB1_RDCLI12__VIRT_CHAN_MASK 0x00000007L 1965 #define DAGB1_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 1966 #define DAGB1_RDCLI12__URG_HIGH_MASK 0x000000F0L 1967 #define DAGB1_RDCLI12__URG_LOW_MASK 0x00000F00L 1968 #define DAGB1_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L 1969 #define DAGB1_RDCLI12__MAX_BW_MASK 0x001FE000L 1970 #define DAGB1_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L 1971 #define DAGB1_RDCLI12__MIN_BW_MASK 0x01C00000L 1972 #define DAGB1_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 1973 #define DAGB1_RDCLI12__MAX_OSD_MASK 0xFC000000L 1974 //DAGB1_RDCLI13 1975 #define DAGB1_RDCLI13__VIRT_CHAN__SHIFT 0x0 1976 #define DAGB1_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 1977 #define DAGB1_RDCLI13__URG_HIGH__SHIFT 0x4 1978 #define DAGB1_RDCLI13__URG_LOW__SHIFT 0x8 1979 #define DAGB1_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc 1980 #define DAGB1_RDCLI13__MAX_BW__SHIFT 0xd 1981 #define DAGB1_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 1982 #define DAGB1_RDCLI13__MIN_BW__SHIFT 0x16 1983 #define DAGB1_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 1984 #define DAGB1_RDCLI13__MAX_OSD__SHIFT 0x1a 1985 #define DAGB1_RDCLI13__VIRT_CHAN_MASK 0x00000007L 1986 #define DAGB1_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 1987 #define DAGB1_RDCLI13__URG_HIGH_MASK 0x000000F0L 1988 #define DAGB1_RDCLI13__URG_LOW_MASK 0x00000F00L 1989 #define DAGB1_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L 1990 #define DAGB1_RDCLI13__MAX_BW_MASK 0x001FE000L 1991 #define DAGB1_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L 1992 #define DAGB1_RDCLI13__MIN_BW_MASK 0x01C00000L 1993 #define DAGB1_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 1994 #define DAGB1_RDCLI13__MAX_OSD_MASK 0xFC000000L 1995 //DAGB1_RDCLI14 1996 #define DAGB1_RDCLI14__VIRT_CHAN__SHIFT 0x0 1997 #define DAGB1_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 1998 #define DAGB1_RDCLI14__URG_HIGH__SHIFT 0x4 1999 #define DAGB1_RDCLI14__URG_LOW__SHIFT 0x8 2000 #define DAGB1_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc 2001 #define DAGB1_RDCLI14__MAX_BW__SHIFT 0xd 2002 #define DAGB1_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 2003 #define DAGB1_RDCLI14__MIN_BW__SHIFT 0x16 2004 #define DAGB1_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 2005 #define DAGB1_RDCLI14__MAX_OSD__SHIFT 0x1a 2006 #define DAGB1_RDCLI14__VIRT_CHAN_MASK 0x00000007L 2007 #define DAGB1_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 2008 #define DAGB1_RDCLI14__URG_HIGH_MASK 0x000000F0L 2009 #define DAGB1_RDCLI14__URG_LOW_MASK 0x00000F00L 2010 #define DAGB1_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L 2011 #define DAGB1_RDCLI14__MAX_BW_MASK 0x001FE000L 2012 #define DAGB1_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L 2013 #define DAGB1_RDCLI14__MIN_BW_MASK 0x01C00000L 2014 #define DAGB1_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 2015 #define DAGB1_RDCLI14__MAX_OSD_MASK 0xFC000000L 2016 //DAGB1_RDCLI15 2017 #define DAGB1_RDCLI15__VIRT_CHAN__SHIFT 0x0 2018 #define DAGB1_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 2019 #define DAGB1_RDCLI15__URG_HIGH__SHIFT 0x4 2020 #define DAGB1_RDCLI15__URG_LOW__SHIFT 0x8 2021 #define DAGB1_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc 2022 #define DAGB1_RDCLI15__MAX_BW__SHIFT 0xd 2023 #define DAGB1_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 2024 #define DAGB1_RDCLI15__MIN_BW__SHIFT 0x16 2025 #define DAGB1_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 2026 #define DAGB1_RDCLI15__MAX_OSD__SHIFT 0x1a 2027 #define DAGB1_RDCLI15__VIRT_CHAN_MASK 0x00000007L 2028 #define DAGB1_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 2029 #define DAGB1_RDCLI15__URG_HIGH_MASK 0x000000F0L 2030 #define DAGB1_RDCLI15__URG_LOW_MASK 0x00000F00L 2031 #define DAGB1_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L 2032 #define DAGB1_RDCLI15__MAX_BW_MASK 0x001FE000L 2033 #define DAGB1_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L 2034 #define DAGB1_RDCLI15__MIN_BW_MASK 0x01C00000L 2035 #define DAGB1_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 2036 #define DAGB1_RDCLI15__MAX_OSD_MASK 0xFC000000L 2037 //DAGB1_RD_CNTL 2038 #define DAGB1_RD_CNTL__SCLK_FREQ__SHIFT 0x0 2039 #define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 2040 #define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 2041 #define DAGB1_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 2042 #define DAGB1_RD_CNTL__IO_LEVEL__SHIFT 0x11 2043 #define DAGB1_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 2044 #define DAGB1_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 2045 #define DAGB1_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL 2046 #define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 2047 #define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 2048 #define DAGB1_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 2049 #define DAGB1_RD_CNTL__IO_LEVEL_MASK 0x000E0000L 2050 #define DAGB1_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 2051 #define DAGB1_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L 2052 //DAGB1_RD_GMI_CNTL 2053 #define DAGB1_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 2054 #define DAGB1_RD_GMI_CNTL__LEVEL__SHIFT 0x6 2055 #define DAGB1_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 2056 #define DAGB1_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 2057 #define DAGB1_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 2058 #define DAGB1_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L 2059 #define DAGB1_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 2060 #define DAGB1_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 2061 //DAGB1_RD_ADDR_DAGB 2062 #define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 2063 #define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 2064 #define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 2065 #define DAGB1_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 2066 #define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 2067 #define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 2068 #define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 2069 #define DAGB1_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 2070 //DAGB1_RD_OUTPUT_DAGB_MAX_BURST 2071 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 2072 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 2073 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 2074 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 2075 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 2076 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 2077 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 2078 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 2079 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 2080 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 2081 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 2082 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 2083 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 2084 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 2085 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 2086 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 2087 //DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER 2088 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 2089 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 2090 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 2091 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 2092 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 2093 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 2094 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 2095 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 2096 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 2097 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 2098 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 2099 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 2100 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 2101 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 2102 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 2103 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 2104 //DAGB1_RD_CGTT_CLK_CTRL 2105 #define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 2106 #define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 2107 #define DAGB1_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 2108 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 2109 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 2110 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 2111 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 2112 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 2113 #define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 2114 #define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 2115 #define DAGB1_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 2116 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 2117 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 2118 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 2119 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 2120 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 2121 //DAGB1_L1TLB_RD_CGTT_CLK_CTRL 2122 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 2123 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 2124 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 2125 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 2126 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 2127 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 2128 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 2129 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 2130 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 2131 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 2132 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 2133 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 2134 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 2135 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 2136 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 2137 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 2138 //DAGB1_ATCVM_RD_CGTT_CLK_CTRL 2139 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 2140 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 2141 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 2142 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 2143 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 2144 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 2145 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 2146 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 2147 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 2148 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 2149 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 2150 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 2151 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 2152 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 2153 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 2154 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 2155 //DAGB1_RD_ADDR_DAGB_MAX_BURST0 2156 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 2157 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 2158 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 2159 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 2160 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 2161 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 2162 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 2163 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 2164 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 2165 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 2166 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 2167 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 2168 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 2169 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 2170 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 2171 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 2172 //DAGB1_RD_ADDR_DAGB_LAZY_TIMER0 2173 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 2174 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 2175 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 2176 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 2177 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 2178 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 2179 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 2180 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 2181 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 2182 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 2183 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 2184 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 2185 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 2186 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 2187 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 2188 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 2189 //DAGB1_RD_ADDR_DAGB_MAX_BURST1 2190 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 2191 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 2192 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 2193 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 2194 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 2195 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 2196 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 2197 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 2198 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 2199 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 2200 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 2201 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 2202 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 2203 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 2204 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 2205 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 2206 //DAGB1_RD_ADDR_DAGB_LAZY_TIMER1 2207 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 2208 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 2209 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 2210 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 2211 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 2212 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 2213 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 2214 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 2215 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 2216 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 2217 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 2218 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 2219 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 2220 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 2221 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 2222 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 2223 //DAGB1_RD_VC0_CNTL 2224 #define DAGB1_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 2225 #define DAGB1_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 2226 #define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2227 #define DAGB1_RD_VC0_CNTL__MAX_BW__SHIFT 0xc 2228 #define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2229 #define DAGB1_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 2230 #define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2231 #define DAGB1_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 2232 #define DAGB1_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 2233 #define DAGB1_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 2234 #define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2235 #define DAGB1_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L 2236 #define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2237 #define DAGB1_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L 2238 #define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2239 #define DAGB1_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 2240 //DAGB1_RD_VC1_CNTL 2241 #define DAGB1_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 2242 #define DAGB1_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 2243 #define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2244 #define DAGB1_RD_VC1_CNTL__MAX_BW__SHIFT 0xc 2245 #define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2246 #define DAGB1_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 2247 #define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2248 #define DAGB1_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 2249 #define DAGB1_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 2250 #define DAGB1_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 2251 #define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2252 #define DAGB1_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L 2253 #define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2254 #define DAGB1_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L 2255 #define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2256 #define DAGB1_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 2257 //DAGB1_RD_VC2_CNTL 2258 #define DAGB1_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 2259 #define DAGB1_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 2260 #define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2261 #define DAGB1_RD_VC2_CNTL__MAX_BW__SHIFT 0xc 2262 #define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2263 #define DAGB1_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 2264 #define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2265 #define DAGB1_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 2266 #define DAGB1_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 2267 #define DAGB1_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 2268 #define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2269 #define DAGB1_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L 2270 #define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2271 #define DAGB1_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L 2272 #define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2273 #define DAGB1_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 2274 //DAGB1_RD_VC3_CNTL 2275 #define DAGB1_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 2276 #define DAGB1_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 2277 #define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2278 #define DAGB1_RD_VC3_CNTL__MAX_BW__SHIFT 0xc 2279 #define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2280 #define DAGB1_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 2281 #define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2282 #define DAGB1_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 2283 #define DAGB1_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 2284 #define DAGB1_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 2285 #define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2286 #define DAGB1_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L 2287 #define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2288 #define DAGB1_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L 2289 #define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2290 #define DAGB1_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 2291 //DAGB1_RD_VC4_CNTL 2292 #define DAGB1_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 2293 #define DAGB1_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 2294 #define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2295 #define DAGB1_RD_VC4_CNTL__MAX_BW__SHIFT 0xc 2296 #define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2297 #define DAGB1_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 2298 #define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2299 #define DAGB1_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 2300 #define DAGB1_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 2301 #define DAGB1_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 2302 #define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2303 #define DAGB1_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L 2304 #define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2305 #define DAGB1_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L 2306 #define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2307 #define DAGB1_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 2308 //DAGB1_RD_VC5_CNTL 2309 #define DAGB1_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 2310 #define DAGB1_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 2311 #define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2312 #define DAGB1_RD_VC5_CNTL__MAX_BW__SHIFT 0xc 2313 #define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2314 #define DAGB1_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 2315 #define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2316 #define DAGB1_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 2317 #define DAGB1_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 2318 #define DAGB1_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 2319 #define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2320 #define DAGB1_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L 2321 #define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2322 #define DAGB1_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L 2323 #define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2324 #define DAGB1_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 2325 //DAGB1_RD_VC6_CNTL 2326 #define DAGB1_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 2327 #define DAGB1_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 2328 #define DAGB1_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2329 #define DAGB1_RD_VC6_CNTL__MAX_BW__SHIFT 0xc 2330 #define DAGB1_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2331 #define DAGB1_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 2332 #define DAGB1_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2333 #define DAGB1_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 2334 #define DAGB1_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 2335 #define DAGB1_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 2336 #define DAGB1_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2337 #define DAGB1_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L 2338 #define DAGB1_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2339 #define DAGB1_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L 2340 #define DAGB1_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2341 #define DAGB1_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 2342 //DAGB1_RD_VC7_CNTL 2343 #define DAGB1_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 2344 #define DAGB1_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 2345 #define DAGB1_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2346 #define DAGB1_RD_VC7_CNTL__MAX_BW__SHIFT 0xc 2347 #define DAGB1_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2348 #define DAGB1_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 2349 #define DAGB1_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2350 #define DAGB1_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 2351 #define DAGB1_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 2352 #define DAGB1_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 2353 #define DAGB1_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2354 #define DAGB1_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L 2355 #define DAGB1_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2356 #define DAGB1_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L 2357 #define DAGB1_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2358 #define DAGB1_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 2359 //DAGB1_RD_CNTL_MISC 2360 #define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 2361 #define DAGB1_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 2362 #define DAGB1_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 2363 #define DAGB1_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 2364 #define DAGB1_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 2365 #define DAGB1_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 2366 #define DAGB1_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a 2367 #define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 2368 #define DAGB1_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 2369 #define DAGB1_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 2370 #define DAGB1_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 2371 #define DAGB1_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 2372 #define DAGB1_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 2373 #define DAGB1_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L 2374 //DAGB1_RD_TLB_CREDIT 2375 #define DAGB1_RD_TLB_CREDIT__TLB0__SHIFT 0x0 2376 #define DAGB1_RD_TLB_CREDIT__TLB1__SHIFT 0x5 2377 #define DAGB1_RD_TLB_CREDIT__TLB2__SHIFT 0xa 2378 #define DAGB1_RD_TLB_CREDIT__TLB3__SHIFT 0xf 2379 #define DAGB1_RD_TLB_CREDIT__TLB4__SHIFT 0x14 2380 #define DAGB1_RD_TLB_CREDIT__TLB5__SHIFT 0x19 2381 #define DAGB1_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL 2382 #define DAGB1_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L 2383 #define DAGB1_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L 2384 #define DAGB1_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L 2385 #define DAGB1_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L 2386 #define DAGB1_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L 2387 //DAGB1_RDCLI_ASK_PENDING 2388 #define DAGB1_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 2389 #define DAGB1_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 2390 //DAGB1_RDCLI_GO_PENDING 2391 #define DAGB1_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 2392 #define DAGB1_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 2393 //DAGB1_RDCLI_GBLSEND_PENDING 2394 #define DAGB1_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 2395 #define DAGB1_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 2396 //DAGB1_RDCLI_TLB_PENDING 2397 #define DAGB1_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 2398 #define DAGB1_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 2399 //DAGB1_RDCLI_OARB_PENDING 2400 #define DAGB1_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 2401 #define DAGB1_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 2402 //DAGB1_RDCLI_OSD_PENDING 2403 #define DAGB1_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 2404 #define DAGB1_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 2405 //DAGB1_WRCLI0 2406 #define DAGB1_WRCLI0__VIRT_CHAN__SHIFT 0x0 2407 #define DAGB1_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 2408 #define DAGB1_WRCLI0__URG_HIGH__SHIFT 0x4 2409 #define DAGB1_WRCLI0__URG_LOW__SHIFT 0x8 2410 #define DAGB1_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc 2411 #define DAGB1_WRCLI0__MAX_BW__SHIFT 0xd 2412 #define DAGB1_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 2413 #define DAGB1_WRCLI0__MIN_BW__SHIFT 0x16 2414 #define DAGB1_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 2415 #define DAGB1_WRCLI0__MAX_OSD__SHIFT 0x1a 2416 #define DAGB1_WRCLI0__VIRT_CHAN_MASK 0x00000007L 2417 #define DAGB1_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 2418 #define DAGB1_WRCLI0__URG_HIGH_MASK 0x000000F0L 2419 #define DAGB1_WRCLI0__URG_LOW_MASK 0x00000F00L 2420 #define DAGB1_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L 2421 #define DAGB1_WRCLI0__MAX_BW_MASK 0x001FE000L 2422 #define DAGB1_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L 2423 #define DAGB1_WRCLI0__MIN_BW_MASK 0x01C00000L 2424 #define DAGB1_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 2425 #define DAGB1_WRCLI0__MAX_OSD_MASK 0xFC000000L 2426 //DAGB1_WRCLI1 2427 #define DAGB1_WRCLI1__VIRT_CHAN__SHIFT 0x0 2428 #define DAGB1_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 2429 #define DAGB1_WRCLI1__URG_HIGH__SHIFT 0x4 2430 #define DAGB1_WRCLI1__URG_LOW__SHIFT 0x8 2431 #define DAGB1_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc 2432 #define DAGB1_WRCLI1__MAX_BW__SHIFT 0xd 2433 #define DAGB1_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 2434 #define DAGB1_WRCLI1__MIN_BW__SHIFT 0x16 2435 #define DAGB1_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 2436 #define DAGB1_WRCLI1__MAX_OSD__SHIFT 0x1a 2437 #define DAGB1_WRCLI1__VIRT_CHAN_MASK 0x00000007L 2438 #define DAGB1_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 2439 #define DAGB1_WRCLI1__URG_HIGH_MASK 0x000000F0L 2440 #define DAGB1_WRCLI1__URG_LOW_MASK 0x00000F00L 2441 #define DAGB1_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L 2442 #define DAGB1_WRCLI1__MAX_BW_MASK 0x001FE000L 2443 #define DAGB1_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L 2444 #define DAGB1_WRCLI1__MIN_BW_MASK 0x01C00000L 2445 #define DAGB1_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 2446 #define DAGB1_WRCLI1__MAX_OSD_MASK 0xFC000000L 2447 //DAGB1_WRCLI2 2448 #define DAGB1_WRCLI2__VIRT_CHAN__SHIFT 0x0 2449 #define DAGB1_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 2450 #define DAGB1_WRCLI2__URG_HIGH__SHIFT 0x4 2451 #define DAGB1_WRCLI2__URG_LOW__SHIFT 0x8 2452 #define DAGB1_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc 2453 #define DAGB1_WRCLI2__MAX_BW__SHIFT 0xd 2454 #define DAGB1_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 2455 #define DAGB1_WRCLI2__MIN_BW__SHIFT 0x16 2456 #define DAGB1_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 2457 #define DAGB1_WRCLI2__MAX_OSD__SHIFT 0x1a 2458 #define DAGB1_WRCLI2__VIRT_CHAN_MASK 0x00000007L 2459 #define DAGB1_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 2460 #define DAGB1_WRCLI2__URG_HIGH_MASK 0x000000F0L 2461 #define DAGB1_WRCLI2__URG_LOW_MASK 0x00000F00L 2462 #define DAGB1_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L 2463 #define DAGB1_WRCLI2__MAX_BW_MASK 0x001FE000L 2464 #define DAGB1_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L 2465 #define DAGB1_WRCLI2__MIN_BW_MASK 0x01C00000L 2466 #define DAGB1_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 2467 #define DAGB1_WRCLI2__MAX_OSD_MASK 0xFC000000L 2468 //DAGB1_WRCLI3 2469 #define DAGB1_WRCLI3__VIRT_CHAN__SHIFT 0x0 2470 #define DAGB1_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 2471 #define DAGB1_WRCLI3__URG_HIGH__SHIFT 0x4 2472 #define DAGB1_WRCLI3__URG_LOW__SHIFT 0x8 2473 #define DAGB1_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc 2474 #define DAGB1_WRCLI3__MAX_BW__SHIFT 0xd 2475 #define DAGB1_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 2476 #define DAGB1_WRCLI3__MIN_BW__SHIFT 0x16 2477 #define DAGB1_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 2478 #define DAGB1_WRCLI3__MAX_OSD__SHIFT 0x1a 2479 #define DAGB1_WRCLI3__VIRT_CHAN_MASK 0x00000007L 2480 #define DAGB1_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 2481 #define DAGB1_WRCLI3__URG_HIGH_MASK 0x000000F0L 2482 #define DAGB1_WRCLI3__URG_LOW_MASK 0x00000F00L 2483 #define DAGB1_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L 2484 #define DAGB1_WRCLI3__MAX_BW_MASK 0x001FE000L 2485 #define DAGB1_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L 2486 #define DAGB1_WRCLI3__MIN_BW_MASK 0x01C00000L 2487 #define DAGB1_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 2488 #define DAGB1_WRCLI3__MAX_OSD_MASK 0xFC000000L 2489 //DAGB1_WRCLI4 2490 #define DAGB1_WRCLI4__VIRT_CHAN__SHIFT 0x0 2491 #define DAGB1_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 2492 #define DAGB1_WRCLI4__URG_HIGH__SHIFT 0x4 2493 #define DAGB1_WRCLI4__URG_LOW__SHIFT 0x8 2494 #define DAGB1_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc 2495 #define DAGB1_WRCLI4__MAX_BW__SHIFT 0xd 2496 #define DAGB1_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 2497 #define DAGB1_WRCLI4__MIN_BW__SHIFT 0x16 2498 #define DAGB1_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 2499 #define DAGB1_WRCLI4__MAX_OSD__SHIFT 0x1a 2500 #define DAGB1_WRCLI4__VIRT_CHAN_MASK 0x00000007L 2501 #define DAGB1_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 2502 #define DAGB1_WRCLI4__URG_HIGH_MASK 0x000000F0L 2503 #define DAGB1_WRCLI4__URG_LOW_MASK 0x00000F00L 2504 #define DAGB1_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L 2505 #define DAGB1_WRCLI4__MAX_BW_MASK 0x001FE000L 2506 #define DAGB1_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L 2507 #define DAGB1_WRCLI4__MIN_BW_MASK 0x01C00000L 2508 #define DAGB1_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 2509 #define DAGB1_WRCLI4__MAX_OSD_MASK 0xFC000000L 2510 //DAGB1_WRCLI5 2511 #define DAGB1_WRCLI5__VIRT_CHAN__SHIFT 0x0 2512 #define DAGB1_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 2513 #define DAGB1_WRCLI5__URG_HIGH__SHIFT 0x4 2514 #define DAGB1_WRCLI5__URG_LOW__SHIFT 0x8 2515 #define DAGB1_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc 2516 #define DAGB1_WRCLI5__MAX_BW__SHIFT 0xd 2517 #define DAGB1_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 2518 #define DAGB1_WRCLI5__MIN_BW__SHIFT 0x16 2519 #define DAGB1_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 2520 #define DAGB1_WRCLI5__MAX_OSD__SHIFT 0x1a 2521 #define DAGB1_WRCLI5__VIRT_CHAN_MASK 0x00000007L 2522 #define DAGB1_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 2523 #define DAGB1_WRCLI5__URG_HIGH_MASK 0x000000F0L 2524 #define DAGB1_WRCLI5__URG_LOW_MASK 0x00000F00L 2525 #define DAGB1_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L 2526 #define DAGB1_WRCLI5__MAX_BW_MASK 0x001FE000L 2527 #define DAGB1_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L 2528 #define DAGB1_WRCLI5__MIN_BW_MASK 0x01C00000L 2529 #define DAGB1_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 2530 #define DAGB1_WRCLI5__MAX_OSD_MASK 0xFC000000L 2531 //DAGB1_WRCLI6 2532 #define DAGB1_WRCLI6__VIRT_CHAN__SHIFT 0x0 2533 #define DAGB1_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 2534 #define DAGB1_WRCLI6__URG_HIGH__SHIFT 0x4 2535 #define DAGB1_WRCLI6__URG_LOW__SHIFT 0x8 2536 #define DAGB1_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc 2537 #define DAGB1_WRCLI6__MAX_BW__SHIFT 0xd 2538 #define DAGB1_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 2539 #define DAGB1_WRCLI6__MIN_BW__SHIFT 0x16 2540 #define DAGB1_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 2541 #define DAGB1_WRCLI6__MAX_OSD__SHIFT 0x1a 2542 #define DAGB1_WRCLI6__VIRT_CHAN_MASK 0x00000007L 2543 #define DAGB1_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 2544 #define DAGB1_WRCLI6__URG_HIGH_MASK 0x000000F0L 2545 #define DAGB1_WRCLI6__URG_LOW_MASK 0x00000F00L 2546 #define DAGB1_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L 2547 #define DAGB1_WRCLI6__MAX_BW_MASK 0x001FE000L 2548 #define DAGB1_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L 2549 #define DAGB1_WRCLI6__MIN_BW_MASK 0x01C00000L 2550 #define DAGB1_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 2551 #define DAGB1_WRCLI6__MAX_OSD_MASK 0xFC000000L 2552 //DAGB1_WRCLI7 2553 #define DAGB1_WRCLI7__VIRT_CHAN__SHIFT 0x0 2554 #define DAGB1_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 2555 #define DAGB1_WRCLI7__URG_HIGH__SHIFT 0x4 2556 #define DAGB1_WRCLI7__URG_LOW__SHIFT 0x8 2557 #define DAGB1_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc 2558 #define DAGB1_WRCLI7__MAX_BW__SHIFT 0xd 2559 #define DAGB1_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 2560 #define DAGB1_WRCLI7__MIN_BW__SHIFT 0x16 2561 #define DAGB1_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 2562 #define DAGB1_WRCLI7__MAX_OSD__SHIFT 0x1a 2563 #define DAGB1_WRCLI7__VIRT_CHAN_MASK 0x00000007L 2564 #define DAGB1_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 2565 #define DAGB1_WRCLI7__URG_HIGH_MASK 0x000000F0L 2566 #define DAGB1_WRCLI7__URG_LOW_MASK 0x00000F00L 2567 #define DAGB1_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L 2568 #define DAGB1_WRCLI7__MAX_BW_MASK 0x001FE000L 2569 #define DAGB1_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L 2570 #define DAGB1_WRCLI7__MIN_BW_MASK 0x01C00000L 2571 #define DAGB1_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 2572 #define DAGB1_WRCLI7__MAX_OSD_MASK 0xFC000000L 2573 //DAGB1_WRCLI8 2574 #define DAGB1_WRCLI8__VIRT_CHAN__SHIFT 0x0 2575 #define DAGB1_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 2576 #define DAGB1_WRCLI8__URG_HIGH__SHIFT 0x4 2577 #define DAGB1_WRCLI8__URG_LOW__SHIFT 0x8 2578 #define DAGB1_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc 2579 #define DAGB1_WRCLI8__MAX_BW__SHIFT 0xd 2580 #define DAGB1_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 2581 #define DAGB1_WRCLI8__MIN_BW__SHIFT 0x16 2582 #define DAGB1_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 2583 #define DAGB1_WRCLI8__MAX_OSD__SHIFT 0x1a 2584 #define DAGB1_WRCLI8__VIRT_CHAN_MASK 0x00000007L 2585 #define DAGB1_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 2586 #define DAGB1_WRCLI8__URG_HIGH_MASK 0x000000F0L 2587 #define DAGB1_WRCLI8__URG_LOW_MASK 0x00000F00L 2588 #define DAGB1_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L 2589 #define DAGB1_WRCLI8__MAX_BW_MASK 0x001FE000L 2590 #define DAGB1_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L 2591 #define DAGB1_WRCLI8__MIN_BW_MASK 0x01C00000L 2592 #define DAGB1_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 2593 #define DAGB1_WRCLI8__MAX_OSD_MASK 0xFC000000L 2594 //DAGB1_WRCLI9 2595 #define DAGB1_WRCLI9__VIRT_CHAN__SHIFT 0x0 2596 #define DAGB1_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 2597 #define DAGB1_WRCLI9__URG_HIGH__SHIFT 0x4 2598 #define DAGB1_WRCLI9__URG_LOW__SHIFT 0x8 2599 #define DAGB1_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc 2600 #define DAGB1_WRCLI9__MAX_BW__SHIFT 0xd 2601 #define DAGB1_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 2602 #define DAGB1_WRCLI9__MIN_BW__SHIFT 0x16 2603 #define DAGB1_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 2604 #define DAGB1_WRCLI9__MAX_OSD__SHIFT 0x1a 2605 #define DAGB1_WRCLI9__VIRT_CHAN_MASK 0x00000007L 2606 #define DAGB1_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 2607 #define DAGB1_WRCLI9__URG_HIGH_MASK 0x000000F0L 2608 #define DAGB1_WRCLI9__URG_LOW_MASK 0x00000F00L 2609 #define DAGB1_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L 2610 #define DAGB1_WRCLI9__MAX_BW_MASK 0x001FE000L 2611 #define DAGB1_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L 2612 #define DAGB1_WRCLI9__MIN_BW_MASK 0x01C00000L 2613 #define DAGB1_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 2614 #define DAGB1_WRCLI9__MAX_OSD_MASK 0xFC000000L 2615 //DAGB1_WRCLI10 2616 #define DAGB1_WRCLI10__VIRT_CHAN__SHIFT 0x0 2617 #define DAGB1_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 2618 #define DAGB1_WRCLI10__URG_HIGH__SHIFT 0x4 2619 #define DAGB1_WRCLI10__URG_LOW__SHIFT 0x8 2620 #define DAGB1_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc 2621 #define DAGB1_WRCLI10__MAX_BW__SHIFT 0xd 2622 #define DAGB1_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 2623 #define DAGB1_WRCLI10__MIN_BW__SHIFT 0x16 2624 #define DAGB1_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 2625 #define DAGB1_WRCLI10__MAX_OSD__SHIFT 0x1a 2626 #define DAGB1_WRCLI10__VIRT_CHAN_MASK 0x00000007L 2627 #define DAGB1_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 2628 #define DAGB1_WRCLI10__URG_HIGH_MASK 0x000000F0L 2629 #define DAGB1_WRCLI10__URG_LOW_MASK 0x00000F00L 2630 #define DAGB1_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L 2631 #define DAGB1_WRCLI10__MAX_BW_MASK 0x001FE000L 2632 #define DAGB1_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L 2633 #define DAGB1_WRCLI10__MIN_BW_MASK 0x01C00000L 2634 #define DAGB1_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 2635 #define DAGB1_WRCLI10__MAX_OSD_MASK 0xFC000000L 2636 //DAGB1_WRCLI11 2637 #define DAGB1_WRCLI11__VIRT_CHAN__SHIFT 0x0 2638 #define DAGB1_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 2639 #define DAGB1_WRCLI11__URG_HIGH__SHIFT 0x4 2640 #define DAGB1_WRCLI11__URG_LOW__SHIFT 0x8 2641 #define DAGB1_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc 2642 #define DAGB1_WRCLI11__MAX_BW__SHIFT 0xd 2643 #define DAGB1_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 2644 #define DAGB1_WRCLI11__MIN_BW__SHIFT 0x16 2645 #define DAGB1_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 2646 #define DAGB1_WRCLI11__MAX_OSD__SHIFT 0x1a 2647 #define DAGB1_WRCLI11__VIRT_CHAN_MASK 0x00000007L 2648 #define DAGB1_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 2649 #define DAGB1_WRCLI11__URG_HIGH_MASK 0x000000F0L 2650 #define DAGB1_WRCLI11__URG_LOW_MASK 0x00000F00L 2651 #define DAGB1_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L 2652 #define DAGB1_WRCLI11__MAX_BW_MASK 0x001FE000L 2653 #define DAGB1_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L 2654 #define DAGB1_WRCLI11__MIN_BW_MASK 0x01C00000L 2655 #define DAGB1_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 2656 #define DAGB1_WRCLI11__MAX_OSD_MASK 0xFC000000L 2657 //DAGB1_WRCLI12 2658 #define DAGB1_WRCLI12__VIRT_CHAN__SHIFT 0x0 2659 #define DAGB1_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 2660 #define DAGB1_WRCLI12__URG_HIGH__SHIFT 0x4 2661 #define DAGB1_WRCLI12__URG_LOW__SHIFT 0x8 2662 #define DAGB1_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc 2663 #define DAGB1_WRCLI12__MAX_BW__SHIFT 0xd 2664 #define DAGB1_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 2665 #define DAGB1_WRCLI12__MIN_BW__SHIFT 0x16 2666 #define DAGB1_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 2667 #define DAGB1_WRCLI12__MAX_OSD__SHIFT 0x1a 2668 #define DAGB1_WRCLI12__VIRT_CHAN_MASK 0x00000007L 2669 #define DAGB1_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 2670 #define DAGB1_WRCLI12__URG_HIGH_MASK 0x000000F0L 2671 #define DAGB1_WRCLI12__URG_LOW_MASK 0x00000F00L 2672 #define DAGB1_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L 2673 #define DAGB1_WRCLI12__MAX_BW_MASK 0x001FE000L 2674 #define DAGB1_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L 2675 #define DAGB1_WRCLI12__MIN_BW_MASK 0x01C00000L 2676 #define DAGB1_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 2677 #define DAGB1_WRCLI12__MAX_OSD_MASK 0xFC000000L 2678 //DAGB1_WRCLI13 2679 #define DAGB1_WRCLI13__VIRT_CHAN__SHIFT 0x0 2680 #define DAGB1_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 2681 #define DAGB1_WRCLI13__URG_HIGH__SHIFT 0x4 2682 #define DAGB1_WRCLI13__URG_LOW__SHIFT 0x8 2683 #define DAGB1_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc 2684 #define DAGB1_WRCLI13__MAX_BW__SHIFT 0xd 2685 #define DAGB1_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 2686 #define DAGB1_WRCLI13__MIN_BW__SHIFT 0x16 2687 #define DAGB1_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 2688 #define DAGB1_WRCLI13__MAX_OSD__SHIFT 0x1a 2689 #define DAGB1_WRCLI13__VIRT_CHAN_MASK 0x00000007L 2690 #define DAGB1_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 2691 #define DAGB1_WRCLI13__URG_HIGH_MASK 0x000000F0L 2692 #define DAGB1_WRCLI13__URG_LOW_MASK 0x00000F00L 2693 #define DAGB1_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L 2694 #define DAGB1_WRCLI13__MAX_BW_MASK 0x001FE000L 2695 #define DAGB1_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L 2696 #define DAGB1_WRCLI13__MIN_BW_MASK 0x01C00000L 2697 #define DAGB1_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 2698 #define DAGB1_WRCLI13__MAX_OSD_MASK 0xFC000000L 2699 //DAGB1_WRCLI14 2700 #define DAGB1_WRCLI14__VIRT_CHAN__SHIFT 0x0 2701 #define DAGB1_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 2702 #define DAGB1_WRCLI14__URG_HIGH__SHIFT 0x4 2703 #define DAGB1_WRCLI14__URG_LOW__SHIFT 0x8 2704 #define DAGB1_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc 2705 #define DAGB1_WRCLI14__MAX_BW__SHIFT 0xd 2706 #define DAGB1_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 2707 #define DAGB1_WRCLI14__MIN_BW__SHIFT 0x16 2708 #define DAGB1_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 2709 #define DAGB1_WRCLI14__MAX_OSD__SHIFT 0x1a 2710 #define DAGB1_WRCLI14__VIRT_CHAN_MASK 0x00000007L 2711 #define DAGB1_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 2712 #define DAGB1_WRCLI14__URG_HIGH_MASK 0x000000F0L 2713 #define DAGB1_WRCLI14__URG_LOW_MASK 0x00000F00L 2714 #define DAGB1_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L 2715 #define DAGB1_WRCLI14__MAX_BW_MASK 0x001FE000L 2716 #define DAGB1_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L 2717 #define DAGB1_WRCLI14__MIN_BW_MASK 0x01C00000L 2718 #define DAGB1_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 2719 #define DAGB1_WRCLI14__MAX_OSD_MASK 0xFC000000L 2720 //DAGB1_WRCLI15 2721 #define DAGB1_WRCLI15__VIRT_CHAN__SHIFT 0x0 2722 #define DAGB1_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 2723 #define DAGB1_WRCLI15__URG_HIGH__SHIFT 0x4 2724 #define DAGB1_WRCLI15__URG_LOW__SHIFT 0x8 2725 #define DAGB1_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc 2726 #define DAGB1_WRCLI15__MAX_BW__SHIFT 0xd 2727 #define DAGB1_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 2728 #define DAGB1_WRCLI15__MIN_BW__SHIFT 0x16 2729 #define DAGB1_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 2730 #define DAGB1_WRCLI15__MAX_OSD__SHIFT 0x1a 2731 #define DAGB1_WRCLI15__VIRT_CHAN_MASK 0x00000007L 2732 #define DAGB1_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 2733 #define DAGB1_WRCLI15__URG_HIGH_MASK 0x000000F0L 2734 #define DAGB1_WRCLI15__URG_LOW_MASK 0x00000F00L 2735 #define DAGB1_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L 2736 #define DAGB1_WRCLI15__MAX_BW_MASK 0x001FE000L 2737 #define DAGB1_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L 2738 #define DAGB1_WRCLI15__MIN_BW_MASK 0x01C00000L 2739 #define DAGB1_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 2740 #define DAGB1_WRCLI15__MAX_OSD_MASK 0xFC000000L 2741 //DAGB1_WR_CNTL 2742 #define DAGB1_WR_CNTL__SCLK_FREQ__SHIFT 0x0 2743 #define DAGB1_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 2744 #define DAGB1_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 2745 #define DAGB1_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 2746 #define DAGB1_WR_CNTL__IO_LEVEL__SHIFT 0x11 2747 #define DAGB1_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 2748 #define DAGB1_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 2749 #define DAGB1_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL 2750 #define DAGB1_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 2751 #define DAGB1_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 2752 #define DAGB1_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 2753 #define DAGB1_WR_CNTL__IO_LEVEL_MASK 0x000E0000L 2754 #define DAGB1_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 2755 #define DAGB1_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L 2756 //DAGB1_WR_GMI_CNTL 2757 #define DAGB1_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 2758 #define DAGB1_WR_GMI_CNTL__LEVEL__SHIFT 0x6 2759 #define DAGB1_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 2760 #define DAGB1_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 2761 #define DAGB1_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 2762 #define DAGB1_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L 2763 #define DAGB1_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 2764 #define DAGB1_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 2765 //DAGB1_WR_ADDR_DAGB 2766 #define DAGB1_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 2767 #define DAGB1_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 2768 #define DAGB1_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 2769 #define DAGB1_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 2770 #define DAGB1_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 2771 #define DAGB1_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 2772 #define DAGB1_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 2773 #define DAGB1_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 2774 //DAGB1_WR_OUTPUT_DAGB_MAX_BURST 2775 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 2776 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 2777 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 2778 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 2779 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 2780 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 2781 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 2782 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 2783 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 2784 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 2785 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 2786 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 2787 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 2788 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 2789 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 2790 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 2791 //DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER 2792 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 2793 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 2794 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 2795 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 2796 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 2797 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 2798 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 2799 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 2800 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 2801 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 2802 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 2803 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 2804 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 2805 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 2806 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 2807 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 2808 //DAGB1_WR_CGTT_CLK_CTRL 2809 #define DAGB1_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 2810 #define DAGB1_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 2811 #define DAGB1_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 2812 #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 2813 #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 2814 #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 2815 #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 2816 #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 2817 #define DAGB1_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 2818 #define DAGB1_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 2819 #define DAGB1_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 2820 #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 2821 #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 2822 #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 2823 #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 2824 #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 2825 //DAGB1_L1TLB_WR_CGTT_CLK_CTRL 2826 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 2827 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 2828 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 2829 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 2830 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 2831 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 2832 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 2833 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 2834 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 2835 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 2836 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 2837 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 2838 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 2839 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 2840 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 2841 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 2842 //DAGB1_ATCVM_WR_CGTT_CLK_CTRL 2843 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 2844 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 2845 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 2846 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 2847 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 2848 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 2849 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 2850 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 2851 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 2852 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 2853 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 2854 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 2855 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 2856 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 2857 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 2858 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 2859 //DAGB1_WR_ADDR_DAGB_MAX_BURST0 2860 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 2861 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 2862 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 2863 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 2864 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 2865 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 2866 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 2867 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 2868 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 2869 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 2870 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 2871 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 2872 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 2873 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 2874 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 2875 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 2876 //DAGB1_WR_ADDR_DAGB_LAZY_TIMER0 2877 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 2878 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 2879 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 2880 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 2881 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 2882 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 2883 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 2884 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 2885 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 2886 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 2887 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 2888 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 2889 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 2890 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 2891 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 2892 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 2893 //DAGB1_WR_ADDR_DAGB_MAX_BURST1 2894 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 2895 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 2896 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 2897 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 2898 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 2899 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 2900 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 2901 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 2902 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 2903 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 2904 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 2905 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 2906 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 2907 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 2908 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 2909 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 2910 //DAGB1_WR_ADDR_DAGB_LAZY_TIMER1 2911 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 2912 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 2913 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 2914 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 2915 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 2916 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 2917 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 2918 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 2919 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 2920 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 2921 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 2922 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 2923 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 2924 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 2925 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 2926 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 2927 //DAGB1_WR_DATA_DAGB 2928 #define DAGB1_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 2929 #define DAGB1_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 2930 #define DAGB1_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 2931 #define DAGB1_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 2932 #define DAGB1_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L 2933 #define DAGB1_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 2934 #define DAGB1_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 2935 #define DAGB1_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L 2936 //DAGB1_WR_DATA_DAGB_MAX_BURST0 2937 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 2938 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 2939 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 2940 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 2941 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 2942 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 2943 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 2944 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 2945 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 2946 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 2947 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 2948 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 2949 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 2950 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 2951 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 2952 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 2953 //DAGB1_WR_DATA_DAGB_LAZY_TIMER0 2954 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 2955 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 2956 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 2957 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 2958 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 2959 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 2960 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 2961 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 2962 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 2963 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 2964 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 2965 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 2966 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 2967 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 2968 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 2969 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 2970 //DAGB1_WR_DATA_DAGB_MAX_BURST1 2971 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 2972 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 2973 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 2974 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 2975 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 2976 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 2977 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 2978 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 2979 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 2980 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 2981 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 2982 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 2983 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 2984 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 2985 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 2986 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 2987 //DAGB1_WR_DATA_DAGB_LAZY_TIMER1 2988 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 2989 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 2990 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 2991 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 2992 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 2993 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 2994 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 2995 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 2996 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 2997 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 2998 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 2999 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 3000 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 3001 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 3002 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 3003 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 3004 //DAGB1_WR_VC0_CNTL 3005 #define DAGB1_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 3006 #define DAGB1_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 3007 #define DAGB1_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3008 #define DAGB1_WR_VC0_CNTL__MAX_BW__SHIFT 0xc 3009 #define DAGB1_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3010 #define DAGB1_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 3011 #define DAGB1_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3012 #define DAGB1_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 3013 #define DAGB1_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 3014 #define DAGB1_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 3015 #define DAGB1_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3016 #define DAGB1_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L 3017 #define DAGB1_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3018 #define DAGB1_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L 3019 #define DAGB1_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3020 #define DAGB1_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 3021 //DAGB1_WR_VC1_CNTL 3022 #define DAGB1_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 3023 #define DAGB1_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 3024 #define DAGB1_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3025 #define DAGB1_WR_VC1_CNTL__MAX_BW__SHIFT 0xc 3026 #define DAGB1_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3027 #define DAGB1_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 3028 #define DAGB1_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3029 #define DAGB1_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 3030 #define DAGB1_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 3031 #define DAGB1_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 3032 #define DAGB1_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3033 #define DAGB1_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L 3034 #define DAGB1_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3035 #define DAGB1_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L 3036 #define DAGB1_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3037 #define DAGB1_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 3038 //DAGB1_WR_VC2_CNTL 3039 #define DAGB1_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 3040 #define DAGB1_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 3041 #define DAGB1_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3042 #define DAGB1_WR_VC2_CNTL__MAX_BW__SHIFT 0xc 3043 #define DAGB1_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3044 #define DAGB1_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 3045 #define DAGB1_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3046 #define DAGB1_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 3047 #define DAGB1_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 3048 #define DAGB1_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 3049 #define DAGB1_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3050 #define DAGB1_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L 3051 #define DAGB1_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3052 #define DAGB1_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L 3053 #define DAGB1_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3054 #define DAGB1_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 3055 //DAGB1_WR_VC3_CNTL 3056 #define DAGB1_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 3057 #define DAGB1_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 3058 #define DAGB1_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3059 #define DAGB1_WR_VC3_CNTL__MAX_BW__SHIFT 0xc 3060 #define DAGB1_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3061 #define DAGB1_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 3062 #define DAGB1_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3063 #define DAGB1_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 3064 #define DAGB1_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 3065 #define DAGB1_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 3066 #define DAGB1_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3067 #define DAGB1_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L 3068 #define DAGB1_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3069 #define DAGB1_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L 3070 #define DAGB1_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3071 #define DAGB1_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 3072 //DAGB1_WR_VC4_CNTL 3073 #define DAGB1_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 3074 #define DAGB1_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 3075 #define DAGB1_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3076 #define DAGB1_WR_VC4_CNTL__MAX_BW__SHIFT 0xc 3077 #define DAGB1_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3078 #define DAGB1_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 3079 #define DAGB1_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3080 #define DAGB1_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 3081 #define DAGB1_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 3082 #define DAGB1_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 3083 #define DAGB1_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3084 #define DAGB1_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L 3085 #define DAGB1_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3086 #define DAGB1_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L 3087 #define DAGB1_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3088 #define DAGB1_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 3089 //DAGB1_WR_VC5_CNTL 3090 #define DAGB1_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 3091 #define DAGB1_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 3092 #define DAGB1_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3093 #define DAGB1_WR_VC5_CNTL__MAX_BW__SHIFT 0xc 3094 #define DAGB1_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3095 #define DAGB1_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 3096 #define DAGB1_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3097 #define DAGB1_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 3098 #define DAGB1_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 3099 #define DAGB1_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 3100 #define DAGB1_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3101 #define DAGB1_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L 3102 #define DAGB1_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3103 #define DAGB1_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L 3104 #define DAGB1_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3105 #define DAGB1_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 3106 //DAGB1_WR_VC6_CNTL 3107 #define DAGB1_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 3108 #define DAGB1_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 3109 #define DAGB1_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3110 #define DAGB1_WR_VC6_CNTL__MAX_BW__SHIFT 0xc 3111 #define DAGB1_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3112 #define DAGB1_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 3113 #define DAGB1_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3114 #define DAGB1_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 3115 #define DAGB1_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 3116 #define DAGB1_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 3117 #define DAGB1_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3118 #define DAGB1_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L 3119 #define DAGB1_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3120 #define DAGB1_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L 3121 #define DAGB1_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3122 #define DAGB1_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 3123 //DAGB1_WR_VC7_CNTL 3124 #define DAGB1_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 3125 #define DAGB1_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 3126 #define DAGB1_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3127 #define DAGB1_WR_VC7_CNTL__MAX_BW__SHIFT 0xc 3128 #define DAGB1_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3129 #define DAGB1_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 3130 #define DAGB1_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3131 #define DAGB1_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 3132 #define DAGB1_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 3133 #define DAGB1_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 3134 #define DAGB1_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3135 #define DAGB1_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L 3136 #define DAGB1_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3137 #define DAGB1_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L 3138 #define DAGB1_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3139 #define DAGB1_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 3140 //DAGB1_WR_CNTL_MISC 3141 #define DAGB1_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 3142 #define DAGB1_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 3143 #define DAGB1_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 3144 #define DAGB1_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 3145 #define DAGB1_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 3146 #define DAGB1_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 3147 #define DAGB1_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a 3148 #define DAGB1_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 3149 #define DAGB1_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 3150 #define DAGB1_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 3151 #define DAGB1_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 3152 #define DAGB1_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 3153 #define DAGB1_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 3154 #define DAGB1_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L 3155 //DAGB1_WR_TLB_CREDIT 3156 #define DAGB1_WR_TLB_CREDIT__TLB0__SHIFT 0x0 3157 #define DAGB1_WR_TLB_CREDIT__TLB1__SHIFT 0x5 3158 #define DAGB1_WR_TLB_CREDIT__TLB2__SHIFT 0xa 3159 #define DAGB1_WR_TLB_CREDIT__TLB3__SHIFT 0xf 3160 #define DAGB1_WR_TLB_CREDIT__TLB4__SHIFT 0x14 3161 #define DAGB1_WR_TLB_CREDIT__TLB5__SHIFT 0x19 3162 #define DAGB1_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL 3163 #define DAGB1_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L 3164 #define DAGB1_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L 3165 #define DAGB1_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L 3166 #define DAGB1_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L 3167 #define DAGB1_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L 3168 //DAGB1_WR_DATA_CREDIT 3169 #define DAGB1_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 3170 #define DAGB1_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 3171 #define DAGB1_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 3172 #define DAGB1_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 3173 #define DAGB1_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL 3174 #define DAGB1_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L 3175 #define DAGB1_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L 3176 #define DAGB1_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L 3177 //DAGB1_WR_MISC_CREDIT 3178 #define DAGB1_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 3179 #define DAGB1_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 3180 #define DAGB1_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 3181 #define DAGB1_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 3182 #define DAGB1_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL 3183 #define DAGB1_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L 3184 #define DAGB1_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L 3185 #define DAGB1_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L 3186 //DAGB1_WRCLI_ASK_PENDING 3187 #define DAGB1_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 3188 #define DAGB1_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 3189 //DAGB1_WRCLI_GO_PENDING 3190 #define DAGB1_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 3191 #define DAGB1_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 3192 //DAGB1_WRCLI_GBLSEND_PENDING 3193 #define DAGB1_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 3194 #define DAGB1_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 3195 //DAGB1_WRCLI_TLB_PENDING 3196 #define DAGB1_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 3197 #define DAGB1_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 3198 //DAGB1_WRCLI_OARB_PENDING 3199 #define DAGB1_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 3200 #define DAGB1_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 3201 //DAGB1_WRCLI_OSD_PENDING 3202 #define DAGB1_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 3203 #define DAGB1_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 3204 //DAGB1_WRCLI_DBUS_ASK_PENDING 3205 #define DAGB1_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 3206 #define DAGB1_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 3207 //DAGB1_WRCLI_DBUS_GO_PENDING 3208 #define DAGB1_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 3209 #define DAGB1_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 3210 //DAGB1_DAGB_DLY 3211 #define DAGB1_DAGB_DLY__DLY__SHIFT 0x0 3212 #define DAGB1_DAGB_DLY__CLI__SHIFT 0x8 3213 #define DAGB1_DAGB_DLY__POS__SHIFT 0x10 3214 #define DAGB1_DAGB_DLY__DLY_MASK 0x000000FFL 3215 #define DAGB1_DAGB_DLY__CLI_MASK 0x0000FF00L 3216 #define DAGB1_DAGB_DLY__POS_MASK 0x000F0000L 3217 //DAGB1_CNTL_MISC 3218 #define DAGB1_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 3219 #define DAGB1_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 3220 #define DAGB1_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 3221 #define DAGB1_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 3222 #define DAGB1_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc 3223 #define DAGB1_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf 3224 #define DAGB1_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 3225 #define DAGB1_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 3226 #define DAGB1_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 3227 #define DAGB1_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e 3228 #define DAGB1_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L 3229 #define DAGB1_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L 3230 #define DAGB1_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L 3231 #define DAGB1_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L 3232 #define DAGB1_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L 3233 #define DAGB1_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L 3234 #define DAGB1_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L 3235 #define DAGB1_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L 3236 #define DAGB1_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L 3237 #define DAGB1_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L 3238 //DAGB1_CNTL_MISC2 3239 #define DAGB1_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 3240 #define DAGB1_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 3241 #define DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 3242 #define DAGB1_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 3243 #define DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 3244 #define DAGB1_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 3245 #define DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 3246 #define DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 3247 #define DAGB1_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 3248 #define DAGB1_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 3249 #define DAGB1_CNTL_MISC2__SWAP_CTL__SHIFT 0xa 3250 #define DAGB1_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xb 3251 #define DAGB1_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x11 3252 #define DAGB1_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L 3253 #define DAGB1_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L 3254 #define DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L 3255 #define DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L 3256 #define DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L 3257 #define DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L 3258 #define DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L 3259 #define DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L 3260 #define DAGB1_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L 3261 #define DAGB1_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L 3262 #define DAGB1_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L 3263 #define DAGB1_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000800L 3264 #define DAGB1_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x007E0000L 3265 //DAGB1_FIFO_EMPTY 3266 #define DAGB1_FIFO_EMPTY__EMPTY__SHIFT 0x0 3267 #define DAGB1_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL 3268 //DAGB1_FIFO_FULL 3269 #define DAGB1_FIFO_FULL__FULL__SHIFT 0x0 3270 #define DAGB1_FIFO_FULL__FULL_MASK 0x007FFFFFL 3271 //DAGB1_WR_CREDITS_FULL 3272 #define DAGB1_WR_CREDITS_FULL__FULL__SHIFT 0x0 3273 #define DAGB1_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL 3274 //DAGB1_RD_CREDITS_FULL 3275 #define DAGB1_RD_CREDITS_FULL__FULL__SHIFT 0x0 3276 #define DAGB1_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL 3277 //DAGB1_PERFCOUNTER_LO 3278 #define DAGB1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 3279 #define DAGB1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 3280 //DAGB1_PERFCOUNTER_HI 3281 #define DAGB1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 3282 #define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 3283 #define DAGB1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 3284 #define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 3285 //DAGB1_PERFCOUNTER0_CFG 3286 #define DAGB1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 3287 #define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 3288 #define DAGB1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 3289 #define DAGB1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 3290 #define DAGB1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 3291 #define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 3292 #define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 3293 #define DAGB1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 3294 #define DAGB1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 3295 #define DAGB1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 3296 //DAGB1_PERFCOUNTER1_CFG 3297 #define DAGB1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 3298 #define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 3299 #define DAGB1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 3300 #define DAGB1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 3301 #define DAGB1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 3302 #define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 3303 #define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 3304 #define DAGB1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 3305 #define DAGB1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 3306 #define DAGB1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 3307 //DAGB1_PERFCOUNTER2_CFG 3308 #define DAGB1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 3309 #define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 3310 #define DAGB1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 3311 #define DAGB1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 3312 #define DAGB1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 3313 #define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 3314 #define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 3315 #define DAGB1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 3316 #define DAGB1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 3317 #define DAGB1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 3318 //DAGB1_PERFCOUNTER_RSLT_CNTL 3319 #define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 3320 #define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 3321 #define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 3322 #define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 3323 #define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 3324 #define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 3325 #define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 3326 #define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 3327 #define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 3328 #define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 3329 #define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 3330 #define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 3331 //DAGB1_RESERVE0 3332 #define DAGB1_RESERVE0__RESERVE__SHIFT 0x0 3333 #define DAGB1_RESERVE0__RESERVE_MASK 0xFFFFFFFFL 3334 //DAGB1_RESERVE1 3335 #define DAGB1_RESERVE1__RESERVE__SHIFT 0x0 3336 #define DAGB1_RESERVE1__RESERVE_MASK 0xFFFFFFFFL 3337 //DAGB1_RESERVE2 3338 #define DAGB1_RESERVE2__RESERVE__SHIFT 0x0 3339 #define DAGB1_RESERVE2__RESERVE_MASK 0xFFFFFFFFL 3340 //DAGB1_RESERVE3 3341 #define DAGB1_RESERVE3__RESERVE__SHIFT 0x0 3342 #define DAGB1_RESERVE3__RESERVE_MASK 0xFFFFFFFFL 3343 //DAGB1_RESERVE4 3344 #define DAGB1_RESERVE4__RESERVE__SHIFT 0x0 3345 #define DAGB1_RESERVE4__RESERVE_MASK 0xFFFFFFFFL 3346 //DAGB1_RESERVE5 3347 #define DAGB1_RESERVE5__RESERVE__SHIFT 0x0 3348 #define DAGB1_RESERVE5__RESERVE_MASK 0xFFFFFFFFL 3349 //DAGB1_RESERVE6 3350 #define DAGB1_RESERVE6__RESERVE__SHIFT 0x0 3351 #define DAGB1_RESERVE6__RESERVE_MASK 0xFFFFFFFFL 3352 //DAGB1_RESERVE7 3353 #define DAGB1_RESERVE7__RESERVE__SHIFT 0x0 3354 #define DAGB1_RESERVE7__RESERVE_MASK 0xFFFFFFFFL 3355 //DAGB1_RESERVE8 3356 #define DAGB1_RESERVE8__RESERVE__SHIFT 0x0 3357 #define DAGB1_RESERVE8__RESERVE_MASK 0xFFFFFFFFL 3358 //DAGB1_RESERVE9 3359 #define DAGB1_RESERVE9__RESERVE__SHIFT 0x0 3360 #define DAGB1_RESERVE9__RESERVE_MASK 0xFFFFFFFFL 3361 //DAGB1_RESERVE10 3362 #define DAGB1_RESERVE10__RESERVE__SHIFT 0x0 3363 #define DAGB1_RESERVE10__RESERVE_MASK 0xFFFFFFFFL 3364 //DAGB1_RESERVE11 3365 #define DAGB1_RESERVE11__RESERVE__SHIFT 0x0 3366 #define DAGB1_RESERVE11__RESERVE_MASK 0xFFFFFFFFL 3367 //DAGB1_RESERVE12 3368 #define DAGB1_RESERVE12__RESERVE__SHIFT 0x0 3369 #define DAGB1_RESERVE12__RESERVE_MASK 0xFFFFFFFFL 3370 //DAGB1_RESERVE13 3371 #define DAGB1_RESERVE13__RESERVE__SHIFT 0x0 3372 #define DAGB1_RESERVE13__RESERVE_MASK 0xFFFFFFFFL 3373 3374 3375 // addressBlock: mmhub_dagb_dagbdec2 3376 //DAGB2_RDCLI0 3377 #define DAGB2_RDCLI0__VIRT_CHAN__SHIFT 0x0 3378 #define DAGB2_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 3379 #define DAGB2_RDCLI0__URG_HIGH__SHIFT 0x4 3380 #define DAGB2_RDCLI0__URG_LOW__SHIFT 0x8 3381 #define DAGB2_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 3382 #define DAGB2_RDCLI0__MAX_BW__SHIFT 0xd 3383 #define DAGB2_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 3384 #define DAGB2_RDCLI0__MIN_BW__SHIFT 0x16 3385 #define DAGB2_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 3386 #define DAGB2_RDCLI0__MAX_OSD__SHIFT 0x1a 3387 #define DAGB2_RDCLI0__VIRT_CHAN_MASK 0x00000007L 3388 #define DAGB2_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 3389 #define DAGB2_RDCLI0__URG_HIGH_MASK 0x000000F0L 3390 #define DAGB2_RDCLI0__URG_LOW_MASK 0x00000F00L 3391 #define DAGB2_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L 3392 #define DAGB2_RDCLI0__MAX_BW_MASK 0x001FE000L 3393 #define DAGB2_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L 3394 #define DAGB2_RDCLI0__MIN_BW_MASK 0x01C00000L 3395 #define DAGB2_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 3396 #define DAGB2_RDCLI0__MAX_OSD_MASK 0xFC000000L 3397 //DAGB2_RDCLI1 3398 #define DAGB2_RDCLI1__VIRT_CHAN__SHIFT 0x0 3399 #define DAGB2_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 3400 #define DAGB2_RDCLI1__URG_HIGH__SHIFT 0x4 3401 #define DAGB2_RDCLI1__URG_LOW__SHIFT 0x8 3402 #define DAGB2_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc 3403 #define DAGB2_RDCLI1__MAX_BW__SHIFT 0xd 3404 #define DAGB2_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 3405 #define DAGB2_RDCLI1__MIN_BW__SHIFT 0x16 3406 #define DAGB2_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 3407 #define DAGB2_RDCLI1__MAX_OSD__SHIFT 0x1a 3408 #define DAGB2_RDCLI1__VIRT_CHAN_MASK 0x00000007L 3409 #define DAGB2_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 3410 #define DAGB2_RDCLI1__URG_HIGH_MASK 0x000000F0L 3411 #define DAGB2_RDCLI1__URG_LOW_MASK 0x00000F00L 3412 #define DAGB2_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L 3413 #define DAGB2_RDCLI1__MAX_BW_MASK 0x001FE000L 3414 #define DAGB2_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L 3415 #define DAGB2_RDCLI1__MIN_BW_MASK 0x01C00000L 3416 #define DAGB2_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 3417 #define DAGB2_RDCLI1__MAX_OSD_MASK 0xFC000000L 3418 //DAGB2_RDCLI2 3419 #define DAGB2_RDCLI2__VIRT_CHAN__SHIFT 0x0 3420 #define DAGB2_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 3421 #define DAGB2_RDCLI2__URG_HIGH__SHIFT 0x4 3422 #define DAGB2_RDCLI2__URG_LOW__SHIFT 0x8 3423 #define DAGB2_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc 3424 #define DAGB2_RDCLI2__MAX_BW__SHIFT 0xd 3425 #define DAGB2_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 3426 #define DAGB2_RDCLI2__MIN_BW__SHIFT 0x16 3427 #define DAGB2_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 3428 #define DAGB2_RDCLI2__MAX_OSD__SHIFT 0x1a 3429 #define DAGB2_RDCLI2__VIRT_CHAN_MASK 0x00000007L 3430 #define DAGB2_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 3431 #define DAGB2_RDCLI2__URG_HIGH_MASK 0x000000F0L 3432 #define DAGB2_RDCLI2__URG_LOW_MASK 0x00000F00L 3433 #define DAGB2_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L 3434 #define DAGB2_RDCLI2__MAX_BW_MASK 0x001FE000L 3435 #define DAGB2_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L 3436 #define DAGB2_RDCLI2__MIN_BW_MASK 0x01C00000L 3437 #define DAGB2_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 3438 #define DAGB2_RDCLI2__MAX_OSD_MASK 0xFC000000L 3439 //DAGB2_RDCLI3 3440 #define DAGB2_RDCLI3__VIRT_CHAN__SHIFT 0x0 3441 #define DAGB2_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 3442 #define DAGB2_RDCLI3__URG_HIGH__SHIFT 0x4 3443 #define DAGB2_RDCLI3__URG_LOW__SHIFT 0x8 3444 #define DAGB2_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc 3445 #define DAGB2_RDCLI3__MAX_BW__SHIFT 0xd 3446 #define DAGB2_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 3447 #define DAGB2_RDCLI3__MIN_BW__SHIFT 0x16 3448 #define DAGB2_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 3449 #define DAGB2_RDCLI3__MAX_OSD__SHIFT 0x1a 3450 #define DAGB2_RDCLI3__VIRT_CHAN_MASK 0x00000007L 3451 #define DAGB2_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 3452 #define DAGB2_RDCLI3__URG_HIGH_MASK 0x000000F0L 3453 #define DAGB2_RDCLI3__URG_LOW_MASK 0x00000F00L 3454 #define DAGB2_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L 3455 #define DAGB2_RDCLI3__MAX_BW_MASK 0x001FE000L 3456 #define DAGB2_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L 3457 #define DAGB2_RDCLI3__MIN_BW_MASK 0x01C00000L 3458 #define DAGB2_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 3459 #define DAGB2_RDCLI3__MAX_OSD_MASK 0xFC000000L 3460 //DAGB2_RDCLI4 3461 #define DAGB2_RDCLI4__VIRT_CHAN__SHIFT 0x0 3462 #define DAGB2_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 3463 #define DAGB2_RDCLI4__URG_HIGH__SHIFT 0x4 3464 #define DAGB2_RDCLI4__URG_LOW__SHIFT 0x8 3465 #define DAGB2_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc 3466 #define DAGB2_RDCLI4__MAX_BW__SHIFT 0xd 3467 #define DAGB2_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 3468 #define DAGB2_RDCLI4__MIN_BW__SHIFT 0x16 3469 #define DAGB2_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 3470 #define DAGB2_RDCLI4__MAX_OSD__SHIFT 0x1a 3471 #define DAGB2_RDCLI4__VIRT_CHAN_MASK 0x00000007L 3472 #define DAGB2_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 3473 #define DAGB2_RDCLI4__URG_HIGH_MASK 0x000000F0L 3474 #define DAGB2_RDCLI4__URG_LOW_MASK 0x00000F00L 3475 #define DAGB2_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L 3476 #define DAGB2_RDCLI4__MAX_BW_MASK 0x001FE000L 3477 #define DAGB2_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L 3478 #define DAGB2_RDCLI4__MIN_BW_MASK 0x01C00000L 3479 #define DAGB2_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 3480 #define DAGB2_RDCLI4__MAX_OSD_MASK 0xFC000000L 3481 //DAGB2_RDCLI5 3482 #define DAGB2_RDCLI5__VIRT_CHAN__SHIFT 0x0 3483 #define DAGB2_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 3484 #define DAGB2_RDCLI5__URG_HIGH__SHIFT 0x4 3485 #define DAGB2_RDCLI5__URG_LOW__SHIFT 0x8 3486 #define DAGB2_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc 3487 #define DAGB2_RDCLI5__MAX_BW__SHIFT 0xd 3488 #define DAGB2_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 3489 #define DAGB2_RDCLI5__MIN_BW__SHIFT 0x16 3490 #define DAGB2_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 3491 #define DAGB2_RDCLI5__MAX_OSD__SHIFT 0x1a 3492 #define DAGB2_RDCLI5__VIRT_CHAN_MASK 0x00000007L 3493 #define DAGB2_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 3494 #define DAGB2_RDCLI5__URG_HIGH_MASK 0x000000F0L 3495 #define DAGB2_RDCLI5__URG_LOW_MASK 0x00000F00L 3496 #define DAGB2_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L 3497 #define DAGB2_RDCLI5__MAX_BW_MASK 0x001FE000L 3498 #define DAGB2_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L 3499 #define DAGB2_RDCLI5__MIN_BW_MASK 0x01C00000L 3500 #define DAGB2_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 3501 #define DAGB2_RDCLI5__MAX_OSD_MASK 0xFC000000L 3502 //DAGB2_RDCLI6 3503 #define DAGB2_RDCLI6__VIRT_CHAN__SHIFT 0x0 3504 #define DAGB2_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 3505 #define DAGB2_RDCLI6__URG_HIGH__SHIFT 0x4 3506 #define DAGB2_RDCLI6__URG_LOW__SHIFT 0x8 3507 #define DAGB2_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc 3508 #define DAGB2_RDCLI6__MAX_BW__SHIFT 0xd 3509 #define DAGB2_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 3510 #define DAGB2_RDCLI6__MIN_BW__SHIFT 0x16 3511 #define DAGB2_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 3512 #define DAGB2_RDCLI6__MAX_OSD__SHIFT 0x1a 3513 #define DAGB2_RDCLI6__VIRT_CHAN_MASK 0x00000007L 3514 #define DAGB2_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 3515 #define DAGB2_RDCLI6__URG_HIGH_MASK 0x000000F0L 3516 #define DAGB2_RDCLI6__URG_LOW_MASK 0x00000F00L 3517 #define DAGB2_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L 3518 #define DAGB2_RDCLI6__MAX_BW_MASK 0x001FE000L 3519 #define DAGB2_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L 3520 #define DAGB2_RDCLI6__MIN_BW_MASK 0x01C00000L 3521 #define DAGB2_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 3522 #define DAGB2_RDCLI6__MAX_OSD_MASK 0xFC000000L 3523 //DAGB2_RDCLI7 3524 #define DAGB2_RDCLI7__VIRT_CHAN__SHIFT 0x0 3525 #define DAGB2_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 3526 #define DAGB2_RDCLI7__URG_HIGH__SHIFT 0x4 3527 #define DAGB2_RDCLI7__URG_LOW__SHIFT 0x8 3528 #define DAGB2_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc 3529 #define DAGB2_RDCLI7__MAX_BW__SHIFT 0xd 3530 #define DAGB2_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 3531 #define DAGB2_RDCLI7__MIN_BW__SHIFT 0x16 3532 #define DAGB2_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 3533 #define DAGB2_RDCLI7__MAX_OSD__SHIFT 0x1a 3534 #define DAGB2_RDCLI7__VIRT_CHAN_MASK 0x00000007L 3535 #define DAGB2_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 3536 #define DAGB2_RDCLI7__URG_HIGH_MASK 0x000000F0L 3537 #define DAGB2_RDCLI7__URG_LOW_MASK 0x00000F00L 3538 #define DAGB2_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L 3539 #define DAGB2_RDCLI7__MAX_BW_MASK 0x001FE000L 3540 #define DAGB2_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L 3541 #define DAGB2_RDCLI7__MIN_BW_MASK 0x01C00000L 3542 #define DAGB2_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 3543 #define DAGB2_RDCLI7__MAX_OSD_MASK 0xFC000000L 3544 //DAGB2_RDCLI8 3545 #define DAGB2_RDCLI8__VIRT_CHAN__SHIFT 0x0 3546 #define DAGB2_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 3547 #define DAGB2_RDCLI8__URG_HIGH__SHIFT 0x4 3548 #define DAGB2_RDCLI8__URG_LOW__SHIFT 0x8 3549 #define DAGB2_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc 3550 #define DAGB2_RDCLI8__MAX_BW__SHIFT 0xd 3551 #define DAGB2_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 3552 #define DAGB2_RDCLI8__MIN_BW__SHIFT 0x16 3553 #define DAGB2_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 3554 #define DAGB2_RDCLI8__MAX_OSD__SHIFT 0x1a 3555 #define DAGB2_RDCLI8__VIRT_CHAN_MASK 0x00000007L 3556 #define DAGB2_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 3557 #define DAGB2_RDCLI8__URG_HIGH_MASK 0x000000F0L 3558 #define DAGB2_RDCLI8__URG_LOW_MASK 0x00000F00L 3559 #define DAGB2_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L 3560 #define DAGB2_RDCLI8__MAX_BW_MASK 0x001FE000L 3561 #define DAGB2_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L 3562 #define DAGB2_RDCLI8__MIN_BW_MASK 0x01C00000L 3563 #define DAGB2_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 3564 #define DAGB2_RDCLI8__MAX_OSD_MASK 0xFC000000L 3565 //DAGB2_RDCLI9 3566 #define DAGB2_RDCLI9__VIRT_CHAN__SHIFT 0x0 3567 #define DAGB2_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 3568 #define DAGB2_RDCLI9__URG_HIGH__SHIFT 0x4 3569 #define DAGB2_RDCLI9__URG_LOW__SHIFT 0x8 3570 #define DAGB2_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc 3571 #define DAGB2_RDCLI9__MAX_BW__SHIFT 0xd 3572 #define DAGB2_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 3573 #define DAGB2_RDCLI9__MIN_BW__SHIFT 0x16 3574 #define DAGB2_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 3575 #define DAGB2_RDCLI9__MAX_OSD__SHIFT 0x1a 3576 #define DAGB2_RDCLI9__VIRT_CHAN_MASK 0x00000007L 3577 #define DAGB2_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 3578 #define DAGB2_RDCLI9__URG_HIGH_MASK 0x000000F0L 3579 #define DAGB2_RDCLI9__URG_LOW_MASK 0x00000F00L 3580 #define DAGB2_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L 3581 #define DAGB2_RDCLI9__MAX_BW_MASK 0x001FE000L 3582 #define DAGB2_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L 3583 #define DAGB2_RDCLI9__MIN_BW_MASK 0x01C00000L 3584 #define DAGB2_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 3585 #define DAGB2_RDCLI9__MAX_OSD_MASK 0xFC000000L 3586 //DAGB2_RDCLI10 3587 #define DAGB2_RDCLI10__VIRT_CHAN__SHIFT 0x0 3588 #define DAGB2_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 3589 #define DAGB2_RDCLI10__URG_HIGH__SHIFT 0x4 3590 #define DAGB2_RDCLI10__URG_LOW__SHIFT 0x8 3591 #define DAGB2_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc 3592 #define DAGB2_RDCLI10__MAX_BW__SHIFT 0xd 3593 #define DAGB2_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 3594 #define DAGB2_RDCLI10__MIN_BW__SHIFT 0x16 3595 #define DAGB2_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 3596 #define DAGB2_RDCLI10__MAX_OSD__SHIFT 0x1a 3597 #define DAGB2_RDCLI10__VIRT_CHAN_MASK 0x00000007L 3598 #define DAGB2_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 3599 #define DAGB2_RDCLI10__URG_HIGH_MASK 0x000000F0L 3600 #define DAGB2_RDCLI10__URG_LOW_MASK 0x00000F00L 3601 #define DAGB2_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L 3602 #define DAGB2_RDCLI10__MAX_BW_MASK 0x001FE000L 3603 #define DAGB2_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L 3604 #define DAGB2_RDCLI10__MIN_BW_MASK 0x01C00000L 3605 #define DAGB2_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 3606 #define DAGB2_RDCLI10__MAX_OSD_MASK 0xFC000000L 3607 //DAGB2_RDCLI11 3608 #define DAGB2_RDCLI11__VIRT_CHAN__SHIFT 0x0 3609 #define DAGB2_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 3610 #define DAGB2_RDCLI11__URG_HIGH__SHIFT 0x4 3611 #define DAGB2_RDCLI11__URG_LOW__SHIFT 0x8 3612 #define DAGB2_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc 3613 #define DAGB2_RDCLI11__MAX_BW__SHIFT 0xd 3614 #define DAGB2_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 3615 #define DAGB2_RDCLI11__MIN_BW__SHIFT 0x16 3616 #define DAGB2_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 3617 #define DAGB2_RDCLI11__MAX_OSD__SHIFT 0x1a 3618 #define DAGB2_RDCLI11__VIRT_CHAN_MASK 0x00000007L 3619 #define DAGB2_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 3620 #define DAGB2_RDCLI11__URG_HIGH_MASK 0x000000F0L 3621 #define DAGB2_RDCLI11__URG_LOW_MASK 0x00000F00L 3622 #define DAGB2_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L 3623 #define DAGB2_RDCLI11__MAX_BW_MASK 0x001FE000L 3624 #define DAGB2_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L 3625 #define DAGB2_RDCLI11__MIN_BW_MASK 0x01C00000L 3626 #define DAGB2_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 3627 #define DAGB2_RDCLI11__MAX_OSD_MASK 0xFC000000L 3628 //DAGB2_RDCLI12 3629 #define DAGB2_RDCLI12__VIRT_CHAN__SHIFT 0x0 3630 #define DAGB2_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 3631 #define DAGB2_RDCLI12__URG_HIGH__SHIFT 0x4 3632 #define DAGB2_RDCLI12__URG_LOW__SHIFT 0x8 3633 #define DAGB2_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc 3634 #define DAGB2_RDCLI12__MAX_BW__SHIFT 0xd 3635 #define DAGB2_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 3636 #define DAGB2_RDCLI12__MIN_BW__SHIFT 0x16 3637 #define DAGB2_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 3638 #define DAGB2_RDCLI12__MAX_OSD__SHIFT 0x1a 3639 #define DAGB2_RDCLI12__VIRT_CHAN_MASK 0x00000007L 3640 #define DAGB2_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 3641 #define DAGB2_RDCLI12__URG_HIGH_MASK 0x000000F0L 3642 #define DAGB2_RDCLI12__URG_LOW_MASK 0x00000F00L 3643 #define DAGB2_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L 3644 #define DAGB2_RDCLI12__MAX_BW_MASK 0x001FE000L 3645 #define DAGB2_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L 3646 #define DAGB2_RDCLI12__MIN_BW_MASK 0x01C00000L 3647 #define DAGB2_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 3648 #define DAGB2_RDCLI12__MAX_OSD_MASK 0xFC000000L 3649 //DAGB2_RDCLI13 3650 #define DAGB2_RDCLI13__VIRT_CHAN__SHIFT 0x0 3651 #define DAGB2_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 3652 #define DAGB2_RDCLI13__URG_HIGH__SHIFT 0x4 3653 #define DAGB2_RDCLI13__URG_LOW__SHIFT 0x8 3654 #define DAGB2_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc 3655 #define DAGB2_RDCLI13__MAX_BW__SHIFT 0xd 3656 #define DAGB2_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 3657 #define DAGB2_RDCLI13__MIN_BW__SHIFT 0x16 3658 #define DAGB2_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 3659 #define DAGB2_RDCLI13__MAX_OSD__SHIFT 0x1a 3660 #define DAGB2_RDCLI13__VIRT_CHAN_MASK 0x00000007L 3661 #define DAGB2_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 3662 #define DAGB2_RDCLI13__URG_HIGH_MASK 0x000000F0L 3663 #define DAGB2_RDCLI13__URG_LOW_MASK 0x00000F00L 3664 #define DAGB2_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L 3665 #define DAGB2_RDCLI13__MAX_BW_MASK 0x001FE000L 3666 #define DAGB2_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L 3667 #define DAGB2_RDCLI13__MIN_BW_MASK 0x01C00000L 3668 #define DAGB2_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 3669 #define DAGB2_RDCLI13__MAX_OSD_MASK 0xFC000000L 3670 //DAGB2_RDCLI14 3671 #define DAGB2_RDCLI14__VIRT_CHAN__SHIFT 0x0 3672 #define DAGB2_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 3673 #define DAGB2_RDCLI14__URG_HIGH__SHIFT 0x4 3674 #define DAGB2_RDCLI14__URG_LOW__SHIFT 0x8 3675 #define DAGB2_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc 3676 #define DAGB2_RDCLI14__MAX_BW__SHIFT 0xd 3677 #define DAGB2_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 3678 #define DAGB2_RDCLI14__MIN_BW__SHIFT 0x16 3679 #define DAGB2_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 3680 #define DAGB2_RDCLI14__MAX_OSD__SHIFT 0x1a 3681 #define DAGB2_RDCLI14__VIRT_CHAN_MASK 0x00000007L 3682 #define DAGB2_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 3683 #define DAGB2_RDCLI14__URG_HIGH_MASK 0x000000F0L 3684 #define DAGB2_RDCLI14__URG_LOW_MASK 0x00000F00L 3685 #define DAGB2_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L 3686 #define DAGB2_RDCLI14__MAX_BW_MASK 0x001FE000L 3687 #define DAGB2_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L 3688 #define DAGB2_RDCLI14__MIN_BW_MASK 0x01C00000L 3689 #define DAGB2_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 3690 #define DAGB2_RDCLI14__MAX_OSD_MASK 0xFC000000L 3691 //DAGB2_RDCLI15 3692 #define DAGB2_RDCLI15__VIRT_CHAN__SHIFT 0x0 3693 #define DAGB2_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 3694 #define DAGB2_RDCLI15__URG_HIGH__SHIFT 0x4 3695 #define DAGB2_RDCLI15__URG_LOW__SHIFT 0x8 3696 #define DAGB2_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc 3697 #define DAGB2_RDCLI15__MAX_BW__SHIFT 0xd 3698 #define DAGB2_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 3699 #define DAGB2_RDCLI15__MIN_BW__SHIFT 0x16 3700 #define DAGB2_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 3701 #define DAGB2_RDCLI15__MAX_OSD__SHIFT 0x1a 3702 #define DAGB2_RDCLI15__VIRT_CHAN_MASK 0x00000007L 3703 #define DAGB2_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 3704 #define DAGB2_RDCLI15__URG_HIGH_MASK 0x000000F0L 3705 #define DAGB2_RDCLI15__URG_LOW_MASK 0x00000F00L 3706 #define DAGB2_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L 3707 #define DAGB2_RDCLI15__MAX_BW_MASK 0x001FE000L 3708 #define DAGB2_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L 3709 #define DAGB2_RDCLI15__MIN_BW_MASK 0x01C00000L 3710 #define DAGB2_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 3711 #define DAGB2_RDCLI15__MAX_OSD_MASK 0xFC000000L 3712 //DAGB2_RD_CNTL 3713 #define DAGB2_RD_CNTL__SCLK_FREQ__SHIFT 0x0 3714 #define DAGB2_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 3715 #define DAGB2_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 3716 #define DAGB2_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 3717 #define DAGB2_RD_CNTL__IO_LEVEL__SHIFT 0x11 3718 #define DAGB2_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 3719 #define DAGB2_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 3720 #define DAGB2_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL 3721 #define DAGB2_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 3722 #define DAGB2_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 3723 #define DAGB2_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 3724 #define DAGB2_RD_CNTL__IO_LEVEL_MASK 0x000E0000L 3725 #define DAGB2_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 3726 #define DAGB2_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L 3727 //DAGB2_RD_GMI_CNTL 3728 #define DAGB2_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 3729 #define DAGB2_RD_GMI_CNTL__LEVEL__SHIFT 0x6 3730 #define DAGB2_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 3731 #define DAGB2_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 3732 #define DAGB2_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 3733 #define DAGB2_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L 3734 #define DAGB2_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 3735 #define DAGB2_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 3736 //DAGB2_RD_ADDR_DAGB 3737 #define DAGB2_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 3738 #define DAGB2_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 3739 #define DAGB2_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 3740 #define DAGB2_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 3741 #define DAGB2_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 3742 #define DAGB2_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 3743 #define DAGB2_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 3744 #define DAGB2_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 3745 //DAGB2_RD_OUTPUT_DAGB_MAX_BURST 3746 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 3747 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 3748 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 3749 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 3750 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 3751 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 3752 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 3753 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 3754 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 3755 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 3756 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 3757 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 3758 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 3759 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 3760 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 3761 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 3762 //DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER 3763 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 3764 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 3765 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 3766 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 3767 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 3768 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 3769 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 3770 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 3771 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 3772 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 3773 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 3774 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 3775 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 3776 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 3777 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 3778 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 3779 //DAGB2_RD_CGTT_CLK_CTRL 3780 #define DAGB2_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 3781 #define DAGB2_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 3782 #define DAGB2_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 3783 #define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 3784 #define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 3785 #define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 3786 #define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 3787 #define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 3788 #define DAGB2_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 3789 #define DAGB2_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 3790 #define DAGB2_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 3791 #define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 3792 #define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 3793 #define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 3794 #define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 3795 #define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 3796 //DAGB2_L1TLB_RD_CGTT_CLK_CTRL 3797 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 3798 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 3799 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 3800 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 3801 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 3802 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 3803 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 3804 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 3805 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 3806 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 3807 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 3808 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 3809 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 3810 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 3811 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 3812 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 3813 //DAGB2_ATCVM_RD_CGTT_CLK_CTRL 3814 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 3815 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 3816 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 3817 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 3818 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 3819 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 3820 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 3821 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 3822 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 3823 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 3824 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 3825 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 3826 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 3827 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 3828 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 3829 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 3830 //DAGB2_RD_ADDR_DAGB_MAX_BURST0 3831 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 3832 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 3833 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 3834 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 3835 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 3836 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 3837 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 3838 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 3839 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 3840 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 3841 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 3842 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 3843 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 3844 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 3845 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 3846 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 3847 //DAGB2_RD_ADDR_DAGB_LAZY_TIMER0 3848 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 3849 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 3850 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 3851 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 3852 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 3853 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 3854 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 3855 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 3856 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 3857 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 3858 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 3859 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 3860 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 3861 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 3862 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 3863 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 3864 //DAGB2_RD_ADDR_DAGB_MAX_BURST1 3865 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 3866 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 3867 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 3868 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 3869 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 3870 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 3871 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 3872 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 3873 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 3874 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 3875 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 3876 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 3877 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 3878 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 3879 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 3880 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 3881 //DAGB2_RD_ADDR_DAGB_LAZY_TIMER1 3882 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 3883 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 3884 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 3885 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 3886 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 3887 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 3888 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 3889 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 3890 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 3891 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 3892 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 3893 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 3894 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 3895 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 3896 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 3897 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 3898 //DAGB2_RD_VC0_CNTL 3899 #define DAGB2_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 3900 #define DAGB2_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 3901 #define DAGB2_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3902 #define DAGB2_RD_VC0_CNTL__MAX_BW__SHIFT 0xc 3903 #define DAGB2_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3904 #define DAGB2_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 3905 #define DAGB2_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3906 #define DAGB2_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 3907 #define DAGB2_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 3908 #define DAGB2_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 3909 #define DAGB2_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3910 #define DAGB2_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L 3911 #define DAGB2_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3912 #define DAGB2_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L 3913 #define DAGB2_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3914 #define DAGB2_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 3915 //DAGB2_RD_VC1_CNTL 3916 #define DAGB2_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 3917 #define DAGB2_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 3918 #define DAGB2_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3919 #define DAGB2_RD_VC1_CNTL__MAX_BW__SHIFT 0xc 3920 #define DAGB2_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3921 #define DAGB2_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 3922 #define DAGB2_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3923 #define DAGB2_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 3924 #define DAGB2_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 3925 #define DAGB2_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 3926 #define DAGB2_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3927 #define DAGB2_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L 3928 #define DAGB2_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3929 #define DAGB2_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L 3930 #define DAGB2_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3931 #define DAGB2_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 3932 //DAGB2_RD_VC2_CNTL 3933 #define DAGB2_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 3934 #define DAGB2_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 3935 #define DAGB2_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3936 #define DAGB2_RD_VC2_CNTL__MAX_BW__SHIFT 0xc 3937 #define DAGB2_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3938 #define DAGB2_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 3939 #define DAGB2_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3940 #define DAGB2_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 3941 #define DAGB2_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 3942 #define DAGB2_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 3943 #define DAGB2_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3944 #define DAGB2_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L 3945 #define DAGB2_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3946 #define DAGB2_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L 3947 #define DAGB2_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3948 #define DAGB2_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 3949 //DAGB2_RD_VC3_CNTL 3950 #define DAGB2_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 3951 #define DAGB2_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 3952 #define DAGB2_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3953 #define DAGB2_RD_VC3_CNTL__MAX_BW__SHIFT 0xc 3954 #define DAGB2_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3955 #define DAGB2_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 3956 #define DAGB2_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3957 #define DAGB2_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 3958 #define DAGB2_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 3959 #define DAGB2_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 3960 #define DAGB2_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3961 #define DAGB2_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L 3962 #define DAGB2_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3963 #define DAGB2_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L 3964 #define DAGB2_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3965 #define DAGB2_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 3966 //DAGB2_RD_VC4_CNTL 3967 #define DAGB2_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 3968 #define DAGB2_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 3969 #define DAGB2_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3970 #define DAGB2_RD_VC4_CNTL__MAX_BW__SHIFT 0xc 3971 #define DAGB2_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3972 #define DAGB2_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 3973 #define DAGB2_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3974 #define DAGB2_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 3975 #define DAGB2_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 3976 #define DAGB2_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 3977 #define DAGB2_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3978 #define DAGB2_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L 3979 #define DAGB2_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3980 #define DAGB2_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L 3981 #define DAGB2_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3982 #define DAGB2_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 3983 //DAGB2_RD_VC5_CNTL 3984 #define DAGB2_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 3985 #define DAGB2_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 3986 #define DAGB2_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3987 #define DAGB2_RD_VC5_CNTL__MAX_BW__SHIFT 0xc 3988 #define DAGB2_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3989 #define DAGB2_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 3990 #define DAGB2_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3991 #define DAGB2_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 3992 #define DAGB2_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 3993 #define DAGB2_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 3994 #define DAGB2_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3995 #define DAGB2_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L 3996 #define DAGB2_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3997 #define DAGB2_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L 3998 #define DAGB2_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3999 #define DAGB2_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 4000 //DAGB2_RD_VC6_CNTL 4001 #define DAGB2_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 4002 #define DAGB2_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 4003 #define DAGB2_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 4004 #define DAGB2_RD_VC6_CNTL__MAX_BW__SHIFT 0xc 4005 #define DAGB2_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 4006 #define DAGB2_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 4007 #define DAGB2_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 4008 #define DAGB2_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 4009 #define DAGB2_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 4010 #define DAGB2_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 4011 #define DAGB2_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 4012 #define DAGB2_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L 4013 #define DAGB2_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 4014 #define DAGB2_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L 4015 #define DAGB2_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 4016 #define DAGB2_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 4017 //DAGB2_RD_VC7_CNTL 4018 #define DAGB2_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 4019 #define DAGB2_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 4020 #define DAGB2_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 4021 #define DAGB2_RD_VC7_CNTL__MAX_BW__SHIFT 0xc 4022 #define DAGB2_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 4023 #define DAGB2_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 4024 #define DAGB2_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 4025 #define DAGB2_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 4026 #define DAGB2_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 4027 #define DAGB2_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 4028 #define DAGB2_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 4029 #define DAGB2_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L 4030 #define DAGB2_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 4031 #define DAGB2_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L 4032 #define DAGB2_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 4033 #define DAGB2_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 4034 //DAGB2_RD_CNTL_MISC 4035 #define DAGB2_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 4036 #define DAGB2_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 4037 #define DAGB2_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 4038 #define DAGB2_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 4039 #define DAGB2_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 4040 #define DAGB2_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 4041 #define DAGB2_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a 4042 #define DAGB2_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 4043 #define DAGB2_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 4044 #define DAGB2_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 4045 #define DAGB2_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 4046 #define DAGB2_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 4047 #define DAGB2_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 4048 #define DAGB2_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L 4049 //DAGB2_RD_TLB_CREDIT 4050 #define DAGB2_RD_TLB_CREDIT__TLB0__SHIFT 0x0 4051 #define DAGB2_RD_TLB_CREDIT__TLB1__SHIFT 0x5 4052 #define DAGB2_RD_TLB_CREDIT__TLB2__SHIFT 0xa 4053 #define DAGB2_RD_TLB_CREDIT__TLB3__SHIFT 0xf 4054 #define DAGB2_RD_TLB_CREDIT__TLB4__SHIFT 0x14 4055 #define DAGB2_RD_TLB_CREDIT__TLB5__SHIFT 0x19 4056 #define DAGB2_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL 4057 #define DAGB2_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L 4058 #define DAGB2_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L 4059 #define DAGB2_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L 4060 #define DAGB2_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L 4061 #define DAGB2_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L 4062 //DAGB2_RDCLI_ASK_PENDING 4063 #define DAGB2_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 4064 #define DAGB2_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 4065 //DAGB2_RDCLI_GO_PENDING 4066 #define DAGB2_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 4067 #define DAGB2_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 4068 //DAGB2_RDCLI_GBLSEND_PENDING 4069 #define DAGB2_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 4070 #define DAGB2_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 4071 //DAGB2_RDCLI_TLB_PENDING 4072 #define DAGB2_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 4073 #define DAGB2_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 4074 //DAGB2_RDCLI_OARB_PENDING 4075 #define DAGB2_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 4076 #define DAGB2_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 4077 //DAGB2_RDCLI_OSD_PENDING 4078 #define DAGB2_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 4079 #define DAGB2_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 4080 //DAGB2_WRCLI0 4081 #define DAGB2_WRCLI0__VIRT_CHAN__SHIFT 0x0 4082 #define DAGB2_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 4083 #define DAGB2_WRCLI0__URG_HIGH__SHIFT 0x4 4084 #define DAGB2_WRCLI0__URG_LOW__SHIFT 0x8 4085 #define DAGB2_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc 4086 #define DAGB2_WRCLI0__MAX_BW__SHIFT 0xd 4087 #define DAGB2_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 4088 #define DAGB2_WRCLI0__MIN_BW__SHIFT 0x16 4089 #define DAGB2_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 4090 #define DAGB2_WRCLI0__MAX_OSD__SHIFT 0x1a 4091 #define DAGB2_WRCLI0__VIRT_CHAN_MASK 0x00000007L 4092 #define DAGB2_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 4093 #define DAGB2_WRCLI0__URG_HIGH_MASK 0x000000F0L 4094 #define DAGB2_WRCLI0__URG_LOW_MASK 0x00000F00L 4095 #define DAGB2_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L 4096 #define DAGB2_WRCLI0__MAX_BW_MASK 0x001FE000L 4097 #define DAGB2_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L 4098 #define DAGB2_WRCLI0__MIN_BW_MASK 0x01C00000L 4099 #define DAGB2_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 4100 #define DAGB2_WRCLI0__MAX_OSD_MASK 0xFC000000L 4101 //DAGB2_WRCLI1 4102 #define DAGB2_WRCLI1__VIRT_CHAN__SHIFT 0x0 4103 #define DAGB2_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 4104 #define DAGB2_WRCLI1__URG_HIGH__SHIFT 0x4 4105 #define DAGB2_WRCLI1__URG_LOW__SHIFT 0x8 4106 #define DAGB2_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc 4107 #define DAGB2_WRCLI1__MAX_BW__SHIFT 0xd 4108 #define DAGB2_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 4109 #define DAGB2_WRCLI1__MIN_BW__SHIFT 0x16 4110 #define DAGB2_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 4111 #define DAGB2_WRCLI1__MAX_OSD__SHIFT 0x1a 4112 #define DAGB2_WRCLI1__VIRT_CHAN_MASK 0x00000007L 4113 #define DAGB2_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 4114 #define DAGB2_WRCLI1__URG_HIGH_MASK 0x000000F0L 4115 #define DAGB2_WRCLI1__URG_LOW_MASK 0x00000F00L 4116 #define DAGB2_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L 4117 #define DAGB2_WRCLI1__MAX_BW_MASK 0x001FE000L 4118 #define DAGB2_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L 4119 #define DAGB2_WRCLI1__MIN_BW_MASK 0x01C00000L 4120 #define DAGB2_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 4121 #define DAGB2_WRCLI1__MAX_OSD_MASK 0xFC000000L 4122 //DAGB2_WRCLI2 4123 #define DAGB2_WRCLI2__VIRT_CHAN__SHIFT 0x0 4124 #define DAGB2_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 4125 #define DAGB2_WRCLI2__URG_HIGH__SHIFT 0x4 4126 #define DAGB2_WRCLI2__URG_LOW__SHIFT 0x8 4127 #define DAGB2_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc 4128 #define DAGB2_WRCLI2__MAX_BW__SHIFT 0xd 4129 #define DAGB2_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 4130 #define DAGB2_WRCLI2__MIN_BW__SHIFT 0x16 4131 #define DAGB2_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 4132 #define DAGB2_WRCLI2__MAX_OSD__SHIFT 0x1a 4133 #define DAGB2_WRCLI2__VIRT_CHAN_MASK 0x00000007L 4134 #define DAGB2_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 4135 #define DAGB2_WRCLI2__URG_HIGH_MASK 0x000000F0L 4136 #define DAGB2_WRCLI2__URG_LOW_MASK 0x00000F00L 4137 #define DAGB2_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L 4138 #define DAGB2_WRCLI2__MAX_BW_MASK 0x001FE000L 4139 #define DAGB2_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L 4140 #define DAGB2_WRCLI2__MIN_BW_MASK 0x01C00000L 4141 #define DAGB2_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 4142 #define DAGB2_WRCLI2__MAX_OSD_MASK 0xFC000000L 4143 //DAGB2_WRCLI3 4144 #define DAGB2_WRCLI3__VIRT_CHAN__SHIFT 0x0 4145 #define DAGB2_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 4146 #define DAGB2_WRCLI3__URG_HIGH__SHIFT 0x4 4147 #define DAGB2_WRCLI3__URG_LOW__SHIFT 0x8 4148 #define DAGB2_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc 4149 #define DAGB2_WRCLI3__MAX_BW__SHIFT 0xd 4150 #define DAGB2_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 4151 #define DAGB2_WRCLI3__MIN_BW__SHIFT 0x16 4152 #define DAGB2_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 4153 #define DAGB2_WRCLI3__MAX_OSD__SHIFT 0x1a 4154 #define DAGB2_WRCLI3__VIRT_CHAN_MASK 0x00000007L 4155 #define DAGB2_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 4156 #define DAGB2_WRCLI3__URG_HIGH_MASK 0x000000F0L 4157 #define DAGB2_WRCLI3__URG_LOW_MASK 0x00000F00L 4158 #define DAGB2_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L 4159 #define DAGB2_WRCLI3__MAX_BW_MASK 0x001FE000L 4160 #define DAGB2_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L 4161 #define DAGB2_WRCLI3__MIN_BW_MASK 0x01C00000L 4162 #define DAGB2_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 4163 #define DAGB2_WRCLI3__MAX_OSD_MASK 0xFC000000L 4164 //DAGB2_WRCLI4 4165 #define DAGB2_WRCLI4__VIRT_CHAN__SHIFT 0x0 4166 #define DAGB2_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 4167 #define DAGB2_WRCLI4__URG_HIGH__SHIFT 0x4 4168 #define DAGB2_WRCLI4__URG_LOW__SHIFT 0x8 4169 #define DAGB2_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc 4170 #define DAGB2_WRCLI4__MAX_BW__SHIFT 0xd 4171 #define DAGB2_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 4172 #define DAGB2_WRCLI4__MIN_BW__SHIFT 0x16 4173 #define DAGB2_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 4174 #define DAGB2_WRCLI4__MAX_OSD__SHIFT 0x1a 4175 #define DAGB2_WRCLI4__VIRT_CHAN_MASK 0x00000007L 4176 #define DAGB2_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 4177 #define DAGB2_WRCLI4__URG_HIGH_MASK 0x000000F0L 4178 #define DAGB2_WRCLI4__URG_LOW_MASK 0x00000F00L 4179 #define DAGB2_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L 4180 #define DAGB2_WRCLI4__MAX_BW_MASK 0x001FE000L 4181 #define DAGB2_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L 4182 #define DAGB2_WRCLI4__MIN_BW_MASK 0x01C00000L 4183 #define DAGB2_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 4184 #define DAGB2_WRCLI4__MAX_OSD_MASK 0xFC000000L 4185 //DAGB2_WRCLI5 4186 #define DAGB2_WRCLI5__VIRT_CHAN__SHIFT 0x0 4187 #define DAGB2_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 4188 #define DAGB2_WRCLI5__URG_HIGH__SHIFT 0x4 4189 #define DAGB2_WRCLI5__URG_LOW__SHIFT 0x8 4190 #define DAGB2_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc 4191 #define DAGB2_WRCLI5__MAX_BW__SHIFT 0xd 4192 #define DAGB2_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 4193 #define DAGB2_WRCLI5__MIN_BW__SHIFT 0x16 4194 #define DAGB2_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 4195 #define DAGB2_WRCLI5__MAX_OSD__SHIFT 0x1a 4196 #define DAGB2_WRCLI5__VIRT_CHAN_MASK 0x00000007L 4197 #define DAGB2_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 4198 #define DAGB2_WRCLI5__URG_HIGH_MASK 0x000000F0L 4199 #define DAGB2_WRCLI5__URG_LOW_MASK 0x00000F00L 4200 #define DAGB2_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L 4201 #define DAGB2_WRCLI5__MAX_BW_MASK 0x001FE000L 4202 #define DAGB2_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L 4203 #define DAGB2_WRCLI5__MIN_BW_MASK 0x01C00000L 4204 #define DAGB2_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 4205 #define DAGB2_WRCLI5__MAX_OSD_MASK 0xFC000000L 4206 //DAGB2_WRCLI6 4207 #define DAGB2_WRCLI6__VIRT_CHAN__SHIFT 0x0 4208 #define DAGB2_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 4209 #define DAGB2_WRCLI6__URG_HIGH__SHIFT 0x4 4210 #define DAGB2_WRCLI6__URG_LOW__SHIFT 0x8 4211 #define DAGB2_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc 4212 #define DAGB2_WRCLI6__MAX_BW__SHIFT 0xd 4213 #define DAGB2_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 4214 #define DAGB2_WRCLI6__MIN_BW__SHIFT 0x16 4215 #define DAGB2_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 4216 #define DAGB2_WRCLI6__MAX_OSD__SHIFT 0x1a 4217 #define DAGB2_WRCLI6__VIRT_CHAN_MASK 0x00000007L 4218 #define DAGB2_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 4219 #define DAGB2_WRCLI6__URG_HIGH_MASK 0x000000F0L 4220 #define DAGB2_WRCLI6__URG_LOW_MASK 0x00000F00L 4221 #define DAGB2_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L 4222 #define DAGB2_WRCLI6__MAX_BW_MASK 0x001FE000L 4223 #define DAGB2_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L 4224 #define DAGB2_WRCLI6__MIN_BW_MASK 0x01C00000L 4225 #define DAGB2_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 4226 #define DAGB2_WRCLI6__MAX_OSD_MASK 0xFC000000L 4227 //DAGB2_WRCLI7 4228 #define DAGB2_WRCLI7__VIRT_CHAN__SHIFT 0x0 4229 #define DAGB2_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 4230 #define DAGB2_WRCLI7__URG_HIGH__SHIFT 0x4 4231 #define DAGB2_WRCLI7__URG_LOW__SHIFT 0x8 4232 #define DAGB2_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc 4233 #define DAGB2_WRCLI7__MAX_BW__SHIFT 0xd 4234 #define DAGB2_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 4235 #define DAGB2_WRCLI7__MIN_BW__SHIFT 0x16 4236 #define DAGB2_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 4237 #define DAGB2_WRCLI7__MAX_OSD__SHIFT 0x1a 4238 #define DAGB2_WRCLI7__VIRT_CHAN_MASK 0x00000007L 4239 #define DAGB2_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 4240 #define DAGB2_WRCLI7__URG_HIGH_MASK 0x000000F0L 4241 #define DAGB2_WRCLI7__URG_LOW_MASK 0x00000F00L 4242 #define DAGB2_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L 4243 #define DAGB2_WRCLI7__MAX_BW_MASK 0x001FE000L 4244 #define DAGB2_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L 4245 #define DAGB2_WRCLI7__MIN_BW_MASK 0x01C00000L 4246 #define DAGB2_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 4247 #define DAGB2_WRCLI7__MAX_OSD_MASK 0xFC000000L 4248 //DAGB2_WRCLI8 4249 #define DAGB2_WRCLI8__VIRT_CHAN__SHIFT 0x0 4250 #define DAGB2_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 4251 #define DAGB2_WRCLI8__URG_HIGH__SHIFT 0x4 4252 #define DAGB2_WRCLI8__URG_LOW__SHIFT 0x8 4253 #define DAGB2_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc 4254 #define DAGB2_WRCLI8__MAX_BW__SHIFT 0xd 4255 #define DAGB2_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 4256 #define DAGB2_WRCLI8__MIN_BW__SHIFT 0x16 4257 #define DAGB2_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 4258 #define DAGB2_WRCLI8__MAX_OSD__SHIFT 0x1a 4259 #define DAGB2_WRCLI8__VIRT_CHAN_MASK 0x00000007L 4260 #define DAGB2_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 4261 #define DAGB2_WRCLI8__URG_HIGH_MASK 0x000000F0L 4262 #define DAGB2_WRCLI8__URG_LOW_MASK 0x00000F00L 4263 #define DAGB2_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L 4264 #define DAGB2_WRCLI8__MAX_BW_MASK 0x001FE000L 4265 #define DAGB2_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L 4266 #define DAGB2_WRCLI8__MIN_BW_MASK 0x01C00000L 4267 #define DAGB2_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 4268 #define DAGB2_WRCLI8__MAX_OSD_MASK 0xFC000000L 4269 //DAGB2_WRCLI9 4270 #define DAGB2_WRCLI9__VIRT_CHAN__SHIFT 0x0 4271 #define DAGB2_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 4272 #define DAGB2_WRCLI9__URG_HIGH__SHIFT 0x4 4273 #define DAGB2_WRCLI9__URG_LOW__SHIFT 0x8 4274 #define DAGB2_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc 4275 #define DAGB2_WRCLI9__MAX_BW__SHIFT 0xd 4276 #define DAGB2_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 4277 #define DAGB2_WRCLI9__MIN_BW__SHIFT 0x16 4278 #define DAGB2_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 4279 #define DAGB2_WRCLI9__MAX_OSD__SHIFT 0x1a 4280 #define DAGB2_WRCLI9__VIRT_CHAN_MASK 0x00000007L 4281 #define DAGB2_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 4282 #define DAGB2_WRCLI9__URG_HIGH_MASK 0x000000F0L 4283 #define DAGB2_WRCLI9__URG_LOW_MASK 0x00000F00L 4284 #define DAGB2_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L 4285 #define DAGB2_WRCLI9__MAX_BW_MASK 0x001FE000L 4286 #define DAGB2_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L 4287 #define DAGB2_WRCLI9__MIN_BW_MASK 0x01C00000L 4288 #define DAGB2_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 4289 #define DAGB2_WRCLI9__MAX_OSD_MASK 0xFC000000L 4290 //DAGB2_WRCLI10 4291 #define DAGB2_WRCLI10__VIRT_CHAN__SHIFT 0x0 4292 #define DAGB2_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 4293 #define DAGB2_WRCLI10__URG_HIGH__SHIFT 0x4 4294 #define DAGB2_WRCLI10__URG_LOW__SHIFT 0x8 4295 #define DAGB2_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc 4296 #define DAGB2_WRCLI10__MAX_BW__SHIFT 0xd 4297 #define DAGB2_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 4298 #define DAGB2_WRCLI10__MIN_BW__SHIFT 0x16 4299 #define DAGB2_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 4300 #define DAGB2_WRCLI10__MAX_OSD__SHIFT 0x1a 4301 #define DAGB2_WRCLI10__VIRT_CHAN_MASK 0x00000007L 4302 #define DAGB2_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 4303 #define DAGB2_WRCLI10__URG_HIGH_MASK 0x000000F0L 4304 #define DAGB2_WRCLI10__URG_LOW_MASK 0x00000F00L 4305 #define DAGB2_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L 4306 #define DAGB2_WRCLI10__MAX_BW_MASK 0x001FE000L 4307 #define DAGB2_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L 4308 #define DAGB2_WRCLI10__MIN_BW_MASK 0x01C00000L 4309 #define DAGB2_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 4310 #define DAGB2_WRCLI10__MAX_OSD_MASK 0xFC000000L 4311 //DAGB2_WRCLI11 4312 #define DAGB2_WRCLI11__VIRT_CHAN__SHIFT 0x0 4313 #define DAGB2_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 4314 #define DAGB2_WRCLI11__URG_HIGH__SHIFT 0x4 4315 #define DAGB2_WRCLI11__URG_LOW__SHIFT 0x8 4316 #define DAGB2_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc 4317 #define DAGB2_WRCLI11__MAX_BW__SHIFT 0xd 4318 #define DAGB2_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 4319 #define DAGB2_WRCLI11__MIN_BW__SHIFT 0x16 4320 #define DAGB2_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 4321 #define DAGB2_WRCLI11__MAX_OSD__SHIFT 0x1a 4322 #define DAGB2_WRCLI11__VIRT_CHAN_MASK 0x00000007L 4323 #define DAGB2_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 4324 #define DAGB2_WRCLI11__URG_HIGH_MASK 0x000000F0L 4325 #define DAGB2_WRCLI11__URG_LOW_MASK 0x00000F00L 4326 #define DAGB2_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L 4327 #define DAGB2_WRCLI11__MAX_BW_MASK 0x001FE000L 4328 #define DAGB2_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L 4329 #define DAGB2_WRCLI11__MIN_BW_MASK 0x01C00000L 4330 #define DAGB2_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 4331 #define DAGB2_WRCLI11__MAX_OSD_MASK 0xFC000000L 4332 //DAGB2_WRCLI12 4333 #define DAGB2_WRCLI12__VIRT_CHAN__SHIFT 0x0 4334 #define DAGB2_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 4335 #define DAGB2_WRCLI12__URG_HIGH__SHIFT 0x4 4336 #define DAGB2_WRCLI12__URG_LOW__SHIFT 0x8 4337 #define DAGB2_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc 4338 #define DAGB2_WRCLI12__MAX_BW__SHIFT 0xd 4339 #define DAGB2_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 4340 #define DAGB2_WRCLI12__MIN_BW__SHIFT 0x16 4341 #define DAGB2_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 4342 #define DAGB2_WRCLI12__MAX_OSD__SHIFT 0x1a 4343 #define DAGB2_WRCLI12__VIRT_CHAN_MASK 0x00000007L 4344 #define DAGB2_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 4345 #define DAGB2_WRCLI12__URG_HIGH_MASK 0x000000F0L 4346 #define DAGB2_WRCLI12__URG_LOW_MASK 0x00000F00L 4347 #define DAGB2_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L 4348 #define DAGB2_WRCLI12__MAX_BW_MASK 0x001FE000L 4349 #define DAGB2_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L 4350 #define DAGB2_WRCLI12__MIN_BW_MASK 0x01C00000L 4351 #define DAGB2_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 4352 #define DAGB2_WRCLI12__MAX_OSD_MASK 0xFC000000L 4353 //DAGB2_WRCLI13 4354 #define DAGB2_WRCLI13__VIRT_CHAN__SHIFT 0x0 4355 #define DAGB2_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 4356 #define DAGB2_WRCLI13__URG_HIGH__SHIFT 0x4 4357 #define DAGB2_WRCLI13__URG_LOW__SHIFT 0x8 4358 #define DAGB2_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc 4359 #define DAGB2_WRCLI13__MAX_BW__SHIFT 0xd 4360 #define DAGB2_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 4361 #define DAGB2_WRCLI13__MIN_BW__SHIFT 0x16 4362 #define DAGB2_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 4363 #define DAGB2_WRCLI13__MAX_OSD__SHIFT 0x1a 4364 #define DAGB2_WRCLI13__VIRT_CHAN_MASK 0x00000007L 4365 #define DAGB2_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 4366 #define DAGB2_WRCLI13__URG_HIGH_MASK 0x000000F0L 4367 #define DAGB2_WRCLI13__URG_LOW_MASK 0x00000F00L 4368 #define DAGB2_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L 4369 #define DAGB2_WRCLI13__MAX_BW_MASK 0x001FE000L 4370 #define DAGB2_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L 4371 #define DAGB2_WRCLI13__MIN_BW_MASK 0x01C00000L 4372 #define DAGB2_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 4373 #define DAGB2_WRCLI13__MAX_OSD_MASK 0xFC000000L 4374 //DAGB2_WRCLI14 4375 #define DAGB2_WRCLI14__VIRT_CHAN__SHIFT 0x0 4376 #define DAGB2_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 4377 #define DAGB2_WRCLI14__URG_HIGH__SHIFT 0x4 4378 #define DAGB2_WRCLI14__URG_LOW__SHIFT 0x8 4379 #define DAGB2_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc 4380 #define DAGB2_WRCLI14__MAX_BW__SHIFT 0xd 4381 #define DAGB2_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 4382 #define DAGB2_WRCLI14__MIN_BW__SHIFT 0x16 4383 #define DAGB2_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 4384 #define DAGB2_WRCLI14__MAX_OSD__SHIFT 0x1a 4385 #define DAGB2_WRCLI14__VIRT_CHAN_MASK 0x00000007L 4386 #define DAGB2_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 4387 #define DAGB2_WRCLI14__URG_HIGH_MASK 0x000000F0L 4388 #define DAGB2_WRCLI14__URG_LOW_MASK 0x00000F00L 4389 #define DAGB2_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L 4390 #define DAGB2_WRCLI14__MAX_BW_MASK 0x001FE000L 4391 #define DAGB2_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L 4392 #define DAGB2_WRCLI14__MIN_BW_MASK 0x01C00000L 4393 #define DAGB2_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 4394 #define DAGB2_WRCLI14__MAX_OSD_MASK 0xFC000000L 4395 //DAGB2_WRCLI15 4396 #define DAGB2_WRCLI15__VIRT_CHAN__SHIFT 0x0 4397 #define DAGB2_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 4398 #define DAGB2_WRCLI15__URG_HIGH__SHIFT 0x4 4399 #define DAGB2_WRCLI15__URG_LOW__SHIFT 0x8 4400 #define DAGB2_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc 4401 #define DAGB2_WRCLI15__MAX_BW__SHIFT 0xd 4402 #define DAGB2_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 4403 #define DAGB2_WRCLI15__MIN_BW__SHIFT 0x16 4404 #define DAGB2_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 4405 #define DAGB2_WRCLI15__MAX_OSD__SHIFT 0x1a 4406 #define DAGB2_WRCLI15__VIRT_CHAN_MASK 0x00000007L 4407 #define DAGB2_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 4408 #define DAGB2_WRCLI15__URG_HIGH_MASK 0x000000F0L 4409 #define DAGB2_WRCLI15__URG_LOW_MASK 0x00000F00L 4410 #define DAGB2_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L 4411 #define DAGB2_WRCLI15__MAX_BW_MASK 0x001FE000L 4412 #define DAGB2_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L 4413 #define DAGB2_WRCLI15__MIN_BW_MASK 0x01C00000L 4414 #define DAGB2_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 4415 #define DAGB2_WRCLI15__MAX_OSD_MASK 0xFC000000L 4416 //DAGB2_WR_CNTL 4417 #define DAGB2_WR_CNTL__SCLK_FREQ__SHIFT 0x0 4418 #define DAGB2_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 4419 #define DAGB2_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 4420 #define DAGB2_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 4421 #define DAGB2_WR_CNTL__IO_LEVEL__SHIFT 0x11 4422 #define DAGB2_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 4423 #define DAGB2_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 4424 #define DAGB2_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL 4425 #define DAGB2_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 4426 #define DAGB2_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 4427 #define DAGB2_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 4428 #define DAGB2_WR_CNTL__IO_LEVEL_MASK 0x000E0000L 4429 #define DAGB2_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 4430 #define DAGB2_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L 4431 //DAGB2_WR_GMI_CNTL 4432 #define DAGB2_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 4433 #define DAGB2_WR_GMI_CNTL__LEVEL__SHIFT 0x6 4434 #define DAGB2_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 4435 #define DAGB2_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 4436 #define DAGB2_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 4437 #define DAGB2_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L 4438 #define DAGB2_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 4439 #define DAGB2_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 4440 //DAGB2_WR_ADDR_DAGB 4441 #define DAGB2_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 4442 #define DAGB2_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 4443 #define DAGB2_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 4444 #define DAGB2_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 4445 #define DAGB2_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 4446 #define DAGB2_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 4447 #define DAGB2_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 4448 #define DAGB2_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 4449 //DAGB2_WR_OUTPUT_DAGB_MAX_BURST 4450 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 4451 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 4452 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 4453 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 4454 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 4455 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 4456 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 4457 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 4458 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 4459 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 4460 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 4461 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 4462 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 4463 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 4464 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 4465 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 4466 //DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER 4467 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 4468 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 4469 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 4470 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 4471 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 4472 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 4473 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 4474 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 4475 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 4476 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 4477 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 4478 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 4479 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 4480 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 4481 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 4482 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 4483 //DAGB2_WR_CGTT_CLK_CTRL 4484 #define DAGB2_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 4485 #define DAGB2_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 4486 #define DAGB2_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 4487 #define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 4488 #define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 4489 #define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 4490 #define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 4491 #define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 4492 #define DAGB2_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 4493 #define DAGB2_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 4494 #define DAGB2_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 4495 #define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 4496 #define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 4497 #define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 4498 #define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 4499 #define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 4500 //DAGB2_L1TLB_WR_CGTT_CLK_CTRL 4501 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 4502 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 4503 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 4504 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 4505 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 4506 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 4507 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 4508 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 4509 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 4510 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 4511 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 4512 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 4513 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 4514 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 4515 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 4516 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 4517 //DAGB2_ATCVM_WR_CGTT_CLK_CTRL 4518 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 4519 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 4520 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 4521 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 4522 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 4523 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 4524 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 4525 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 4526 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 4527 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 4528 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 4529 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 4530 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 4531 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 4532 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 4533 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 4534 //DAGB2_WR_ADDR_DAGB_MAX_BURST0 4535 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 4536 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 4537 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 4538 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 4539 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 4540 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 4541 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 4542 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 4543 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 4544 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 4545 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 4546 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 4547 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 4548 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 4549 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 4550 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 4551 //DAGB2_WR_ADDR_DAGB_LAZY_TIMER0 4552 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 4553 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 4554 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 4555 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 4556 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 4557 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 4558 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 4559 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 4560 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 4561 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 4562 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 4563 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 4564 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 4565 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 4566 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 4567 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 4568 //DAGB2_WR_ADDR_DAGB_MAX_BURST1 4569 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 4570 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 4571 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 4572 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 4573 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 4574 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 4575 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 4576 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 4577 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 4578 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 4579 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 4580 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 4581 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 4582 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 4583 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 4584 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 4585 //DAGB2_WR_ADDR_DAGB_LAZY_TIMER1 4586 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 4587 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 4588 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 4589 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 4590 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 4591 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 4592 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 4593 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 4594 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 4595 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 4596 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 4597 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 4598 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 4599 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 4600 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 4601 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 4602 //DAGB2_WR_DATA_DAGB 4603 #define DAGB2_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 4604 #define DAGB2_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 4605 #define DAGB2_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 4606 #define DAGB2_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 4607 #define DAGB2_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L 4608 #define DAGB2_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 4609 #define DAGB2_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 4610 #define DAGB2_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L 4611 //DAGB2_WR_DATA_DAGB_MAX_BURST0 4612 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 4613 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 4614 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 4615 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 4616 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 4617 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 4618 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 4619 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 4620 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 4621 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 4622 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 4623 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 4624 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 4625 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 4626 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 4627 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 4628 //DAGB2_WR_DATA_DAGB_LAZY_TIMER0 4629 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 4630 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 4631 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 4632 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 4633 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 4634 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 4635 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 4636 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 4637 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 4638 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 4639 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 4640 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 4641 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 4642 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 4643 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 4644 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 4645 //DAGB2_WR_DATA_DAGB_MAX_BURST1 4646 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 4647 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 4648 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 4649 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 4650 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 4651 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 4652 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 4653 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 4654 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 4655 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 4656 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 4657 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 4658 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 4659 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 4660 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 4661 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 4662 //DAGB2_WR_DATA_DAGB_LAZY_TIMER1 4663 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 4664 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 4665 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 4666 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 4667 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 4668 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 4669 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 4670 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 4671 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 4672 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 4673 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 4674 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 4675 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 4676 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 4677 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 4678 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 4679 //DAGB2_WR_VC0_CNTL 4680 #define DAGB2_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 4681 #define DAGB2_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 4682 #define DAGB2_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 4683 #define DAGB2_WR_VC0_CNTL__MAX_BW__SHIFT 0xc 4684 #define DAGB2_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 4685 #define DAGB2_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 4686 #define DAGB2_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 4687 #define DAGB2_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 4688 #define DAGB2_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 4689 #define DAGB2_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 4690 #define DAGB2_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 4691 #define DAGB2_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L 4692 #define DAGB2_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 4693 #define DAGB2_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L 4694 #define DAGB2_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 4695 #define DAGB2_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 4696 //DAGB2_WR_VC1_CNTL 4697 #define DAGB2_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 4698 #define DAGB2_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 4699 #define DAGB2_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 4700 #define DAGB2_WR_VC1_CNTL__MAX_BW__SHIFT 0xc 4701 #define DAGB2_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 4702 #define DAGB2_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 4703 #define DAGB2_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 4704 #define DAGB2_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 4705 #define DAGB2_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 4706 #define DAGB2_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 4707 #define DAGB2_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 4708 #define DAGB2_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L 4709 #define DAGB2_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 4710 #define DAGB2_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L 4711 #define DAGB2_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 4712 #define DAGB2_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 4713 //DAGB2_WR_VC2_CNTL 4714 #define DAGB2_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 4715 #define DAGB2_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 4716 #define DAGB2_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 4717 #define DAGB2_WR_VC2_CNTL__MAX_BW__SHIFT 0xc 4718 #define DAGB2_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 4719 #define DAGB2_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 4720 #define DAGB2_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 4721 #define DAGB2_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 4722 #define DAGB2_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 4723 #define DAGB2_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 4724 #define DAGB2_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 4725 #define DAGB2_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L 4726 #define DAGB2_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 4727 #define DAGB2_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L 4728 #define DAGB2_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 4729 #define DAGB2_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 4730 //DAGB2_WR_VC3_CNTL 4731 #define DAGB2_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 4732 #define DAGB2_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 4733 #define DAGB2_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 4734 #define DAGB2_WR_VC3_CNTL__MAX_BW__SHIFT 0xc 4735 #define DAGB2_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 4736 #define DAGB2_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 4737 #define DAGB2_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 4738 #define DAGB2_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 4739 #define DAGB2_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 4740 #define DAGB2_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 4741 #define DAGB2_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 4742 #define DAGB2_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L 4743 #define DAGB2_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 4744 #define DAGB2_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L 4745 #define DAGB2_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 4746 #define DAGB2_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 4747 //DAGB2_WR_VC4_CNTL 4748 #define DAGB2_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 4749 #define DAGB2_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 4750 #define DAGB2_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 4751 #define DAGB2_WR_VC4_CNTL__MAX_BW__SHIFT 0xc 4752 #define DAGB2_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 4753 #define DAGB2_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 4754 #define DAGB2_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 4755 #define DAGB2_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 4756 #define DAGB2_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 4757 #define DAGB2_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 4758 #define DAGB2_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 4759 #define DAGB2_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L 4760 #define DAGB2_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 4761 #define DAGB2_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L 4762 #define DAGB2_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 4763 #define DAGB2_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 4764 //DAGB2_WR_VC5_CNTL 4765 #define DAGB2_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 4766 #define DAGB2_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 4767 #define DAGB2_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 4768 #define DAGB2_WR_VC5_CNTL__MAX_BW__SHIFT 0xc 4769 #define DAGB2_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 4770 #define DAGB2_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 4771 #define DAGB2_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 4772 #define DAGB2_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 4773 #define DAGB2_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 4774 #define DAGB2_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 4775 #define DAGB2_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 4776 #define DAGB2_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L 4777 #define DAGB2_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 4778 #define DAGB2_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L 4779 #define DAGB2_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 4780 #define DAGB2_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 4781 //DAGB2_WR_VC6_CNTL 4782 #define DAGB2_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 4783 #define DAGB2_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 4784 #define DAGB2_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 4785 #define DAGB2_WR_VC6_CNTL__MAX_BW__SHIFT 0xc 4786 #define DAGB2_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 4787 #define DAGB2_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 4788 #define DAGB2_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 4789 #define DAGB2_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 4790 #define DAGB2_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 4791 #define DAGB2_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 4792 #define DAGB2_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 4793 #define DAGB2_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L 4794 #define DAGB2_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 4795 #define DAGB2_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L 4796 #define DAGB2_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 4797 #define DAGB2_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 4798 //DAGB2_WR_VC7_CNTL 4799 #define DAGB2_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 4800 #define DAGB2_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 4801 #define DAGB2_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 4802 #define DAGB2_WR_VC7_CNTL__MAX_BW__SHIFT 0xc 4803 #define DAGB2_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 4804 #define DAGB2_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 4805 #define DAGB2_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 4806 #define DAGB2_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 4807 #define DAGB2_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 4808 #define DAGB2_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 4809 #define DAGB2_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 4810 #define DAGB2_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L 4811 #define DAGB2_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 4812 #define DAGB2_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L 4813 #define DAGB2_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 4814 #define DAGB2_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 4815 //DAGB2_WR_CNTL_MISC 4816 #define DAGB2_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 4817 #define DAGB2_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 4818 #define DAGB2_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 4819 #define DAGB2_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 4820 #define DAGB2_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 4821 #define DAGB2_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 4822 #define DAGB2_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a 4823 #define DAGB2_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 4824 #define DAGB2_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 4825 #define DAGB2_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 4826 #define DAGB2_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 4827 #define DAGB2_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 4828 #define DAGB2_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 4829 #define DAGB2_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L 4830 //DAGB2_WR_TLB_CREDIT 4831 #define DAGB2_WR_TLB_CREDIT__TLB0__SHIFT 0x0 4832 #define DAGB2_WR_TLB_CREDIT__TLB1__SHIFT 0x5 4833 #define DAGB2_WR_TLB_CREDIT__TLB2__SHIFT 0xa 4834 #define DAGB2_WR_TLB_CREDIT__TLB3__SHIFT 0xf 4835 #define DAGB2_WR_TLB_CREDIT__TLB4__SHIFT 0x14 4836 #define DAGB2_WR_TLB_CREDIT__TLB5__SHIFT 0x19 4837 #define DAGB2_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL 4838 #define DAGB2_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L 4839 #define DAGB2_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L 4840 #define DAGB2_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L 4841 #define DAGB2_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L 4842 #define DAGB2_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L 4843 //DAGB2_WR_DATA_CREDIT 4844 #define DAGB2_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 4845 #define DAGB2_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 4846 #define DAGB2_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 4847 #define DAGB2_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 4848 #define DAGB2_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL 4849 #define DAGB2_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L 4850 #define DAGB2_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L 4851 #define DAGB2_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L 4852 //DAGB2_WR_MISC_CREDIT 4853 #define DAGB2_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 4854 #define DAGB2_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 4855 #define DAGB2_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 4856 #define DAGB2_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 4857 #define DAGB2_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL 4858 #define DAGB2_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L 4859 #define DAGB2_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L 4860 #define DAGB2_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L 4861 //DAGB2_WRCLI_ASK_PENDING 4862 #define DAGB2_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 4863 #define DAGB2_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 4864 //DAGB2_WRCLI_GO_PENDING 4865 #define DAGB2_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 4866 #define DAGB2_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 4867 //DAGB2_WRCLI_GBLSEND_PENDING 4868 #define DAGB2_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 4869 #define DAGB2_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 4870 //DAGB2_WRCLI_TLB_PENDING 4871 #define DAGB2_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 4872 #define DAGB2_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 4873 //DAGB2_WRCLI_OARB_PENDING 4874 #define DAGB2_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 4875 #define DAGB2_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 4876 //DAGB2_WRCLI_OSD_PENDING 4877 #define DAGB2_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 4878 #define DAGB2_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 4879 //DAGB2_WRCLI_DBUS_ASK_PENDING 4880 #define DAGB2_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 4881 #define DAGB2_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 4882 //DAGB2_WRCLI_DBUS_GO_PENDING 4883 #define DAGB2_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 4884 #define DAGB2_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 4885 //DAGB2_DAGB_DLY 4886 #define DAGB2_DAGB_DLY__DLY__SHIFT 0x0 4887 #define DAGB2_DAGB_DLY__CLI__SHIFT 0x8 4888 #define DAGB2_DAGB_DLY__POS__SHIFT 0x10 4889 #define DAGB2_DAGB_DLY__DLY_MASK 0x000000FFL 4890 #define DAGB2_DAGB_DLY__CLI_MASK 0x0000FF00L 4891 #define DAGB2_DAGB_DLY__POS_MASK 0x000F0000L 4892 //DAGB2_CNTL_MISC 4893 #define DAGB2_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 4894 #define DAGB2_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 4895 #define DAGB2_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 4896 #define DAGB2_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 4897 #define DAGB2_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc 4898 #define DAGB2_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf 4899 #define DAGB2_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 4900 #define DAGB2_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 4901 #define DAGB2_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 4902 #define DAGB2_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e 4903 #define DAGB2_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L 4904 #define DAGB2_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L 4905 #define DAGB2_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L 4906 #define DAGB2_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L 4907 #define DAGB2_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L 4908 #define DAGB2_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L 4909 #define DAGB2_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L 4910 #define DAGB2_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L 4911 #define DAGB2_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L 4912 #define DAGB2_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L 4913 //DAGB2_CNTL_MISC2 4914 #define DAGB2_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 4915 #define DAGB2_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 4916 #define DAGB2_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 4917 #define DAGB2_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 4918 #define DAGB2_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 4919 #define DAGB2_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 4920 #define DAGB2_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 4921 #define DAGB2_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 4922 #define DAGB2_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 4923 #define DAGB2_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 4924 #define DAGB2_CNTL_MISC2__SWAP_CTL__SHIFT 0xa 4925 #define DAGB2_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xb 4926 #define DAGB2_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x11 4927 #define DAGB2_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L 4928 #define DAGB2_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L 4929 #define DAGB2_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L 4930 #define DAGB2_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L 4931 #define DAGB2_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L 4932 #define DAGB2_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L 4933 #define DAGB2_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L 4934 #define DAGB2_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L 4935 #define DAGB2_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L 4936 #define DAGB2_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L 4937 #define DAGB2_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L 4938 #define DAGB2_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000800L 4939 #define DAGB2_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x007E0000L 4940 //DAGB2_FIFO_EMPTY 4941 #define DAGB2_FIFO_EMPTY__EMPTY__SHIFT 0x0 4942 #define DAGB2_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL 4943 //DAGB2_FIFO_FULL 4944 #define DAGB2_FIFO_FULL__FULL__SHIFT 0x0 4945 #define DAGB2_FIFO_FULL__FULL_MASK 0x007FFFFFL 4946 //DAGB2_WR_CREDITS_FULL 4947 #define DAGB2_WR_CREDITS_FULL__FULL__SHIFT 0x0 4948 #define DAGB2_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL 4949 //DAGB2_RD_CREDITS_FULL 4950 #define DAGB2_RD_CREDITS_FULL__FULL__SHIFT 0x0 4951 #define DAGB2_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL 4952 //DAGB2_PERFCOUNTER_LO 4953 #define DAGB2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 4954 #define DAGB2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 4955 //DAGB2_PERFCOUNTER_HI 4956 #define DAGB2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 4957 #define DAGB2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 4958 #define DAGB2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 4959 #define DAGB2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 4960 //DAGB2_PERFCOUNTER0_CFG 4961 #define DAGB2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 4962 #define DAGB2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 4963 #define DAGB2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 4964 #define DAGB2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 4965 #define DAGB2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 4966 #define DAGB2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 4967 #define DAGB2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 4968 #define DAGB2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 4969 #define DAGB2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 4970 #define DAGB2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 4971 //DAGB2_PERFCOUNTER1_CFG 4972 #define DAGB2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 4973 #define DAGB2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 4974 #define DAGB2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 4975 #define DAGB2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 4976 #define DAGB2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 4977 #define DAGB2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 4978 #define DAGB2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 4979 #define DAGB2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 4980 #define DAGB2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 4981 #define DAGB2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 4982 //DAGB2_PERFCOUNTER2_CFG 4983 #define DAGB2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 4984 #define DAGB2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 4985 #define DAGB2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 4986 #define DAGB2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 4987 #define DAGB2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 4988 #define DAGB2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 4989 #define DAGB2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 4990 #define DAGB2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 4991 #define DAGB2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 4992 #define DAGB2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 4993 //DAGB2_PERFCOUNTER_RSLT_CNTL 4994 #define DAGB2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 4995 #define DAGB2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 4996 #define DAGB2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 4997 #define DAGB2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 4998 #define DAGB2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 4999 #define DAGB2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 5000 #define DAGB2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 5001 #define DAGB2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 5002 #define DAGB2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 5003 #define DAGB2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 5004 #define DAGB2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 5005 #define DAGB2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 5006 //DAGB2_RESERVE0 5007 #define DAGB2_RESERVE0__RESERVE__SHIFT 0x0 5008 #define DAGB2_RESERVE0__RESERVE_MASK 0xFFFFFFFFL 5009 //DAGB2_RESERVE1 5010 #define DAGB2_RESERVE1__RESERVE__SHIFT 0x0 5011 #define DAGB2_RESERVE1__RESERVE_MASK 0xFFFFFFFFL 5012 //DAGB2_RESERVE2 5013 #define DAGB2_RESERVE2__RESERVE__SHIFT 0x0 5014 #define DAGB2_RESERVE2__RESERVE_MASK 0xFFFFFFFFL 5015 //DAGB2_RESERVE3 5016 #define DAGB2_RESERVE3__RESERVE__SHIFT 0x0 5017 #define DAGB2_RESERVE3__RESERVE_MASK 0xFFFFFFFFL 5018 //DAGB2_RESERVE4 5019 #define DAGB2_RESERVE4__RESERVE__SHIFT 0x0 5020 #define DAGB2_RESERVE4__RESERVE_MASK 0xFFFFFFFFL 5021 //DAGB2_RESERVE5 5022 #define DAGB2_RESERVE5__RESERVE__SHIFT 0x0 5023 #define DAGB2_RESERVE5__RESERVE_MASK 0xFFFFFFFFL 5024 //DAGB2_RESERVE6 5025 #define DAGB2_RESERVE6__RESERVE__SHIFT 0x0 5026 #define DAGB2_RESERVE6__RESERVE_MASK 0xFFFFFFFFL 5027 //DAGB2_RESERVE7 5028 #define DAGB2_RESERVE7__RESERVE__SHIFT 0x0 5029 #define DAGB2_RESERVE7__RESERVE_MASK 0xFFFFFFFFL 5030 //DAGB2_RESERVE8 5031 #define DAGB2_RESERVE8__RESERVE__SHIFT 0x0 5032 #define DAGB2_RESERVE8__RESERVE_MASK 0xFFFFFFFFL 5033 //DAGB2_RESERVE9 5034 #define DAGB2_RESERVE9__RESERVE__SHIFT 0x0 5035 #define DAGB2_RESERVE9__RESERVE_MASK 0xFFFFFFFFL 5036 //DAGB2_RESERVE10 5037 #define DAGB2_RESERVE10__RESERVE__SHIFT 0x0 5038 #define DAGB2_RESERVE10__RESERVE_MASK 0xFFFFFFFFL 5039 //DAGB2_RESERVE11 5040 #define DAGB2_RESERVE11__RESERVE__SHIFT 0x0 5041 #define DAGB2_RESERVE11__RESERVE_MASK 0xFFFFFFFFL 5042 //DAGB2_RESERVE12 5043 #define DAGB2_RESERVE12__RESERVE__SHIFT 0x0 5044 #define DAGB2_RESERVE12__RESERVE_MASK 0xFFFFFFFFL 5045 //DAGB2_RESERVE13 5046 #define DAGB2_RESERVE13__RESERVE__SHIFT 0x0 5047 #define DAGB2_RESERVE13__RESERVE_MASK 0xFFFFFFFFL 5048 5049 5050 // addressBlock: mmhub_dagb_dagbdec3 5051 //DAGB3_RDCLI0 5052 #define DAGB3_RDCLI0__VIRT_CHAN__SHIFT 0x0 5053 #define DAGB3_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 5054 #define DAGB3_RDCLI0__URG_HIGH__SHIFT 0x4 5055 #define DAGB3_RDCLI0__URG_LOW__SHIFT 0x8 5056 #define DAGB3_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 5057 #define DAGB3_RDCLI0__MAX_BW__SHIFT 0xd 5058 #define DAGB3_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 5059 #define DAGB3_RDCLI0__MIN_BW__SHIFT 0x16 5060 #define DAGB3_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 5061 #define DAGB3_RDCLI0__MAX_OSD__SHIFT 0x1a 5062 #define DAGB3_RDCLI0__VIRT_CHAN_MASK 0x00000007L 5063 #define DAGB3_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 5064 #define DAGB3_RDCLI0__URG_HIGH_MASK 0x000000F0L 5065 #define DAGB3_RDCLI0__URG_LOW_MASK 0x00000F00L 5066 #define DAGB3_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L 5067 #define DAGB3_RDCLI0__MAX_BW_MASK 0x001FE000L 5068 #define DAGB3_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L 5069 #define DAGB3_RDCLI0__MIN_BW_MASK 0x01C00000L 5070 #define DAGB3_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 5071 #define DAGB3_RDCLI0__MAX_OSD_MASK 0xFC000000L 5072 //DAGB3_RDCLI1 5073 #define DAGB3_RDCLI1__VIRT_CHAN__SHIFT 0x0 5074 #define DAGB3_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 5075 #define DAGB3_RDCLI1__URG_HIGH__SHIFT 0x4 5076 #define DAGB3_RDCLI1__URG_LOW__SHIFT 0x8 5077 #define DAGB3_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc 5078 #define DAGB3_RDCLI1__MAX_BW__SHIFT 0xd 5079 #define DAGB3_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 5080 #define DAGB3_RDCLI1__MIN_BW__SHIFT 0x16 5081 #define DAGB3_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 5082 #define DAGB3_RDCLI1__MAX_OSD__SHIFT 0x1a 5083 #define DAGB3_RDCLI1__VIRT_CHAN_MASK 0x00000007L 5084 #define DAGB3_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 5085 #define DAGB3_RDCLI1__URG_HIGH_MASK 0x000000F0L 5086 #define DAGB3_RDCLI1__URG_LOW_MASK 0x00000F00L 5087 #define DAGB3_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L 5088 #define DAGB3_RDCLI1__MAX_BW_MASK 0x001FE000L 5089 #define DAGB3_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L 5090 #define DAGB3_RDCLI1__MIN_BW_MASK 0x01C00000L 5091 #define DAGB3_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 5092 #define DAGB3_RDCLI1__MAX_OSD_MASK 0xFC000000L 5093 //DAGB3_RDCLI2 5094 #define DAGB3_RDCLI2__VIRT_CHAN__SHIFT 0x0 5095 #define DAGB3_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 5096 #define DAGB3_RDCLI2__URG_HIGH__SHIFT 0x4 5097 #define DAGB3_RDCLI2__URG_LOW__SHIFT 0x8 5098 #define DAGB3_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc 5099 #define DAGB3_RDCLI2__MAX_BW__SHIFT 0xd 5100 #define DAGB3_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 5101 #define DAGB3_RDCLI2__MIN_BW__SHIFT 0x16 5102 #define DAGB3_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 5103 #define DAGB3_RDCLI2__MAX_OSD__SHIFT 0x1a 5104 #define DAGB3_RDCLI2__VIRT_CHAN_MASK 0x00000007L 5105 #define DAGB3_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 5106 #define DAGB3_RDCLI2__URG_HIGH_MASK 0x000000F0L 5107 #define DAGB3_RDCLI2__URG_LOW_MASK 0x00000F00L 5108 #define DAGB3_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L 5109 #define DAGB3_RDCLI2__MAX_BW_MASK 0x001FE000L 5110 #define DAGB3_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L 5111 #define DAGB3_RDCLI2__MIN_BW_MASK 0x01C00000L 5112 #define DAGB3_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 5113 #define DAGB3_RDCLI2__MAX_OSD_MASK 0xFC000000L 5114 //DAGB3_RDCLI3 5115 #define DAGB3_RDCLI3__VIRT_CHAN__SHIFT 0x0 5116 #define DAGB3_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 5117 #define DAGB3_RDCLI3__URG_HIGH__SHIFT 0x4 5118 #define DAGB3_RDCLI3__URG_LOW__SHIFT 0x8 5119 #define DAGB3_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc 5120 #define DAGB3_RDCLI3__MAX_BW__SHIFT 0xd 5121 #define DAGB3_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 5122 #define DAGB3_RDCLI3__MIN_BW__SHIFT 0x16 5123 #define DAGB3_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 5124 #define DAGB3_RDCLI3__MAX_OSD__SHIFT 0x1a 5125 #define DAGB3_RDCLI3__VIRT_CHAN_MASK 0x00000007L 5126 #define DAGB3_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 5127 #define DAGB3_RDCLI3__URG_HIGH_MASK 0x000000F0L 5128 #define DAGB3_RDCLI3__URG_LOW_MASK 0x00000F00L 5129 #define DAGB3_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L 5130 #define DAGB3_RDCLI3__MAX_BW_MASK 0x001FE000L 5131 #define DAGB3_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L 5132 #define DAGB3_RDCLI3__MIN_BW_MASK 0x01C00000L 5133 #define DAGB3_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 5134 #define DAGB3_RDCLI3__MAX_OSD_MASK 0xFC000000L 5135 //DAGB3_RDCLI4 5136 #define DAGB3_RDCLI4__VIRT_CHAN__SHIFT 0x0 5137 #define DAGB3_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 5138 #define DAGB3_RDCLI4__URG_HIGH__SHIFT 0x4 5139 #define DAGB3_RDCLI4__URG_LOW__SHIFT 0x8 5140 #define DAGB3_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc 5141 #define DAGB3_RDCLI4__MAX_BW__SHIFT 0xd 5142 #define DAGB3_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 5143 #define DAGB3_RDCLI4__MIN_BW__SHIFT 0x16 5144 #define DAGB3_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 5145 #define DAGB3_RDCLI4__MAX_OSD__SHIFT 0x1a 5146 #define DAGB3_RDCLI4__VIRT_CHAN_MASK 0x00000007L 5147 #define DAGB3_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 5148 #define DAGB3_RDCLI4__URG_HIGH_MASK 0x000000F0L 5149 #define DAGB3_RDCLI4__URG_LOW_MASK 0x00000F00L 5150 #define DAGB3_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L 5151 #define DAGB3_RDCLI4__MAX_BW_MASK 0x001FE000L 5152 #define DAGB3_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L 5153 #define DAGB3_RDCLI4__MIN_BW_MASK 0x01C00000L 5154 #define DAGB3_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 5155 #define DAGB3_RDCLI4__MAX_OSD_MASK 0xFC000000L 5156 //DAGB3_RDCLI5 5157 #define DAGB3_RDCLI5__VIRT_CHAN__SHIFT 0x0 5158 #define DAGB3_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 5159 #define DAGB3_RDCLI5__URG_HIGH__SHIFT 0x4 5160 #define DAGB3_RDCLI5__URG_LOW__SHIFT 0x8 5161 #define DAGB3_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc 5162 #define DAGB3_RDCLI5__MAX_BW__SHIFT 0xd 5163 #define DAGB3_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 5164 #define DAGB3_RDCLI5__MIN_BW__SHIFT 0x16 5165 #define DAGB3_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 5166 #define DAGB3_RDCLI5__MAX_OSD__SHIFT 0x1a 5167 #define DAGB3_RDCLI5__VIRT_CHAN_MASK 0x00000007L 5168 #define DAGB3_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 5169 #define DAGB3_RDCLI5__URG_HIGH_MASK 0x000000F0L 5170 #define DAGB3_RDCLI5__URG_LOW_MASK 0x00000F00L 5171 #define DAGB3_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L 5172 #define DAGB3_RDCLI5__MAX_BW_MASK 0x001FE000L 5173 #define DAGB3_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L 5174 #define DAGB3_RDCLI5__MIN_BW_MASK 0x01C00000L 5175 #define DAGB3_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 5176 #define DAGB3_RDCLI5__MAX_OSD_MASK 0xFC000000L 5177 //DAGB3_RDCLI6 5178 #define DAGB3_RDCLI6__VIRT_CHAN__SHIFT 0x0 5179 #define DAGB3_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 5180 #define DAGB3_RDCLI6__URG_HIGH__SHIFT 0x4 5181 #define DAGB3_RDCLI6__URG_LOW__SHIFT 0x8 5182 #define DAGB3_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc 5183 #define DAGB3_RDCLI6__MAX_BW__SHIFT 0xd 5184 #define DAGB3_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 5185 #define DAGB3_RDCLI6__MIN_BW__SHIFT 0x16 5186 #define DAGB3_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 5187 #define DAGB3_RDCLI6__MAX_OSD__SHIFT 0x1a 5188 #define DAGB3_RDCLI6__VIRT_CHAN_MASK 0x00000007L 5189 #define DAGB3_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 5190 #define DAGB3_RDCLI6__URG_HIGH_MASK 0x000000F0L 5191 #define DAGB3_RDCLI6__URG_LOW_MASK 0x00000F00L 5192 #define DAGB3_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L 5193 #define DAGB3_RDCLI6__MAX_BW_MASK 0x001FE000L 5194 #define DAGB3_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L 5195 #define DAGB3_RDCLI6__MIN_BW_MASK 0x01C00000L 5196 #define DAGB3_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 5197 #define DAGB3_RDCLI6__MAX_OSD_MASK 0xFC000000L 5198 //DAGB3_RDCLI7 5199 #define DAGB3_RDCLI7__VIRT_CHAN__SHIFT 0x0 5200 #define DAGB3_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 5201 #define DAGB3_RDCLI7__URG_HIGH__SHIFT 0x4 5202 #define DAGB3_RDCLI7__URG_LOW__SHIFT 0x8 5203 #define DAGB3_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc 5204 #define DAGB3_RDCLI7__MAX_BW__SHIFT 0xd 5205 #define DAGB3_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 5206 #define DAGB3_RDCLI7__MIN_BW__SHIFT 0x16 5207 #define DAGB3_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 5208 #define DAGB3_RDCLI7__MAX_OSD__SHIFT 0x1a 5209 #define DAGB3_RDCLI7__VIRT_CHAN_MASK 0x00000007L 5210 #define DAGB3_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 5211 #define DAGB3_RDCLI7__URG_HIGH_MASK 0x000000F0L 5212 #define DAGB3_RDCLI7__URG_LOW_MASK 0x00000F00L 5213 #define DAGB3_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L 5214 #define DAGB3_RDCLI7__MAX_BW_MASK 0x001FE000L 5215 #define DAGB3_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L 5216 #define DAGB3_RDCLI7__MIN_BW_MASK 0x01C00000L 5217 #define DAGB3_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 5218 #define DAGB3_RDCLI7__MAX_OSD_MASK 0xFC000000L 5219 //DAGB3_RDCLI8 5220 #define DAGB3_RDCLI8__VIRT_CHAN__SHIFT 0x0 5221 #define DAGB3_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 5222 #define DAGB3_RDCLI8__URG_HIGH__SHIFT 0x4 5223 #define DAGB3_RDCLI8__URG_LOW__SHIFT 0x8 5224 #define DAGB3_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc 5225 #define DAGB3_RDCLI8__MAX_BW__SHIFT 0xd 5226 #define DAGB3_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 5227 #define DAGB3_RDCLI8__MIN_BW__SHIFT 0x16 5228 #define DAGB3_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 5229 #define DAGB3_RDCLI8__MAX_OSD__SHIFT 0x1a 5230 #define DAGB3_RDCLI8__VIRT_CHAN_MASK 0x00000007L 5231 #define DAGB3_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 5232 #define DAGB3_RDCLI8__URG_HIGH_MASK 0x000000F0L 5233 #define DAGB3_RDCLI8__URG_LOW_MASK 0x00000F00L 5234 #define DAGB3_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L 5235 #define DAGB3_RDCLI8__MAX_BW_MASK 0x001FE000L 5236 #define DAGB3_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L 5237 #define DAGB3_RDCLI8__MIN_BW_MASK 0x01C00000L 5238 #define DAGB3_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 5239 #define DAGB3_RDCLI8__MAX_OSD_MASK 0xFC000000L 5240 //DAGB3_RDCLI9 5241 #define DAGB3_RDCLI9__VIRT_CHAN__SHIFT 0x0 5242 #define DAGB3_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 5243 #define DAGB3_RDCLI9__URG_HIGH__SHIFT 0x4 5244 #define DAGB3_RDCLI9__URG_LOW__SHIFT 0x8 5245 #define DAGB3_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc 5246 #define DAGB3_RDCLI9__MAX_BW__SHIFT 0xd 5247 #define DAGB3_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 5248 #define DAGB3_RDCLI9__MIN_BW__SHIFT 0x16 5249 #define DAGB3_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 5250 #define DAGB3_RDCLI9__MAX_OSD__SHIFT 0x1a 5251 #define DAGB3_RDCLI9__VIRT_CHAN_MASK 0x00000007L 5252 #define DAGB3_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 5253 #define DAGB3_RDCLI9__URG_HIGH_MASK 0x000000F0L 5254 #define DAGB3_RDCLI9__URG_LOW_MASK 0x00000F00L 5255 #define DAGB3_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L 5256 #define DAGB3_RDCLI9__MAX_BW_MASK 0x001FE000L 5257 #define DAGB3_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L 5258 #define DAGB3_RDCLI9__MIN_BW_MASK 0x01C00000L 5259 #define DAGB3_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 5260 #define DAGB3_RDCLI9__MAX_OSD_MASK 0xFC000000L 5261 //DAGB3_RDCLI10 5262 #define DAGB3_RDCLI10__VIRT_CHAN__SHIFT 0x0 5263 #define DAGB3_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 5264 #define DAGB3_RDCLI10__URG_HIGH__SHIFT 0x4 5265 #define DAGB3_RDCLI10__URG_LOW__SHIFT 0x8 5266 #define DAGB3_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc 5267 #define DAGB3_RDCLI10__MAX_BW__SHIFT 0xd 5268 #define DAGB3_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 5269 #define DAGB3_RDCLI10__MIN_BW__SHIFT 0x16 5270 #define DAGB3_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 5271 #define DAGB3_RDCLI10__MAX_OSD__SHIFT 0x1a 5272 #define DAGB3_RDCLI10__VIRT_CHAN_MASK 0x00000007L 5273 #define DAGB3_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 5274 #define DAGB3_RDCLI10__URG_HIGH_MASK 0x000000F0L 5275 #define DAGB3_RDCLI10__URG_LOW_MASK 0x00000F00L 5276 #define DAGB3_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L 5277 #define DAGB3_RDCLI10__MAX_BW_MASK 0x001FE000L 5278 #define DAGB3_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L 5279 #define DAGB3_RDCLI10__MIN_BW_MASK 0x01C00000L 5280 #define DAGB3_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 5281 #define DAGB3_RDCLI10__MAX_OSD_MASK 0xFC000000L 5282 //DAGB3_RDCLI11 5283 #define DAGB3_RDCLI11__VIRT_CHAN__SHIFT 0x0 5284 #define DAGB3_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 5285 #define DAGB3_RDCLI11__URG_HIGH__SHIFT 0x4 5286 #define DAGB3_RDCLI11__URG_LOW__SHIFT 0x8 5287 #define DAGB3_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc 5288 #define DAGB3_RDCLI11__MAX_BW__SHIFT 0xd 5289 #define DAGB3_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 5290 #define DAGB3_RDCLI11__MIN_BW__SHIFT 0x16 5291 #define DAGB3_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 5292 #define DAGB3_RDCLI11__MAX_OSD__SHIFT 0x1a 5293 #define DAGB3_RDCLI11__VIRT_CHAN_MASK 0x00000007L 5294 #define DAGB3_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 5295 #define DAGB3_RDCLI11__URG_HIGH_MASK 0x000000F0L 5296 #define DAGB3_RDCLI11__URG_LOW_MASK 0x00000F00L 5297 #define DAGB3_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L 5298 #define DAGB3_RDCLI11__MAX_BW_MASK 0x001FE000L 5299 #define DAGB3_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L 5300 #define DAGB3_RDCLI11__MIN_BW_MASK 0x01C00000L 5301 #define DAGB3_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 5302 #define DAGB3_RDCLI11__MAX_OSD_MASK 0xFC000000L 5303 //DAGB3_RDCLI12 5304 #define DAGB3_RDCLI12__VIRT_CHAN__SHIFT 0x0 5305 #define DAGB3_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 5306 #define DAGB3_RDCLI12__URG_HIGH__SHIFT 0x4 5307 #define DAGB3_RDCLI12__URG_LOW__SHIFT 0x8 5308 #define DAGB3_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc 5309 #define DAGB3_RDCLI12__MAX_BW__SHIFT 0xd 5310 #define DAGB3_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 5311 #define DAGB3_RDCLI12__MIN_BW__SHIFT 0x16 5312 #define DAGB3_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 5313 #define DAGB3_RDCLI12__MAX_OSD__SHIFT 0x1a 5314 #define DAGB3_RDCLI12__VIRT_CHAN_MASK 0x00000007L 5315 #define DAGB3_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 5316 #define DAGB3_RDCLI12__URG_HIGH_MASK 0x000000F0L 5317 #define DAGB3_RDCLI12__URG_LOW_MASK 0x00000F00L 5318 #define DAGB3_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L 5319 #define DAGB3_RDCLI12__MAX_BW_MASK 0x001FE000L 5320 #define DAGB3_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L 5321 #define DAGB3_RDCLI12__MIN_BW_MASK 0x01C00000L 5322 #define DAGB3_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 5323 #define DAGB3_RDCLI12__MAX_OSD_MASK 0xFC000000L 5324 //DAGB3_RDCLI13 5325 #define DAGB3_RDCLI13__VIRT_CHAN__SHIFT 0x0 5326 #define DAGB3_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 5327 #define DAGB3_RDCLI13__URG_HIGH__SHIFT 0x4 5328 #define DAGB3_RDCLI13__URG_LOW__SHIFT 0x8 5329 #define DAGB3_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc 5330 #define DAGB3_RDCLI13__MAX_BW__SHIFT 0xd 5331 #define DAGB3_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 5332 #define DAGB3_RDCLI13__MIN_BW__SHIFT 0x16 5333 #define DAGB3_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 5334 #define DAGB3_RDCLI13__MAX_OSD__SHIFT 0x1a 5335 #define DAGB3_RDCLI13__VIRT_CHAN_MASK 0x00000007L 5336 #define DAGB3_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 5337 #define DAGB3_RDCLI13__URG_HIGH_MASK 0x000000F0L 5338 #define DAGB3_RDCLI13__URG_LOW_MASK 0x00000F00L 5339 #define DAGB3_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L 5340 #define DAGB3_RDCLI13__MAX_BW_MASK 0x001FE000L 5341 #define DAGB3_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L 5342 #define DAGB3_RDCLI13__MIN_BW_MASK 0x01C00000L 5343 #define DAGB3_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 5344 #define DAGB3_RDCLI13__MAX_OSD_MASK 0xFC000000L 5345 //DAGB3_RDCLI14 5346 #define DAGB3_RDCLI14__VIRT_CHAN__SHIFT 0x0 5347 #define DAGB3_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 5348 #define DAGB3_RDCLI14__URG_HIGH__SHIFT 0x4 5349 #define DAGB3_RDCLI14__URG_LOW__SHIFT 0x8 5350 #define DAGB3_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc 5351 #define DAGB3_RDCLI14__MAX_BW__SHIFT 0xd 5352 #define DAGB3_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 5353 #define DAGB3_RDCLI14__MIN_BW__SHIFT 0x16 5354 #define DAGB3_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 5355 #define DAGB3_RDCLI14__MAX_OSD__SHIFT 0x1a 5356 #define DAGB3_RDCLI14__VIRT_CHAN_MASK 0x00000007L 5357 #define DAGB3_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 5358 #define DAGB3_RDCLI14__URG_HIGH_MASK 0x000000F0L 5359 #define DAGB3_RDCLI14__URG_LOW_MASK 0x00000F00L 5360 #define DAGB3_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L 5361 #define DAGB3_RDCLI14__MAX_BW_MASK 0x001FE000L 5362 #define DAGB3_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L 5363 #define DAGB3_RDCLI14__MIN_BW_MASK 0x01C00000L 5364 #define DAGB3_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 5365 #define DAGB3_RDCLI14__MAX_OSD_MASK 0xFC000000L 5366 //DAGB3_RDCLI15 5367 #define DAGB3_RDCLI15__VIRT_CHAN__SHIFT 0x0 5368 #define DAGB3_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 5369 #define DAGB3_RDCLI15__URG_HIGH__SHIFT 0x4 5370 #define DAGB3_RDCLI15__URG_LOW__SHIFT 0x8 5371 #define DAGB3_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc 5372 #define DAGB3_RDCLI15__MAX_BW__SHIFT 0xd 5373 #define DAGB3_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 5374 #define DAGB3_RDCLI15__MIN_BW__SHIFT 0x16 5375 #define DAGB3_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 5376 #define DAGB3_RDCLI15__MAX_OSD__SHIFT 0x1a 5377 #define DAGB3_RDCLI15__VIRT_CHAN_MASK 0x00000007L 5378 #define DAGB3_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 5379 #define DAGB3_RDCLI15__URG_HIGH_MASK 0x000000F0L 5380 #define DAGB3_RDCLI15__URG_LOW_MASK 0x00000F00L 5381 #define DAGB3_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L 5382 #define DAGB3_RDCLI15__MAX_BW_MASK 0x001FE000L 5383 #define DAGB3_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L 5384 #define DAGB3_RDCLI15__MIN_BW_MASK 0x01C00000L 5385 #define DAGB3_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 5386 #define DAGB3_RDCLI15__MAX_OSD_MASK 0xFC000000L 5387 //DAGB3_RD_CNTL 5388 #define DAGB3_RD_CNTL__SCLK_FREQ__SHIFT 0x0 5389 #define DAGB3_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 5390 #define DAGB3_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 5391 #define DAGB3_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 5392 #define DAGB3_RD_CNTL__IO_LEVEL__SHIFT 0x11 5393 #define DAGB3_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 5394 #define DAGB3_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 5395 #define DAGB3_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL 5396 #define DAGB3_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 5397 #define DAGB3_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 5398 #define DAGB3_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 5399 #define DAGB3_RD_CNTL__IO_LEVEL_MASK 0x000E0000L 5400 #define DAGB3_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 5401 #define DAGB3_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L 5402 //DAGB3_RD_GMI_CNTL 5403 #define DAGB3_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 5404 #define DAGB3_RD_GMI_CNTL__LEVEL__SHIFT 0x6 5405 #define DAGB3_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 5406 #define DAGB3_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 5407 #define DAGB3_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 5408 #define DAGB3_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L 5409 #define DAGB3_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 5410 #define DAGB3_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 5411 //DAGB3_RD_ADDR_DAGB 5412 #define DAGB3_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 5413 #define DAGB3_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 5414 #define DAGB3_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 5415 #define DAGB3_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 5416 #define DAGB3_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 5417 #define DAGB3_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 5418 #define DAGB3_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 5419 #define DAGB3_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 5420 //DAGB3_RD_OUTPUT_DAGB_MAX_BURST 5421 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 5422 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 5423 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 5424 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 5425 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 5426 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 5427 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 5428 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 5429 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 5430 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 5431 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 5432 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 5433 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 5434 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 5435 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 5436 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 5437 //DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER 5438 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 5439 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 5440 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 5441 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 5442 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 5443 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 5444 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 5445 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 5446 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 5447 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 5448 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 5449 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 5450 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 5451 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 5452 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 5453 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 5454 //DAGB3_RD_CGTT_CLK_CTRL 5455 #define DAGB3_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 5456 #define DAGB3_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 5457 #define DAGB3_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 5458 #define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 5459 #define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 5460 #define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 5461 #define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 5462 #define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 5463 #define DAGB3_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 5464 #define DAGB3_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 5465 #define DAGB3_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 5466 #define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 5467 #define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 5468 #define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 5469 #define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 5470 #define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 5471 //DAGB3_L1TLB_RD_CGTT_CLK_CTRL 5472 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 5473 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 5474 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 5475 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 5476 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 5477 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 5478 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 5479 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 5480 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 5481 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 5482 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 5483 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 5484 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 5485 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 5486 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 5487 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 5488 //DAGB3_ATCVM_RD_CGTT_CLK_CTRL 5489 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 5490 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 5491 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 5492 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 5493 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 5494 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 5495 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 5496 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 5497 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 5498 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 5499 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 5500 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 5501 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 5502 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 5503 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 5504 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 5505 //DAGB3_RD_ADDR_DAGB_MAX_BURST0 5506 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 5507 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 5508 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 5509 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 5510 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 5511 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 5512 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 5513 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 5514 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 5515 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 5516 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 5517 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 5518 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 5519 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 5520 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 5521 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 5522 //DAGB3_RD_ADDR_DAGB_LAZY_TIMER0 5523 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 5524 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 5525 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 5526 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 5527 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 5528 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 5529 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 5530 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 5531 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 5532 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 5533 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 5534 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 5535 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 5536 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 5537 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 5538 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 5539 //DAGB3_RD_ADDR_DAGB_MAX_BURST1 5540 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 5541 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 5542 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 5543 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 5544 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 5545 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 5546 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 5547 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 5548 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 5549 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 5550 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 5551 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 5552 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 5553 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 5554 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 5555 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 5556 //DAGB3_RD_ADDR_DAGB_LAZY_TIMER1 5557 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 5558 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 5559 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 5560 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 5561 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 5562 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 5563 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 5564 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 5565 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 5566 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 5567 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 5568 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 5569 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 5570 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 5571 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 5572 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 5573 //DAGB3_RD_VC0_CNTL 5574 #define DAGB3_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 5575 #define DAGB3_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 5576 #define DAGB3_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 5577 #define DAGB3_RD_VC0_CNTL__MAX_BW__SHIFT 0xc 5578 #define DAGB3_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 5579 #define DAGB3_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 5580 #define DAGB3_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 5581 #define DAGB3_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 5582 #define DAGB3_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 5583 #define DAGB3_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 5584 #define DAGB3_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 5585 #define DAGB3_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L 5586 #define DAGB3_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 5587 #define DAGB3_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L 5588 #define DAGB3_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 5589 #define DAGB3_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 5590 //DAGB3_RD_VC1_CNTL 5591 #define DAGB3_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 5592 #define DAGB3_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 5593 #define DAGB3_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 5594 #define DAGB3_RD_VC1_CNTL__MAX_BW__SHIFT 0xc 5595 #define DAGB3_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 5596 #define DAGB3_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 5597 #define DAGB3_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 5598 #define DAGB3_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 5599 #define DAGB3_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 5600 #define DAGB3_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 5601 #define DAGB3_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 5602 #define DAGB3_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L 5603 #define DAGB3_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 5604 #define DAGB3_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L 5605 #define DAGB3_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 5606 #define DAGB3_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 5607 //DAGB3_RD_VC2_CNTL 5608 #define DAGB3_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 5609 #define DAGB3_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 5610 #define DAGB3_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 5611 #define DAGB3_RD_VC2_CNTL__MAX_BW__SHIFT 0xc 5612 #define DAGB3_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 5613 #define DAGB3_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 5614 #define DAGB3_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 5615 #define DAGB3_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 5616 #define DAGB3_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 5617 #define DAGB3_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 5618 #define DAGB3_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 5619 #define DAGB3_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L 5620 #define DAGB3_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 5621 #define DAGB3_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L 5622 #define DAGB3_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 5623 #define DAGB3_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 5624 //DAGB3_RD_VC3_CNTL 5625 #define DAGB3_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 5626 #define DAGB3_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 5627 #define DAGB3_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 5628 #define DAGB3_RD_VC3_CNTL__MAX_BW__SHIFT 0xc 5629 #define DAGB3_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 5630 #define DAGB3_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 5631 #define DAGB3_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 5632 #define DAGB3_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 5633 #define DAGB3_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 5634 #define DAGB3_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 5635 #define DAGB3_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 5636 #define DAGB3_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L 5637 #define DAGB3_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 5638 #define DAGB3_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L 5639 #define DAGB3_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 5640 #define DAGB3_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 5641 //DAGB3_RD_VC4_CNTL 5642 #define DAGB3_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 5643 #define DAGB3_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 5644 #define DAGB3_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 5645 #define DAGB3_RD_VC4_CNTL__MAX_BW__SHIFT 0xc 5646 #define DAGB3_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 5647 #define DAGB3_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 5648 #define DAGB3_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 5649 #define DAGB3_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 5650 #define DAGB3_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 5651 #define DAGB3_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 5652 #define DAGB3_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 5653 #define DAGB3_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L 5654 #define DAGB3_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 5655 #define DAGB3_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L 5656 #define DAGB3_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 5657 #define DAGB3_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 5658 //DAGB3_RD_VC5_CNTL 5659 #define DAGB3_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 5660 #define DAGB3_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 5661 #define DAGB3_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 5662 #define DAGB3_RD_VC5_CNTL__MAX_BW__SHIFT 0xc 5663 #define DAGB3_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 5664 #define DAGB3_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 5665 #define DAGB3_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 5666 #define DAGB3_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 5667 #define DAGB3_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 5668 #define DAGB3_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 5669 #define DAGB3_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 5670 #define DAGB3_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L 5671 #define DAGB3_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 5672 #define DAGB3_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L 5673 #define DAGB3_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 5674 #define DAGB3_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 5675 //DAGB3_RD_VC6_CNTL 5676 #define DAGB3_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 5677 #define DAGB3_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 5678 #define DAGB3_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 5679 #define DAGB3_RD_VC6_CNTL__MAX_BW__SHIFT 0xc 5680 #define DAGB3_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 5681 #define DAGB3_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 5682 #define DAGB3_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 5683 #define DAGB3_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 5684 #define DAGB3_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 5685 #define DAGB3_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 5686 #define DAGB3_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 5687 #define DAGB3_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L 5688 #define DAGB3_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 5689 #define DAGB3_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L 5690 #define DAGB3_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 5691 #define DAGB3_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 5692 //DAGB3_RD_VC7_CNTL 5693 #define DAGB3_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 5694 #define DAGB3_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 5695 #define DAGB3_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 5696 #define DAGB3_RD_VC7_CNTL__MAX_BW__SHIFT 0xc 5697 #define DAGB3_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 5698 #define DAGB3_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 5699 #define DAGB3_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 5700 #define DAGB3_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 5701 #define DAGB3_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 5702 #define DAGB3_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 5703 #define DAGB3_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 5704 #define DAGB3_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L 5705 #define DAGB3_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 5706 #define DAGB3_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L 5707 #define DAGB3_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 5708 #define DAGB3_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 5709 //DAGB3_RD_CNTL_MISC 5710 #define DAGB3_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 5711 #define DAGB3_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 5712 #define DAGB3_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 5713 #define DAGB3_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 5714 #define DAGB3_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 5715 #define DAGB3_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 5716 #define DAGB3_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a 5717 #define DAGB3_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 5718 #define DAGB3_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 5719 #define DAGB3_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 5720 #define DAGB3_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 5721 #define DAGB3_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 5722 #define DAGB3_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 5723 #define DAGB3_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L 5724 //DAGB3_RD_TLB_CREDIT 5725 #define DAGB3_RD_TLB_CREDIT__TLB0__SHIFT 0x0 5726 #define DAGB3_RD_TLB_CREDIT__TLB1__SHIFT 0x5 5727 #define DAGB3_RD_TLB_CREDIT__TLB2__SHIFT 0xa 5728 #define DAGB3_RD_TLB_CREDIT__TLB3__SHIFT 0xf 5729 #define DAGB3_RD_TLB_CREDIT__TLB4__SHIFT 0x14 5730 #define DAGB3_RD_TLB_CREDIT__TLB5__SHIFT 0x19 5731 #define DAGB3_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL 5732 #define DAGB3_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L 5733 #define DAGB3_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L 5734 #define DAGB3_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L 5735 #define DAGB3_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L 5736 #define DAGB3_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L 5737 //DAGB3_RDCLI_ASK_PENDING 5738 #define DAGB3_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 5739 #define DAGB3_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 5740 //DAGB3_RDCLI_GO_PENDING 5741 #define DAGB3_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 5742 #define DAGB3_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 5743 //DAGB3_RDCLI_GBLSEND_PENDING 5744 #define DAGB3_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 5745 #define DAGB3_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 5746 //DAGB3_RDCLI_TLB_PENDING 5747 #define DAGB3_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 5748 #define DAGB3_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 5749 //DAGB3_RDCLI_OARB_PENDING 5750 #define DAGB3_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 5751 #define DAGB3_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 5752 //DAGB3_RDCLI_OSD_PENDING 5753 #define DAGB3_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 5754 #define DAGB3_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 5755 //DAGB3_WRCLI0 5756 #define DAGB3_WRCLI0__VIRT_CHAN__SHIFT 0x0 5757 #define DAGB3_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 5758 #define DAGB3_WRCLI0__URG_HIGH__SHIFT 0x4 5759 #define DAGB3_WRCLI0__URG_LOW__SHIFT 0x8 5760 #define DAGB3_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc 5761 #define DAGB3_WRCLI0__MAX_BW__SHIFT 0xd 5762 #define DAGB3_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 5763 #define DAGB3_WRCLI0__MIN_BW__SHIFT 0x16 5764 #define DAGB3_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 5765 #define DAGB3_WRCLI0__MAX_OSD__SHIFT 0x1a 5766 #define DAGB3_WRCLI0__VIRT_CHAN_MASK 0x00000007L 5767 #define DAGB3_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 5768 #define DAGB3_WRCLI0__URG_HIGH_MASK 0x000000F0L 5769 #define DAGB3_WRCLI0__URG_LOW_MASK 0x00000F00L 5770 #define DAGB3_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L 5771 #define DAGB3_WRCLI0__MAX_BW_MASK 0x001FE000L 5772 #define DAGB3_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L 5773 #define DAGB3_WRCLI0__MIN_BW_MASK 0x01C00000L 5774 #define DAGB3_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 5775 #define DAGB3_WRCLI0__MAX_OSD_MASK 0xFC000000L 5776 //DAGB3_WRCLI1 5777 #define DAGB3_WRCLI1__VIRT_CHAN__SHIFT 0x0 5778 #define DAGB3_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 5779 #define DAGB3_WRCLI1__URG_HIGH__SHIFT 0x4 5780 #define DAGB3_WRCLI1__URG_LOW__SHIFT 0x8 5781 #define DAGB3_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc 5782 #define DAGB3_WRCLI1__MAX_BW__SHIFT 0xd 5783 #define DAGB3_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 5784 #define DAGB3_WRCLI1__MIN_BW__SHIFT 0x16 5785 #define DAGB3_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 5786 #define DAGB3_WRCLI1__MAX_OSD__SHIFT 0x1a 5787 #define DAGB3_WRCLI1__VIRT_CHAN_MASK 0x00000007L 5788 #define DAGB3_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 5789 #define DAGB3_WRCLI1__URG_HIGH_MASK 0x000000F0L 5790 #define DAGB3_WRCLI1__URG_LOW_MASK 0x00000F00L 5791 #define DAGB3_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L 5792 #define DAGB3_WRCLI1__MAX_BW_MASK 0x001FE000L 5793 #define DAGB3_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L 5794 #define DAGB3_WRCLI1__MIN_BW_MASK 0x01C00000L 5795 #define DAGB3_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 5796 #define DAGB3_WRCLI1__MAX_OSD_MASK 0xFC000000L 5797 //DAGB3_WRCLI2 5798 #define DAGB3_WRCLI2__VIRT_CHAN__SHIFT 0x0 5799 #define DAGB3_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 5800 #define DAGB3_WRCLI2__URG_HIGH__SHIFT 0x4 5801 #define DAGB3_WRCLI2__URG_LOW__SHIFT 0x8 5802 #define DAGB3_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc 5803 #define DAGB3_WRCLI2__MAX_BW__SHIFT 0xd 5804 #define DAGB3_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 5805 #define DAGB3_WRCLI2__MIN_BW__SHIFT 0x16 5806 #define DAGB3_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 5807 #define DAGB3_WRCLI2__MAX_OSD__SHIFT 0x1a 5808 #define DAGB3_WRCLI2__VIRT_CHAN_MASK 0x00000007L 5809 #define DAGB3_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 5810 #define DAGB3_WRCLI2__URG_HIGH_MASK 0x000000F0L 5811 #define DAGB3_WRCLI2__URG_LOW_MASK 0x00000F00L 5812 #define DAGB3_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L 5813 #define DAGB3_WRCLI2__MAX_BW_MASK 0x001FE000L 5814 #define DAGB3_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L 5815 #define DAGB3_WRCLI2__MIN_BW_MASK 0x01C00000L 5816 #define DAGB3_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 5817 #define DAGB3_WRCLI2__MAX_OSD_MASK 0xFC000000L 5818 //DAGB3_WRCLI3 5819 #define DAGB3_WRCLI3__VIRT_CHAN__SHIFT 0x0 5820 #define DAGB3_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 5821 #define DAGB3_WRCLI3__URG_HIGH__SHIFT 0x4 5822 #define DAGB3_WRCLI3__URG_LOW__SHIFT 0x8 5823 #define DAGB3_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc 5824 #define DAGB3_WRCLI3__MAX_BW__SHIFT 0xd 5825 #define DAGB3_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 5826 #define DAGB3_WRCLI3__MIN_BW__SHIFT 0x16 5827 #define DAGB3_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 5828 #define DAGB3_WRCLI3__MAX_OSD__SHIFT 0x1a 5829 #define DAGB3_WRCLI3__VIRT_CHAN_MASK 0x00000007L 5830 #define DAGB3_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 5831 #define DAGB3_WRCLI3__URG_HIGH_MASK 0x000000F0L 5832 #define DAGB3_WRCLI3__URG_LOW_MASK 0x00000F00L 5833 #define DAGB3_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L 5834 #define DAGB3_WRCLI3__MAX_BW_MASK 0x001FE000L 5835 #define DAGB3_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L 5836 #define DAGB3_WRCLI3__MIN_BW_MASK 0x01C00000L 5837 #define DAGB3_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 5838 #define DAGB3_WRCLI3__MAX_OSD_MASK 0xFC000000L 5839 //DAGB3_WRCLI4 5840 #define DAGB3_WRCLI4__VIRT_CHAN__SHIFT 0x0 5841 #define DAGB3_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 5842 #define DAGB3_WRCLI4__URG_HIGH__SHIFT 0x4 5843 #define DAGB3_WRCLI4__URG_LOW__SHIFT 0x8 5844 #define DAGB3_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc 5845 #define DAGB3_WRCLI4__MAX_BW__SHIFT 0xd 5846 #define DAGB3_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 5847 #define DAGB3_WRCLI4__MIN_BW__SHIFT 0x16 5848 #define DAGB3_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 5849 #define DAGB3_WRCLI4__MAX_OSD__SHIFT 0x1a 5850 #define DAGB3_WRCLI4__VIRT_CHAN_MASK 0x00000007L 5851 #define DAGB3_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 5852 #define DAGB3_WRCLI4__URG_HIGH_MASK 0x000000F0L 5853 #define DAGB3_WRCLI4__URG_LOW_MASK 0x00000F00L 5854 #define DAGB3_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L 5855 #define DAGB3_WRCLI4__MAX_BW_MASK 0x001FE000L 5856 #define DAGB3_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L 5857 #define DAGB3_WRCLI4__MIN_BW_MASK 0x01C00000L 5858 #define DAGB3_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 5859 #define DAGB3_WRCLI4__MAX_OSD_MASK 0xFC000000L 5860 //DAGB3_WRCLI5 5861 #define DAGB3_WRCLI5__VIRT_CHAN__SHIFT 0x0 5862 #define DAGB3_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 5863 #define DAGB3_WRCLI5__URG_HIGH__SHIFT 0x4 5864 #define DAGB3_WRCLI5__URG_LOW__SHIFT 0x8 5865 #define DAGB3_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc 5866 #define DAGB3_WRCLI5__MAX_BW__SHIFT 0xd 5867 #define DAGB3_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 5868 #define DAGB3_WRCLI5__MIN_BW__SHIFT 0x16 5869 #define DAGB3_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 5870 #define DAGB3_WRCLI5__MAX_OSD__SHIFT 0x1a 5871 #define DAGB3_WRCLI5__VIRT_CHAN_MASK 0x00000007L 5872 #define DAGB3_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 5873 #define DAGB3_WRCLI5__URG_HIGH_MASK 0x000000F0L 5874 #define DAGB3_WRCLI5__URG_LOW_MASK 0x00000F00L 5875 #define DAGB3_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L 5876 #define DAGB3_WRCLI5__MAX_BW_MASK 0x001FE000L 5877 #define DAGB3_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L 5878 #define DAGB3_WRCLI5__MIN_BW_MASK 0x01C00000L 5879 #define DAGB3_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 5880 #define DAGB3_WRCLI5__MAX_OSD_MASK 0xFC000000L 5881 //DAGB3_WRCLI6 5882 #define DAGB3_WRCLI6__VIRT_CHAN__SHIFT 0x0 5883 #define DAGB3_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 5884 #define DAGB3_WRCLI6__URG_HIGH__SHIFT 0x4 5885 #define DAGB3_WRCLI6__URG_LOW__SHIFT 0x8 5886 #define DAGB3_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc 5887 #define DAGB3_WRCLI6__MAX_BW__SHIFT 0xd 5888 #define DAGB3_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 5889 #define DAGB3_WRCLI6__MIN_BW__SHIFT 0x16 5890 #define DAGB3_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 5891 #define DAGB3_WRCLI6__MAX_OSD__SHIFT 0x1a 5892 #define DAGB3_WRCLI6__VIRT_CHAN_MASK 0x00000007L 5893 #define DAGB3_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 5894 #define DAGB3_WRCLI6__URG_HIGH_MASK 0x000000F0L 5895 #define DAGB3_WRCLI6__URG_LOW_MASK 0x00000F00L 5896 #define DAGB3_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L 5897 #define DAGB3_WRCLI6__MAX_BW_MASK 0x001FE000L 5898 #define DAGB3_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L 5899 #define DAGB3_WRCLI6__MIN_BW_MASK 0x01C00000L 5900 #define DAGB3_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 5901 #define DAGB3_WRCLI6__MAX_OSD_MASK 0xFC000000L 5902 //DAGB3_WRCLI7 5903 #define DAGB3_WRCLI7__VIRT_CHAN__SHIFT 0x0 5904 #define DAGB3_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 5905 #define DAGB3_WRCLI7__URG_HIGH__SHIFT 0x4 5906 #define DAGB3_WRCLI7__URG_LOW__SHIFT 0x8 5907 #define DAGB3_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc 5908 #define DAGB3_WRCLI7__MAX_BW__SHIFT 0xd 5909 #define DAGB3_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 5910 #define DAGB3_WRCLI7__MIN_BW__SHIFT 0x16 5911 #define DAGB3_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 5912 #define DAGB3_WRCLI7__MAX_OSD__SHIFT 0x1a 5913 #define DAGB3_WRCLI7__VIRT_CHAN_MASK 0x00000007L 5914 #define DAGB3_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 5915 #define DAGB3_WRCLI7__URG_HIGH_MASK 0x000000F0L 5916 #define DAGB3_WRCLI7__URG_LOW_MASK 0x00000F00L 5917 #define DAGB3_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L 5918 #define DAGB3_WRCLI7__MAX_BW_MASK 0x001FE000L 5919 #define DAGB3_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L 5920 #define DAGB3_WRCLI7__MIN_BW_MASK 0x01C00000L 5921 #define DAGB3_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 5922 #define DAGB3_WRCLI7__MAX_OSD_MASK 0xFC000000L 5923 //DAGB3_WRCLI8 5924 #define DAGB3_WRCLI8__VIRT_CHAN__SHIFT 0x0 5925 #define DAGB3_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 5926 #define DAGB3_WRCLI8__URG_HIGH__SHIFT 0x4 5927 #define DAGB3_WRCLI8__URG_LOW__SHIFT 0x8 5928 #define DAGB3_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc 5929 #define DAGB3_WRCLI8__MAX_BW__SHIFT 0xd 5930 #define DAGB3_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 5931 #define DAGB3_WRCLI8__MIN_BW__SHIFT 0x16 5932 #define DAGB3_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 5933 #define DAGB3_WRCLI8__MAX_OSD__SHIFT 0x1a 5934 #define DAGB3_WRCLI8__VIRT_CHAN_MASK 0x00000007L 5935 #define DAGB3_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 5936 #define DAGB3_WRCLI8__URG_HIGH_MASK 0x000000F0L 5937 #define DAGB3_WRCLI8__URG_LOW_MASK 0x00000F00L 5938 #define DAGB3_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L 5939 #define DAGB3_WRCLI8__MAX_BW_MASK 0x001FE000L 5940 #define DAGB3_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L 5941 #define DAGB3_WRCLI8__MIN_BW_MASK 0x01C00000L 5942 #define DAGB3_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 5943 #define DAGB3_WRCLI8__MAX_OSD_MASK 0xFC000000L 5944 //DAGB3_WRCLI9 5945 #define DAGB3_WRCLI9__VIRT_CHAN__SHIFT 0x0 5946 #define DAGB3_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 5947 #define DAGB3_WRCLI9__URG_HIGH__SHIFT 0x4 5948 #define DAGB3_WRCLI9__URG_LOW__SHIFT 0x8 5949 #define DAGB3_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc 5950 #define DAGB3_WRCLI9__MAX_BW__SHIFT 0xd 5951 #define DAGB3_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 5952 #define DAGB3_WRCLI9__MIN_BW__SHIFT 0x16 5953 #define DAGB3_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 5954 #define DAGB3_WRCLI9__MAX_OSD__SHIFT 0x1a 5955 #define DAGB3_WRCLI9__VIRT_CHAN_MASK 0x00000007L 5956 #define DAGB3_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 5957 #define DAGB3_WRCLI9__URG_HIGH_MASK 0x000000F0L 5958 #define DAGB3_WRCLI9__URG_LOW_MASK 0x00000F00L 5959 #define DAGB3_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L 5960 #define DAGB3_WRCLI9__MAX_BW_MASK 0x001FE000L 5961 #define DAGB3_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L 5962 #define DAGB3_WRCLI9__MIN_BW_MASK 0x01C00000L 5963 #define DAGB3_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 5964 #define DAGB3_WRCLI9__MAX_OSD_MASK 0xFC000000L 5965 //DAGB3_WRCLI10 5966 #define DAGB3_WRCLI10__VIRT_CHAN__SHIFT 0x0 5967 #define DAGB3_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 5968 #define DAGB3_WRCLI10__URG_HIGH__SHIFT 0x4 5969 #define DAGB3_WRCLI10__URG_LOW__SHIFT 0x8 5970 #define DAGB3_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc 5971 #define DAGB3_WRCLI10__MAX_BW__SHIFT 0xd 5972 #define DAGB3_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 5973 #define DAGB3_WRCLI10__MIN_BW__SHIFT 0x16 5974 #define DAGB3_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 5975 #define DAGB3_WRCLI10__MAX_OSD__SHIFT 0x1a 5976 #define DAGB3_WRCLI10__VIRT_CHAN_MASK 0x00000007L 5977 #define DAGB3_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 5978 #define DAGB3_WRCLI10__URG_HIGH_MASK 0x000000F0L 5979 #define DAGB3_WRCLI10__URG_LOW_MASK 0x00000F00L 5980 #define DAGB3_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L 5981 #define DAGB3_WRCLI10__MAX_BW_MASK 0x001FE000L 5982 #define DAGB3_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L 5983 #define DAGB3_WRCLI10__MIN_BW_MASK 0x01C00000L 5984 #define DAGB3_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 5985 #define DAGB3_WRCLI10__MAX_OSD_MASK 0xFC000000L 5986 //DAGB3_WRCLI11 5987 #define DAGB3_WRCLI11__VIRT_CHAN__SHIFT 0x0 5988 #define DAGB3_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 5989 #define DAGB3_WRCLI11__URG_HIGH__SHIFT 0x4 5990 #define DAGB3_WRCLI11__URG_LOW__SHIFT 0x8 5991 #define DAGB3_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc 5992 #define DAGB3_WRCLI11__MAX_BW__SHIFT 0xd 5993 #define DAGB3_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 5994 #define DAGB3_WRCLI11__MIN_BW__SHIFT 0x16 5995 #define DAGB3_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 5996 #define DAGB3_WRCLI11__MAX_OSD__SHIFT 0x1a 5997 #define DAGB3_WRCLI11__VIRT_CHAN_MASK 0x00000007L 5998 #define DAGB3_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 5999 #define DAGB3_WRCLI11__URG_HIGH_MASK 0x000000F0L 6000 #define DAGB3_WRCLI11__URG_LOW_MASK 0x00000F00L 6001 #define DAGB3_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L 6002 #define DAGB3_WRCLI11__MAX_BW_MASK 0x001FE000L 6003 #define DAGB3_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L 6004 #define DAGB3_WRCLI11__MIN_BW_MASK 0x01C00000L 6005 #define DAGB3_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 6006 #define DAGB3_WRCLI11__MAX_OSD_MASK 0xFC000000L 6007 //DAGB3_WRCLI12 6008 #define DAGB3_WRCLI12__VIRT_CHAN__SHIFT 0x0 6009 #define DAGB3_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 6010 #define DAGB3_WRCLI12__URG_HIGH__SHIFT 0x4 6011 #define DAGB3_WRCLI12__URG_LOW__SHIFT 0x8 6012 #define DAGB3_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc 6013 #define DAGB3_WRCLI12__MAX_BW__SHIFT 0xd 6014 #define DAGB3_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 6015 #define DAGB3_WRCLI12__MIN_BW__SHIFT 0x16 6016 #define DAGB3_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 6017 #define DAGB3_WRCLI12__MAX_OSD__SHIFT 0x1a 6018 #define DAGB3_WRCLI12__VIRT_CHAN_MASK 0x00000007L 6019 #define DAGB3_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 6020 #define DAGB3_WRCLI12__URG_HIGH_MASK 0x000000F0L 6021 #define DAGB3_WRCLI12__URG_LOW_MASK 0x00000F00L 6022 #define DAGB3_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L 6023 #define DAGB3_WRCLI12__MAX_BW_MASK 0x001FE000L 6024 #define DAGB3_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L 6025 #define DAGB3_WRCLI12__MIN_BW_MASK 0x01C00000L 6026 #define DAGB3_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 6027 #define DAGB3_WRCLI12__MAX_OSD_MASK 0xFC000000L 6028 //DAGB3_WRCLI13 6029 #define DAGB3_WRCLI13__VIRT_CHAN__SHIFT 0x0 6030 #define DAGB3_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 6031 #define DAGB3_WRCLI13__URG_HIGH__SHIFT 0x4 6032 #define DAGB3_WRCLI13__URG_LOW__SHIFT 0x8 6033 #define DAGB3_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc 6034 #define DAGB3_WRCLI13__MAX_BW__SHIFT 0xd 6035 #define DAGB3_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 6036 #define DAGB3_WRCLI13__MIN_BW__SHIFT 0x16 6037 #define DAGB3_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 6038 #define DAGB3_WRCLI13__MAX_OSD__SHIFT 0x1a 6039 #define DAGB3_WRCLI13__VIRT_CHAN_MASK 0x00000007L 6040 #define DAGB3_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 6041 #define DAGB3_WRCLI13__URG_HIGH_MASK 0x000000F0L 6042 #define DAGB3_WRCLI13__URG_LOW_MASK 0x00000F00L 6043 #define DAGB3_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L 6044 #define DAGB3_WRCLI13__MAX_BW_MASK 0x001FE000L 6045 #define DAGB3_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L 6046 #define DAGB3_WRCLI13__MIN_BW_MASK 0x01C00000L 6047 #define DAGB3_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 6048 #define DAGB3_WRCLI13__MAX_OSD_MASK 0xFC000000L 6049 //DAGB3_WRCLI14 6050 #define DAGB3_WRCLI14__VIRT_CHAN__SHIFT 0x0 6051 #define DAGB3_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 6052 #define DAGB3_WRCLI14__URG_HIGH__SHIFT 0x4 6053 #define DAGB3_WRCLI14__URG_LOW__SHIFT 0x8 6054 #define DAGB3_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc 6055 #define DAGB3_WRCLI14__MAX_BW__SHIFT 0xd 6056 #define DAGB3_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 6057 #define DAGB3_WRCLI14__MIN_BW__SHIFT 0x16 6058 #define DAGB3_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 6059 #define DAGB3_WRCLI14__MAX_OSD__SHIFT 0x1a 6060 #define DAGB3_WRCLI14__VIRT_CHAN_MASK 0x00000007L 6061 #define DAGB3_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 6062 #define DAGB3_WRCLI14__URG_HIGH_MASK 0x000000F0L 6063 #define DAGB3_WRCLI14__URG_LOW_MASK 0x00000F00L 6064 #define DAGB3_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L 6065 #define DAGB3_WRCLI14__MAX_BW_MASK 0x001FE000L 6066 #define DAGB3_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L 6067 #define DAGB3_WRCLI14__MIN_BW_MASK 0x01C00000L 6068 #define DAGB3_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 6069 #define DAGB3_WRCLI14__MAX_OSD_MASK 0xFC000000L 6070 //DAGB3_WRCLI15 6071 #define DAGB3_WRCLI15__VIRT_CHAN__SHIFT 0x0 6072 #define DAGB3_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 6073 #define DAGB3_WRCLI15__URG_HIGH__SHIFT 0x4 6074 #define DAGB3_WRCLI15__URG_LOW__SHIFT 0x8 6075 #define DAGB3_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc 6076 #define DAGB3_WRCLI15__MAX_BW__SHIFT 0xd 6077 #define DAGB3_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 6078 #define DAGB3_WRCLI15__MIN_BW__SHIFT 0x16 6079 #define DAGB3_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 6080 #define DAGB3_WRCLI15__MAX_OSD__SHIFT 0x1a 6081 #define DAGB3_WRCLI15__VIRT_CHAN_MASK 0x00000007L 6082 #define DAGB3_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 6083 #define DAGB3_WRCLI15__URG_HIGH_MASK 0x000000F0L 6084 #define DAGB3_WRCLI15__URG_LOW_MASK 0x00000F00L 6085 #define DAGB3_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L 6086 #define DAGB3_WRCLI15__MAX_BW_MASK 0x001FE000L 6087 #define DAGB3_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L 6088 #define DAGB3_WRCLI15__MIN_BW_MASK 0x01C00000L 6089 #define DAGB3_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 6090 #define DAGB3_WRCLI15__MAX_OSD_MASK 0xFC000000L 6091 //DAGB3_WR_CNTL 6092 #define DAGB3_WR_CNTL__SCLK_FREQ__SHIFT 0x0 6093 #define DAGB3_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 6094 #define DAGB3_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 6095 #define DAGB3_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 6096 #define DAGB3_WR_CNTL__IO_LEVEL__SHIFT 0x11 6097 #define DAGB3_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 6098 #define DAGB3_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 6099 #define DAGB3_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL 6100 #define DAGB3_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 6101 #define DAGB3_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 6102 #define DAGB3_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 6103 #define DAGB3_WR_CNTL__IO_LEVEL_MASK 0x000E0000L 6104 #define DAGB3_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 6105 #define DAGB3_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L 6106 //DAGB3_WR_GMI_CNTL 6107 #define DAGB3_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 6108 #define DAGB3_WR_GMI_CNTL__LEVEL__SHIFT 0x6 6109 #define DAGB3_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 6110 #define DAGB3_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 6111 #define DAGB3_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 6112 #define DAGB3_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L 6113 #define DAGB3_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 6114 #define DAGB3_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 6115 //DAGB3_WR_ADDR_DAGB 6116 #define DAGB3_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 6117 #define DAGB3_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 6118 #define DAGB3_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 6119 #define DAGB3_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 6120 #define DAGB3_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 6121 #define DAGB3_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 6122 #define DAGB3_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 6123 #define DAGB3_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 6124 //DAGB3_WR_OUTPUT_DAGB_MAX_BURST 6125 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 6126 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 6127 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 6128 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 6129 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 6130 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 6131 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 6132 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 6133 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 6134 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 6135 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 6136 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 6137 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 6138 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 6139 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 6140 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 6141 //DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER 6142 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 6143 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 6144 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 6145 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 6146 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 6147 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 6148 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 6149 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 6150 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 6151 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 6152 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 6153 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 6154 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 6155 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 6156 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 6157 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 6158 //DAGB3_WR_CGTT_CLK_CTRL 6159 #define DAGB3_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 6160 #define DAGB3_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 6161 #define DAGB3_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 6162 #define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 6163 #define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 6164 #define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 6165 #define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 6166 #define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 6167 #define DAGB3_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 6168 #define DAGB3_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 6169 #define DAGB3_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 6170 #define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 6171 #define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 6172 #define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 6173 #define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 6174 #define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 6175 //DAGB3_L1TLB_WR_CGTT_CLK_CTRL 6176 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 6177 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 6178 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 6179 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 6180 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 6181 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 6182 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 6183 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 6184 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 6185 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 6186 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 6187 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 6188 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 6189 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 6190 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 6191 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 6192 //DAGB3_ATCVM_WR_CGTT_CLK_CTRL 6193 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 6194 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 6195 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 6196 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 6197 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 6198 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 6199 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 6200 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 6201 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 6202 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 6203 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 6204 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 6205 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 6206 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 6207 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 6208 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 6209 //DAGB3_WR_ADDR_DAGB_MAX_BURST0 6210 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 6211 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 6212 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 6213 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 6214 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 6215 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 6216 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 6217 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 6218 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 6219 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 6220 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 6221 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 6222 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 6223 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 6224 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 6225 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 6226 //DAGB3_WR_ADDR_DAGB_LAZY_TIMER0 6227 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 6228 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 6229 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 6230 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 6231 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 6232 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 6233 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 6234 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 6235 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 6236 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 6237 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 6238 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 6239 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 6240 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 6241 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 6242 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 6243 //DAGB3_WR_ADDR_DAGB_MAX_BURST1 6244 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 6245 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 6246 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 6247 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 6248 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 6249 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 6250 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 6251 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 6252 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 6253 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 6254 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 6255 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 6256 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 6257 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 6258 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 6259 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 6260 //DAGB3_WR_ADDR_DAGB_LAZY_TIMER1 6261 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 6262 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 6263 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 6264 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 6265 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 6266 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 6267 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 6268 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 6269 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 6270 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 6271 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 6272 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 6273 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 6274 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 6275 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 6276 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 6277 //DAGB3_WR_DATA_DAGB 6278 #define DAGB3_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 6279 #define DAGB3_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 6280 #define DAGB3_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 6281 #define DAGB3_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 6282 #define DAGB3_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L 6283 #define DAGB3_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 6284 #define DAGB3_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 6285 #define DAGB3_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L 6286 //DAGB3_WR_DATA_DAGB_MAX_BURST0 6287 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 6288 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 6289 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 6290 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 6291 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 6292 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 6293 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 6294 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 6295 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 6296 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 6297 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 6298 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 6299 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 6300 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 6301 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 6302 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 6303 //DAGB3_WR_DATA_DAGB_LAZY_TIMER0 6304 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 6305 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 6306 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 6307 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 6308 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 6309 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 6310 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 6311 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 6312 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 6313 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 6314 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 6315 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 6316 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 6317 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 6318 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 6319 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 6320 //DAGB3_WR_DATA_DAGB_MAX_BURST1 6321 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 6322 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 6323 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 6324 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 6325 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 6326 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 6327 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 6328 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 6329 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 6330 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 6331 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 6332 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 6333 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 6334 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 6335 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 6336 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 6337 //DAGB3_WR_DATA_DAGB_LAZY_TIMER1 6338 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 6339 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 6340 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 6341 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 6342 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 6343 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 6344 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 6345 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 6346 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 6347 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 6348 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 6349 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 6350 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 6351 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 6352 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 6353 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 6354 //DAGB3_WR_VC0_CNTL 6355 #define DAGB3_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 6356 #define DAGB3_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 6357 #define DAGB3_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 6358 #define DAGB3_WR_VC0_CNTL__MAX_BW__SHIFT 0xc 6359 #define DAGB3_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 6360 #define DAGB3_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 6361 #define DAGB3_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 6362 #define DAGB3_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 6363 #define DAGB3_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 6364 #define DAGB3_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 6365 #define DAGB3_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 6366 #define DAGB3_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L 6367 #define DAGB3_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 6368 #define DAGB3_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L 6369 #define DAGB3_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 6370 #define DAGB3_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 6371 //DAGB3_WR_VC1_CNTL 6372 #define DAGB3_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 6373 #define DAGB3_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 6374 #define DAGB3_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 6375 #define DAGB3_WR_VC1_CNTL__MAX_BW__SHIFT 0xc 6376 #define DAGB3_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 6377 #define DAGB3_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 6378 #define DAGB3_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 6379 #define DAGB3_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 6380 #define DAGB3_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 6381 #define DAGB3_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 6382 #define DAGB3_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 6383 #define DAGB3_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L 6384 #define DAGB3_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 6385 #define DAGB3_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L 6386 #define DAGB3_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 6387 #define DAGB3_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 6388 //DAGB3_WR_VC2_CNTL 6389 #define DAGB3_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 6390 #define DAGB3_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 6391 #define DAGB3_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 6392 #define DAGB3_WR_VC2_CNTL__MAX_BW__SHIFT 0xc 6393 #define DAGB3_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 6394 #define DAGB3_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 6395 #define DAGB3_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 6396 #define DAGB3_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 6397 #define DAGB3_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 6398 #define DAGB3_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 6399 #define DAGB3_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 6400 #define DAGB3_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L 6401 #define DAGB3_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 6402 #define DAGB3_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L 6403 #define DAGB3_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 6404 #define DAGB3_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 6405 //DAGB3_WR_VC3_CNTL 6406 #define DAGB3_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 6407 #define DAGB3_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 6408 #define DAGB3_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 6409 #define DAGB3_WR_VC3_CNTL__MAX_BW__SHIFT 0xc 6410 #define DAGB3_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 6411 #define DAGB3_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 6412 #define DAGB3_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 6413 #define DAGB3_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 6414 #define DAGB3_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 6415 #define DAGB3_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 6416 #define DAGB3_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 6417 #define DAGB3_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L 6418 #define DAGB3_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 6419 #define DAGB3_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L 6420 #define DAGB3_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 6421 #define DAGB3_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 6422 //DAGB3_WR_VC4_CNTL 6423 #define DAGB3_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 6424 #define DAGB3_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 6425 #define DAGB3_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 6426 #define DAGB3_WR_VC4_CNTL__MAX_BW__SHIFT 0xc 6427 #define DAGB3_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 6428 #define DAGB3_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 6429 #define DAGB3_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 6430 #define DAGB3_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 6431 #define DAGB3_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 6432 #define DAGB3_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 6433 #define DAGB3_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 6434 #define DAGB3_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L 6435 #define DAGB3_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 6436 #define DAGB3_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L 6437 #define DAGB3_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 6438 #define DAGB3_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 6439 //DAGB3_WR_VC5_CNTL 6440 #define DAGB3_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 6441 #define DAGB3_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 6442 #define DAGB3_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 6443 #define DAGB3_WR_VC5_CNTL__MAX_BW__SHIFT 0xc 6444 #define DAGB3_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 6445 #define DAGB3_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 6446 #define DAGB3_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 6447 #define DAGB3_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 6448 #define DAGB3_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 6449 #define DAGB3_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 6450 #define DAGB3_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 6451 #define DAGB3_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L 6452 #define DAGB3_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 6453 #define DAGB3_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L 6454 #define DAGB3_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 6455 #define DAGB3_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 6456 //DAGB3_WR_VC6_CNTL 6457 #define DAGB3_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 6458 #define DAGB3_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 6459 #define DAGB3_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 6460 #define DAGB3_WR_VC6_CNTL__MAX_BW__SHIFT 0xc 6461 #define DAGB3_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 6462 #define DAGB3_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 6463 #define DAGB3_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 6464 #define DAGB3_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 6465 #define DAGB3_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 6466 #define DAGB3_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 6467 #define DAGB3_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 6468 #define DAGB3_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L 6469 #define DAGB3_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 6470 #define DAGB3_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L 6471 #define DAGB3_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 6472 #define DAGB3_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 6473 //DAGB3_WR_VC7_CNTL 6474 #define DAGB3_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 6475 #define DAGB3_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 6476 #define DAGB3_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 6477 #define DAGB3_WR_VC7_CNTL__MAX_BW__SHIFT 0xc 6478 #define DAGB3_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 6479 #define DAGB3_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 6480 #define DAGB3_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 6481 #define DAGB3_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 6482 #define DAGB3_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 6483 #define DAGB3_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 6484 #define DAGB3_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 6485 #define DAGB3_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L 6486 #define DAGB3_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 6487 #define DAGB3_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L 6488 #define DAGB3_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 6489 #define DAGB3_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 6490 //DAGB3_WR_CNTL_MISC 6491 #define DAGB3_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 6492 #define DAGB3_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 6493 #define DAGB3_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 6494 #define DAGB3_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 6495 #define DAGB3_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 6496 #define DAGB3_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 6497 #define DAGB3_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a 6498 #define DAGB3_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 6499 #define DAGB3_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 6500 #define DAGB3_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 6501 #define DAGB3_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 6502 #define DAGB3_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 6503 #define DAGB3_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 6504 #define DAGB3_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L 6505 //DAGB3_WR_TLB_CREDIT 6506 #define DAGB3_WR_TLB_CREDIT__TLB0__SHIFT 0x0 6507 #define DAGB3_WR_TLB_CREDIT__TLB1__SHIFT 0x5 6508 #define DAGB3_WR_TLB_CREDIT__TLB2__SHIFT 0xa 6509 #define DAGB3_WR_TLB_CREDIT__TLB3__SHIFT 0xf 6510 #define DAGB3_WR_TLB_CREDIT__TLB4__SHIFT 0x14 6511 #define DAGB3_WR_TLB_CREDIT__TLB5__SHIFT 0x19 6512 #define DAGB3_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL 6513 #define DAGB3_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L 6514 #define DAGB3_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L 6515 #define DAGB3_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L 6516 #define DAGB3_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L 6517 #define DAGB3_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L 6518 //DAGB3_WR_DATA_CREDIT 6519 #define DAGB3_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 6520 #define DAGB3_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 6521 #define DAGB3_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 6522 #define DAGB3_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 6523 #define DAGB3_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL 6524 #define DAGB3_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L 6525 #define DAGB3_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L 6526 #define DAGB3_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L 6527 //DAGB3_WR_MISC_CREDIT 6528 #define DAGB3_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 6529 #define DAGB3_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 6530 #define DAGB3_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 6531 #define DAGB3_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 6532 #define DAGB3_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL 6533 #define DAGB3_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L 6534 #define DAGB3_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L 6535 #define DAGB3_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L 6536 //DAGB3_WRCLI_ASK_PENDING 6537 #define DAGB3_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 6538 #define DAGB3_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 6539 //DAGB3_WRCLI_GO_PENDING 6540 #define DAGB3_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 6541 #define DAGB3_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 6542 //DAGB3_WRCLI_GBLSEND_PENDING 6543 #define DAGB3_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 6544 #define DAGB3_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 6545 //DAGB3_WRCLI_TLB_PENDING 6546 #define DAGB3_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 6547 #define DAGB3_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 6548 //DAGB3_WRCLI_OARB_PENDING 6549 #define DAGB3_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 6550 #define DAGB3_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 6551 //DAGB3_WRCLI_OSD_PENDING 6552 #define DAGB3_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 6553 #define DAGB3_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 6554 //DAGB3_WRCLI_DBUS_ASK_PENDING 6555 #define DAGB3_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 6556 #define DAGB3_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 6557 //DAGB3_WRCLI_DBUS_GO_PENDING 6558 #define DAGB3_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 6559 #define DAGB3_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 6560 //DAGB3_DAGB_DLY 6561 #define DAGB3_DAGB_DLY__DLY__SHIFT 0x0 6562 #define DAGB3_DAGB_DLY__CLI__SHIFT 0x8 6563 #define DAGB3_DAGB_DLY__POS__SHIFT 0x10 6564 #define DAGB3_DAGB_DLY__DLY_MASK 0x000000FFL 6565 #define DAGB3_DAGB_DLY__CLI_MASK 0x0000FF00L 6566 #define DAGB3_DAGB_DLY__POS_MASK 0x000F0000L 6567 //DAGB3_CNTL_MISC 6568 #define DAGB3_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 6569 #define DAGB3_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 6570 #define DAGB3_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 6571 #define DAGB3_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 6572 #define DAGB3_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc 6573 #define DAGB3_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf 6574 #define DAGB3_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 6575 #define DAGB3_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 6576 #define DAGB3_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 6577 #define DAGB3_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e 6578 #define DAGB3_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L 6579 #define DAGB3_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L 6580 #define DAGB3_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L 6581 #define DAGB3_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L 6582 #define DAGB3_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L 6583 #define DAGB3_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L 6584 #define DAGB3_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L 6585 #define DAGB3_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L 6586 #define DAGB3_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L 6587 #define DAGB3_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L 6588 //DAGB3_CNTL_MISC2 6589 #define DAGB3_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 6590 #define DAGB3_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 6591 #define DAGB3_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 6592 #define DAGB3_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 6593 #define DAGB3_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 6594 #define DAGB3_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 6595 #define DAGB3_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 6596 #define DAGB3_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 6597 #define DAGB3_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 6598 #define DAGB3_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 6599 #define DAGB3_CNTL_MISC2__SWAP_CTL__SHIFT 0xa 6600 #define DAGB3_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xb 6601 #define DAGB3_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x11 6602 #define DAGB3_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L 6603 #define DAGB3_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L 6604 #define DAGB3_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L 6605 #define DAGB3_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L 6606 #define DAGB3_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L 6607 #define DAGB3_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L 6608 #define DAGB3_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L 6609 #define DAGB3_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L 6610 #define DAGB3_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L 6611 #define DAGB3_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L 6612 #define DAGB3_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L 6613 #define DAGB3_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000800L 6614 #define DAGB3_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x007E0000L 6615 //DAGB3_FIFO_EMPTY 6616 #define DAGB3_FIFO_EMPTY__EMPTY__SHIFT 0x0 6617 #define DAGB3_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL 6618 //DAGB3_FIFO_FULL 6619 #define DAGB3_FIFO_FULL__FULL__SHIFT 0x0 6620 #define DAGB3_FIFO_FULL__FULL_MASK 0x007FFFFFL 6621 //DAGB3_WR_CREDITS_FULL 6622 #define DAGB3_WR_CREDITS_FULL__FULL__SHIFT 0x0 6623 #define DAGB3_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL 6624 //DAGB3_RD_CREDITS_FULL 6625 #define DAGB3_RD_CREDITS_FULL__FULL__SHIFT 0x0 6626 #define DAGB3_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL 6627 //DAGB3_PERFCOUNTER_LO 6628 #define DAGB3_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 6629 #define DAGB3_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 6630 //DAGB3_PERFCOUNTER_HI 6631 #define DAGB3_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 6632 #define DAGB3_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 6633 #define DAGB3_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 6634 #define DAGB3_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 6635 //DAGB3_PERFCOUNTER0_CFG 6636 #define DAGB3_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 6637 #define DAGB3_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 6638 #define DAGB3_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 6639 #define DAGB3_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 6640 #define DAGB3_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 6641 #define DAGB3_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 6642 #define DAGB3_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 6643 #define DAGB3_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 6644 #define DAGB3_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 6645 #define DAGB3_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 6646 //DAGB3_PERFCOUNTER1_CFG 6647 #define DAGB3_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 6648 #define DAGB3_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 6649 #define DAGB3_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 6650 #define DAGB3_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 6651 #define DAGB3_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 6652 #define DAGB3_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 6653 #define DAGB3_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 6654 #define DAGB3_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 6655 #define DAGB3_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 6656 #define DAGB3_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 6657 //DAGB3_PERFCOUNTER2_CFG 6658 #define DAGB3_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 6659 #define DAGB3_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 6660 #define DAGB3_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 6661 #define DAGB3_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 6662 #define DAGB3_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 6663 #define DAGB3_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 6664 #define DAGB3_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 6665 #define DAGB3_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 6666 #define DAGB3_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 6667 #define DAGB3_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 6668 //DAGB3_PERFCOUNTER_RSLT_CNTL 6669 #define DAGB3_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 6670 #define DAGB3_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 6671 #define DAGB3_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 6672 #define DAGB3_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 6673 #define DAGB3_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 6674 #define DAGB3_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 6675 #define DAGB3_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 6676 #define DAGB3_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 6677 #define DAGB3_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 6678 #define DAGB3_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 6679 #define DAGB3_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 6680 #define DAGB3_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 6681 //DAGB3_RESERVE0 6682 #define DAGB3_RESERVE0__RESERVE__SHIFT 0x0 6683 #define DAGB3_RESERVE0__RESERVE_MASK 0xFFFFFFFFL 6684 //DAGB3_RESERVE1 6685 #define DAGB3_RESERVE1__RESERVE__SHIFT 0x0 6686 #define DAGB3_RESERVE1__RESERVE_MASK 0xFFFFFFFFL 6687 //DAGB3_RESERVE2 6688 #define DAGB3_RESERVE2__RESERVE__SHIFT 0x0 6689 #define DAGB3_RESERVE2__RESERVE_MASK 0xFFFFFFFFL 6690 //DAGB3_RESERVE3 6691 #define DAGB3_RESERVE3__RESERVE__SHIFT 0x0 6692 #define DAGB3_RESERVE3__RESERVE_MASK 0xFFFFFFFFL 6693 //DAGB3_RESERVE4 6694 #define DAGB3_RESERVE4__RESERVE__SHIFT 0x0 6695 #define DAGB3_RESERVE4__RESERVE_MASK 0xFFFFFFFFL 6696 //DAGB3_RESERVE5 6697 #define DAGB3_RESERVE5__RESERVE__SHIFT 0x0 6698 #define DAGB3_RESERVE5__RESERVE_MASK 0xFFFFFFFFL 6699 //DAGB3_RESERVE6 6700 #define DAGB3_RESERVE6__RESERVE__SHIFT 0x0 6701 #define DAGB3_RESERVE6__RESERVE_MASK 0xFFFFFFFFL 6702 //DAGB3_RESERVE7 6703 #define DAGB3_RESERVE7__RESERVE__SHIFT 0x0 6704 #define DAGB3_RESERVE7__RESERVE_MASK 0xFFFFFFFFL 6705 //DAGB3_RESERVE8 6706 #define DAGB3_RESERVE8__RESERVE__SHIFT 0x0 6707 #define DAGB3_RESERVE8__RESERVE_MASK 0xFFFFFFFFL 6708 //DAGB3_RESERVE9 6709 #define DAGB3_RESERVE9__RESERVE__SHIFT 0x0 6710 #define DAGB3_RESERVE9__RESERVE_MASK 0xFFFFFFFFL 6711 //DAGB3_RESERVE10 6712 #define DAGB3_RESERVE10__RESERVE__SHIFT 0x0 6713 #define DAGB3_RESERVE10__RESERVE_MASK 0xFFFFFFFFL 6714 //DAGB3_RESERVE11 6715 #define DAGB3_RESERVE11__RESERVE__SHIFT 0x0 6716 #define DAGB3_RESERVE11__RESERVE_MASK 0xFFFFFFFFL 6717 //DAGB3_RESERVE12 6718 #define DAGB3_RESERVE12__RESERVE__SHIFT 0x0 6719 #define DAGB3_RESERVE12__RESERVE_MASK 0xFFFFFFFFL 6720 //DAGB3_RESERVE13 6721 #define DAGB3_RESERVE13__RESERVE__SHIFT 0x0 6722 #define DAGB3_RESERVE13__RESERVE_MASK 0xFFFFFFFFL 6723 6724 6725 // addressBlock: mmhub_dagb_dagbdec4 6726 //DAGB4_RDCLI0 6727 #define DAGB4_RDCLI0__VIRT_CHAN__SHIFT 0x0 6728 #define DAGB4_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 6729 #define DAGB4_RDCLI0__URG_HIGH__SHIFT 0x4 6730 #define DAGB4_RDCLI0__URG_LOW__SHIFT 0x8 6731 #define DAGB4_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 6732 #define DAGB4_RDCLI0__MAX_BW__SHIFT 0xd 6733 #define DAGB4_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 6734 #define DAGB4_RDCLI0__MIN_BW__SHIFT 0x16 6735 #define DAGB4_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 6736 #define DAGB4_RDCLI0__MAX_OSD__SHIFT 0x1a 6737 #define DAGB4_RDCLI0__VIRT_CHAN_MASK 0x00000007L 6738 #define DAGB4_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 6739 #define DAGB4_RDCLI0__URG_HIGH_MASK 0x000000F0L 6740 #define DAGB4_RDCLI0__URG_LOW_MASK 0x00000F00L 6741 #define DAGB4_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L 6742 #define DAGB4_RDCLI0__MAX_BW_MASK 0x001FE000L 6743 #define DAGB4_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L 6744 #define DAGB4_RDCLI0__MIN_BW_MASK 0x01C00000L 6745 #define DAGB4_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 6746 #define DAGB4_RDCLI0__MAX_OSD_MASK 0xFC000000L 6747 //DAGB4_RDCLI1 6748 #define DAGB4_RDCLI1__VIRT_CHAN__SHIFT 0x0 6749 #define DAGB4_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 6750 #define DAGB4_RDCLI1__URG_HIGH__SHIFT 0x4 6751 #define DAGB4_RDCLI1__URG_LOW__SHIFT 0x8 6752 #define DAGB4_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc 6753 #define DAGB4_RDCLI1__MAX_BW__SHIFT 0xd 6754 #define DAGB4_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 6755 #define DAGB4_RDCLI1__MIN_BW__SHIFT 0x16 6756 #define DAGB4_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 6757 #define DAGB4_RDCLI1__MAX_OSD__SHIFT 0x1a 6758 #define DAGB4_RDCLI1__VIRT_CHAN_MASK 0x00000007L 6759 #define DAGB4_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 6760 #define DAGB4_RDCLI1__URG_HIGH_MASK 0x000000F0L 6761 #define DAGB4_RDCLI1__URG_LOW_MASK 0x00000F00L 6762 #define DAGB4_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L 6763 #define DAGB4_RDCLI1__MAX_BW_MASK 0x001FE000L 6764 #define DAGB4_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L 6765 #define DAGB4_RDCLI1__MIN_BW_MASK 0x01C00000L 6766 #define DAGB4_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 6767 #define DAGB4_RDCLI1__MAX_OSD_MASK 0xFC000000L 6768 //DAGB4_RDCLI2 6769 #define DAGB4_RDCLI2__VIRT_CHAN__SHIFT 0x0 6770 #define DAGB4_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 6771 #define DAGB4_RDCLI2__URG_HIGH__SHIFT 0x4 6772 #define DAGB4_RDCLI2__URG_LOW__SHIFT 0x8 6773 #define DAGB4_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc 6774 #define DAGB4_RDCLI2__MAX_BW__SHIFT 0xd 6775 #define DAGB4_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 6776 #define DAGB4_RDCLI2__MIN_BW__SHIFT 0x16 6777 #define DAGB4_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 6778 #define DAGB4_RDCLI2__MAX_OSD__SHIFT 0x1a 6779 #define DAGB4_RDCLI2__VIRT_CHAN_MASK 0x00000007L 6780 #define DAGB4_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 6781 #define DAGB4_RDCLI2__URG_HIGH_MASK 0x000000F0L 6782 #define DAGB4_RDCLI2__URG_LOW_MASK 0x00000F00L 6783 #define DAGB4_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L 6784 #define DAGB4_RDCLI2__MAX_BW_MASK 0x001FE000L 6785 #define DAGB4_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L 6786 #define DAGB4_RDCLI2__MIN_BW_MASK 0x01C00000L 6787 #define DAGB4_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 6788 #define DAGB4_RDCLI2__MAX_OSD_MASK 0xFC000000L 6789 //DAGB4_RDCLI3 6790 #define DAGB4_RDCLI3__VIRT_CHAN__SHIFT 0x0 6791 #define DAGB4_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 6792 #define DAGB4_RDCLI3__URG_HIGH__SHIFT 0x4 6793 #define DAGB4_RDCLI3__URG_LOW__SHIFT 0x8 6794 #define DAGB4_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc 6795 #define DAGB4_RDCLI3__MAX_BW__SHIFT 0xd 6796 #define DAGB4_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 6797 #define DAGB4_RDCLI3__MIN_BW__SHIFT 0x16 6798 #define DAGB4_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 6799 #define DAGB4_RDCLI3__MAX_OSD__SHIFT 0x1a 6800 #define DAGB4_RDCLI3__VIRT_CHAN_MASK 0x00000007L 6801 #define DAGB4_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 6802 #define DAGB4_RDCLI3__URG_HIGH_MASK 0x000000F0L 6803 #define DAGB4_RDCLI3__URG_LOW_MASK 0x00000F00L 6804 #define DAGB4_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L 6805 #define DAGB4_RDCLI3__MAX_BW_MASK 0x001FE000L 6806 #define DAGB4_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L 6807 #define DAGB4_RDCLI3__MIN_BW_MASK 0x01C00000L 6808 #define DAGB4_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 6809 #define DAGB4_RDCLI3__MAX_OSD_MASK 0xFC000000L 6810 //DAGB4_RDCLI4 6811 #define DAGB4_RDCLI4__VIRT_CHAN__SHIFT 0x0 6812 #define DAGB4_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 6813 #define DAGB4_RDCLI4__URG_HIGH__SHIFT 0x4 6814 #define DAGB4_RDCLI4__URG_LOW__SHIFT 0x8 6815 #define DAGB4_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc 6816 #define DAGB4_RDCLI4__MAX_BW__SHIFT 0xd 6817 #define DAGB4_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 6818 #define DAGB4_RDCLI4__MIN_BW__SHIFT 0x16 6819 #define DAGB4_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 6820 #define DAGB4_RDCLI4__MAX_OSD__SHIFT 0x1a 6821 #define DAGB4_RDCLI4__VIRT_CHAN_MASK 0x00000007L 6822 #define DAGB4_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 6823 #define DAGB4_RDCLI4__URG_HIGH_MASK 0x000000F0L 6824 #define DAGB4_RDCLI4__URG_LOW_MASK 0x00000F00L 6825 #define DAGB4_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L 6826 #define DAGB4_RDCLI4__MAX_BW_MASK 0x001FE000L 6827 #define DAGB4_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L 6828 #define DAGB4_RDCLI4__MIN_BW_MASK 0x01C00000L 6829 #define DAGB4_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 6830 #define DAGB4_RDCLI4__MAX_OSD_MASK 0xFC000000L 6831 //DAGB4_RDCLI5 6832 #define DAGB4_RDCLI5__VIRT_CHAN__SHIFT 0x0 6833 #define DAGB4_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 6834 #define DAGB4_RDCLI5__URG_HIGH__SHIFT 0x4 6835 #define DAGB4_RDCLI5__URG_LOW__SHIFT 0x8 6836 #define DAGB4_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc 6837 #define DAGB4_RDCLI5__MAX_BW__SHIFT 0xd 6838 #define DAGB4_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 6839 #define DAGB4_RDCLI5__MIN_BW__SHIFT 0x16 6840 #define DAGB4_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 6841 #define DAGB4_RDCLI5__MAX_OSD__SHIFT 0x1a 6842 #define DAGB4_RDCLI5__VIRT_CHAN_MASK 0x00000007L 6843 #define DAGB4_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 6844 #define DAGB4_RDCLI5__URG_HIGH_MASK 0x000000F0L 6845 #define DAGB4_RDCLI5__URG_LOW_MASK 0x00000F00L 6846 #define DAGB4_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L 6847 #define DAGB4_RDCLI5__MAX_BW_MASK 0x001FE000L 6848 #define DAGB4_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L 6849 #define DAGB4_RDCLI5__MIN_BW_MASK 0x01C00000L 6850 #define DAGB4_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 6851 #define DAGB4_RDCLI5__MAX_OSD_MASK 0xFC000000L 6852 //DAGB4_RDCLI6 6853 #define DAGB4_RDCLI6__VIRT_CHAN__SHIFT 0x0 6854 #define DAGB4_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 6855 #define DAGB4_RDCLI6__URG_HIGH__SHIFT 0x4 6856 #define DAGB4_RDCLI6__URG_LOW__SHIFT 0x8 6857 #define DAGB4_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc 6858 #define DAGB4_RDCLI6__MAX_BW__SHIFT 0xd 6859 #define DAGB4_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 6860 #define DAGB4_RDCLI6__MIN_BW__SHIFT 0x16 6861 #define DAGB4_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 6862 #define DAGB4_RDCLI6__MAX_OSD__SHIFT 0x1a 6863 #define DAGB4_RDCLI6__VIRT_CHAN_MASK 0x00000007L 6864 #define DAGB4_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 6865 #define DAGB4_RDCLI6__URG_HIGH_MASK 0x000000F0L 6866 #define DAGB4_RDCLI6__URG_LOW_MASK 0x00000F00L 6867 #define DAGB4_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L 6868 #define DAGB4_RDCLI6__MAX_BW_MASK 0x001FE000L 6869 #define DAGB4_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L 6870 #define DAGB4_RDCLI6__MIN_BW_MASK 0x01C00000L 6871 #define DAGB4_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 6872 #define DAGB4_RDCLI6__MAX_OSD_MASK 0xFC000000L 6873 //DAGB4_RDCLI7 6874 #define DAGB4_RDCLI7__VIRT_CHAN__SHIFT 0x0 6875 #define DAGB4_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 6876 #define DAGB4_RDCLI7__URG_HIGH__SHIFT 0x4 6877 #define DAGB4_RDCLI7__URG_LOW__SHIFT 0x8 6878 #define DAGB4_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc 6879 #define DAGB4_RDCLI7__MAX_BW__SHIFT 0xd 6880 #define DAGB4_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 6881 #define DAGB4_RDCLI7__MIN_BW__SHIFT 0x16 6882 #define DAGB4_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 6883 #define DAGB4_RDCLI7__MAX_OSD__SHIFT 0x1a 6884 #define DAGB4_RDCLI7__VIRT_CHAN_MASK 0x00000007L 6885 #define DAGB4_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 6886 #define DAGB4_RDCLI7__URG_HIGH_MASK 0x000000F0L 6887 #define DAGB4_RDCLI7__URG_LOW_MASK 0x00000F00L 6888 #define DAGB4_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L 6889 #define DAGB4_RDCLI7__MAX_BW_MASK 0x001FE000L 6890 #define DAGB4_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L 6891 #define DAGB4_RDCLI7__MIN_BW_MASK 0x01C00000L 6892 #define DAGB4_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 6893 #define DAGB4_RDCLI7__MAX_OSD_MASK 0xFC000000L 6894 //DAGB4_RDCLI8 6895 #define DAGB4_RDCLI8__VIRT_CHAN__SHIFT 0x0 6896 #define DAGB4_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 6897 #define DAGB4_RDCLI8__URG_HIGH__SHIFT 0x4 6898 #define DAGB4_RDCLI8__URG_LOW__SHIFT 0x8 6899 #define DAGB4_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc 6900 #define DAGB4_RDCLI8__MAX_BW__SHIFT 0xd 6901 #define DAGB4_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 6902 #define DAGB4_RDCLI8__MIN_BW__SHIFT 0x16 6903 #define DAGB4_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 6904 #define DAGB4_RDCLI8__MAX_OSD__SHIFT 0x1a 6905 #define DAGB4_RDCLI8__VIRT_CHAN_MASK 0x00000007L 6906 #define DAGB4_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 6907 #define DAGB4_RDCLI8__URG_HIGH_MASK 0x000000F0L 6908 #define DAGB4_RDCLI8__URG_LOW_MASK 0x00000F00L 6909 #define DAGB4_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L 6910 #define DAGB4_RDCLI8__MAX_BW_MASK 0x001FE000L 6911 #define DAGB4_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L 6912 #define DAGB4_RDCLI8__MIN_BW_MASK 0x01C00000L 6913 #define DAGB4_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 6914 #define DAGB4_RDCLI8__MAX_OSD_MASK 0xFC000000L 6915 //DAGB4_RDCLI9 6916 #define DAGB4_RDCLI9__VIRT_CHAN__SHIFT 0x0 6917 #define DAGB4_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 6918 #define DAGB4_RDCLI9__URG_HIGH__SHIFT 0x4 6919 #define DAGB4_RDCLI9__URG_LOW__SHIFT 0x8 6920 #define DAGB4_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc 6921 #define DAGB4_RDCLI9__MAX_BW__SHIFT 0xd 6922 #define DAGB4_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 6923 #define DAGB4_RDCLI9__MIN_BW__SHIFT 0x16 6924 #define DAGB4_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 6925 #define DAGB4_RDCLI9__MAX_OSD__SHIFT 0x1a 6926 #define DAGB4_RDCLI9__VIRT_CHAN_MASK 0x00000007L 6927 #define DAGB4_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 6928 #define DAGB4_RDCLI9__URG_HIGH_MASK 0x000000F0L 6929 #define DAGB4_RDCLI9__URG_LOW_MASK 0x00000F00L 6930 #define DAGB4_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L 6931 #define DAGB4_RDCLI9__MAX_BW_MASK 0x001FE000L 6932 #define DAGB4_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L 6933 #define DAGB4_RDCLI9__MIN_BW_MASK 0x01C00000L 6934 #define DAGB4_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 6935 #define DAGB4_RDCLI9__MAX_OSD_MASK 0xFC000000L 6936 //DAGB4_RDCLI10 6937 #define DAGB4_RDCLI10__VIRT_CHAN__SHIFT 0x0 6938 #define DAGB4_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 6939 #define DAGB4_RDCLI10__URG_HIGH__SHIFT 0x4 6940 #define DAGB4_RDCLI10__URG_LOW__SHIFT 0x8 6941 #define DAGB4_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc 6942 #define DAGB4_RDCLI10__MAX_BW__SHIFT 0xd 6943 #define DAGB4_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 6944 #define DAGB4_RDCLI10__MIN_BW__SHIFT 0x16 6945 #define DAGB4_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 6946 #define DAGB4_RDCLI10__MAX_OSD__SHIFT 0x1a 6947 #define DAGB4_RDCLI10__VIRT_CHAN_MASK 0x00000007L 6948 #define DAGB4_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 6949 #define DAGB4_RDCLI10__URG_HIGH_MASK 0x000000F0L 6950 #define DAGB4_RDCLI10__URG_LOW_MASK 0x00000F00L 6951 #define DAGB4_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L 6952 #define DAGB4_RDCLI10__MAX_BW_MASK 0x001FE000L 6953 #define DAGB4_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L 6954 #define DAGB4_RDCLI10__MIN_BW_MASK 0x01C00000L 6955 #define DAGB4_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 6956 #define DAGB4_RDCLI10__MAX_OSD_MASK 0xFC000000L 6957 //DAGB4_RDCLI11 6958 #define DAGB4_RDCLI11__VIRT_CHAN__SHIFT 0x0 6959 #define DAGB4_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 6960 #define DAGB4_RDCLI11__URG_HIGH__SHIFT 0x4 6961 #define DAGB4_RDCLI11__URG_LOW__SHIFT 0x8 6962 #define DAGB4_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc 6963 #define DAGB4_RDCLI11__MAX_BW__SHIFT 0xd 6964 #define DAGB4_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 6965 #define DAGB4_RDCLI11__MIN_BW__SHIFT 0x16 6966 #define DAGB4_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 6967 #define DAGB4_RDCLI11__MAX_OSD__SHIFT 0x1a 6968 #define DAGB4_RDCLI11__VIRT_CHAN_MASK 0x00000007L 6969 #define DAGB4_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 6970 #define DAGB4_RDCLI11__URG_HIGH_MASK 0x000000F0L 6971 #define DAGB4_RDCLI11__URG_LOW_MASK 0x00000F00L 6972 #define DAGB4_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L 6973 #define DAGB4_RDCLI11__MAX_BW_MASK 0x001FE000L 6974 #define DAGB4_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L 6975 #define DAGB4_RDCLI11__MIN_BW_MASK 0x01C00000L 6976 #define DAGB4_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 6977 #define DAGB4_RDCLI11__MAX_OSD_MASK 0xFC000000L 6978 //DAGB4_RDCLI12 6979 #define DAGB4_RDCLI12__VIRT_CHAN__SHIFT 0x0 6980 #define DAGB4_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 6981 #define DAGB4_RDCLI12__URG_HIGH__SHIFT 0x4 6982 #define DAGB4_RDCLI12__URG_LOW__SHIFT 0x8 6983 #define DAGB4_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc 6984 #define DAGB4_RDCLI12__MAX_BW__SHIFT 0xd 6985 #define DAGB4_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 6986 #define DAGB4_RDCLI12__MIN_BW__SHIFT 0x16 6987 #define DAGB4_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 6988 #define DAGB4_RDCLI12__MAX_OSD__SHIFT 0x1a 6989 #define DAGB4_RDCLI12__VIRT_CHAN_MASK 0x00000007L 6990 #define DAGB4_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 6991 #define DAGB4_RDCLI12__URG_HIGH_MASK 0x000000F0L 6992 #define DAGB4_RDCLI12__URG_LOW_MASK 0x00000F00L 6993 #define DAGB4_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L 6994 #define DAGB4_RDCLI12__MAX_BW_MASK 0x001FE000L 6995 #define DAGB4_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L 6996 #define DAGB4_RDCLI12__MIN_BW_MASK 0x01C00000L 6997 #define DAGB4_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 6998 #define DAGB4_RDCLI12__MAX_OSD_MASK 0xFC000000L 6999 //DAGB4_RDCLI13 7000 #define DAGB4_RDCLI13__VIRT_CHAN__SHIFT 0x0 7001 #define DAGB4_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 7002 #define DAGB4_RDCLI13__URG_HIGH__SHIFT 0x4 7003 #define DAGB4_RDCLI13__URG_LOW__SHIFT 0x8 7004 #define DAGB4_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc 7005 #define DAGB4_RDCLI13__MAX_BW__SHIFT 0xd 7006 #define DAGB4_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 7007 #define DAGB4_RDCLI13__MIN_BW__SHIFT 0x16 7008 #define DAGB4_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 7009 #define DAGB4_RDCLI13__MAX_OSD__SHIFT 0x1a 7010 #define DAGB4_RDCLI13__VIRT_CHAN_MASK 0x00000007L 7011 #define DAGB4_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 7012 #define DAGB4_RDCLI13__URG_HIGH_MASK 0x000000F0L 7013 #define DAGB4_RDCLI13__URG_LOW_MASK 0x00000F00L 7014 #define DAGB4_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L 7015 #define DAGB4_RDCLI13__MAX_BW_MASK 0x001FE000L 7016 #define DAGB4_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L 7017 #define DAGB4_RDCLI13__MIN_BW_MASK 0x01C00000L 7018 #define DAGB4_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 7019 #define DAGB4_RDCLI13__MAX_OSD_MASK 0xFC000000L 7020 //DAGB4_RDCLI14 7021 #define DAGB4_RDCLI14__VIRT_CHAN__SHIFT 0x0 7022 #define DAGB4_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 7023 #define DAGB4_RDCLI14__URG_HIGH__SHIFT 0x4 7024 #define DAGB4_RDCLI14__URG_LOW__SHIFT 0x8 7025 #define DAGB4_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc 7026 #define DAGB4_RDCLI14__MAX_BW__SHIFT 0xd 7027 #define DAGB4_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 7028 #define DAGB4_RDCLI14__MIN_BW__SHIFT 0x16 7029 #define DAGB4_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 7030 #define DAGB4_RDCLI14__MAX_OSD__SHIFT 0x1a 7031 #define DAGB4_RDCLI14__VIRT_CHAN_MASK 0x00000007L 7032 #define DAGB4_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 7033 #define DAGB4_RDCLI14__URG_HIGH_MASK 0x000000F0L 7034 #define DAGB4_RDCLI14__URG_LOW_MASK 0x00000F00L 7035 #define DAGB4_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L 7036 #define DAGB4_RDCLI14__MAX_BW_MASK 0x001FE000L 7037 #define DAGB4_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L 7038 #define DAGB4_RDCLI14__MIN_BW_MASK 0x01C00000L 7039 #define DAGB4_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 7040 #define DAGB4_RDCLI14__MAX_OSD_MASK 0xFC000000L 7041 //DAGB4_RDCLI15 7042 #define DAGB4_RDCLI15__VIRT_CHAN__SHIFT 0x0 7043 #define DAGB4_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 7044 #define DAGB4_RDCLI15__URG_HIGH__SHIFT 0x4 7045 #define DAGB4_RDCLI15__URG_LOW__SHIFT 0x8 7046 #define DAGB4_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc 7047 #define DAGB4_RDCLI15__MAX_BW__SHIFT 0xd 7048 #define DAGB4_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 7049 #define DAGB4_RDCLI15__MIN_BW__SHIFT 0x16 7050 #define DAGB4_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 7051 #define DAGB4_RDCLI15__MAX_OSD__SHIFT 0x1a 7052 #define DAGB4_RDCLI15__VIRT_CHAN_MASK 0x00000007L 7053 #define DAGB4_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 7054 #define DAGB4_RDCLI15__URG_HIGH_MASK 0x000000F0L 7055 #define DAGB4_RDCLI15__URG_LOW_MASK 0x00000F00L 7056 #define DAGB4_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L 7057 #define DAGB4_RDCLI15__MAX_BW_MASK 0x001FE000L 7058 #define DAGB4_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L 7059 #define DAGB4_RDCLI15__MIN_BW_MASK 0x01C00000L 7060 #define DAGB4_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 7061 #define DAGB4_RDCLI15__MAX_OSD_MASK 0xFC000000L 7062 //DAGB4_RD_CNTL 7063 #define DAGB4_RD_CNTL__SCLK_FREQ__SHIFT 0x0 7064 #define DAGB4_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 7065 #define DAGB4_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 7066 #define DAGB4_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 7067 #define DAGB4_RD_CNTL__IO_LEVEL__SHIFT 0x11 7068 #define DAGB4_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 7069 #define DAGB4_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 7070 #define DAGB4_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL 7071 #define DAGB4_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 7072 #define DAGB4_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 7073 #define DAGB4_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 7074 #define DAGB4_RD_CNTL__IO_LEVEL_MASK 0x000E0000L 7075 #define DAGB4_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 7076 #define DAGB4_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L 7077 //DAGB4_RD_GMI_CNTL 7078 #define DAGB4_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 7079 #define DAGB4_RD_GMI_CNTL__LEVEL__SHIFT 0x6 7080 #define DAGB4_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 7081 #define DAGB4_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 7082 #define DAGB4_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 7083 #define DAGB4_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L 7084 #define DAGB4_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 7085 #define DAGB4_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 7086 //DAGB4_RD_ADDR_DAGB 7087 #define DAGB4_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 7088 #define DAGB4_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 7089 #define DAGB4_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 7090 #define DAGB4_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 7091 #define DAGB4_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 7092 #define DAGB4_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 7093 #define DAGB4_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 7094 #define DAGB4_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 7095 //DAGB4_RD_OUTPUT_DAGB_MAX_BURST 7096 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 7097 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 7098 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 7099 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 7100 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 7101 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 7102 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 7103 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 7104 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 7105 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 7106 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 7107 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 7108 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 7109 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 7110 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 7111 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 7112 //DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER 7113 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 7114 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 7115 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 7116 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 7117 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 7118 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 7119 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 7120 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 7121 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 7122 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 7123 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 7124 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 7125 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 7126 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 7127 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 7128 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 7129 //DAGB4_RD_CGTT_CLK_CTRL 7130 #define DAGB4_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 7131 #define DAGB4_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 7132 #define DAGB4_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 7133 #define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 7134 #define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 7135 #define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 7136 #define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 7137 #define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 7138 #define DAGB4_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 7139 #define DAGB4_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 7140 #define DAGB4_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 7141 #define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 7142 #define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 7143 #define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 7144 #define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 7145 #define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 7146 //DAGB4_L1TLB_RD_CGTT_CLK_CTRL 7147 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 7148 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 7149 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 7150 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 7151 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 7152 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 7153 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 7154 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 7155 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 7156 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 7157 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 7158 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 7159 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 7160 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 7161 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 7162 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 7163 //DAGB4_ATCVM_RD_CGTT_CLK_CTRL 7164 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 7165 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 7166 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 7167 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 7168 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 7169 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 7170 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 7171 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 7172 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 7173 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 7174 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 7175 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 7176 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 7177 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 7178 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 7179 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 7180 //DAGB4_RD_ADDR_DAGB_MAX_BURST0 7181 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 7182 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 7183 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 7184 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 7185 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 7186 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 7187 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 7188 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 7189 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 7190 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 7191 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 7192 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 7193 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 7194 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 7195 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 7196 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 7197 //DAGB4_RD_ADDR_DAGB_LAZY_TIMER0 7198 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 7199 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 7200 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 7201 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 7202 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 7203 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 7204 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 7205 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 7206 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 7207 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 7208 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 7209 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 7210 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 7211 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 7212 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 7213 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 7214 //DAGB4_RD_ADDR_DAGB_MAX_BURST1 7215 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 7216 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 7217 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 7218 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 7219 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 7220 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 7221 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 7222 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 7223 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 7224 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 7225 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 7226 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 7227 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 7228 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 7229 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 7230 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 7231 //DAGB4_RD_ADDR_DAGB_LAZY_TIMER1 7232 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 7233 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 7234 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 7235 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 7236 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 7237 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 7238 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 7239 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 7240 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 7241 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 7242 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 7243 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 7244 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 7245 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 7246 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 7247 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 7248 //DAGB4_RD_VC0_CNTL 7249 #define DAGB4_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 7250 #define DAGB4_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 7251 #define DAGB4_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 7252 #define DAGB4_RD_VC0_CNTL__MAX_BW__SHIFT 0xc 7253 #define DAGB4_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 7254 #define DAGB4_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 7255 #define DAGB4_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 7256 #define DAGB4_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 7257 #define DAGB4_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 7258 #define DAGB4_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 7259 #define DAGB4_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 7260 #define DAGB4_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L 7261 #define DAGB4_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 7262 #define DAGB4_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L 7263 #define DAGB4_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 7264 #define DAGB4_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 7265 //DAGB4_RD_VC1_CNTL 7266 #define DAGB4_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 7267 #define DAGB4_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 7268 #define DAGB4_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 7269 #define DAGB4_RD_VC1_CNTL__MAX_BW__SHIFT 0xc 7270 #define DAGB4_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 7271 #define DAGB4_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 7272 #define DAGB4_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 7273 #define DAGB4_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 7274 #define DAGB4_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 7275 #define DAGB4_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 7276 #define DAGB4_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 7277 #define DAGB4_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L 7278 #define DAGB4_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 7279 #define DAGB4_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L 7280 #define DAGB4_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 7281 #define DAGB4_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 7282 //DAGB4_RD_VC2_CNTL 7283 #define DAGB4_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 7284 #define DAGB4_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 7285 #define DAGB4_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 7286 #define DAGB4_RD_VC2_CNTL__MAX_BW__SHIFT 0xc 7287 #define DAGB4_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 7288 #define DAGB4_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 7289 #define DAGB4_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 7290 #define DAGB4_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 7291 #define DAGB4_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 7292 #define DAGB4_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 7293 #define DAGB4_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 7294 #define DAGB4_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L 7295 #define DAGB4_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 7296 #define DAGB4_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L 7297 #define DAGB4_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 7298 #define DAGB4_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 7299 //DAGB4_RD_VC3_CNTL 7300 #define DAGB4_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 7301 #define DAGB4_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 7302 #define DAGB4_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 7303 #define DAGB4_RD_VC3_CNTL__MAX_BW__SHIFT 0xc 7304 #define DAGB4_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 7305 #define DAGB4_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 7306 #define DAGB4_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 7307 #define DAGB4_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 7308 #define DAGB4_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 7309 #define DAGB4_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 7310 #define DAGB4_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 7311 #define DAGB4_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L 7312 #define DAGB4_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 7313 #define DAGB4_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L 7314 #define DAGB4_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 7315 #define DAGB4_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 7316 //DAGB4_RD_VC4_CNTL 7317 #define DAGB4_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 7318 #define DAGB4_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 7319 #define DAGB4_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 7320 #define DAGB4_RD_VC4_CNTL__MAX_BW__SHIFT 0xc 7321 #define DAGB4_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 7322 #define DAGB4_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 7323 #define DAGB4_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 7324 #define DAGB4_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 7325 #define DAGB4_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 7326 #define DAGB4_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 7327 #define DAGB4_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 7328 #define DAGB4_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L 7329 #define DAGB4_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 7330 #define DAGB4_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L 7331 #define DAGB4_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 7332 #define DAGB4_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 7333 //DAGB4_RD_VC5_CNTL 7334 #define DAGB4_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 7335 #define DAGB4_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 7336 #define DAGB4_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 7337 #define DAGB4_RD_VC5_CNTL__MAX_BW__SHIFT 0xc 7338 #define DAGB4_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 7339 #define DAGB4_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 7340 #define DAGB4_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 7341 #define DAGB4_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 7342 #define DAGB4_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 7343 #define DAGB4_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 7344 #define DAGB4_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 7345 #define DAGB4_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L 7346 #define DAGB4_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 7347 #define DAGB4_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L 7348 #define DAGB4_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 7349 #define DAGB4_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 7350 //DAGB4_RD_VC6_CNTL 7351 #define DAGB4_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 7352 #define DAGB4_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 7353 #define DAGB4_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 7354 #define DAGB4_RD_VC6_CNTL__MAX_BW__SHIFT 0xc 7355 #define DAGB4_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 7356 #define DAGB4_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 7357 #define DAGB4_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 7358 #define DAGB4_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 7359 #define DAGB4_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 7360 #define DAGB4_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 7361 #define DAGB4_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 7362 #define DAGB4_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L 7363 #define DAGB4_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 7364 #define DAGB4_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L 7365 #define DAGB4_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 7366 #define DAGB4_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 7367 //DAGB4_RD_VC7_CNTL 7368 #define DAGB4_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 7369 #define DAGB4_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 7370 #define DAGB4_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 7371 #define DAGB4_RD_VC7_CNTL__MAX_BW__SHIFT 0xc 7372 #define DAGB4_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 7373 #define DAGB4_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 7374 #define DAGB4_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 7375 #define DAGB4_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 7376 #define DAGB4_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 7377 #define DAGB4_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 7378 #define DAGB4_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 7379 #define DAGB4_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L 7380 #define DAGB4_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 7381 #define DAGB4_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L 7382 #define DAGB4_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 7383 #define DAGB4_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 7384 //DAGB4_RD_CNTL_MISC 7385 #define DAGB4_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 7386 #define DAGB4_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 7387 #define DAGB4_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 7388 #define DAGB4_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 7389 #define DAGB4_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 7390 #define DAGB4_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 7391 #define DAGB4_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a 7392 #define DAGB4_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 7393 #define DAGB4_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 7394 #define DAGB4_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 7395 #define DAGB4_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 7396 #define DAGB4_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 7397 #define DAGB4_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 7398 #define DAGB4_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L 7399 //DAGB4_RD_TLB_CREDIT 7400 #define DAGB4_RD_TLB_CREDIT__TLB0__SHIFT 0x0 7401 #define DAGB4_RD_TLB_CREDIT__TLB1__SHIFT 0x5 7402 #define DAGB4_RD_TLB_CREDIT__TLB2__SHIFT 0xa 7403 #define DAGB4_RD_TLB_CREDIT__TLB3__SHIFT 0xf 7404 #define DAGB4_RD_TLB_CREDIT__TLB4__SHIFT 0x14 7405 #define DAGB4_RD_TLB_CREDIT__TLB5__SHIFT 0x19 7406 #define DAGB4_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL 7407 #define DAGB4_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L 7408 #define DAGB4_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L 7409 #define DAGB4_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L 7410 #define DAGB4_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L 7411 #define DAGB4_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L 7412 //DAGB4_RDCLI_ASK_PENDING 7413 #define DAGB4_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 7414 #define DAGB4_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 7415 //DAGB4_RDCLI_GO_PENDING 7416 #define DAGB4_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 7417 #define DAGB4_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 7418 //DAGB4_RDCLI_GBLSEND_PENDING 7419 #define DAGB4_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 7420 #define DAGB4_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 7421 //DAGB4_RDCLI_TLB_PENDING 7422 #define DAGB4_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 7423 #define DAGB4_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 7424 //DAGB4_RDCLI_OARB_PENDING 7425 #define DAGB4_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 7426 #define DAGB4_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 7427 //DAGB4_RDCLI_OSD_PENDING 7428 #define DAGB4_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 7429 #define DAGB4_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 7430 //DAGB4_WRCLI0 7431 #define DAGB4_WRCLI0__VIRT_CHAN__SHIFT 0x0 7432 #define DAGB4_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 7433 #define DAGB4_WRCLI0__URG_HIGH__SHIFT 0x4 7434 #define DAGB4_WRCLI0__URG_LOW__SHIFT 0x8 7435 #define DAGB4_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc 7436 #define DAGB4_WRCLI0__MAX_BW__SHIFT 0xd 7437 #define DAGB4_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 7438 #define DAGB4_WRCLI0__MIN_BW__SHIFT 0x16 7439 #define DAGB4_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 7440 #define DAGB4_WRCLI0__MAX_OSD__SHIFT 0x1a 7441 #define DAGB4_WRCLI0__VIRT_CHAN_MASK 0x00000007L 7442 #define DAGB4_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 7443 #define DAGB4_WRCLI0__URG_HIGH_MASK 0x000000F0L 7444 #define DAGB4_WRCLI0__URG_LOW_MASK 0x00000F00L 7445 #define DAGB4_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L 7446 #define DAGB4_WRCLI0__MAX_BW_MASK 0x001FE000L 7447 #define DAGB4_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L 7448 #define DAGB4_WRCLI0__MIN_BW_MASK 0x01C00000L 7449 #define DAGB4_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 7450 #define DAGB4_WRCLI0__MAX_OSD_MASK 0xFC000000L 7451 //DAGB4_WRCLI1 7452 #define DAGB4_WRCLI1__VIRT_CHAN__SHIFT 0x0 7453 #define DAGB4_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 7454 #define DAGB4_WRCLI1__URG_HIGH__SHIFT 0x4 7455 #define DAGB4_WRCLI1__URG_LOW__SHIFT 0x8 7456 #define DAGB4_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc 7457 #define DAGB4_WRCLI1__MAX_BW__SHIFT 0xd 7458 #define DAGB4_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 7459 #define DAGB4_WRCLI1__MIN_BW__SHIFT 0x16 7460 #define DAGB4_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 7461 #define DAGB4_WRCLI1__MAX_OSD__SHIFT 0x1a 7462 #define DAGB4_WRCLI1__VIRT_CHAN_MASK 0x00000007L 7463 #define DAGB4_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 7464 #define DAGB4_WRCLI1__URG_HIGH_MASK 0x000000F0L 7465 #define DAGB4_WRCLI1__URG_LOW_MASK 0x00000F00L 7466 #define DAGB4_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L 7467 #define DAGB4_WRCLI1__MAX_BW_MASK 0x001FE000L 7468 #define DAGB4_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L 7469 #define DAGB4_WRCLI1__MIN_BW_MASK 0x01C00000L 7470 #define DAGB4_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 7471 #define DAGB4_WRCLI1__MAX_OSD_MASK 0xFC000000L 7472 //DAGB4_WRCLI2 7473 #define DAGB4_WRCLI2__VIRT_CHAN__SHIFT 0x0 7474 #define DAGB4_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 7475 #define DAGB4_WRCLI2__URG_HIGH__SHIFT 0x4 7476 #define DAGB4_WRCLI2__URG_LOW__SHIFT 0x8 7477 #define DAGB4_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc 7478 #define DAGB4_WRCLI2__MAX_BW__SHIFT 0xd 7479 #define DAGB4_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 7480 #define DAGB4_WRCLI2__MIN_BW__SHIFT 0x16 7481 #define DAGB4_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 7482 #define DAGB4_WRCLI2__MAX_OSD__SHIFT 0x1a 7483 #define DAGB4_WRCLI2__VIRT_CHAN_MASK 0x00000007L 7484 #define DAGB4_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 7485 #define DAGB4_WRCLI2__URG_HIGH_MASK 0x000000F0L 7486 #define DAGB4_WRCLI2__URG_LOW_MASK 0x00000F00L 7487 #define DAGB4_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L 7488 #define DAGB4_WRCLI2__MAX_BW_MASK 0x001FE000L 7489 #define DAGB4_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L 7490 #define DAGB4_WRCLI2__MIN_BW_MASK 0x01C00000L 7491 #define DAGB4_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 7492 #define DAGB4_WRCLI2__MAX_OSD_MASK 0xFC000000L 7493 //DAGB4_WRCLI3 7494 #define DAGB4_WRCLI3__VIRT_CHAN__SHIFT 0x0 7495 #define DAGB4_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 7496 #define DAGB4_WRCLI3__URG_HIGH__SHIFT 0x4 7497 #define DAGB4_WRCLI3__URG_LOW__SHIFT 0x8 7498 #define DAGB4_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc 7499 #define DAGB4_WRCLI3__MAX_BW__SHIFT 0xd 7500 #define DAGB4_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 7501 #define DAGB4_WRCLI3__MIN_BW__SHIFT 0x16 7502 #define DAGB4_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 7503 #define DAGB4_WRCLI3__MAX_OSD__SHIFT 0x1a 7504 #define DAGB4_WRCLI3__VIRT_CHAN_MASK 0x00000007L 7505 #define DAGB4_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 7506 #define DAGB4_WRCLI3__URG_HIGH_MASK 0x000000F0L 7507 #define DAGB4_WRCLI3__URG_LOW_MASK 0x00000F00L 7508 #define DAGB4_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L 7509 #define DAGB4_WRCLI3__MAX_BW_MASK 0x001FE000L 7510 #define DAGB4_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L 7511 #define DAGB4_WRCLI3__MIN_BW_MASK 0x01C00000L 7512 #define DAGB4_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 7513 #define DAGB4_WRCLI3__MAX_OSD_MASK 0xFC000000L 7514 //DAGB4_WRCLI4 7515 #define DAGB4_WRCLI4__VIRT_CHAN__SHIFT 0x0 7516 #define DAGB4_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 7517 #define DAGB4_WRCLI4__URG_HIGH__SHIFT 0x4 7518 #define DAGB4_WRCLI4__URG_LOW__SHIFT 0x8 7519 #define DAGB4_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc 7520 #define DAGB4_WRCLI4__MAX_BW__SHIFT 0xd 7521 #define DAGB4_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 7522 #define DAGB4_WRCLI4__MIN_BW__SHIFT 0x16 7523 #define DAGB4_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 7524 #define DAGB4_WRCLI4__MAX_OSD__SHIFT 0x1a 7525 #define DAGB4_WRCLI4__VIRT_CHAN_MASK 0x00000007L 7526 #define DAGB4_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 7527 #define DAGB4_WRCLI4__URG_HIGH_MASK 0x000000F0L 7528 #define DAGB4_WRCLI4__URG_LOW_MASK 0x00000F00L 7529 #define DAGB4_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L 7530 #define DAGB4_WRCLI4__MAX_BW_MASK 0x001FE000L 7531 #define DAGB4_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L 7532 #define DAGB4_WRCLI4__MIN_BW_MASK 0x01C00000L 7533 #define DAGB4_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 7534 #define DAGB4_WRCLI4__MAX_OSD_MASK 0xFC000000L 7535 //DAGB4_WRCLI5 7536 #define DAGB4_WRCLI5__VIRT_CHAN__SHIFT 0x0 7537 #define DAGB4_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 7538 #define DAGB4_WRCLI5__URG_HIGH__SHIFT 0x4 7539 #define DAGB4_WRCLI5__URG_LOW__SHIFT 0x8 7540 #define DAGB4_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc 7541 #define DAGB4_WRCLI5__MAX_BW__SHIFT 0xd 7542 #define DAGB4_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 7543 #define DAGB4_WRCLI5__MIN_BW__SHIFT 0x16 7544 #define DAGB4_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 7545 #define DAGB4_WRCLI5__MAX_OSD__SHIFT 0x1a 7546 #define DAGB4_WRCLI5__VIRT_CHAN_MASK 0x00000007L 7547 #define DAGB4_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 7548 #define DAGB4_WRCLI5__URG_HIGH_MASK 0x000000F0L 7549 #define DAGB4_WRCLI5__URG_LOW_MASK 0x00000F00L 7550 #define DAGB4_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L 7551 #define DAGB4_WRCLI5__MAX_BW_MASK 0x001FE000L 7552 #define DAGB4_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L 7553 #define DAGB4_WRCLI5__MIN_BW_MASK 0x01C00000L 7554 #define DAGB4_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 7555 #define DAGB4_WRCLI5__MAX_OSD_MASK 0xFC000000L 7556 //DAGB4_WRCLI6 7557 #define DAGB4_WRCLI6__VIRT_CHAN__SHIFT 0x0 7558 #define DAGB4_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 7559 #define DAGB4_WRCLI6__URG_HIGH__SHIFT 0x4 7560 #define DAGB4_WRCLI6__URG_LOW__SHIFT 0x8 7561 #define DAGB4_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc 7562 #define DAGB4_WRCLI6__MAX_BW__SHIFT 0xd 7563 #define DAGB4_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 7564 #define DAGB4_WRCLI6__MIN_BW__SHIFT 0x16 7565 #define DAGB4_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 7566 #define DAGB4_WRCLI6__MAX_OSD__SHIFT 0x1a 7567 #define DAGB4_WRCLI6__VIRT_CHAN_MASK 0x00000007L 7568 #define DAGB4_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 7569 #define DAGB4_WRCLI6__URG_HIGH_MASK 0x000000F0L 7570 #define DAGB4_WRCLI6__URG_LOW_MASK 0x00000F00L 7571 #define DAGB4_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L 7572 #define DAGB4_WRCLI6__MAX_BW_MASK 0x001FE000L 7573 #define DAGB4_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L 7574 #define DAGB4_WRCLI6__MIN_BW_MASK 0x01C00000L 7575 #define DAGB4_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 7576 #define DAGB4_WRCLI6__MAX_OSD_MASK 0xFC000000L 7577 //DAGB4_WRCLI7 7578 #define DAGB4_WRCLI7__VIRT_CHAN__SHIFT 0x0 7579 #define DAGB4_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 7580 #define DAGB4_WRCLI7__URG_HIGH__SHIFT 0x4 7581 #define DAGB4_WRCLI7__URG_LOW__SHIFT 0x8 7582 #define DAGB4_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc 7583 #define DAGB4_WRCLI7__MAX_BW__SHIFT 0xd 7584 #define DAGB4_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 7585 #define DAGB4_WRCLI7__MIN_BW__SHIFT 0x16 7586 #define DAGB4_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 7587 #define DAGB4_WRCLI7__MAX_OSD__SHIFT 0x1a 7588 #define DAGB4_WRCLI7__VIRT_CHAN_MASK 0x00000007L 7589 #define DAGB4_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 7590 #define DAGB4_WRCLI7__URG_HIGH_MASK 0x000000F0L 7591 #define DAGB4_WRCLI7__URG_LOW_MASK 0x00000F00L 7592 #define DAGB4_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L 7593 #define DAGB4_WRCLI7__MAX_BW_MASK 0x001FE000L 7594 #define DAGB4_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L 7595 #define DAGB4_WRCLI7__MIN_BW_MASK 0x01C00000L 7596 #define DAGB4_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 7597 #define DAGB4_WRCLI7__MAX_OSD_MASK 0xFC000000L 7598 //DAGB4_WRCLI8 7599 #define DAGB4_WRCLI8__VIRT_CHAN__SHIFT 0x0 7600 #define DAGB4_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 7601 #define DAGB4_WRCLI8__URG_HIGH__SHIFT 0x4 7602 #define DAGB4_WRCLI8__URG_LOW__SHIFT 0x8 7603 #define DAGB4_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc 7604 #define DAGB4_WRCLI8__MAX_BW__SHIFT 0xd 7605 #define DAGB4_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 7606 #define DAGB4_WRCLI8__MIN_BW__SHIFT 0x16 7607 #define DAGB4_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 7608 #define DAGB4_WRCLI8__MAX_OSD__SHIFT 0x1a 7609 #define DAGB4_WRCLI8__VIRT_CHAN_MASK 0x00000007L 7610 #define DAGB4_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 7611 #define DAGB4_WRCLI8__URG_HIGH_MASK 0x000000F0L 7612 #define DAGB4_WRCLI8__URG_LOW_MASK 0x00000F00L 7613 #define DAGB4_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L 7614 #define DAGB4_WRCLI8__MAX_BW_MASK 0x001FE000L 7615 #define DAGB4_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L 7616 #define DAGB4_WRCLI8__MIN_BW_MASK 0x01C00000L 7617 #define DAGB4_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 7618 #define DAGB4_WRCLI8__MAX_OSD_MASK 0xFC000000L 7619 //DAGB4_WRCLI9 7620 #define DAGB4_WRCLI9__VIRT_CHAN__SHIFT 0x0 7621 #define DAGB4_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 7622 #define DAGB4_WRCLI9__URG_HIGH__SHIFT 0x4 7623 #define DAGB4_WRCLI9__URG_LOW__SHIFT 0x8 7624 #define DAGB4_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc 7625 #define DAGB4_WRCLI9__MAX_BW__SHIFT 0xd 7626 #define DAGB4_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 7627 #define DAGB4_WRCLI9__MIN_BW__SHIFT 0x16 7628 #define DAGB4_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 7629 #define DAGB4_WRCLI9__MAX_OSD__SHIFT 0x1a 7630 #define DAGB4_WRCLI9__VIRT_CHAN_MASK 0x00000007L 7631 #define DAGB4_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 7632 #define DAGB4_WRCLI9__URG_HIGH_MASK 0x000000F0L 7633 #define DAGB4_WRCLI9__URG_LOW_MASK 0x00000F00L 7634 #define DAGB4_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L 7635 #define DAGB4_WRCLI9__MAX_BW_MASK 0x001FE000L 7636 #define DAGB4_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L 7637 #define DAGB4_WRCLI9__MIN_BW_MASK 0x01C00000L 7638 #define DAGB4_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 7639 #define DAGB4_WRCLI9__MAX_OSD_MASK 0xFC000000L 7640 //DAGB4_WRCLI10 7641 #define DAGB4_WRCLI10__VIRT_CHAN__SHIFT 0x0 7642 #define DAGB4_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 7643 #define DAGB4_WRCLI10__URG_HIGH__SHIFT 0x4 7644 #define DAGB4_WRCLI10__URG_LOW__SHIFT 0x8 7645 #define DAGB4_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc 7646 #define DAGB4_WRCLI10__MAX_BW__SHIFT 0xd 7647 #define DAGB4_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 7648 #define DAGB4_WRCLI10__MIN_BW__SHIFT 0x16 7649 #define DAGB4_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 7650 #define DAGB4_WRCLI10__MAX_OSD__SHIFT 0x1a 7651 #define DAGB4_WRCLI10__VIRT_CHAN_MASK 0x00000007L 7652 #define DAGB4_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 7653 #define DAGB4_WRCLI10__URG_HIGH_MASK 0x000000F0L 7654 #define DAGB4_WRCLI10__URG_LOW_MASK 0x00000F00L 7655 #define DAGB4_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L 7656 #define DAGB4_WRCLI10__MAX_BW_MASK 0x001FE000L 7657 #define DAGB4_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L 7658 #define DAGB4_WRCLI10__MIN_BW_MASK 0x01C00000L 7659 #define DAGB4_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 7660 #define DAGB4_WRCLI10__MAX_OSD_MASK 0xFC000000L 7661 //DAGB4_WRCLI11 7662 #define DAGB4_WRCLI11__VIRT_CHAN__SHIFT 0x0 7663 #define DAGB4_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 7664 #define DAGB4_WRCLI11__URG_HIGH__SHIFT 0x4 7665 #define DAGB4_WRCLI11__URG_LOW__SHIFT 0x8 7666 #define DAGB4_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc 7667 #define DAGB4_WRCLI11__MAX_BW__SHIFT 0xd 7668 #define DAGB4_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 7669 #define DAGB4_WRCLI11__MIN_BW__SHIFT 0x16 7670 #define DAGB4_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 7671 #define DAGB4_WRCLI11__MAX_OSD__SHIFT 0x1a 7672 #define DAGB4_WRCLI11__VIRT_CHAN_MASK 0x00000007L 7673 #define DAGB4_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 7674 #define DAGB4_WRCLI11__URG_HIGH_MASK 0x000000F0L 7675 #define DAGB4_WRCLI11__URG_LOW_MASK 0x00000F00L 7676 #define DAGB4_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L 7677 #define DAGB4_WRCLI11__MAX_BW_MASK 0x001FE000L 7678 #define DAGB4_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L 7679 #define DAGB4_WRCLI11__MIN_BW_MASK 0x01C00000L 7680 #define DAGB4_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 7681 #define DAGB4_WRCLI11__MAX_OSD_MASK 0xFC000000L 7682 //DAGB4_WRCLI12 7683 #define DAGB4_WRCLI12__VIRT_CHAN__SHIFT 0x0 7684 #define DAGB4_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 7685 #define DAGB4_WRCLI12__URG_HIGH__SHIFT 0x4 7686 #define DAGB4_WRCLI12__URG_LOW__SHIFT 0x8 7687 #define DAGB4_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc 7688 #define DAGB4_WRCLI12__MAX_BW__SHIFT 0xd 7689 #define DAGB4_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 7690 #define DAGB4_WRCLI12__MIN_BW__SHIFT 0x16 7691 #define DAGB4_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 7692 #define DAGB4_WRCLI12__MAX_OSD__SHIFT 0x1a 7693 #define DAGB4_WRCLI12__VIRT_CHAN_MASK 0x00000007L 7694 #define DAGB4_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 7695 #define DAGB4_WRCLI12__URG_HIGH_MASK 0x000000F0L 7696 #define DAGB4_WRCLI12__URG_LOW_MASK 0x00000F00L 7697 #define DAGB4_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L 7698 #define DAGB4_WRCLI12__MAX_BW_MASK 0x001FE000L 7699 #define DAGB4_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L 7700 #define DAGB4_WRCLI12__MIN_BW_MASK 0x01C00000L 7701 #define DAGB4_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 7702 #define DAGB4_WRCLI12__MAX_OSD_MASK 0xFC000000L 7703 //DAGB4_WRCLI13 7704 #define DAGB4_WRCLI13__VIRT_CHAN__SHIFT 0x0 7705 #define DAGB4_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 7706 #define DAGB4_WRCLI13__URG_HIGH__SHIFT 0x4 7707 #define DAGB4_WRCLI13__URG_LOW__SHIFT 0x8 7708 #define DAGB4_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc 7709 #define DAGB4_WRCLI13__MAX_BW__SHIFT 0xd 7710 #define DAGB4_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 7711 #define DAGB4_WRCLI13__MIN_BW__SHIFT 0x16 7712 #define DAGB4_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 7713 #define DAGB4_WRCLI13__MAX_OSD__SHIFT 0x1a 7714 #define DAGB4_WRCLI13__VIRT_CHAN_MASK 0x00000007L 7715 #define DAGB4_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 7716 #define DAGB4_WRCLI13__URG_HIGH_MASK 0x000000F0L 7717 #define DAGB4_WRCLI13__URG_LOW_MASK 0x00000F00L 7718 #define DAGB4_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L 7719 #define DAGB4_WRCLI13__MAX_BW_MASK 0x001FE000L 7720 #define DAGB4_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L 7721 #define DAGB4_WRCLI13__MIN_BW_MASK 0x01C00000L 7722 #define DAGB4_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 7723 #define DAGB4_WRCLI13__MAX_OSD_MASK 0xFC000000L 7724 //DAGB4_WRCLI14 7725 #define DAGB4_WRCLI14__VIRT_CHAN__SHIFT 0x0 7726 #define DAGB4_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 7727 #define DAGB4_WRCLI14__URG_HIGH__SHIFT 0x4 7728 #define DAGB4_WRCLI14__URG_LOW__SHIFT 0x8 7729 #define DAGB4_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc 7730 #define DAGB4_WRCLI14__MAX_BW__SHIFT 0xd 7731 #define DAGB4_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 7732 #define DAGB4_WRCLI14__MIN_BW__SHIFT 0x16 7733 #define DAGB4_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 7734 #define DAGB4_WRCLI14__MAX_OSD__SHIFT 0x1a 7735 #define DAGB4_WRCLI14__VIRT_CHAN_MASK 0x00000007L 7736 #define DAGB4_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 7737 #define DAGB4_WRCLI14__URG_HIGH_MASK 0x000000F0L 7738 #define DAGB4_WRCLI14__URG_LOW_MASK 0x00000F00L 7739 #define DAGB4_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L 7740 #define DAGB4_WRCLI14__MAX_BW_MASK 0x001FE000L 7741 #define DAGB4_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L 7742 #define DAGB4_WRCLI14__MIN_BW_MASK 0x01C00000L 7743 #define DAGB4_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 7744 #define DAGB4_WRCLI14__MAX_OSD_MASK 0xFC000000L 7745 //DAGB4_WRCLI15 7746 #define DAGB4_WRCLI15__VIRT_CHAN__SHIFT 0x0 7747 #define DAGB4_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 7748 #define DAGB4_WRCLI15__URG_HIGH__SHIFT 0x4 7749 #define DAGB4_WRCLI15__URG_LOW__SHIFT 0x8 7750 #define DAGB4_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc 7751 #define DAGB4_WRCLI15__MAX_BW__SHIFT 0xd 7752 #define DAGB4_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 7753 #define DAGB4_WRCLI15__MIN_BW__SHIFT 0x16 7754 #define DAGB4_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 7755 #define DAGB4_WRCLI15__MAX_OSD__SHIFT 0x1a 7756 #define DAGB4_WRCLI15__VIRT_CHAN_MASK 0x00000007L 7757 #define DAGB4_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 7758 #define DAGB4_WRCLI15__URG_HIGH_MASK 0x000000F0L 7759 #define DAGB4_WRCLI15__URG_LOW_MASK 0x00000F00L 7760 #define DAGB4_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L 7761 #define DAGB4_WRCLI15__MAX_BW_MASK 0x001FE000L 7762 #define DAGB4_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L 7763 #define DAGB4_WRCLI15__MIN_BW_MASK 0x01C00000L 7764 #define DAGB4_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 7765 #define DAGB4_WRCLI15__MAX_OSD_MASK 0xFC000000L 7766 //DAGB4_WR_CNTL 7767 #define DAGB4_WR_CNTL__SCLK_FREQ__SHIFT 0x0 7768 #define DAGB4_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 7769 #define DAGB4_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 7770 #define DAGB4_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 7771 #define DAGB4_WR_CNTL__IO_LEVEL__SHIFT 0x11 7772 #define DAGB4_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 7773 #define DAGB4_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 7774 #define DAGB4_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL 7775 #define DAGB4_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 7776 #define DAGB4_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 7777 #define DAGB4_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 7778 #define DAGB4_WR_CNTL__IO_LEVEL_MASK 0x000E0000L 7779 #define DAGB4_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 7780 #define DAGB4_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L 7781 //DAGB4_WR_GMI_CNTL 7782 #define DAGB4_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 7783 #define DAGB4_WR_GMI_CNTL__LEVEL__SHIFT 0x6 7784 #define DAGB4_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 7785 #define DAGB4_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 7786 #define DAGB4_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 7787 #define DAGB4_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L 7788 #define DAGB4_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 7789 #define DAGB4_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 7790 //DAGB4_WR_ADDR_DAGB 7791 #define DAGB4_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 7792 #define DAGB4_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 7793 #define DAGB4_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 7794 #define DAGB4_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 7795 #define DAGB4_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 7796 #define DAGB4_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 7797 #define DAGB4_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 7798 #define DAGB4_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 7799 //DAGB4_WR_OUTPUT_DAGB_MAX_BURST 7800 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 7801 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 7802 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 7803 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 7804 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 7805 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 7806 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 7807 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 7808 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 7809 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 7810 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 7811 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 7812 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 7813 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 7814 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 7815 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 7816 //DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER 7817 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 7818 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 7819 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 7820 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 7821 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 7822 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 7823 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 7824 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 7825 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 7826 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 7827 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 7828 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 7829 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 7830 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 7831 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 7832 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 7833 //DAGB4_WR_CGTT_CLK_CTRL 7834 #define DAGB4_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 7835 #define DAGB4_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 7836 #define DAGB4_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 7837 #define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 7838 #define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 7839 #define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 7840 #define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 7841 #define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 7842 #define DAGB4_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 7843 #define DAGB4_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 7844 #define DAGB4_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 7845 #define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 7846 #define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 7847 #define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 7848 #define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 7849 #define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 7850 //DAGB4_L1TLB_WR_CGTT_CLK_CTRL 7851 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 7852 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 7853 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 7854 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 7855 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 7856 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 7857 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 7858 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 7859 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 7860 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 7861 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 7862 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 7863 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 7864 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 7865 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 7866 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 7867 //DAGB4_ATCVM_WR_CGTT_CLK_CTRL 7868 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 7869 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 7870 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 7871 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 7872 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 7873 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 7874 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 7875 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 7876 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 7877 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 7878 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 7879 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 7880 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 7881 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 7882 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 7883 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 7884 //DAGB4_WR_ADDR_DAGB_MAX_BURST0 7885 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 7886 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 7887 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 7888 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 7889 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 7890 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 7891 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 7892 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 7893 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 7894 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 7895 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 7896 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 7897 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 7898 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 7899 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 7900 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 7901 //DAGB4_WR_ADDR_DAGB_LAZY_TIMER0 7902 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 7903 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 7904 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 7905 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 7906 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 7907 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 7908 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 7909 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 7910 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 7911 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 7912 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 7913 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 7914 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 7915 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 7916 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 7917 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 7918 //DAGB4_WR_ADDR_DAGB_MAX_BURST1 7919 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 7920 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 7921 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 7922 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 7923 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 7924 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 7925 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 7926 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 7927 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 7928 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 7929 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 7930 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 7931 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 7932 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 7933 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 7934 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 7935 //DAGB4_WR_ADDR_DAGB_LAZY_TIMER1 7936 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 7937 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 7938 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 7939 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 7940 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 7941 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 7942 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 7943 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 7944 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 7945 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 7946 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 7947 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 7948 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 7949 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 7950 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 7951 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 7952 //DAGB4_WR_DATA_DAGB 7953 #define DAGB4_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 7954 #define DAGB4_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 7955 #define DAGB4_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 7956 #define DAGB4_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 7957 #define DAGB4_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L 7958 #define DAGB4_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 7959 #define DAGB4_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 7960 #define DAGB4_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L 7961 //DAGB4_WR_DATA_DAGB_MAX_BURST0 7962 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 7963 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 7964 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 7965 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 7966 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 7967 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 7968 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 7969 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 7970 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 7971 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 7972 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 7973 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 7974 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 7975 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 7976 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 7977 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 7978 //DAGB4_WR_DATA_DAGB_LAZY_TIMER0 7979 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 7980 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 7981 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 7982 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 7983 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 7984 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 7985 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 7986 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 7987 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 7988 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 7989 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 7990 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 7991 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 7992 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 7993 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 7994 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 7995 //DAGB4_WR_DATA_DAGB_MAX_BURST1 7996 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 7997 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 7998 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 7999 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 8000 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 8001 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 8002 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 8003 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 8004 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 8005 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 8006 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 8007 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 8008 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 8009 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 8010 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 8011 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 8012 //DAGB4_WR_DATA_DAGB_LAZY_TIMER1 8013 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 8014 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 8015 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 8016 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 8017 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 8018 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 8019 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 8020 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 8021 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 8022 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 8023 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 8024 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 8025 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 8026 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 8027 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 8028 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 8029 //DAGB4_WR_VC0_CNTL 8030 #define DAGB4_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 8031 #define DAGB4_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 8032 #define DAGB4_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 8033 #define DAGB4_WR_VC0_CNTL__MAX_BW__SHIFT 0xc 8034 #define DAGB4_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 8035 #define DAGB4_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 8036 #define DAGB4_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 8037 #define DAGB4_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 8038 #define DAGB4_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 8039 #define DAGB4_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 8040 #define DAGB4_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 8041 #define DAGB4_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L 8042 #define DAGB4_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 8043 #define DAGB4_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L 8044 #define DAGB4_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 8045 #define DAGB4_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 8046 //DAGB4_WR_VC1_CNTL 8047 #define DAGB4_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 8048 #define DAGB4_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 8049 #define DAGB4_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 8050 #define DAGB4_WR_VC1_CNTL__MAX_BW__SHIFT 0xc 8051 #define DAGB4_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 8052 #define DAGB4_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 8053 #define DAGB4_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 8054 #define DAGB4_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 8055 #define DAGB4_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 8056 #define DAGB4_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 8057 #define DAGB4_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 8058 #define DAGB4_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L 8059 #define DAGB4_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 8060 #define DAGB4_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L 8061 #define DAGB4_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 8062 #define DAGB4_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 8063 //DAGB4_WR_VC2_CNTL 8064 #define DAGB4_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 8065 #define DAGB4_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 8066 #define DAGB4_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 8067 #define DAGB4_WR_VC2_CNTL__MAX_BW__SHIFT 0xc 8068 #define DAGB4_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 8069 #define DAGB4_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 8070 #define DAGB4_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 8071 #define DAGB4_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 8072 #define DAGB4_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 8073 #define DAGB4_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 8074 #define DAGB4_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 8075 #define DAGB4_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L 8076 #define DAGB4_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 8077 #define DAGB4_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L 8078 #define DAGB4_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 8079 #define DAGB4_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 8080 //DAGB4_WR_VC3_CNTL 8081 #define DAGB4_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 8082 #define DAGB4_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 8083 #define DAGB4_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 8084 #define DAGB4_WR_VC3_CNTL__MAX_BW__SHIFT 0xc 8085 #define DAGB4_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 8086 #define DAGB4_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 8087 #define DAGB4_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 8088 #define DAGB4_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 8089 #define DAGB4_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 8090 #define DAGB4_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 8091 #define DAGB4_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 8092 #define DAGB4_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L 8093 #define DAGB4_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 8094 #define DAGB4_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L 8095 #define DAGB4_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 8096 #define DAGB4_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 8097 //DAGB4_WR_VC4_CNTL 8098 #define DAGB4_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 8099 #define DAGB4_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 8100 #define DAGB4_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 8101 #define DAGB4_WR_VC4_CNTL__MAX_BW__SHIFT 0xc 8102 #define DAGB4_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 8103 #define DAGB4_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 8104 #define DAGB4_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 8105 #define DAGB4_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 8106 #define DAGB4_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 8107 #define DAGB4_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 8108 #define DAGB4_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 8109 #define DAGB4_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L 8110 #define DAGB4_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 8111 #define DAGB4_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L 8112 #define DAGB4_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 8113 #define DAGB4_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 8114 //DAGB4_WR_VC5_CNTL 8115 #define DAGB4_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 8116 #define DAGB4_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 8117 #define DAGB4_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 8118 #define DAGB4_WR_VC5_CNTL__MAX_BW__SHIFT 0xc 8119 #define DAGB4_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 8120 #define DAGB4_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 8121 #define DAGB4_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 8122 #define DAGB4_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 8123 #define DAGB4_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 8124 #define DAGB4_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 8125 #define DAGB4_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 8126 #define DAGB4_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L 8127 #define DAGB4_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 8128 #define DAGB4_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L 8129 #define DAGB4_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 8130 #define DAGB4_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 8131 //DAGB4_WR_VC6_CNTL 8132 #define DAGB4_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 8133 #define DAGB4_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 8134 #define DAGB4_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 8135 #define DAGB4_WR_VC6_CNTL__MAX_BW__SHIFT 0xc 8136 #define DAGB4_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 8137 #define DAGB4_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 8138 #define DAGB4_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 8139 #define DAGB4_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 8140 #define DAGB4_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 8141 #define DAGB4_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 8142 #define DAGB4_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 8143 #define DAGB4_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L 8144 #define DAGB4_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 8145 #define DAGB4_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L 8146 #define DAGB4_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 8147 #define DAGB4_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 8148 //DAGB4_WR_VC7_CNTL 8149 #define DAGB4_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 8150 #define DAGB4_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 8151 #define DAGB4_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 8152 #define DAGB4_WR_VC7_CNTL__MAX_BW__SHIFT 0xc 8153 #define DAGB4_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 8154 #define DAGB4_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 8155 #define DAGB4_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 8156 #define DAGB4_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 8157 #define DAGB4_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 8158 #define DAGB4_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 8159 #define DAGB4_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 8160 #define DAGB4_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L 8161 #define DAGB4_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 8162 #define DAGB4_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L 8163 #define DAGB4_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 8164 #define DAGB4_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 8165 //DAGB4_WR_CNTL_MISC 8166 #define DAGB4_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 8167 #define DAGB4_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 8168 #define DAGB4_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 8169 #define DAGB4_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 8170 #define DAGB4_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 8171 #define DAGB4_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 8172 #define DAGB4_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a 8173 #define DAGB4_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 8174 #define DAGB4_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 8175 #define DAGB4_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 8176 #define DAGB4_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 8177 #define DAGB4_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 8178 #define DAGB4_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 8179 #define DAGB4_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L 8180 //DAGB4_WR_TLB_CREDIT 8181 #define DAGB4_WR_TLB_CREDIT__TLB0__SHIFT 0x0 8182 #define DAGB4_WR_TLB_CREDIT__TLB1__SHIFT 0x5 8183 #define DAGB4_WR_TLB_CREDIT__TLB2__SHIFT 0xa 8184 #define DAGB4_WR_TLB_CREDIT__TLB3__SHIFT 0xf 8185 #define DAGB4_WR_TLB_CREDIT__TLB4__SHIFT 0x14 8186 #define DAGB4_WR_TLB_CREDIT__TLB5__SHIFT 0x19 8187 #define DAGB4_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL 8188 #define DAGB4_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L 8189 #define DAGB4_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L 8190 #define DAGB4_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L 8191 #define DAGB4_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L 8192 #define DAGB4_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L 8193 //DAGB4_WR_DATA_CREDIT 8194 #define DAGB4_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 8195 #define DAGB4_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 8196 #define DAGB4_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 8197 #define DAGB4_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 8198 #define DAGB4_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL 8199 #define DAGB4_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L 8200 #define DAGB4_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L 8201 #define DAGB4_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L 8202 //DAGB4_WR_MISC_CREDIT 8203 #define DAGB4_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 8204 #define DAGB4_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 8205 #define DAGB4_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 8206 #define DAGB4_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 8207 #define DAGB4_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL 8208 #define DAGB4_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L 8209 #define DAGB4_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L 8210 #define DAGB4_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L 8211 //DAGB4_WRCLI_ASK_PENDING 8212 #define DAGB4_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 8213 #define DAGB4_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 8214 //DAGB4_WRCLI_GO_PENDING 8215 #define DAGB4_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 8216 #define DAGB4_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 8217 //DAGB4_WRCLI_GBLSEND_PENDING 8218 #define DAGB4_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 8219 #define DAGB4_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 8220 //DAGB4_WRCLI_TLB_PENDING 8221 #define DAGB4_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 8222 #define DAGB4_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 8223 //DAGB4_WRCLI_OARB_PENDING 8224 #define DAGB4_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 8225 #define DAGB4_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 8226 //DAGB4_WRCLI_OSD_PENDING 8227 #define DAGB4_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 8228 #define DAGB4_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 8229 //DAGB4_WRCLI_DBUS_ASK_PENDING 8230 #define DAGB4_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 8231 #define DAGB4_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 8232 //DAGB4_WRCLI_DBUS_GO_PENDING 8233 #define DAGB4_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 8234 #define DAGB4_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 8235 //DAGB4_DAGB_DLY 8236 #define DAGB4_DAGB_DLY__DLY__SHIFT 0x0 8237 #define DAGB4_DAGB_DLY__CLI__SHIFT 0x8 8238 #define DAGB4_DAGB_DLY__POS__SHIFT 0x10 8239 #define DAGB4_DAGB_DLY__DLY_MASK 0x000000FFL 8240 #define DAGB4_DAGB_DLY__CLI_MASK 0x0000FF00L 8241 #define DAGB4_DAGB_DLY__POS_MASK 0x000F0000L 8242 //DAGB4_CNTL_MISC 8243 #define DAGB4_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 8244 #define DAGB4_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 8245 #define DAGB4_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 8246 #define DAGB4_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 8247 #define DAGB4_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc 8248 #define DAGB4_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf 8249 #define DAGB4_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 8250 #define DAGB4_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 8251 #define DAGB4_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 8252 #define DAGB4_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e 8253 #define DAGB4_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L 8254 #define DAGB4_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L 8255 #define DAGB4_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L 8256 #define DAGB4_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L 8257 #define DAGB4_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L 8258 #define DAGB4_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L 8259 #define DAGB4_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L 8260 #define DAGB4_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L 8261 #define DAGB4_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L 8262 #define DAGB4_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L 8263 //DAGB4_CNTL_MISC2 8264 #define DAGB4_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 8265 #define DAGB4_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 8266 #define DAGB4_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 8267 #define DAGB4_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 8268 #define DAGB4_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 8269 #define DAGB4_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 8270 #define DAGB4_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 8271 #define DAGB4_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 8272 #define DAGB4_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 8273 #define DAGB4_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 8274 #define DAGB4_CNTL_MISC2__SWAP_CTL__SHIFT 0xa 8275 #define DAGB4_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xb 8276 #define DAGB4_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x11 8277 #define DAGB4_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L 8278 #define DAGB4_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L 8279 #define DAGB4_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L 8280 #define DAGB4_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L 8281 #define DAGB4_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L 8282 #define DAGB4_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L 8283 #define DAGB4_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L 8284 #define DAGB4_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L 8285 #define DAGB4_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L 8286 #define DAGB4_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L 8287 #define DAGB4_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L 8288 #define DAGB4_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000800L 8289 #define DAGB4_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x007E0000L 8290 //DAGB4_FIFO_EMPTY 8291 #define DAGB4_FIFO_EMPTY__EMPTY__SHIFT 0x0 8292 #define DAGB4_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL 8293 //DAGB4_FIFO_FULL 8294 #define DAGB4_FIFO_FULL__FULL__SHIFT 0x0 8295 #define DAGB4_FIFO_FULL__FULL_MASK 0x007FFFFFL 8296 //DAGB4_WR_CREDITS_FULL 8297 #define DAGB4_WR_CREDITS_FULL__FULL__SHIFT 0x0 8298 #define DAGB4_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL 8299 //DAGB4_RD_CREDITS_FULL 8300 #define DAGB4_RD_CREDITS_FULL__FULL__SHIFT 0x0 8301 #define DAGB4_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL 8302 //DAGB4_PERFCOUNTER_LO 8303 #define DAGB4_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 8304 #define DAGB4_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 8305 //DAGB4_PERFCOUNTER_HI 8306 #define DAGB4_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 8307 #define DAGB4_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 8308 #define DAGB4_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 8309 #define DAGB4_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 8310 //DAGB4_PERFCOUNTER0_CFG 8311 #define DAGB4_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 8312 #define DAGB4_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 8313 #define DAGB4_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 8314 #define DAGB4_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 8315 #define DAGB4_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 8316 #define DAGB4_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 8317 #define DAGB4_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 8318 #define DAGB4_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 8319 #define DAGB4_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 8320 #define DAGB4_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 8321 //DAGB4_PERFCOUNTER1_CFG 8322 #define DAGB4_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 8323 #define DAGB4_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 8324 #define DAGB4_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 8325 #define DAGB4_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 8326 #define DAGB4_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 8327 #define DAGB4_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 8328 #define DAGB4_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 8329 #define DAGB4_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 8330 #define DAGB4_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 8331 #define DAGB4_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 8332 //DAGB4_PERFCOUNTER2_CFG 8333 #define DAGB4_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 8334 #define DAGB4_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 8335 #define DAGB4_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 8336 #define DAGB4_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 8337 #define DAGB4_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 8338 #define DAGB4_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 8339 #define DAGB4_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 8340 #define DAGB4_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 8341 #define DAGB4_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 8342 #define DAGB4_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 8343 //DAGB4_PERFCOUNTER_RSLT_CNTL 8344 #define DAGB4_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 8345 #define DAGB4_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 8346 #define DAGB4_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 8347 #define DAGB4_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 8348 #define DAGB4_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 8349 #define DAGB4_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 8350 #define DAGB4_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 8351 #define DAGB4_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 8352 #define DAGB4_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 8353 #define DAGB4_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 8354 #define DAGB4_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 8355 #define DAGB4_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 8356 //DAGB4_RESERVE0 8357 #define DAGB4_RESERVE0__RESERVE__SHIFT 0x0 8358 #define DAGB4_RESERVE0__RESERVE_MASK 0xFFFFFFFFL 8359 //DAGB4_RESERVE1 8360 #define DAGB4_RESERVE1__RESERVE__SHIFT 0x0 8361 #define DAGB4_RESERVE1__RESERVE_MASK 0xFFFFFFFFL 8362 //DAGB4_RESERVE2 8363 #define DAGB4_RESERVE2__RESERVE__SHIFT 0x0 8364 #define DAGB4_RESERVE2__RESERVE_MASK 0xFFFFFFFFL 8365 //DAGB4_RESERVE3 8366 #define DAGB4_RESERVE3__RESERVE__SHIFT 0x0 8367 #define DAGB4_RESERVE3__RESERVE_MASK 0xFFFFFFFFL 8368 //DAGB4_RESERVE4 8369 #define DAGB4_RESERVE4__RESERVE__SHIFT 0x0 8370 #define DAGB4_RESERVE4__RESERVE_MASK 0xFFFFFFFFL 8371 //DAGB4_RESERVE5 8372 #define DAGB4_RESERVE5__RESERVE__SHIFT 0x0 8373 #define DAGB4_RESERVE5__RESERVE_MASK 0xFFFFFFFFL 8374 //DAGB4_RESERVE6 8375 #define DAGB4_RESERVE6__RESERVE__SHIFT 0x0 8376 #define DAGB4_RESERVE6__RESERVE_MASK 0xFFFFFFFFL 8377 //DAGB4_RESERVE7 8378 #define DAGB4_RESERVE7__RESERVE__SHIFT 0x0 8379 #define DAGB4_RESERVE7__RESERVE_MASK 0xFFFFFFFFL 8380 //DAGB4_RESERVE8 8381 #define DAGB4_RESERVE8__RESERVE__SHIFT 0x0 8382 #define DAGB4_RESERVE8__RESERVE_MASK 0xFFFFFFFFL 8383 //DAGB4_RESERVE9 8384 #define DAGB4_RESERVE9__RESERVE__SHIFT 0x0 8385 #define DAGB4_RESERVE9__RESERVE_MASK 0xFFFFFFFFL 8386 //DAGB4_RESERVE10 8387 #define DAGB4_RESERVE10__RESERVE__SHIFT 0x0 8388 #define DAGB4_RESERVE10__RESERVE_MASK 0xFFFFFFFFL 8389 //DAGB4_RESERVE11 8390 #define DAGB4_RESERVE11__RESERVE__SHIFT 0x0 8391 #define DAGB4_RESERVE11__RESERVE_MASK 0xFFFFFFFFL 8392 //DAGB4_RESERVE12 8393 #define DAGB4_RESERVE12__RESERVE__SHIFT 0x0 8394 #define DAGB4_RESERVE12__RESERVE_MASK 0xFFFFFFFFL 8395 //DAGB4_RESERVE13 8396 #define DAGB4_RESERVE13__RESERVE__SHIFT 0x0 8397 #define DAGB4_RESERVE13__RESERVE_MASK 0xFFFFFFFFL 8398 8399 8400 // addressBlock: mmhub_ea_mmeadec0 8401 //MMEA0_DRAM_RD_CLI2GRP_MAP0 8402 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 8403 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 8404 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 8405 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 8406 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 8407 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 8408 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 8409 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 8410 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 8411 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 8412 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 8413 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 8414 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 8415 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 8416 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 8417 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 8418 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 8419 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 8420 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 8421 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 8422 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 8423 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 8424 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 8425 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 8426 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 8427 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 8428 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 8429 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 8430 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 8431 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 8432 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 8433 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 8434 //MMEA0_DRAM_RD_CLI2GRP_MAP1 8435 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 8436 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 8437 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 8438 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 8439 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 8440 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 8441 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 8442 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 8443 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 8444 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 8445 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 8446 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 8447 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 8448 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 8449 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 8450 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 8451 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 8452 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 8453 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 8454 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 8455 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 8456 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 8457 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 8458 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 8459 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 8460 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 8461 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 8462 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 8463 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 8464 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 8465 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 8466 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 8467 //MMEA0_DRAM_WR_CLI2GRP_MAP0 8468 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 8469 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 8470 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 8471 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 8472 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 8473 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 8474 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 8475 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 8476 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 8477 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 8478 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 8479 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 8480 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 8481 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 8482 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 8483 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 8484 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 8485 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 8486 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 8487 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 8488 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 8489 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 8490 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 8491 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 8492 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 8493 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 8494 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 8495 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 8496 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 8497 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 8498 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 8499 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 8500 //MMEA0_DRAM_WR_CLI2GRP_MAP1 8501 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 8502 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 8503 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 8504 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 8505 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 8506 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 8507 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 8508 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 8509 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 8510 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 8511 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 8512 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 8513 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 8514 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 8515 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 8516 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 8517 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 8518 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 8519 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 8520 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 8521 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 8522 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 8523 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 8524 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 8525 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 8526 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 8527 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 8528 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 8529 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 8530 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 8531 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 8532 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 8533 //MMEA0_DRAM_RD_GRP2VC_MAP 8534 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 8535 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 8536 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 8537 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 8538 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 8539 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 8540 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 8541 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 8542 //MMEA0_DRAM_WR_GRP2VC_MAP 8543 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 8544 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 8545 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 8546 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 8547 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 8548 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 8549 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 8550 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 8551 //MMEA0_DRAM_RD_LAZY 8552 #define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 8553 #define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 8554 #define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 8555 #define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 8556 #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 8557 #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 8558 #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 8559 #define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L 8560 #define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L 8561 #define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L 8562 #define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L 8563 #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 8564 #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 8565 #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 8566 //MMEA0_DRAM_WR_LAZY 8567 #define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 8568 #define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 8569 #define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 8570 #define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 8571 #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 8572 #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 8573 #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 8574 #define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L 8575 #define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L 8576 #define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L 8577 #define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L 8578 #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 8579 #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 8580 #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 8581 //MMEA0_DRAM_RD_CAM_CNTL 8582 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 8583 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 8584 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 8585 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 8586 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 8587 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 8588 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 8589 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 8590 #define MMEA0_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 8591 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 8592 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 8593 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 8594 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 8595 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 8596 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 8597 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 8598 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 8599 #define MMEA0_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 8600 //MMEA0_DRAM_WR_CAM_CNTL 8601 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 8602 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 8603 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 8604 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 8605 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 8606 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 8607 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 8608 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 8609 #define MMEA0_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 8610 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 8611 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 8612 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 8613 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 8614 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 8615 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 8616 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 8617 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 8618 #define MMEA0_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 8619 //MMEA0_DRAM_PAGE_BURST 8620 #define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 8621 #define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 8622 #define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 8623 #define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 8624 #define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL 8625 #define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 8626 #define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 8627 #define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L 8628 //MMEA0_DRAM_RD_PRI_AGE 8629 #define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 8630 #define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 8631 #define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 8632 #define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 8633 #define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 8634 #define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 8635 #define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 8636 #define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 8637 #define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 8638 #define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 8639 #define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 8640 #define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 8641 #define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 8642 #define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 8643 #define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 8644 #define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 8645 //MMEA0_DRAM_WR_PRI_AGE 8646 #define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 8647 #define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 8648 #define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 8649 #define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 8650 #define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 8651 #define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 8652 #define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 8653 #define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 8654 #define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 8655 #define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 8656 #define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 8657 #define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 8658 #define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 8659 #define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 8660 #define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 8661 #define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 8662 //MMEA0_DRAM_RD_PRI_QUEUING 8663 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 8664 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 8665 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 8666 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 8667 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 8668 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 8669 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 8670 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 8671 //MMEA0_DRAM_WR_PRI_QUEUING 8672 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 8673 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 8674 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 8675 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 8676 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 8677 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 8678 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 8679 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 8680 //MMEA0_DRAM_RD_PRI_FIXED 8681 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 8682 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 8683 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 8684 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 8685 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 8686 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 8687 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 8688 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 8689 //MMEA0_DRAM_WR_PRI_FIXED 8690 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 8691 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 8692 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 8693 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 8694 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 8695 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 8696 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 8697 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 8698 //MMEA0_DRAM_RD_PRI_URGENCY 8699 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 8700 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 8701 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 8702 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 8703 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 8704 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 8705 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 8706 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 8707 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 8708 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 8709 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 8710 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 8711 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 8712 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 8713 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 8714 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 8715 //MMEA0_DRAM_WR_PRI_URGENCY 8716 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 8717 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 8718 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 8719 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 8720 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 8721 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 8722 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 8723 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 8724 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 8725 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 8726 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 8727 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 8728 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 8729 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 8730 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 8731 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 8732 //MMEA0_DRAM_RD_PRI_QUANT_PRI1 8733 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 8734 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 8735 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 8736 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 8737 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 8738 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 8739 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 8740 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 8741 //MMEA0_DRAM_RD_PRI_QUANT_PRI2 8742 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 8743 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 8744 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 8745 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 8746 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 8747 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 8748 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 8749 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 8750 //MMEA0_DRAM_RD_PRI_QUANT_PRI3 8751 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 8752 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 8753 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 8754 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 8755 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 8756 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 8757 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 8758 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 8759 //MMEA0_DRAM_WR_PRI_QUANT_PRI1 8760 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 8761 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 8762 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 8763 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 8764 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 8765 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 8766 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 8767 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 8768 //MMEA0_DRAM_WR_PRI_QUANT_PRI2 8769 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 8770 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 8771 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 8772 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 8773 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 8774 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 8775 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 8776 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 8777 //MMEA0_DRAM_WR_PRI_QUANT_PRI3 8778 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 8779 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 8780 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 8781 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 8782 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 8783 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 8784 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 8785 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 8786 //MMEA0_GMI_RD_CLI2GRP_MAP0 8787 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 8788 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 8789 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 8790 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 8791 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 8792 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 8793 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 8794 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 8795 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 8796 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 8797 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 8798 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 8799 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 8800 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 8801 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 8802 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 8803 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 8804 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 8805 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 8806 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 8807 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 8808 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 8809 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 8810 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 8811 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 8812 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 8813 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 8814 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 8815 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 8816 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 8817 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 8818 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 8819 //MMEA0_GMI_RD_CLI2GRP_MAP1 8820 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 8821 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 8822 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 8823 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 8824 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 8825 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 8826 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 8827 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 8828 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 8829 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 8830 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 8831 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 8832 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 8833 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 8834 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 8835 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 8836 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 8837 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 8838 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 8839 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 8840 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 8841 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 8842 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 8843 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 8844 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 8845 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 8846 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 8847 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 8848 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 8849 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 8850 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 8851 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 8852 //MMEA0_GMI_WR_CLI2GRP_MAP0 8853 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 8854 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 8855 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 8856 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 8857 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 8858 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 8859 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 8860 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 8861 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 8862 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 8863 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 8864 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 8865 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 8866 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 8867 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 8868 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 8869 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 8870 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 8871 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 8872 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 8873 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 8874 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 8875 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 8876 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 8877 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 8878 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 8879 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 8880 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 8881 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 8882 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 8883 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 8884 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 8885 //MMEA0_GMI_WR_CLI2GRP_MAP1 8886 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 8887 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 8888 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 8889 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 8890 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 8891 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 8892 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 8893 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 8894 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 8895 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 8896 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 8897 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 8898 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 8899 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 8900 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 8901 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 8902 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 8903 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 8904 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 8905 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 8906 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 8907 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 8908 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 8909 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 8910 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 8911 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 8912 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 8913 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 8914 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 8915 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 8916 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 8917 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 8918 //MMEA0_GMI_RD_GRP2VC_MAP 8919 #define MMEA0_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 8920 #define MMEA0_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 8921 #define MMEA0_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 8922 #define MMEA0_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 8923 #define MMEA0_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 8924 #define MMEA0_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 8925 #define MMEA0_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 8926 #define MMEA0_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 8927 //MMEA0_GMI_WR_GRP2VC_MAP 8928 #define MMEA0_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 8929 #define MMEA0_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 8930 #define MMEA0_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 8931 #define MMEA0_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 8932 #define MMEA0_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 8933 #define MMEA0_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 8934 #define MMEA0_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 8935 #define MMEA0_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 8936 //MMEA0_GMI_RD_LAZY 8937 #define MMEA0_GMI_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 8938 #define MMEA0_GMI_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 8939 #define MMEA0_GMI_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 8940 #define MMEA0_GMI_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 8941 #define MMEA0_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 8942 #define MMEA0_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 8943 #define MMEA0_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 8944 #define MMEA0_GMI_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L 8945 #define MMEA0_GMI_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L 8946 #define MMEA0_GMI_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L 8947 #define MMEA0_GMI_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L 8948 #define MMEA0_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 8949 #define MMEA0_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 8950 #define MMEA0_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 8951 //MMEA0_GMI_WR_LAZY 8952 #define MMEA0_GMI_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 8953 #define MMEA0_GMI_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 8954 #define MMEA0_GMI_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 8955 #define MMEA0_GMI_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 8956 #define MMEA0_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 8957 #define MMEA0_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 8958 #define MMEA0_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 8959 #define MMEA0_GMI_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L 8960 #define MMEA0_GMI_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L 8961 #define MMEA0_GMI_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L 8962 #define MMEA0_GMI_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L 8963 #define MMEA0_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 8964 #define MMEA0_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 8965 #define MMEA0_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 8966 //MMEA0_GMI_RD_CAM_CNTL 8967 #define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 8968 #define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 8969 #define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 8970 #define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 8971 #define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 8972 #define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 8973 #define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 8974 #define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 8975 #define MMEA0_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 8976 #define MMEA0_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d 8977 #define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 8978 #define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 8979 #define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 8980 #define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 8981 #define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 8982 #define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 8983 #define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 8984 #define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 8985 #define MMEA0_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 8986 #define MMEA0_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L 8987 //MMEA0_GMI_WR_CAM_CNTL 8988 #define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 8989 #define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 8990 #define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 8991 #define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 8992 #define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 8993 #define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 8994 #define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 8995 #define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 8996 #define MMEA0_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 8997 #define MMEA0_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d 8998 #define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 8999 #define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 9000 #define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 9001 #define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 9002 #define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 9003 #define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 9004 #define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 9005 #define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 9006 #define MMEA0_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 9007 #define MMEA0_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L 9008 //MMEA0_GMI_PAGE_BURST 9009 #define MMEA0_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 9010 #define MMEA0_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 9011 #define MMEA0_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 9012 #define MMEA0_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 9013 #define MMEA0_GMI_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL 9014 #define MMEA0_GMI_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 9015 #define MMEA0_GMI_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 9016 #define MMEA0_GMI_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L 9017 //MMEA0_GMI_RD_PRI_AGE 9018 #define MMEA0_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 9019 #define MMEA0_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 9020 #define MMEA0_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 9021 #define MMEA0_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 9022 #define MMEA0_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 9023 #define MMEA0_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 9024 #define MMEA0_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 9025 #define MMEA0_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 9026 #define MMEA0_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 9027 #define MMEA0_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 9028 #define MMEA0_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 9029 #define MMEA0_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 9030 #define MMEA0_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 9031 #define MMEA0_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 9032 #define MMEA0_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 9033 #define MMEA0_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 9034 //MMEA0_GMI_WR_PRI_AGE 9035 #define MMEA0_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 9036 #define MMEA0_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 9037 #define MMEA0_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 9038 #define MMEA0_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 9039 #define MMEA0_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 9040 #define MMEA0_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 9041 #define MMEA0_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 9042 #define MMEA0_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 9043 #define MMEA0_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 9044 #define MMEA0_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 9045 #define MMEA0_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 9046 #define MMEA0_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 9047 #define MMEA0_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 9048 #define MMEA0_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 9049 #define MMEA0_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 9050 #define MMEA0_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 9051 //MMEA0_GMI_RD_PRI_QUEUING 9052 #define MMEA0_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 9053 #define MMEA0_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 9054 #define MMEA0_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 9055 #define MMEA0_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 9056 #define MMEA0_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 9057 #define MMEA0_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 9058 #define MMEA0_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 9059 #define MMEA0_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 9060 //MMEA0_GMI_WR_PRI_QUEUING 9061 #define MMEA0_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 9062 #define MMEA0_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 9063 #define MMEA0_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 9064 #define MMEA0_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 9065 #define MMEA0_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 9066 #define MMEA0_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 9067 #define MMEA0_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 9068 #define MMEA0_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 9069 //MMEA0_GMI_RD_PRI_FIXED 9070 #define MMEA0_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 9071 #define MMEA0_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 9072 #define MMEA0_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 9073 #define MMEA0_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 9074 #define MMEA0_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 9075 #define MMEA0_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 9076 #define MMEA0_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 9077 #define MMEA0_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 9078 //MMEA0_GMI_WR_PRI_FIXED 9079 #define MMEA0_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 9080 #define MMEA0_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 9081 #define MMEA0_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 9082 #define MMEA0_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 9083 #define MMEA0_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 9084 #define MMEA0_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 9085 #define MMEA0_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 9086 #define MMEA0_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 9087 //MMEA0_GMI_RD_PRI_URGENCY 9088 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 9089 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 9090 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 9091 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 9092 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 9093 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 9094 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 9095 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 9096 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 9097 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 9098 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 9099 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 9100 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 9101 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 9102 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 9103 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 9104 //MMEA0_GMI_WR_PRI_URGENCY 9105 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 9106 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 9107 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 9108 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 9109 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 9110 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 9111 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 9112 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 9113 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 9114 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 9115 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 9116 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 9117 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 9118 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 9119 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 9120 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 9121 //MMEA0_GMI_RD_PRI_URGENCY_MASKING 9122 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 9123 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 9124 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 9125 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 9126 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 9127 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 9128 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 9129 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 9130 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 9131 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 9132 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 9133 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 9134 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 9135 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 9136 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 9137 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 9138 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 9139 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 9140 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 9141 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 9142 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 9143 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 9144 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 9145 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 9146 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 9147 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 9148 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 9149 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 9150 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 9151 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 9152 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 9153 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 9154 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 9155 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 9156 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 9157 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 9158 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 9159 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 9160 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 9161 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 9162 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 9163 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 9164 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 9165 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 9166 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 9167 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 9168 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 9169 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 9170 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 9171 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 9172 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 9173 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 9174 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 9175 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 9176 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 9177 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 9178 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 9179 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 9180 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 9181 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 9182 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 9183 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 9184 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 9185 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 9186 //MMEA0_GMI_WR_PRI_URGENCY_MASKING 9187 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 9188 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 9189 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 9190 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 9191 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 9192 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 9193 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 9194 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 9195 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 9196 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 9197 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 9198 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 9199 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 9200 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 9201 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 9202 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 9203 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 9204 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 9205 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 9206 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 9207 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 9208 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 9209 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 9210 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 9211 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 9212 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 9213 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 9214 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 9215 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 9216 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 9217 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 9218 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 9219 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 9220 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 9221 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 9222 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 9223 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 9224 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 9225 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 9226 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 9227 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 9228 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 9229 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 9230 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 9231 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 9232 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 9233 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 9234 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 9235 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 9236 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 9237 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 9238 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 9239 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 9240 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 9241 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 9242 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 9243 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 9244 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 9245 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 9246 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 9247 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 9248 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 9249 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 9250 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 9251 //MMEA0_GMI_RD_PRI_QUANT_PRI1 9252 #define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 9253 #define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 9254 #define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 9255 #define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 9256 #define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 9257 #define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 9258 #define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 9259 #define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 9260 //MMEA0_GMI_RD_PRI_QUANT_PRI2 9261 #define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 9262 #define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 9263 #define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 9264 #define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 9265 #define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 9266 #define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 9267 #define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 9268 #define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 9269 //MMEA0_GMI_RD_PRI_QUANT_PRI3 9270 #define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 9271 #define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 9272 #define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 9273 #define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 9274 #define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 9275 #define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 9276 #define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 9277 #define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 9278 //MMEA0_GMI_WR_PRI_QUANT_PRI1 9279 #define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 9280 #define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 9281 #define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 9282 #define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 9283 #define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 9284 #define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 9285 #define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 9286 #define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 9287 //MMEA0_GMI_WR_PRI_QUANT_PRI2 9288 #define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 9289 #define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 9290 #define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 9291 #define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 9292 #define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 9293 #define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 9294 #define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 9295 #define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 9296 //MMEA0_GMI_WR_PRI_QUANT_PRI3 9297 #define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 9298 #define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 9299 #define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 9300 #define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 9301 #define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 9302 #define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 9303 #define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 9304 #define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 9305 //MMEA0_ADDRNORM_BASE_ADDR0 9306 #define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 9307 #define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 9308 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 9309 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x6 9310 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 9311 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 9312 #define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc 9313 #define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L 9314 #define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 9315 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000003CL 9316 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x000000C0L 9317 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L 9318 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L 9319 #define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L 9320 //MMEA0_ADDRNORM_LIMIT_ADDR0 9321 #define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 9322 #define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc 9323 #define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL 9324 #define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L 9325 //MMEA0_ADDRNORM_BASE_ADDR1 9326 #define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 9327 #define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 9328 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 9329 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x6 9330 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 9331 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 9332 #define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc 9333 #define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L 9334 #define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 9335 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000003CL 9336 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x000000C0L 9337 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L 9338 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L 9339 #define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L 9340 //MMEA0_ADDRNORM_LIMIT_ADDR1 9341 #define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 9342 #define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc 9343 #define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL 9344 #define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L 9345 //MMEA0_ADDRNORM_OFFSET_ADDR1 9346 #define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 9347 #define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 9348 #define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L 9349 #define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L 9350 //MMEA0_ADDRNORM_BASE_ADDR2 9351 #define MMEA0_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT 0x0 9352 #define MMEA0_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT 0x1 9353 #define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT 0x2 9354 #define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT 0x6 9355 #define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT 0x8 9356 #define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT 0x9 9357 #define MMEA0_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT 0xc 9358 #define MMEA0_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK 0x00000001L 9359 #define MMEA0_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 9360 #define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK 0x0000003CL 9361 #define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK 0x000000C0L 9362 #define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK 0x00000100L 9363 #define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK 0x00000E00L 9364 #define MMEA0_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK 0xFFFFF000L 9365 //MMEA0_ADDRNORM_LIMIT_ADDR2 9366 #define MMEA0_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT 0x0 9367 #define MMEA0_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT 0xc 9368 #define MMEA0_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK 0x0000001FL 9369 #define MMEA0_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK 0xFFFFF000L 9370 //MMEA0_ADDRNORM_BASE_ADDR3 9371 #define MMEA0_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT 0x0 9372 #define MMEA0_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT 0x1 9373 #define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT 0x2 9374 #define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT 0x6 9375 #define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT 0x8 9376 #define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT 0x9 9377 #define MMEA0_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT 0xc 9378 #define MMEA0_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK 0x00000001L 9379 #define MMEA0_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 9380 #define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK 0x0000003CL 9381 #define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK 0x000000C0L 9382 #define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK 0x00000100L 9383 #define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK 0x00000E00L 9384 #define MMEA0_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK 0xFFFFF000L 9385 //MMEA0_ADDRNORM_LIMIT_ADDR3 9386 #define MMEA0_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT 0x0 9387 #define MMEA0_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT 0xc 9388 #define MMEA0_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK 0x0000001FL 9389 #define MMEA0_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK 0xFFFFF000L 9390 //MMEA0_ADDRNORM_OFFSET_ADDR3 9391 #define MMEA0_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT 0x0 9392 #define MMEA0_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT 0x14 9393 #define MMEA0_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK 0x00000001L 9394 #define MMEA0_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK 0xFFF00000L 9395 //MMEA0_ADDRNORM_BASE_ADDR4 9396 #define MMEA0_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL__SHIFT 0x0 9397 #define MMEA0_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN__SHIFT 0x1 9398 #define MMEA0_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN__SHIFT 0x2 9399 #define MMEA0_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES__SHIFT 0x6 9400 #define MMEA0_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS__SHIFT 0x8 9401 #define MMEA0_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL__SHIFT 0x9 9402 #define MMEA0_ADDRNORM_BASE_ADDR4__BASE_ADDR__SHIFT 0xc 9403 #define MMEA0_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL_MASK 0x00000001L 9404 #define MMEA0_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 9405 #define MMEA0_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN_MASK 0x0000003CL 9406 #define MMEA0_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES_MASK 0x000000C0L 9407 #define MMEA0_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS_MASK 0x00000100L 9408 #define MMEA0_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL_MASK 0x00000E00L 9409 #define MMEA0_ADDRNORM_BASE_ADDR4__BASE_ADDR_MASK 0xFFFFF000L 9410 //MMEA0_ADDRNORM_LIMIT_ADDR4 9411 #define MMEA0_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID__SHIFT 0x0 9412 #define MMEA0_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR__SHIFT 0xc 9413 #define MMEA0_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID_MASK 0x0000001FL 9414 #define MMEA0_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR_MASK 0xFFFFF000L 9415 //MMEA0_ADDRNORM_BASE_ADDR5 9416 #define MMEA0_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL__SHIFT 0x0 9417 #define MMEA0_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN__SHIFT 0x1 9418 #define MMEA0_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN__SHIFT 0x2 9419 #define MMEA0_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES__SHIFT 0x6 9420 #define MMEA0_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS__SHIFT 0x8 9421 #define MMEA0_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL__SHIFT 0x9 9422 #define MMEA0_ADDRNORM_BASE_ADDR5__BASE_ADDR__SHIFT 0xc 9423 #define MMEA0_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL_MASK 0x00000001L 9424 #define MMEA0_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 9425 #define MMEA0_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN_MASK 0x0000003CL 9426 #define MMEA0_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES_MASK 0x000000C0L 9427 #define MMEA0_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS_MASK 0x00000100L 9428 #define MMEA0_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL_MASK 0x00000E00L 9429 #define MMEA0_ADDRNORM_BASE_ADDR5__BASE_ADDR_MASK 0xFFFFF000L 9430 //MMEA0_ADDRNORM_LIMIT_ADDR5 9431 #define MMEA0_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID__SHIFT 0x0 9432 #define MMEA0_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR__SHIFT 0xc 9433 #define MMEA0_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID_MASK 0x0000001FL 9434 #define MMEA0_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR_MASK 0xFFFFF000L 9435 //MMEA0_ADDRNORM_OFFSET_ADDR5 9436 #define MMEA0_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN__SHIFT 0x0 9437 #define MMEA0_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET__SHIFT 0x14 9438 #define MMEA0_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN_MASK 0x00000001L 9439 #define MMEA0_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_MASK 0xFFF00000L 9440 //MMEA0_ADDRNORMDRAM_HOLE_CNTL 9441 #define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 9442 #define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 9443 #define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L 9444 #define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L 9445 //MMEA0_ADDRNORMGMI_HOLE_CNTL 9446 #define MMEA0_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 9447 #define MMEA0_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 9448 #define MMEA0_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L 9449 #define MMEA0_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L 9450 //MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG 9451 #define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0 9452 #define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6 9453 #define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL 9454 #define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L 9455 //MMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG 9456 #define MMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT 0x0 9457 #define MMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT 0x6 9458 #define MMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK 0x0000003FL 9459 #define MMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK 0x00000FC0L 9460 //MMEA0_ADDRDEC_BANK_CFG 9461 #define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 9462 #define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x6 9463 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xc 9464 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xf 9465 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x12 9466 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x13 9467 #define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000003FL 9468 #define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x00000FC0L 9469 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00007000L 9470 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x00038000L 9471 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00040000L 9472 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00080000L 9473 //MMEA0_ADDRDEC_MISC_CFG 9474 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 9475 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 9476 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 9477 #define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 9478 #define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 9479 #define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc 9480 #define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11 9481 #define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16 9482 #define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18 9483 #define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a 9484 #define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d 9485 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L 9486 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L 9487 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L 9488 #define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L 9489 #define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L 9490 #define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L 9491 #define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L 9492 #define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L 9493 #define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L 9494 #define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L 9495 #define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L 9496 //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0 9497 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 9498 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 9499 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe 9500 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L 9501 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL 9502 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L 9503 //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1 9504 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 9505 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 9506 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe 9507 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L 9508 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL 9509 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L 9510 //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2 9511 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 9512 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 9513 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe 9514 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L 9515 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL 9516 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L 9517 //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3 9518 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 9519 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 9520 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe 9521 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L 9522 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL 9523 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L 9524 //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4 9525 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 9526 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 9527 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe 9528 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L 9529 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL 9530 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L 9531 //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5 9532 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT 0x0 9533 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR__SHIFT 0x1 9534 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR__SHIFT 0xe 9535 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE_MASK 0x00000001L 9536 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR_MASK 0x00003FFEL 9537 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR_MASK 0xFFFFC000L 9538 //MMEA0_ADDRDECDRAM_ADDR_HASH_PC 9539 #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 9540 #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 9541 #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe 9542 #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L 9543 #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL 9544 #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L 9545 //MMEA0_ADDRDECDRAM_ADDR_HASH_PC2 9546 #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 9547 #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000003FL 9548 //MMEA0_ADDRDECDRAM_ADDR_HASH_CS0 9549 #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 9550 #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 9551 #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L 9552 #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL 9553 //MMEA0_ADDRDECDRAM_ADDR_HASH_CS1 9554 #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 9555 #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 9556 #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L 9557 #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL 9558 //MMEA0_ADDRDECDRAM_HARVEST_ENABLE 9559 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 9560 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 9561 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 9562 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 9563 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 9564 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 9565 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L 9566 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L 9567 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L 9568 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L 9569 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L 9570 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L 9571 //MMEA0_ADDRDECGMI_ADDR_HASH_BANK0 9572 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 9573 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 9574 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe 9575 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L 9576 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL 9577 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L 9578 //MMEA0_ADDRDECGMI_ADDR_HASH_BANK1 9579 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 9580 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 9581 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe 9582 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L 9583 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL 9584 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L 9585 //MMEA0_ADDRDECGMI_ADDR_HASH_BANK2 9586 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 9587 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 9588 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe 9589 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L 9590 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL 9591 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L 9592 //MMEA0_ADDRDECGMI_ADDR_HASH_BANK3 9593 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 9594 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 9595 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe 9596 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L 9597 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL 9598 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L 9599 //MMEA0_ADDRDECGMI_ADDR_HASH_BANK4 9600 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 9601 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 9602 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe 9603 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L 9604 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL 9605 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L 9606 //MMEA0_ADDRDECGMI_ADDR_HASH_BANK5 9607 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT 0x0 9608 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR__SHIFT 0x1 9609 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR__SHIFT 0xe 9610 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE_MASK 0x00000001L 9611 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR_MASK 0x00003FFEL 9612 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR_MASK 0xFFFFC000L 9613 //MMEA0_ADDRDECGMI_ADDR_HASH_PC 9614 #define MMEA0_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 9615 #define MMEA0_ADDRDECGMI_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 9616 #define MMEA0_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe 9617 #define MMEA0_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L 9618 #define MMEA0_ADDRDECGMI_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL 9619 #define MMEA0_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L 9620 //MMEA0_ADDRDECGMI_ADDR_HASH_PC2 9621 #define MMEA0_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 9622 #define MMEA0_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000003FL 9623 //MMEA0_ADDRDECGMI_ADDR_HASH_CS0 9624 #define MMEA0_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 9625 #define MMEA0_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 9626 #define MMEA0_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L 9627 #define MMEA0_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL 9628 //MMEA0_ADDRDECGMI_ADDR_HASH_CS1 9629 #define MMEA0_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 9630 #define MMEA0_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 9631 #define MMEA0_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L 9632 #define MMEA0_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL 9633 //MMEA0_ADDRDECGMI_HARVEST_ENABLE 9634 #define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 9635 #define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 9636 #define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 9637 #define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 9638 #define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 9639 #define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 9640 #define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L 9641 #define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L 9642 #define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L 9643 #define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L 9644 #define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L 9645 #define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L 9646 //MMEA0_ADDRDEC0_BASE_ADDR_CS0 9647 #define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 9648 #define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 9649 #define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 9650 #define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 9651 //MMEA0_ADDRDEC0_BASE_ADDR_CS1 9652 #define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 9653 #define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 9654 #define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 9655 #define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 9656 //MMEA0_ADDRDEC0_BASE_ADDR_CS2 9657 #define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 9658 #define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 9659 #define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 9660 #define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 9661 //MMEA0_ADDRDEC0_BASE_ADDR_CS3 9662 #define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 9663 #define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 9664 #define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 9665 #define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 9666 //MMEA0_ADDRDEC0_BASE_ADDR_SECCS0 9667 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 9668 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 9669 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 9670 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 9671 //MMEA0_ADDRDEC0_BASE_ADDR_SECCS1 9672 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 9673 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 9674 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 9675 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 9676 //MMEA0_ADDRDEC0_BASE_ADDR_SECCS2 9677 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 9678 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 9679 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 9680 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 9681 //MMEA0_ADDRDEC0_BASE_ADDR_SECCS3 9682 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 9683 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 9684 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 9685 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 9686 //MMEA0_ADDRDEC0_ADDR_MASK_CS01 9687 #define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 9688 #define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 9689 //MMEA0_ADDRDEC0_ADDR_MASK_CS23 9690 #define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 9691 #define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 9692 //MMEA0_ADDRDEC0_ADDR_MASK_SECCS01 9693 #define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 9694 #define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 9695 //MMEA0_ADDRDEC0_ADDR_MASK_SECCS23 9696 #define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 9697 #define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 9698 //MMEA0_ADDRDEC0_ADDR_CFG_CS01 9699 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 9700 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 9701 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 9702 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 9703 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 9704 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 9705 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 9706 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 9707 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 9708 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 9709 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 9710 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 9711 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 9712 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 9713 //MMEA0_ADDRDEC0_ADDR_CFG_CS23 9714 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 9715 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 9716 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 9717 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 9718 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 9719 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 9720 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 9721 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 9722 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 9723 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 9724 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 9725 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 9726 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 9727 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 9728 //MMEA0_ADDRDEC0_ADDR_SEL_CS01 9729 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 9730 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 9731 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 9732 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc 9733 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 9734 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 9735 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 9736 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 9737 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 9738 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 9739 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 9740 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 9741 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 9742 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 9743 //MMEA0_ADDRDEC0_ADDR_SEL_CS23 9744 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 9745 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 9746 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 9747 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc 9748 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 9749 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 9750 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 9751 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 9752 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 9753 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 9754 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 9755 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 9756 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 9757 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 9758 //MMEA0_ADDRDEC0_ADDR_SEL2_CS01 9759 #define MMEA0_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 9760 #define MMEA0_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 9761 //MMEA0_ADDRDEC0_ADDR_SEL2_CS23 9762 #define MMEA0_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 9763 #define MMEA0_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 9764 //MMEA0_ADDRDEC0_COL_SEL_LO_CS01 9765 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 9766 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 9767 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 9768 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc 9769 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 9770 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 9771 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 9772 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 9773 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 9774 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 9775 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 9776 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 9777 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 9778 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 9779 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 9780 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 9781 //MMEA0_ADDRDEC0_COL_SEL_LO_CS23 9782 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 9783 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 9784 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 9785 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc 9786 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 9787 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 9788 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 9789 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 9790 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 9791 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 9792 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 9793 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 9794 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 9795 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 9796 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 9797 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 9798 //MMEA0_ADDRDEC0_COL_SEL_HI_CS01 9799 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 9800 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 9801 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 9802 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc 9803 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 9804 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 9805 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 9806 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 9807 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 9808 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 9809 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 9810 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 9811 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 9812 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 9813 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 9814 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 9815 //MMEA0_ADDRDEC0_COL_SEL_HI_CS23 9816 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 9817 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 9818 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 9819 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc 9820 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 9821 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 9822 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 9823 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 9824 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 9825 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 9826 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 9827 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 9828 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 9829 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 9830 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 9831 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 9832 //MMEA0_ADDRDEC0_RM_SEL_CS01 9833 #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 9834 #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 9835 #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 9836 #define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 9837 #define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 9838 #define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 9839 #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL 9840 #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L 9841 #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L 9842 #define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 9843 #define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 9844 #define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 9845 //MMEA0_ADDRDEC0_RM_SEL_CS23 9846 #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 9847 #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 9848 #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 9849 #define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 9850 #define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 9851 #define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 9852 #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL 9853 #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L 9854 #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L 9855 #define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 9856 #define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 9857 #define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 9858 //MMEA0_ADDRDEC0_RM_SEL_SECCS01 9859 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 9860 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 9861 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 9862 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 9863 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 9864 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 9865 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 9866 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 9867 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 9868 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 9869 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 9870 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 9871 //MMEA0_ADDRDEC0_RM_SEL_SECCS23 9872 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 9873 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 9874 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 9875 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 9876 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 9877 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 9878 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 9879 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 9880 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 9881 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 9882 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 9883 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 9884 //MMEA0_ADDRDEC1_BASE_ADDR_CS0 9885 #define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 9886 #define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 9887 #define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 9888 #define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 9889 //MMEA0_ADDRDEC1_BASE_ADDR_CS1 9890 #define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 9891 #define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 9892 #define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 9893 #define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 9894 //MMEA0_ADDRDEC1_BASE_ADDR_CS2 9895 #define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 9896 #define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 9897 #define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 9898 #define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 9899 //MMEA0_ADDRDEC1_BASE_ADDR_CS3 9900 #define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 9901 #define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 9902 #define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 9903 #define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 9904 //MMEA0_ADDRDEC1_BASE_ADDR_SECCS0 9905 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 9906 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 9907 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 9908 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 9909 //MMEA0_ADDRDEC1_BASE_ADDR_SECCS1 9910 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 9911 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 9912 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 9913 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 9914 //MMEA0_ADDRDEC1_BASE_ADDR_SECCS2 9915 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 9916 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 9917 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 9918 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 9919 //MMEA0_ADDRDEC1_BASE_ADDR_SECCS3 9920 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 9921 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 9922 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 9923 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 9924 //MMEA0_ADDRDEC1_ADDR_MASK_CS01 9925 #define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 9926 #define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 9927 //MMEA0_ADDRDEC1_ADDR_MASK_CS23 9928 #define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 9929 #define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 9930 //MMEA0_ADDRDEC1_ADDR_MASK_SECCS01 9931 #define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 9932 #define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 9933 //MMEA0_ADDRDEC1_ADDR_MASK_SECCS23 9934 #define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 9935 #define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 9936 //MMEA0_ADDRDEC1_ADDR_CFG_CS01 9937 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 9938 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 9939 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 9940 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 9941 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 9942 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 9943 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 9944 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 9945 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 9946 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 9947 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 9948 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 9949 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 9950 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 9951 //MMEA0_ADDRDEC1_ADDR_CFG_CS23 9952 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 9953 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 9954 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 9955 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 9956 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 9957 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 9958 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 9959 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 9960 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 9961 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 9962 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 9963 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 9964 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 9965 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 9966 //MMEA0_ADDRDEC1_ADDR_SEL_CS01 9967 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 9968 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 9969 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 9970 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc 9971 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 9972 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 9973 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 9974 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 9975 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 9976 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 9977 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 9978 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 9979 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 9980 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 9981 //MMEA0_ADDRDEC1_ADDR_SEL_CS23 9982 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 9983 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 9984 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 9985 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc 9986 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 9987 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 9988 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 9989 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 9990 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 9991 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 9992 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 9993 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 9994 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 9995 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 9996 //MMEA0_ADDRDEC1_ADDR_SEL2_CS01 9997 #define MMEA0_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 9998 #define MMEA0_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 9999 //MMEA0_ADDRDEC1_ADDR_SEL2_CS23 10000 #define MMEA0_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 10001 #define MMEA0_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 10002 //MMEA0_ADDRDEC1_COL_SEL_LO_CS01 10003 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 10004 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 10005 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 10006 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc 10007 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 10008 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 10009 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 10010 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 10011 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 10012 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 10013 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 10014 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 10015 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 10016 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 10017 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 10018 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 10019 //MMEA0_ADDRDEC1_COL_SEL_LO_CS23 10020 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 10021 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 10022 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 10023 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc 10024 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 10025 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 10026 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 10027 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 10028 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 10029 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 10030 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 10031 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 10032 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 10033 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 10034 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 10035 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 10036 //MMEA0_ADDRDEC1_COL_SEL_HI_CS01 10037 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 10038 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 10039 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 10040 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc 10041 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 10042 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 10043 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 10044 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 10045 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 10046 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 10047 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 10048 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 10049 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 10050 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 10051 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 10052 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 10053 //MMEA0_ADDRDEC1_COL_SEL_HI_CS23 10054 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 10055 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 10056 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 10057 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc 10058 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 10059 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 10060 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 10061 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 10062 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 10063 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 10064 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 10065 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 10066 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 10067 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 10068 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 10069 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 10070 //MMEA0_ADDRDEC1_RM_SEL_CS01 10071 #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 10072 #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 10073 #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 10074 #define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 10075 #define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 10076 #define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 10077 #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL 10078 #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L 10079 #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L 10080 #define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 10081 #define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 10082 #define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 10083 //MMEA0_ADDRDEC1_RM_SEL_CS23 10084 #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 10085 #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 10086 #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 10087 #define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 10088 #define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 10089 #define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 10090 #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL 10091 #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L 10092 #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L 10093 #define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 10094 #define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 10095 #define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 10096 //MMEA0_ADDRDEC1_RM_SEL_SECCS01 10097 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 10098 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 10099 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 10100 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 10101 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 10102 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 10103 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 10104 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 10105 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 10106 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 10107 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 10108 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 10109 //MMEA0_ADDRDEC1_RM_SEL_SECCS23 10110 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 10111 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 10112 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 10113 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 10114 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 10115 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 10116 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 10117 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 10118 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 10119 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 10120 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 10121 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 10122 //MMEA0_ADDRDEC2_BASE_ADDR_CS0 10123 #define MMEA0_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 10124 #define MMEA0_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 10125 #define MMEA0_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 10126 #define MMEA0_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 10127 //MMEA0_ADDRDEC2_BASE_ADDR_CS1 10128 #define MMEA0_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 10129 #define MMEA0_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 10130 #define MMEA0_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 10131 #define MMEA0_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 10132 //MMEA0_ADDRDEC2_BASE_ADDR_CS2 10133 #define MMEA0_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 10134 #define MMEA0_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 10135 #define MMEA0_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 10136 #define MMEA0_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 10137 //MMEA0_ADDRDEC2_BASE_ADDR_CS3 10138 #define MMEA0_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 10139 #define MMEA0_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 10140 #define MMEA0_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 10141 #define MMEA0_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 10142 //MMEA0_ADDRDEC2_BASE_ADDR_SECCS0 10143 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 10144 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 10145 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 10146 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 10147 //MMEA0_ADDRDEC2_BASE_ADDR_SECCS1 10148 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 10149 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 10150 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 10151 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 10152 //MMEA0_ADDRDEC2_BASE_ADDR_SECCS2 10153 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 10154 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 10155 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 10156 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 10157 //MMEA0_ADDRDEC2_BASE_ADDR_SECCS3 10158 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 10159 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 10160 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 10161 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 10162 //MMEA0_ADDRDEC2_ADDR_MASK_CS01 10163 #define MMEA0_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 10164 #define MMEA0_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 10165 //MMEA0_ADDRDEC2_ADDR_MASK_CS23 10166 #define MMEA0_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 10167 #define MMEA0_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 10168 //MMEA0_ADDRDEC2_ADDR_MASK_SECCS01 10169 #define MMEA0_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 10170 #define MMEA0_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 10171 //MMEA0_ADDRDEC2_ADDR_MASK_SECCS23 10172 #define MMEA0_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 10173 #define MMEA0_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 10174 //MMEA0_ADDRDEC2_ADDR_CFG_CS01 10175 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 10176 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 10177 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 10178 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 10179 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 10180 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 10181 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 10182 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 10183 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 10184 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 10185 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 10186 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 10187 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 10188 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 10189 //MMEA0_ADDRDEC2_ADDR_CFG_CS23 10190 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 10191 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 10192 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 10193 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 10194 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 10195 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 10196 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 10197 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 10198 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 10199 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 10200 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 10201 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 10202 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 10203 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 10204 //MMEA0_ADDRDEC2_ADDR_SEL_CS01 10205 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT 0x0 10206 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT 0x4 10207 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT 0x8 10208 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT 0xc 10209 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT 0x10 10210 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 10211 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 10212 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 10213 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 10214 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 10215 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 10216 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 10217 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 10218 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 10219 //MMEA0_ADDRDEC2_ADDR_SEL_CS23 10220 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT 0x0 10221 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT 0x4 10222 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT 0x8 10223 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT 0xc 10224 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT 0x10 10225 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 10226 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 10227 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 10228 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 10229 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 10230 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 10231 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 10232 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 10233 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 10234 //MMEA0_ADDRDEC2_ADDR_SEL2_CS01 10235 #define MMEA0_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 10236 #define MMEA0_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 10237 //MMEA0_ADDRDEC2_ADDR_SEL2_CS23 10238 #define MMEA0_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 10239 #define MMEA0_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 10240 //MMEA0_ADDRDEC2_COL_SEL_LO_CS01 10241 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT 0x0 10242 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT 0x4 10243 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT 0x8 10244 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT 0xc 10245 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT 0x10 10246 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT 0x14 10247 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT 0x18 10248 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 10249 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 10250 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 10251 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 10252 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 10253 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 10254 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 10255 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 10256 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 10257 //MMEA0_ADDRDEC2_COL_SEL_LO_CS23 10258 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT 0x0 10259 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT 0x4 10260 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT 0x8 10261 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT 0xc 10262 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT 0x10 10263 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT 0x14 10264 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT 0x18 10265 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 10266 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 10267 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 10268 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 10269 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 10270 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 10271 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 10272 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 10273 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 10274 //MMEA0_ADDRDEC2_COL_SEL_HI_CS01 10275 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT 0x0 10276 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT 0x4 10277 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT 0x8 10278 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT 0xc 10279 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT 0x10 10280 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT 0x14 10281 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT 0x18 10282 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 10283 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 10284 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 10285 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 10286 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 10287 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 10288 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 10289 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 10290 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 10291 //MMEA0_ADDRDEC2_COL_SEL_HI_CS23 10292 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT 0x0 10293 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT 0x4 10294 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT 0x8 10295 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT 0xc 10296 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT 0x10 10297 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT 0x14 10298 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT 0x18 10299 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 10300 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 10301 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 10302 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 10303 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 10304 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 10305 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 10306 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 10307 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 10308 //MMEA0_ADDRDEC2_RM_SEL_CS01 10309 #define MMEA0_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT 0x0 10310 #define MMEA0_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT 0x4 10311 #define MMEA0_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT 0x8 10312 #define MMEA0_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 10313 #define MMEA0_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 10314 #define MMEA0_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 10315 #define MMEA0_ADDRDEC2_RM_SEL_CS01__RM0_MASK 0x0000000FL 10316 #define MMEA0_ADDRDEC2_RM_SEL_CS01__RM1_MASK 0x000000F0L 10317 #define MMEA0_ADDRDEC2_RM_SEL_CS01__RM2_MASK 0x00000F00L 10318 #define MMEA0_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 10319 #define MMEA0_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 10320 #define MMEA0_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 10321 //MMEA0_ADDRDEC2_RM_SEL_CS23 10322 #define MMEA0_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT 0x0 10323 #define MMEA0_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT 0x4 10324 #define MMEA0_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT 0x8 10325 #define MMEA0_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 10326 #define MMEA0_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 10327 #define MMEA0_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 10328 #define MMEA0_ADDRDEC2_RM_SEL_CS23__RM0_MASK 0x0000000FL 10329 #define MMEA0_ADDRDEC2_RM_SEL_CS23__RM1_MASK 0x000000F0L 10330 #define MMEA0_ADDRDEC2_RM_SEL_CS23__RM2_MASK 0x00000F00L 10331 #define MMEA0_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 10332 #define MMEA0_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 10333 #define MMEA0_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 10334 //MMEA0_ADDRDEC2_RM_SEL_SECCS01 10335 #define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT 0x0 10336 #define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT 0x4 10337 #define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT 0x8 10338 #define MMEA0_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 10339 #define MMEA0_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 10340 #define MMEA0_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 10341 #define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 10342 #define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 10343 #define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 10344 #define MMEA0_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 10345 #define MMEA0_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 10346 #define MMEA0_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 10347 //MMEA0_ADDRDEC2_RM_SEL_SECCS23 10348 #define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT 0x0 10349 #define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT 0x4 10350 #define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT 0x8 10351 #define MMEA0_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 10352 #define MMEA0_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 10353 #define MMEA0_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 10354 #define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 10355 #define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 10356 #define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 10357 #define MMEA0_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 10358 #define MMEA0_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 10359 #define MMEA0_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 10360 //MMEA0_ADDRNORMDRAM_GLOBAL_CNTL 10361 #define MMEA0_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT 0x14 10362 #define MMEA0_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT 0x15 10363 #define MMEA0_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT 0x16 10364 #define MMEA0_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK 0x00100000L 10365 #define MMEA0_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK 0x00200000L 10366 #define MMEA0_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK 0x00400000L 10367 //MMEA0_ADDRNORMGMI_GLOBAL_CNTL 10368 #define MMEA0_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT 0x14 10369 #define MMEA0_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT 0x15 10370 #define MMEA0_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT 0x16 10371 #define MMEA0_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK 0x00100000L 10372 #define MMEA0_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK 0x00200000L 10373 #define MMEA0_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK 0x00400000L 10374 //MMEA0_IO_RD_CLI2GRP_MAP0 10375 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 10376 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 10377 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 10378 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 10379 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 10380 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 10381 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 10382 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 10383 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 10384 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 10385 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 10386 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 10387 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 10388 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 10389 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 10390 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 10391 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 10392 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 10393 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 10394 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 10395 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 10396 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 10397 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 10398 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 10399 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 10400 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 10401 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 10402 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 10403 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 10404 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 10405 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 10406 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 10407 //MMEA0_IO_RD_CLI2GRP_MAP1 10408 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 10409 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 10410 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 10411 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 10412 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 10413 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 10414 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 10415 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 10416 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 10417 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 10418 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 10419 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 10420 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 10421 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 10422 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 10423 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 10424 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 10425 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 10426 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 10427 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 10428 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 10429 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 10430 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 10431 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 10432 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 10433 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 10434 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 10435 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 10436 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 10437 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 10438 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 10439 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 10440 //MMEA0_IO_WR_CLI2GRP_MAP0 10441 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 10442 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 10443 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 10444 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 10445 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 10446 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 10447 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 10448 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 10449 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 10450 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 10451 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 10452 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 10453 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 10454 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 10455 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 10456 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 10457 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 10458 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 10459 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 10460 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 10461 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 10462 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 10463 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 10464 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 10465 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 10466 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 10467 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 10468 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 10469 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 10470 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 10471 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 10472 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 10473 //MMEA0_IO_WR_CLI2GRP_MAP1 10474 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 10475 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 10476 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 10477 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 10478 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 10479 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 10480 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 10481 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 10482 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 10483 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 10484 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 10485 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 10486 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 10487 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 10488 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 10489 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 10490 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 10491 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 10492 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 10493 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 10494 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 10495 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 10496 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 10497 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 10498 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 10499 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 10500 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 10501 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 10502 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 10503 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 10504 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 10505 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 10506 //MMEA0_IO_RD_COMBINE_FLUSH 10507 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 10508 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 10509 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 10510 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 10511 #define MMEA0_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT 0x10 10512 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 10513 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 10514 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 10515 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 10516 #define MMEA0_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK 0x00010000L 10517 //MMEA0_IO_WR_COMBINE_FLUSH 10518 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 10519 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 10520 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 10521 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 10522 #define MMEA0_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT 0x10 10523 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 10524 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 10525 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 10526 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 10527 #define MMEA0_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK 0x00010000L 10528 //MMEA0_IO_GROUP_BURST 10529 #define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 10530 #define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 10531 #define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 10532 #define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 10533 #define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL 10534 #define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 10535 #define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 10536 #define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L 10537 //MMEA0_IO_RD_PRI_AGE 10538 #define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 10539 #define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 10540 #define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 10541 #define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 10542 #define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 10543 #define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 10544 #define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 10545 #define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 10546 #define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 10547 #define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 10548 #define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 10549 #define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 10550 #define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 10551 #define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 10552 #define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 10553 #define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 10554 //MMEA0_IO_WR_PRI_AGE 10555 #define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 10556 #define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 10557 #define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 10558 #define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 10559 #define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 10560 #define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 10561 #define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 10562 #define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 10563 #define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 10564 #define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 10565 #define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 10566 #define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 10567 #define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 10568 #define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 10569 #define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 10570 #define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 10571 //MMEA0_IO_RD_PRI_QUEUING 10572 #define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 10573 #define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 10574 #define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 10575 #define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 10576 #define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 10577 #define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 10578 #define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 10579 #define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 10580 //MMEA0_IO_WR_PRI_QUEUING 10581 #define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 10582 #define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 10583 #define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 10584 #define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 10585 #define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 10586 #define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 10587 #define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 10588 #define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 10589 //MMEA0_IO_RD_PRI_FIXED 10590 #define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 10591 #define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 10592 #define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 10593 #define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 10594 #define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 10595 #define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 10596 #define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 10597 #define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 10598 //MMEA0_IO_WR_PRI_FIXED 10599 #define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 10600 #define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 10601 #define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 10602 #define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 10603 #define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 10604 #define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 10605 #define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 10606 #define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 10607 //MMEA0_IO_RD_PRI_URGENCY 10608 #define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 10609 #define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 10610 #define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 10611 #define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 10612 #define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 10613 #define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 10614 #define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 10615 #define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 10616 #define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 10617 #define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 10618 #define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 10619 #define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 10620 #define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 10621 #define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 10622 #define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 10623 #define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 10624 //MMEA0_IO_WR_PRI_URGENCY 10625 #define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 10626 #define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 10627 #define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 10628 #define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 10629 #define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 10630 #define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 10631 #define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 10632 #define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 10633 #define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 10634 #define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 10635 #define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 10636 #define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 10637 #define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 10638 #define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 10639 #define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 10640 #define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 10641 //MMEA0_IO_RD_PRI_URGENCY_MASKING 10642 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 10643 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 10644 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 10645 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 10646 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 10647 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 10648 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 10649 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 10650 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 10651 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 10652 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 10653 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 10654 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 10655 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 10656 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 10657 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 10658 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 10659 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 10660 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 10661 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 10662 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 10663 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 10664 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 10665 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 10666 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 10667 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 10668 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 10669 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 10670 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 10671 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 10672 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 10673 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 10674 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 10675 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 10676 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 10677 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 10678 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 10679 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 10680 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 10681 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 10682 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 10683 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 10684 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 10685 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 10686 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 10687 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 10688 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 10689 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 10690 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 10691 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 10692 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 10693 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 10694 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 10695 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 10696 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 10697 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 10698 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 10699 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 10700 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 10701 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 10702 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 10703 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 10704 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 10705 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 10706 //MMEA0_IO_WR_PRI_URGENCY_MASKING 10707 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 10708 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 10709 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 10710 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 10711 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 10712 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 10713 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 10714 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 10715 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 10716 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 10717 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 10718 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 10719 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 10720 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 10721 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 10722 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 10723 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 10724 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 10725 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 10726 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 10727 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 10728 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 10729 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 10730 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 10731 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 10732 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 10733 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 10734 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 10735 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 10736 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 10737 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 10738 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 10739 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 10740 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 10741 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 10742 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 10743 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 10744 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 10745 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 10746 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 10747 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 10748 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 10749 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 10750 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 10751 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 10752 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 10753 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 10754 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 10755 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 10756 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 10757 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 10758 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 10759 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 10760 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 10761 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 10762 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 10763 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 10764 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 10765 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 10766 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 10767 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 10768 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 10769 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 10770 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 10771 //MMEA0_IO_RD_PRI_QUANT_PRI1 10772 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 10773 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 10774 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 10775 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 10776 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 10777 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 10778 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 10779 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 10780 //MMEA0_IO_RD_PRI_QUANT_PRI2 10781 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 10782 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 10783 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 10784 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 10785 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 10786 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 10787 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 10788 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 10789 //MMEA0_IO_RD_PRI_QUANT_PRI3 10790 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 10791 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 10792 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 10793 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 10794 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 10795 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 10796 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 10797 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 10798 //MMEA0_IO_WR_PRI_QUANT_PRI1 10799 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 10800 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 10801 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 10802 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 10803 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 10804 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 10805 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 10806 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 10807 //MMEA0_IO_WR_PRI_QUANT_PRI2 10808 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 10809 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 10810 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 10811 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 10812 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 10813 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 10814 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 10815 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 10816 //MMEA0_IO_WR_PRI_QUANT_PRI3 10817 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 10818 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 10819 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 10820 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 10821 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 10822 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 10823 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 10824 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 10825 //MMEA0_SDP_ARB_DRAM 10826 #define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 10827 #define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 10828 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 10829 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 10830 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 10831 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 10832 #define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 10833 #define MMEA0_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 10834 #define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL 10835 #define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L 10836 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L 10837 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L 10838 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L 10839 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L 10840 #define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L 10841 #define MMEA0_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L 10842 //MMEA0_SDP_ARB_GMI 10843 #define MMEA0_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 10844 #define MMEA0_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 10845 #define MMEA0_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT 0x10 10846 #define MMEA0_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT 0x11 10847 #define MMEA0_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT 0x12 10848 #define MMEA0_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT 0x13 10849 #define MMEA0_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT 0x14 10850 #define MMEA0_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 10851 #define MMEA0_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT 0x16 10852 #define MMEA0_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL 10853 #define MMEA0_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L 10854 #define MMEA0_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK 0x00010000L 10855 #define MMEA0_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK 0x00020000L 10856 #define MMEA0_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK 0x00040000L 10857 #define MMEA0_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK 0x00080000L 10858 #define MMEA0_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK 0x00100000L 10859 #define MMEA0_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L 10860 #define MMEA0_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK 0x00400000L 10861 //MMEA0_SDP_ARB_FINAL 10862 #define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 10863 #define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 10864 #define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa 10865 #define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf 10866 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 10867 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 10868 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 10869 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 10870 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 10871 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 10872 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 10873 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 10874 #define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 10875 #define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a 10876 #define MMEA0_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1b 10877 #define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL 10878 #define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L 10879 #define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L 10880 #define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L 10881 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L 10882 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L 10883 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L 10884 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L 10885 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L 10886 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L 10887 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L 10888 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L 10889 #define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L 10890 #define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L 10891 #define MMEA0_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x08000000L 10892 //MMEA0_SDP_DRAM_PRIORITY 10893 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 10894 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 10895 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 10896 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 10897 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 10898 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 10899 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 10900 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 10901 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 10902 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 10903 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 10904 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 10905 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 10906 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 10907 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 10908 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 10909 //MMEA0_SDP_GMI_PRIORITY 10910 #define MMEA0_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 10911 #define MMEA0_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 10912 #define MMEA0_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 10913 #define MMEA0_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 10914 #define MMEA0_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 10915 #define MMEA0_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 10916 #define MMEA0_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 10917 #define MMEA0_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 10918 #define MMEA0_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 10919 #define MMEA0_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 10920 #define MMEA0_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 10921 #define MMEA0_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 10922 #define MMEA0_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 10923 #define MMEA0_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 10924 #define MMEA0_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 10925 #define MMEA0_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 10926 //MMEA0_SDP_IO_PRIORITY 10927 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 10928 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 10929 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 10930 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 10931 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 10932 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 10933 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 10934 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 10935 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 10936 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 10937 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 10938 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 10939 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 10940 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 10941 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 10942 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 10943 //MMEA0_SDP_CREDITS 10944 #define MMEA0_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 10945 #define MMEA0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 10946 #define MMEA0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 10947 #define MMEA0_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL 10948 #define MMEA0_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L 10949 #define MMEA0_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L 10950 //MMEA0_SDP_TAG_RESERVE0 10951 #define MMEA0_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 10952 #define MMEA0_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 10953 #define MMEA0_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 10954 #define MMEA0_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 10955 #define MMEA0_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL 10956 #define MMEA0_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L 10957 #define MMEA0_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L 10958 #define MMEA0_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L 10959 //MMEA0_SDP_TAG_RESERVE1 10960 #define MMEA0_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 10961 #define MMEA0_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 10962 #define MMEA0_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 10963 #define MMEA0_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 10964 #define MMEA0_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL 10965 #define MMEA0_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L 10966 #define MMEA0_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L 10967 #define MMEA0_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L 10968 //MMEA0_SDP_VCC_RESERVE0 10969 #define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 10970 #define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 10971 #define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc 10972 #define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 10973 #define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 10974 #define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 10975 #define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 10976 #define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 10977 #define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 10978 #define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 10979 //MMEA0_SDP_VCC_RESERVE1 10980 #define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 10981 #define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 10982 #define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc 10983 #define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 10984 #define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 10985 #define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 10986 #define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 10987 #define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 10988 //MMEA0_SDP_VCD_RESERVE0 10989 #define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 10990 #define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 10991 #define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc 10992 #define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 10993 #define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 10994 #define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 10995 #define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 10996 #define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 10997 #define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 10998 #define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 10999 //MMEA0_SDP_VCD_RESERVE1 11000 #define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 11001 #define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 11002 #define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc 11003 #define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 11004 #define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 11005 #define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 11006 #define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 11007 #define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 11008 //MMEA0_SDP_REQ_CNTL 11009 #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 11010 #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 11011 #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 11012 #define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 11013 #define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 11014 #define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 11015 #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L 11016 #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L 11017 #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L 11018 #define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L 11019 #define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L 11020 #define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L 11021 //MMEA0_MISC 11022 #define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 11023 #define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 11024 #define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 11025 #define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 11026 #define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 11027 #define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 11028 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 11029 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 11030 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 11031 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 11032 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa 11033 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb 11034 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc 11035 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd 11036 #define MMEA0_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe 11037 #define MMEA0_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf 11038 #define MMEA0_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 11039 #define MMEA0_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 11040 #define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 11041 #define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a 11042 #define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b 11043 #define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c 11044 #define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d 11045 #define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e 11046 #define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f 11047 #define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L 11048 #define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L 11049 #define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L 11050 #define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L 11051 #define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L 11052 #define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L 11053 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L 11054 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L 11055 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L 11056 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L 11057 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L 11058 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L 11059 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L 11060 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L 11061 #define MMEA0_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L 11062 #define MMEA0_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L 11063 #define MMEA0_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L 11064 #define MMEA0_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L 11065 #define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L 11066 #define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L 11067 #define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L 11068 #define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L 11069 #define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L 11070 #define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L 11071 #define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L 11072 //MMEA0_LATENCY_SAMPLING 11073 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 11074 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 11075 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 11076 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 11077 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 11078 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 11079 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 11080 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 11081 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 11082 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 11083 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa 11084 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb 11085 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc 11086 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd 11087 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe 11088 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 11089 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L 11090 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L 11091 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L 11092 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L 11093 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L 11094 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L 11095 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L 11096 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L 11097 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L 11098 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L 11099 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L 11100 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L 11101 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L 11102 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L 11103 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L 11104 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L 11105 //MMEA0_PERFCOUNTER_LO 11106 #define MMEA0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 11107 #define MMEA0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 11108 //MMEA0_PERFCOUNTER_HI 11109 #define MMEA0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 11110 #define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 11111 #define MMEA0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 11112 #define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 11113 //MMEA0_PERFCOUNTER0_CFG 11114 #define MMEA0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 11115 #define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 11116 #define MMEA0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 11117 #define MMEA0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 11118 #define MMEA0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 11119 #define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 11120 #define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 11121 #define MMEA0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 11122 #define MMEA0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 11123 #define MMEA0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 11124 //MMEA0_PERFCOUNTER1_CFG 11125 #define MMEA0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 11126 #define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 11127 #define MMEA0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 11128 #define MMEA0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 11129 #define MMEA0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 11130 #define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 11131 #define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 11132 #define MMEA0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 11133 #define MMEA0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 11134 #define MMEA0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 11135 //MMEA0_PERFCOUNTER_RSLT_CNTL 11136 #define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 11137 #define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 11138 #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 11139 #define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 11140 #define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 11141 #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 11142 #define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 11143 #define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 11144 #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 11145 #define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 11146 #define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 11147 #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 11148 //MMEA0_EDC_CNT 11149 #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 11150 #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 11151 #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 11152 #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 11153 #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 11154 #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa 11155 #define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc 11156 #define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe 11157 #define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 11158 #define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 11159 #define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 11160 #define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 11161 #define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 11162 #define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a 11163 #define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c 11164 #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 11165 #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 11166 #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 11167 #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 11168 #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 11169 #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 11170 #define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L 11171 #define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L 11172 #define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L 11173 #define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L 11174 #define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L 11175 #define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L 11176 #define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L 11177 #define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L 11178 #define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L 11179 //MMEA0_EDC_CNT2 11180 #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 11181 #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 11182 #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 11183 #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 11184 #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 11185 #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa 11186 #define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc 11187 #define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe 11188 #define MMEA0_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10 11189 #define MMEA0_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12 11190 #define MMEA0_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14 11191 #define MMEA0_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16 11192 #define MMEA0_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT 0x18 11193 #define MMEA0_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT 0x1a 11194 #define MMEA0_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT 0x1c 11195 #define MMEA0_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT 0x1e 11196 #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 11197 #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 11198 #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 11199 #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 11200 #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 11201 #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 11202 #define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L 11203 #define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L 11204 #define MMEA0_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L 11205 #define MMEA0_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L 11206 #define MMEA0_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L 11207 #define MMEA0_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L 11208 #define MMEA0_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK 0x03000000L 11209 #define MMEA0_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK 0x0C000000L 11210 #define MMEA0_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK 0x30000000L 11211 #define MMEA0_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK 0xC0000000L 11212 //MMEA0_DSM_CNTL 11213 #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 11214 #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 11215 #define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 11216 #define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 11217 #define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 11218 #define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 11219 #define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 11220 #define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 11221 #define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 11222 #define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 11223 #define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 11224 #define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 11225 #define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 11226 #define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 11227 #define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 11228 #define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 11229 #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 11230 #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 11231 #define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 11232 #define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 11233 #define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 11234 #define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 11235 #define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 11236 #define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 11237 #define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 11238 #define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 11239 #define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 11240 #define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 11241 #define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 11242 #define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 11243 #define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L 11244 #define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L 11245 //MMEA0_DSM_CNTLA 11246 #define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 11247 #define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 11248 #define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 11249 #define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 11250 #define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 11251 #define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 11252 #define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 11253 #define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 11254 #define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 11255 #define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 11256 #define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 11257 #define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 11258 #define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 11259 #define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 11260 #define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 11261 #define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 11262 #define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 11263 #define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 11264 #define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 11265 #define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 11266 #define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 11267 #define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 11268 #define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 11269 #define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 11270 #define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 11271 #define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 11272 #define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 11273 #define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 11274 //MMEA0_DSM_CNTL2 11275 #define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 11276 #define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 11277 #define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 11278 #define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 11279 #define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 11280 #define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 11281 #define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 11282 #define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb 11283 #define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 11284 #define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe 11285 #define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 11286 #define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 11287 #define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 11288 #define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 11289 #define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 11290 #define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 11291 #define MMEA0_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a 11292 #define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 11293 #define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 11294 #define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 11295 #define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 11296 #define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 11297 #define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 11298 #define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 11299 #define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 11300 #define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 11301 #define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 11302 #define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 11303 #define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 11304 #define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 11305 #define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 11306 #define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L 11307 #define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L 11308 #define MMEA0_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L 11309 //MMEA0_DSM_CNTL2A 11310 #define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 11311 #define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 11312 #define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 11313 #define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 11314 #define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 11315 #define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 11316 #define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 11317 #define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb 11318 #define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 11319 #define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe 11320 #define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 11321 #define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 11322 #define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 11323 #define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 11324 #define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 11325 #define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 11326 #define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 11327 #define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 11328 #define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 11329 #define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 11330 #define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 11331 #define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 11332 #define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 11333 #define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 11334 #define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 11335 #define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 11336 #define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 11337 #define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 11338 //MMEA0_CGTT_CLK_CTRL 11339 #define MMEA0_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 11340 #define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 11341 #define MMEA0_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc 11342 #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 11343 #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 11344 #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 11345 #define MMEA0_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 11346 #define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 11347 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c 11348 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d 11349 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e 11350 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f 11351 #define MMEA0_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 11352 #define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 11353 #define MMEA0_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L 11354 #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L 11355 #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L 11356 #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L 11357 #define MMEA0_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L 11358 #define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 11359 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L 11360 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L 11361 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L 11362 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L 11363 //MMEA0_EDC_MODE 11364 #define MMEA0_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 11365 #define MMEA0_EDC_MODE__GATE_FUE__SHIFT 0x11 11366 #define MMEA0_EDC_MODE__DED_MODE__SHIFT 0x14 11367 #define MMEA0_EDC_MODE__PROP_FED__SHIFT 0x1d 11368 #define MMEA0_EDC_MODE__BYPASS__SHIFT 0x1f 11369 #define MMEA0_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L 11370 #define MMEA0_EDC_MODE__GATE_FUE_MASK 0x00020000L 11371 #define MMEA0_EDC_MODE__DED_MODE_MASK 0x00300000L 11372 #define MMEA0_EDC_MODE__PROP_FED_MASK 0x20000000L 11373 #define MMEA0_EDC_MODE__BYPASS_MASK 0x80000000L 11374 //MMEA0_ERR_STATUS 11375 #define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 11376 #define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 11377 #define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 11378 #define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa 11379 #define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb 11380 #define MMEA0_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc 11381 #define MMEA0_ERR_STATUS__FUE_FLAG__SHIFT 0xd 11382 #define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL 11383 #define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L 11384 #define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L 11385 #define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L 11386 #define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L 11387 #define MMEA0_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L 11388 #define MMEA0_ERR_STATUS__FUE_FLAG_MASK 0x00002000L 11389 //MMEA0_MISC2 11390 #define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 11391 #define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 11392 #define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 11393 #define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 11394 #define MMEA0_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc 11395 #define MMEA0_MISC2__RRET_SWAP_MODE__SHIFT 0xd 11396 #define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L 11397 #define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L 11398 #define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL 11399 #define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L 11400 #define MMEA0_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L 11401 #define MMEA0_MISC2__RRET_SWAP_MODE_MASK 0x00002000L 11402 //MMEA0_ADDRDEC_SELECT 11403 #define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0 11404 #define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5 11405 #define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa 11406 #define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf 11407 #define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL 11408 #define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L 11409 #define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L 11410 #define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L 11411 //MMEA0_EDC_CNT3 11412 #define MMEA0_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0 11413 #define MMEA0_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2 11414 #define MMEA0_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4 11415 #define MMEA0_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6 11416 #define MMEA0_EDC_CNT3__IOWR_DATAMEM_DED_COUNT__SHIFT 0x8 11417 #define MMEA0_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0xa 11418 #define MMEA0_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xc 11419 #define MMEA0_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L 11420 #define MMEA0_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL 11421 #define MMEA0_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L 11422 #define MMEA0_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 11423 #define MMEA0_EDC_CNT3__IOWR_DATAMEM_DED_COUNT_MASK 0x00000300L 11424 #define MMEA0_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000C00L 11425 #define MMEA0_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00003000L 11426 11427 11428 // addressBlock: mmhub_ea_mmeadec1 11429 //MMEA1_DRAM_RD_CLI2GRP_MAP0 11430 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 11431 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 11432 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 11433 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 11434 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 11435 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 11436 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 11437 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 11438 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 11439 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 11440 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 11441 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 11442 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 11443 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 11444 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 11445 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 11446 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 11447 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 11448 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 11449 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 11450 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 11451 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 11452 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 11453 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 11454 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 11455 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 11456 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 11457 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 11458 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 11459 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 11460 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 11461 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 11462 //MMEA1_DRAM_RD_CLI2GRP_MAP1 11463 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 11464 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 11465 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 11466 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 11467 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 11468 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 11469 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 11470 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 11471 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 11472 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 11473 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 11474 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 11475 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 11476 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 11477 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 11478 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 11479 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 11480 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 11481 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 11482 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 11483 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 11484 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 11485 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 11486 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 11487 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 11488 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 11489 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 11490 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 11491 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 11492 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 11493 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 11494 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 11495 //MMEA1_DRAM_WR_CLI2GRP_MAP0 11496 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 11497 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 11498 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 11499 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 11500 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 11501 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 11502 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 11503 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 11504 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 11505 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 11506 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 11507 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 11508 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 11509 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 11510 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 11511 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 11512 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 11513 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 11514 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 11515 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 11516 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 11517 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 11518 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 11519 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 11520 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 11521 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 11522 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 11523 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 11524 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 11525 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 11526 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 11527 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 11528 //MMEA1_DRAM_WR_CLI2GRP_MAP1 11529 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 11530 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 11531 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 11532 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 11533 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 11534 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 11535 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 11536 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 11537 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 11538 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 11539 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 11540 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 11541 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 11542 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 11543 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 11544 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 11545 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 11546 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 11547 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 11548 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 11549 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 11550 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 11551 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 11552 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 11553 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 11554 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 11555 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 11556 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 11557 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 11558 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 11559 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 11560 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 11561 //MMEA1_DRAM_RD_GRP2VC_MAP 11562 #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 11563 #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 11564 #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 11565 #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 11566 #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 11567 #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 11568 #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 11569 #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 11570 //MMEA1_DRAM_WR_GRP2VC_MAP 11571 #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 11572 #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 11573 #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 11574 #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 11575 #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 11576 #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 11577 #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 11578 #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 11579 //MMEA1_DRAM_RD_LAZY 11580 #define MMEA1_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 11581 #define MMEA1_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 11582 #define MMEA1_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 11583 #define MMEA1_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 11584 #define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 11585 #define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 11586 #define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 11587 #define MMEA1_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L 11588 #define MMEA1_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L 11589 #define MMEA1_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L 11590 #define MMEA1_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L 11591 #define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 11592 #define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 11593 #define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 11594 //MMEA1_DRAM_WR_LAZY 11595 #define MMEA1_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 11596 #define MMEA1_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 11597 #define MMEA1_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 11598 #define MMEA1_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 11599 #define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 11600 #define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 11601 #define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 11602 #define MMEA1_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L 11603 #define MMEA1_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L 11604 #define MMEA1_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L 11605 #define MMEA1_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L 11606 #define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 11607 #define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 11608 #define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 11609 //MMEA1_DRAM_RD_CAM_CNTL 11610 #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 11611 #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 11612 #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 11613 #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 11614 #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 11615 #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 11616 #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 11617 #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 11618 #define MMEA1_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 11619 #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 11620 #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 11621 #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 11622 #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 11623 #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 11624 #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 11625 #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 11626 #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 11627 #define MMEA1_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 11628 //MMEA1_DRAM_WR_CAM_CNTL 11629 #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 11630 #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 11631 #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 11632 #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 11633 #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 11634 #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 11635 #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 11636 #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 11637 #define MMEA1_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 11638 #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 11639 #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 11640 #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 11641 #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 11642 #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 11643 #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 11644 #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 11645 #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 11646 #define MMEA1_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 11647 //MMEA1_DRAM_PAGE_BURST 11648 #define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 11649 #define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 11650 #define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 11651 #define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 11652 #define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL 11653 #define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 11654 #define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 11655 #define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L 11656 //MMEA1_DRAM_RD_PRI_AGE 11657 #define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 11658 #define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 11659 #define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 11660 #define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 11661 #define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 11662 #define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 11663 #define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 11664 #define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 11665 #define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 11666 #define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 11667 #define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 11668 #define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 11669 #define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 11670 #define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 11671 #define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 11672 #define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 11673 //MMEA1_DRAM_WR_PRI_AGE 11674 #define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 11675 #define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 11676 #define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 11677 #define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 11678 #define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 11679 #define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 11680 #define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 11681 #define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 11682 #define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 11683 #define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 11684 #define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 11685 #define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 11686 #define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 11687 #define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 11688 #define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 11689 #define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 11690 //MMEA1_DRAM_RD_PRI_QUEUING 11691 #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 11692 #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 11693 #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 11694 #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 11695 #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 11696 #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 11697 #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 11698 #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 11699 //MMEA1_DRAM_WR_PRI_QUEUING 11700 #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 11701 #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 11702 #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 11703 #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 11704 #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 11705 #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 11706 #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 11707 #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 11708 //MMEA1_DRAM_RD_PRI_FIXED 11709 #define MMEA1_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 11710 #define MMEA1_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 11711 #define MMEA1_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 11712 #define MMEA1_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 11713 #define MMEA1_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 11714 #define MMEA1_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 11715 #define MMEA1_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 11716 #define MMEA1_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 11717 //MMEA1_DRAM_WR_PRI_FIXED 11718 #define MMEA1_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 11719 #define MMEA1_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 11720 #define MMEA1_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 11721 #define MMEA1_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 11722 #define MMEA1_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 11723 #define MMEA1_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 11724 #define MMEA1_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 11725 #define MMEA1_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 11726 //MMEA1_DRAM_RD_PRI_URGENCY 11727 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 11728 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 11729 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 11730 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 11731 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 11732 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 11733 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 11734 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 11735 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 11736 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 11737 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 11738 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 11739 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 11740 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 11741 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 11742 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 11743 //MMEA1_DRAM_WR_PRI_URGENCY 11744 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 11745 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 11746 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 11747 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 11748 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 11749 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 11750 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 11751 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 11752 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 11753 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 11754 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 11755 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 11756 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 11757 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 11758 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 11759 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 11760 //MMEA1_DRAM_RD_PRI_QUANT_PRI1 11761 #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 11762 #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 11763 #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 11764 #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 11765 #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 11766 #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 11767 #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 11768 #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 11769 //MMEA1_DRAM_RD_PRI_QUANT_PRI2 11770 #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 11771 #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 11772 #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 11773 #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 11774 #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 11775 #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 11776 #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 11777 #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 11778 //MMEA1_DRAM_RD_PRI_QUANT_PRI3 11779 #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 11780 #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 11781 #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 11782 #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 11783 #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 11784 #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 11785 #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 11786 #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 11787 //MMEA1_DRAM_WR_PRI_QUANT_PRI1 11788 #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 11789 #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 11790 #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 11791 #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 11792 #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 11793 #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 11794 #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 11795 #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 11796 //MMEA1_DRAM_WR_PRI_QUANT_PRI2 11797 #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 11798 #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 11799 #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 11800 #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 11801 #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 11802 #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 11803 #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 11804 #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 11805 //MMEA1_DRAM_WR_PRI_QUANT_PRI3 11806 #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 11807 #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 11808 #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 11809 #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 11810 #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 11811 #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 11812 #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 11813 #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 11814 //MMEA1_GMI_RD_CLI2GRP_MAP0 11815 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 11816 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 11817 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 11818 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 11819 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 11820 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 11821 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 11822 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 11823 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 11824 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 11825 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 11826 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 11827 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 11828 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 11829 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 11830 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 11831 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 11832 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 11833 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 11834 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 11835 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 11836 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 11837 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 11838 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 11839 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 11840 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 11841 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 11842 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 11843 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 11844 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 11845 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 11846 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 11847 //MMEA1_GMI_RD_CLI2GRP_MAP1 11848 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 11849 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 11850 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 11851 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 11852 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 11853 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 11854 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 11855 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 11856 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 11857 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 11858 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 11859 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 11860 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 11861 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 11862 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 11863 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 11864 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 11865 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 11866 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 11867 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 11868 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 11869 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 11870 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 11871 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 11872 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 11873 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 11874 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 11875 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 11876 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 11877 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 11878 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 11879 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 11880 //MMEA1_GMI_WR_CLI2GRP_MAP0 11881 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 11882 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 11883 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 11884 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 11885 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 11886 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 11887 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 11888 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 11889 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 11890 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 11891 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 11892 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 11893 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 11894 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 11895 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 11896 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 11897 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 11898 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 11899 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 11900 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 11901 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 11902 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 11903 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 11904 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 11905 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 11906 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 11907 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 11908 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 11909 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 11910 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 11911 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 11912 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 11913 //MMEA1_GMI_WR_CLI2GRP_MAP1 11914 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 11915 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 11916 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 11917 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 11918 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 11919 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 11920 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 11921 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 11922 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 11923 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 11924 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 11925 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 11926 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 11927 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 11928 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 11929 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 11930 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 11931 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 11932 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 11933 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 11934 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 11935 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 11936 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 11937 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 11938 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 11939 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 11940 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 11941 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 11942 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 11943 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 11944 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 11945 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 11946 //MMEA1_GMI_RD_GRP2VC_MAP 11947 #define MMEA1_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 11948 #define MMEA1_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 11949 #define MMEA1_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 11950 #define MMEA1_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 11951 #define MMEA1_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 11952 #define MMEA1_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 11953 #define MMEA1_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 11954 #define MMEA1_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 11955 //MMEA1_GMI_WR_GRP2VC_MAP 11956 #define MMEA1_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 11957 #define MMEA1_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 11958 #define MMEA1_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 11959 #define MMEA1_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 11960 #define MMEA1_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 11961 #define MMEA1_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 11962 #define MMEA1_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 11963 #define MMEA1_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 11964 //MMEA1_GMI_RD_LAZY 11965 #define MMEA1_GMI_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 11966 #define MMEA1_GMI_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 11967 #define MMEA1_GMI_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 11968 #define MMEA1_GMI_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 11969 #define MMEA1_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 11970 #define MMEA1_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 11971 #define MMEA1_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 11972 #define MMEA1_GMI_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L 11973 #define MMEA1_GMI_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L 11974 #define MMEA1_GMI_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L 11975 #define MMEA1_GMI_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L 11976 #define MMEA1_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 11977 #define MMEA1_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 11978 #define MMEA1_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 11979 //MMEA1_GMI_WR_LAZY 11980 #define MMEA1_GMI_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 11981 #define MMEA1_GMI_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 11982 #define MMEA1_GMI_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 11983 #define MMEA1_GMI_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 11984 #define MMEA1_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 11985 #define MMEA1_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 11986 #define MMEA1_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 11987 #define MMEA1_GMI_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L 11988 #define MMEA1_GMI_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L 11989 #define MMEA1_GMI_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L 11990 #define MMEA1_GMI_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L 11991 #define MMEA1_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 11992 #define MMEA1_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 11993 #define MMEA1_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 11994 //MMEA1_GMI_RD_CAM_CNTL 11995 #define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 11996 #define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 11997 #define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 11998 #define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 11999 #define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 12000 #define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 12001 #define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 12002 #define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 12003 #define MMEA1_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 12004 #define MMEA1_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d 12005 #define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 12006 #define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 12007 #define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 12008 #define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 12009 #define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 12010 #define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 12011 #define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 12012 #define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 12013 #define MMEA1_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 12014 #define MMEA1_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L 12015 //MMEA1_GMI_WR_CAM_CNTL 12016 #define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 12017 #define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 12018 #define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 12019 #define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 12020 #define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 12021 #define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 12022 #define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 12023 #define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 12024 #define MMEA1_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 12025 #define MMEA1_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d 12026 #define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 12027 #define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 12028 #define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 12029 #define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 12030 #define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 12031 #define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 12032 #define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 12033 #define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 12034 #define MMEA1_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 12035 #define MMEA1_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L 12036 //MMEA1_GMI_PAGE_BURST 12037 #define MMEA1_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 12038 #define MMEA1_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 12039 #define MMEA1_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 12040 #define MMEA1_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 12041 #define MMEA1_GMI_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL 12042 #define MMEA1_GMI_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 12043 #define MMEA1_GMI_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 12044 #define MMEA1_GMI_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L 12045 //MMEA1_GMI_RD_PRI_AGE 12046 #define MMEA1_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 12047 #define MMEA1_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 12048 #define MMEA1_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 12049 #define MMEA1_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 12050 #define MMEA1_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 12051 #define MMEA1_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 12052 #define MMEA1_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 12053 #define MMEA1_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 12054 #define MMEA1_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 12055 #define MMEA1_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 12056 #define MMEA1_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 12057 #define MMEA1_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 12058 #define MMEA1_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 12059 #define MMEA1_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 12060 #define MMEA1_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 12061 #define MMEA1_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 12062 //MMEA1_GMI_WR_PRI_AGE 12063 #define MMEA1_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 12064 #define MMEA1_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 12065 #define MMEA1_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 12066 #define MMEA1_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 12067 #define MMEA1_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 12068 #define MMEA1_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 12069 #define MMEA1_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 12070 #define MMEA1_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 12071 #define MMEA1_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 12072 #define MMEA1_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 12073 #define MMEA1_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 12074 #define MMEA1_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 12075 #define MMEA1_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 12076 #define MMEA1_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 12077 #define MMEA1_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 12078 #define MMEA1_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 12079 //MMEA1_GMI_RD_PRI_QUEUING 12080 #define MMEA1_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 12081 #define MMEA1_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 12082 #define MMEA1_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 12083 #define MMEA1_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 12084 #define MMEA1_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 12085 #define MMEA1_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 12086 #define MMEA1_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 12087 #define MMEA1_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 12088 //MMEA1_GMI_WR_PRI_QUEUING 12089 #define MMEA1_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 12090 #define MMEA1_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 12091 #define MMEA1_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 12092 #define MMEA1_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 12093 #define MMEA1_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 12094 #define MMEA1_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 12095 #define MMEA1_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 12096 #define MMEA1_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 12097 //MMEA1_GMI_RD_PRI_FIXED 12098 #define MMEA1_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 12099 #define MMEA1_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 12100 #define MMEA1_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 12101 #define MMEA1_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 12102 #define MMEA1_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 12103 #define MMEA1_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 12104 #define MMEA1_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 12105 #define MMEA1_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 12106 //MMEA1_GMI_WR_PRI_FIXED 12107 #define MMEA1_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 12108 #define MMEA1_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 12109 #define MMEA1_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 12110 #define MMEA1_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 12111 #define MMEA1_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 12112 #define MMEA1_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 12113 #define MMEA1_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 12114 #define MMEA1_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 12115 //MMEA1_GMI_RD_PRI_URGENCY 12116 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 12117 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 12118 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 12119 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 12120 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 12121 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 12122 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 12123 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 12124 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 12125 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 12126 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 12127 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 12128 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 12129 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 12130 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 12131 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 12132 //MMEA1_GMI_WR_PRI_URGENCY 12133 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 12134 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 12135 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 12136 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 12137 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 12138 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 12139 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 12140 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 12141 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 12142 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 12143 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 12144 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 12145 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 12146 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 12147 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 12148 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 12149 //MMEA1_GMI_RD_PRI_URGENCY_MASKING 12150 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 12151 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 12152 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 12153 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 12154 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 12155 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 12156 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 12157 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 12158 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 12159 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 12160 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 12161 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 12162 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 12163 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 12164 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 12165 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 12166 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 12167 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 12168 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 12169 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 12170 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 12171 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 12172 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 12173 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 12174 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 12175 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 12176 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 12177 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 12178 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 12179 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 12180 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 12181 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 12182 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 12183 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 12184 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 12185 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 12186 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 12187 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 12188 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 12189 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 12190 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 12191 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 12192 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 12193 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 12194 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 12195 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 12196 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 12197 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 12198 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 12199 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 12200 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 12201 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 12202 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 12203 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 12204 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 12205 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 12206 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 12207 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 12208 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 12209 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 12210 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 12211 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 12212 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 12213 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 12214 //MMEA1_GMI_WR_PRI_URGENCY_MASKING 12215 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 12216 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 12217 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 12218 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 12219 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 12220 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 12221 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 12222 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 12223 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 12224 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 12225 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 12226 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 12227 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 12228 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 12229 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 12230 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 12231 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 12232 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 12233 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 12234 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 12235 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 12236 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 12237 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 12238 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 12239 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 12240 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 12241 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 12242 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 12243 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 12244 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 12245 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 12246 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 12247 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 12248 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 12249 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 12250 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 12251 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 12252 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 12253 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 12254 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 12255 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 12256 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 12257 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 12258 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 12259 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 12260 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 12261 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 12262 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 12263 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 12264 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 12265 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 12266 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 12267 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 12268 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 12269 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 12270 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 12271 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 12272 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 12273 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 12274 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 12275 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 12276 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 12277 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 12278 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 12279 //MMEA1_GMI_RD_PRI_QUANT_PRI1 12280 #define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 12281 #define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 12282 #define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 12283 #define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 12284 #define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 12285 #define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 12286 #define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 12287 #define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 12288 //MMEA1_GMI_RD_PRI_QUANT_PRI2 12289 #define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 12290 #define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 12291 #define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 12292 #define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 12293 #define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 12294 #define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 12295 #define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 12296 #define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 12297 //MMEA1_GMI_RD_PRI_QUANT_PRI3 12298 #define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 12299 #define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 12300 #define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 12301 #define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 12302 #define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 12303 #define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 12304 #define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 12305 #define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 12306 //MMEA1_GMI_WR_PRI_QUANT_PRI1 12307 #define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 12308 #define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 12309 #define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 12310 #define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 12311 #define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 12312 #define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 12313 #define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 12314 #define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 12315 //MMEA1_GMI_WR_PRI_QUANT_PRI2 12316 #define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 12317 #define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 12318 #define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 12319 #define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 12320 #define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 12321 #define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 12322 #define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 12323 #define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 12324 //MMEA1_GMI_WR_PRI_QUANT_PRI3 12325 #define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 12326 #define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 12327 #define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 12328 #define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 12329 #define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 12330 #define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 12331 #define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 12332 #define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 12333 //MMEA1_ADDRNORM_BASE_ADDR0 12334 #define MMEA1_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 12335 #define MMEA1_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 12336 #define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 12337 #define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x6 12338 #define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 12339 #define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 12340 #define MMEA1_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc 12341 #define MMEA1_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L 12342 #define MMEA1_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 12343 #define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000003CL 12344 #define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x000000C0L 12345 #define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L 12346 #define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L 12347 #define MMEA1_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L 12348 //MMEA1_ADDRNORM_LIMIT_ADDR0 12349 #define MMEA1_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 12350 #define MMEA1_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc 12351 #define MMEA1_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL 12352 #define MMEA1_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L 12353 //MMEA1_ADDRNORM_BASE_ADDR1 12354 #define MMEA1_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 12355 #define MMEA1_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 12356 #define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 12357 #define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x6 12358 #define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 12359 #define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 12360 #define MMEA1_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc 12361 #define MMEA1_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L 12362 #define MMEA1_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 12363 #define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000003CL 12364 #define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x000000C0L 12365 #define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L 12366 #define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L 12367 #define MMEA1_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L 12368 //MMEA1_ADDRNORM_LIMIT_ADDR1 12369 #define MMEA1_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 12370 #define MMEA1_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc 12371 #define MMEA1_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL 12372 #define MMEA1_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L 12373 //MMEA1_ADDRNORM_OFFSET_ADDR1 12374 #define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 12375 #define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 12376 #define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L 12377 #define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L 12378 //MMEA1_ADDRNORM_BASE_ADDR2 12379 #define MMEA1_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT 0x0 12380 #define MMEA1_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT 0x1 12381 #define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT 0x2 12382 #define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT 0x6 12383 #define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT 0x8 12384 #define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT 0x9 12385 #define MMEA1_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT 0xc 12386 #define MMEA1_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK 0x00000001L 12387 #define MMEA1_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 12388 #define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK 0x0000003CL 12389 #define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK 0x000000C0L 12390 #define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK 0x00000100L 12391 #define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK 0x00000E00L 12392 #define MMEA1_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK 0xFFFFF000L 12393 //MMEA1_ADDRNORM_LIMIT_ADDR2 12394 #define MMEA1_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT 0x0 12395 #define MMEA1_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT 0xc 12396 #define MMEA1_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK 0x0000001FL 12397 #define MMEA1_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK 0xFFFFF000L 12398 //MMEA1_ADDRNORM_BASE_ADDR3 12399 #define MMEA1_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT 0x0 12400 #define MMEA1_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT 0x1 12401 #define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT 0x2 12402 #define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT 0x6 12403 #define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT 0x8 12404 #define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT 0x9 12405 #define MMEA1_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT 0xc 12406 #define MMEA1_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK 0x00000001L 12407 #define MMEA1_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 12408 #define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK 0x0000003CL 12409 #define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK 0x000000C0L 12410 #define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK 0x00000100L 12411 #define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK 0x00000E00L 12412 #define MMEA1_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK 0xFFFFF000L 12413 //MMEA1_ADDRNORM_LIMIT_ADDR3 12414 #define MMEA1_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT 0x0 12415 #define MMEA1_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT 0xc 12416 #define MMEA1_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK 0x0000001FL 12417 #define MMEA1_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK 0xFFFFF000L 12418 //MMEA1_ADDRNORM_OFFSET_ADDR3 12419 #define MMEA1_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT 0x0 12420 #define MMEA1_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT 0x14 12421 #define MMEA1_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK 0x00000001L 12422 #define MMEA1_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK 0xFFF00000L 12423 //MMEA1_ADDRNORM_BASE_ADDR4 12424 #define MMEA1_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL__SHIFT 0x0 12425 #define MMEA1_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN__SHIFT 0x1 12426 #define MMEA1_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN__SHIFT 0x2 12427 #define MMEA1_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES__SHIFT 0x6 12428 #define MMEA1_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS__SHIFT 0x8 12429 #define MMEA1_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL__SHIFT 0x9 12430 #define MMEA1_ADDRNORM_BASE_ADDR4__BASE_ADDR__SHIFT 0xc 12431 #define MMEA1_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL_MASK 0x00000001L 12432 #define MMEA1_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 12433 #define MMEA1_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN_MASK 0x0000003CL 12434 #define MMEA1_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES_MASK 0x000000C0L 12435 #define MMEA1_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS_MASK 0x00000100L 12436 #define MMEA1_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL_MASK 0x00000E00L 12437 #define MMEA1_ADDRNORM_BASE_ADDR4__BASE_ADDR_MASK 0xFFFFF000L 12438 //MMEA1_ADDRNORM_LIMIT_ADDR4 12439 #define MMEA1_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID__SHIFT 0x0 12440 #define MMEA1_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR__SHIFT 0xc 12441 #define MMEA1_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID_MASK 0x0000001FL 12442 #define MMEA1_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR_MASK 0xFFFFF000L 12443 //MMEA1_ADDRNORM_BASE_ADDR5 12444 #define MMEA1_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL__SHIFT 0x0 12445 #define MMEA1_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN__SHIFT 0x1 12446 #define MMEA1_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN__SHIFT 0x2 12447 #define MMEA1_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES__SHIFT 0x6 12448 #define MMEA1_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS__SHIFT 0x8 12449 #define MMEA1_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL__SHIFT 0x9 12450 #define MMEA1_ADDRNORM_BASE_ADDR5__BASE_ADDR__SHIFT 0xc 12451 #define MMEA1_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL_MASK 0x00000001L 12452 #define MMEA1_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 12453 #define MMEA1_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN_MASK 0x0000003CL 12454 #define MMEA1_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES_MASK 0x000000C0L 12455 #define MMEA1_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS_MASK 0x00000100L 12456 #define MMEA1_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL_MASK 0x00000E00L 12457 #define MMEA1_ADDRNORM_BASE_ADDR5__BASE_ADDR_MASK 0xFFFFF000L 12458 //MMEA1_ADDRNORM_LIMIT_ADDR5 12459 #define MMEA1_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID__SHIFT 0x0 12460 #define MMEA1_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR__SHIFT 0xc 12461 #define MMEA1_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID_MASK 0x0000001FL 12462 #define MMEA1_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR_MASK 0xFFFFF000L 12463 //MMEA1_ADDRNORM_OFFSET_ADDR5 12464 #define MMEA1_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN__SHIFT 0x0 12465 #define MMEA1_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET__SHIFT 0x14 12466 #define MMEA1_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN_MASK 0x00000001L 12467 #define MMEA1_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_MASK 0xFFF00000L 12468 //MMEA1_ADDRNORMDRAM_HOLE_CNTL 12469 #define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 12470 #define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 12471 #define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L 12472 #define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L 12473 //MMEA1_ADDRNORMGMI_HOLE_CNTL 12474 #define MMEA1_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 12475 #define MMEA1_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 12476 #define MMEA1_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L 12477 #define MMEA1_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L 12478 //MMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG 12479 #define MMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0 12480 #define MMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6 12481 #define MMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL 12482 #define MMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L 12483 //MMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG 12484 #define MMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT 0x0 12485 #define MMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT 0x6 12486 #define MMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK 0x0000003FL 12487 #define MMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK 0x00000FC0L 12488 //MMEA1_ADDRDEC_BANK_CFG 12489 #define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 12490 #define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x6 12491 #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xc 12492 #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xf 12493 #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x12 12494 #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x13 12495 #define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000003FL 12496 #define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x00000FC0L 12497 #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00007000L 12498 #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x00038000L 12499 #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00040000L 12500 #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00080000L 12501 //MMEA1_ADDRDEC_MISC_CFG 12502 #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 12503 #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 12504 #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 12505 #define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 12506 #define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 12507 #define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc 12508 #define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11 12509 #define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16 12510 #define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18 12511 #define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a 12512 #define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d 12513 #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L 12514 #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L 12515 #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L 12516 #define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L 12517 #define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L 12518 #define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L 12519 #define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L 12520 #define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L 12521 #define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L 12522 #define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L 12523 #define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L 12524 //MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0 12525 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 12526 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 12527 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe 12528 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L 12529 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL 12530 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L 12531 //MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1 12532 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 12533 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 12534 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe 12535 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L 12536 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL 12537 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L 12538 //MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2 12539 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 12540 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 12541 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe 12542 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L 12543 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL 12544 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L 12545 //MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3 12546 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 12547 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 12548 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe 12549 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L 12550 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL 12551 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L 12552 //MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4 12553 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 12554 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 12555 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe 12556 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L 12557 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL 12558 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L 12559 //MMEA1_ADDRDECDRAM_ADDR_HASH_BANK5 12560 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT 0x0 12561 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR__SHIFT 0x1 12562 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR__SHIFT 0xe 12563 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE_MASK 0x00000001L 12564 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR_MASK 0x00003FFEL 12565 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR_MASK 0xFFFFC000L 12566 //MMEA1_ADDRDECDRAM_ADDR_HASH_PC 12567 #define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 12568 #define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 12569 #define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe 12570 #define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L 12571 #define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL 12572 #define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L 12573 //MMEA1_ADDRDECDRAM_ADDR_HASH_PC2 12574 #define MMEA1_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 12575 #define MMEA1_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000003FL 12576 //MMEA1_ADDRDECDRAM_ADDR_HASH_CS0 12577 #define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 12578 #define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 12579 #define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L 12580 #define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL 12581 //MMEA1_ADDRDECDRAM_ADDR_HASH_CS1 12582 #define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 12583 #define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 12584 #define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L 12585 #define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL 12586 //MMEA1_ADDRDECDRAM_HARVEST_ENABLE 12587 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 12588 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 12589 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 12590 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 12591 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 12592 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 12593 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L 12594 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L 12595 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L 12596 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L 12597 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L 12598 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L 12599 //MMEA1_ADDRDECGMI_ADDR_HASH_BANK0 12600 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 12601 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 12602 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe 12603 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L 12604 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL 12605 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L 12606 //MMEA1_ADDRDECGMI_ADDR_HASH_BANK1 12607 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 12608 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 12609 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe 12610 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L 12611 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL 12612 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L 12613 //MMEA1_ADDRDECGMI_ADDR_HASH_BANK2 12614 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 12615 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 12616 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe 12617 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L 12618 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL 12619 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L 12620 //MMEA1_ADDRDECGMI_ADDR_HASH_BANK3 12621 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 12622 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 12623 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe 12624 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L 12625 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL 12626 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L 12627 //MMEA1_ADDRDECGMI_ADDR_HASH_BANK4 12628 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 12629 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 12630 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe 12631 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L 12632 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL 12633 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L 12634 //MMEA1_ADDRDECGMI_ADDR_HASH_BANK5 12635 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT 0x0 12636 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR__SHIFT 0x1 12637 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR__SHIFT 0xe 12638 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE_MASK 0x00000001L 12639 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR_MASK 0x00003FFEL 12640 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR_MASK 0xFFFFC000L 12641 //MMEA1_ADDRDECGMI_ADDR_HASH_PC 12642 #define MMEA1_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 12643 #define MMEA1_ADDRDECGMI_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 12644 #define MMEA1_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe 12645 #define MMEA1_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L 12646 #define MMEA1_ADDRDECGMI_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL 12647 #define MMEA1_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L 12648 //MMEA1_ADDRDECGMI_ADDR_HASH_PC2 12649 #define MMEA1_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 12650 #define MMEA1_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000003FL 12651 //MMEA1_ADDRDECGMI_ADDR_HASH_CS0 12652 #define MMEA1_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 12653 #define MMEA1_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 12654 #define MMEA1_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L 12655 #define MMEA1_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL 12656 //MMEA1_ADDRDECGMI_ADDR_HASH_CS1 12657 #define MMEA1_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 12658 #define MMEA1_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 12659 #define MMEA1_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L 12660 #define MMEA1_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL 12661 //MMEA1_ADDRDECGMI_HARVEST_ENABLE 12662 #define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 12663 #define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 12664 #define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 12665 #define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 12666 #define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 12667 #define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 12668 #define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L 12669 #define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L 12670 #define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L 12671 #define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L 12672 #define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L 12673 #define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L 12674 //MMEA1_ADDRDEC0_BASE_ADDR_CS0 12675 #define MMEA1_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 12676 #define MMEA1_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 12677 #define MMEA1_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 12678 #define MMEA1_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 12679 //MMEA1_ADDRDEC0_BASE_ADDR_CS1 12680 #define MMEA1_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 12681 #define MMEA1_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 12682 #define MMEA1_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 12683 #define MMEA1_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 12684 //MMEA1_ADDRDEC0_BASE_ADDR_CS2 12685 #define MMEA1_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 12686 #define MMEA1_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 12687 #define MMEA1_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 12688 #define MMEA1_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 12689 //MMEA1_ADDRDEC0_BASE_ADDR_CS3 12690 #define MMEA1_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 12691 #define MMEA1_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 12692 #define MMEA1_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 12693 #define MMEA1_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 12694 //MMEA1_ADDRDEC0_BASE_ADDR_SECCS0 12695 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 12696 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 12697 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 12698 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 12699 //MMEA1_ADDRDEC0_BASE_ADDR_SECCS1 12700 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 12701 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 12702 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 12703 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 12704 //MMEA1_ADDRDEC0_BASE_ADDR_SECCS2 12705 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 12706 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 12707 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 12708 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 12709 //MMEA1_ADDRDEC0_BASE_ADDR_SECCS3 12710 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 12711 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 12712 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 12713 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 12714 //MMEA1_ADDRDEC0_ADDR_MASK_CS01 12715 #define MMEA1_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 12716 #define MMEA1_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 12717 //MMEA1_ADDRDEC0_ADDR_MASK_CS23 12718 #define MMEA1_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 12719 #define MMEA1_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 12720 //MMEA1_ADDRDEC0_ADDR_MASK_SECCS01 12721 #define MMEA1_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 12722 #define MMEA1_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 12723 //MMEA1_ADDRDEC0_ADDR_MASK_SECCS23 12724 #define MMEA1_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 12725 #define MMEA1_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 12726 //MMEA1_ADDRDEC0_ADDR_CFG_CS01 12727 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 12728 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 12729 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 12730 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 12731 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 12732 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 12733 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 12734 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 12735 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 12736 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 12737 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 12738 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 12739 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 12740 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 12741 //MMEA1_ADDRDEC0_ADDR_CFG_CS23 12742 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 12743 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 12744 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 12745 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 12746 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 12747 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 12748 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 12749 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 12750 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 12751 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 12752 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 12753 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 12754 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 12755 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 12756 //MMEA1_ADDRDEC0_ADDR_SEL_CS01 12757 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 12758 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 12759 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 12760 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc 12761 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 12762 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 12763 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 12764 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 12765 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 12766 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 12767 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 12768 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 12769 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 12770 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 12771 //MMEA1_ADDRDEC0_ADDR_SEL_CS23 12772 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 12773 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 12774 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 12775 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc 12776 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 12777 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 12778 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 12779 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 12780 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 12781 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 12782 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 12783 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 12784 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 12785 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 12786 //MMEA1_ADDRDEC0_ADDR_SEL2_CS01 12787 #define MMEA1_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 12788 #define MMEA1_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 12789 //MMEA1_ADDRDEC0_ADDR_SEL2_CS23 12790 #define MMEA1_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 12791 #define MMEA1_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 12792 //MMEA1_ADDRDEC0_COL_SEL_LO_CS01 12793 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 12794 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 12795 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 12796 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc 12797 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 12798 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 12799 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 12800 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 12801 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 12802 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 12803 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 12804 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 12805 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 12806 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 12807 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 12808 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 12809 //MMEA1_ADDRDEC0_COL_SEL_LO_CS23 12810 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 12811 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 12812 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 12813 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc 12814 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 12815 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 12816 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 12817 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 12818 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 12819 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 12820 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 12821 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 12822 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 12823 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 12824 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 12825 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 12826 //MMEA1_ADDRDEC0_COL_SEL_HI_CS01 12827 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 12828 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 12829 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 12830 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc 12831 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 12832 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 12833 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 12834 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 12835 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 12836 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 12837 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 12838 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 12839 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 12840 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 12841 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 12842 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 12843 //MMEA1_ADDRDEC0_COL_SEL_HI_CS23 12844 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 12845 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 12846 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 12847 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc 12848 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 12849 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 12850 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 12851 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 12852 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 12853 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 12854 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 12855 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 12856 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 12857 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 12858 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 12859 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 12860 //MMEA1_ADDRDEC0_RM_SEL_CS01 12861 #define MMEA1_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 12862 #define MMEA1_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 12863 #define MMEA1_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 12864 #define MMEA1_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 12865 #define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 12866 #define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 12867 #define MMEA1_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL 12868 #define MMEA1_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L 12869 #define MMEA1_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L 12870 #define MMEA1_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 12871 #define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 12872 #define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 12873 //MMEA1_ADDRDEC0_RM_SEL_CS23 12874 #define MMEA1_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 12875 #define MMEA1_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 12876 #define MMEA1_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 12877 #define MMEA1_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 12878 #define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 12879 #define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 12880 #define MMEA1_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL 12881 #define MMEA1_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L 12882 #define MMEA1_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L 12883 #define MMEA1_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 12884 #define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 12885 #define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 12886 //MMEA1_ADDRDEC0_RM_SEL_SECCS01 12887 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 12888 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 12889 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 12890 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 12891 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 12892 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 12893 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 12894 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 12895 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 12896 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 12897 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 12898 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 12899 //MMEA1_ADDRDEC0_RM_SEL_SECCS23 12900 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 12901 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 12902 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 12903 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 12904 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 12905 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 12906 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 12907 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 12908 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 12909 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 12910 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 12911 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 12912 //MMEA1_ADDRDEC1_BASE_ADDR_CS0 12913 #define MMEA1_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 12914 #define MMEA1_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 12915 #define MMEA1_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 12916 #define MMEA1_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 12917 //MMEA1_ADDRDEC1_BASE_ADDR_CS1 12918 #define MMEA1_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 12919 #define MMEA1_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 12920 #define MMEA1_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 12921 #define MMEA1_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 12922 //MMEA1_ADDRDEC1_BASE_ADDR_CS2 12923 #define MMEA1_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 12924 #define MMEA1_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 12925 #define MMEA1_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 12926 #define MMEA1_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 12927 //MMEA1_ADDRDEC1_BASE_ADDR_CS3 12928 #define MMEA1_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 12929 #define MMEA1_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 12930 #define MMEA1_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 12931 #define MMEA1_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 12932 //MMEA1_ADDRDEC1_BASE_ADDR_SECCS0 12933 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 12934 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 12935 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 12936 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 12937 //MMEA1_ADDRDEC1_BASE_ADDR_SECCS1 12938 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 12939 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 12940 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 12941 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 12942 //MMEA1_ADDRDEC1_BASE_ADDR_SECCS2 12943 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 12944 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 12945 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 12946 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 12947 //MMEA1_ADDRDEC1_BASE_ADDR_SECCS3 12948 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 12949 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 12950 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 12951 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 12952 //MMEA1_ADDRDEC1_ADDR_MASK_CS01 12953 #define MMEA1_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 12954 #define MMEA1_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 12955 //MMEA1_ADDRDEC1_ADDR_MASK_CS23 12956 #define MMEA1_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 12957 #define MMEA1_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 12958 //MMEA1_ADDRDEC1_ADDR_MASK_SECCS01 12959 #define MMEA1_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 12960 #define MMEA1_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 12961 //MMEA1_ADDRDEC1_ADDR_MASK_SECCS23 12962 #define MMEA1_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 12963 #define MMEA1_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 12964 //MMEA1_ADDRDEC1_ADDR_CFG_CS01 12965 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 12966 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 12967 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 12968 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 12969 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 12970 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 12971 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 12972 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 12973 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 12974 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 12975 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 12976 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 12977 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 12978 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 12979 //MMEA1_ADDRDEC1_ADDR_CFG_CS23 12980 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 12981 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 12982 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 12983 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 12984 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 12985 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 12986 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 12987 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 12988 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 12989 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 12990 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 12991 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 12992 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 12993 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 12994 //MMEA1_ADDRDEC1_ADDR_SEL_CS01 12995 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 12996 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 12997 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 12998 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc 12999 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 13000 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 13001 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 13002 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 13003 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 13004 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 13005 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 13006 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 13007 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 13008 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 13009 //MMEA1_ADDRDEC1_ADDR_SEL_CS23 13010 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 13011 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 13012 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 13013 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc 13014 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 13015 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 13016 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 13017 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 13018 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 13019 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 13020 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 13021 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 13022 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 13023 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 13024 //MMEA1_ADDRDEC1_ADDR_SEL2_CS01 13025 #define MMEA1_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 13026 #define MMEA1_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 13027 //MMEA1_ADDRDEC1_ADDR_SEL2_CS23 13028 #define MMEA1_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 13029 #define MMEA1_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 13030 //MMEA1_ADDRDEC1_COL_SEL_LO_CS01 13031 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 13032 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 13033 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 13034 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc 13035 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 13036 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 13037 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 13038 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 13039 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 13040 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 13041 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 13042 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 13043 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 13044 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 13045 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 13046 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 13047 //MMEA1_ADDRDEC1_COL_SEL_LO_CS23 13048 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 13049 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 13050 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 13051 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc 13052 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 13053 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 13054 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 13055 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 13056 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 13057 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 13058 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 13059 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 13060 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 13061 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 13062 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 13063 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 13064 //MMEA1_ADDRDEC1_COL_SEL_HI_CS01 13065 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 13066 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 13067 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 13068 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc 13069 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 13070 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 13071 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 13072 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 13073 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 13074 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 13075 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 13076 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 13077 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 13078 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 13079 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 13080 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 13081 //MMEA1_ADDRDEC1_COL_SEL_HI_CS23 13082 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 13083 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 13084 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 13085 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc 13086 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 13087 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 13088 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 13089 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 13090 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 13091 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 13092 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 13093 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 13094 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 13095 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 13096 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 13097 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 13098 //MMEA1_ADDRDEC1_RM_SEL_CS01 13099 #define MMEA1_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 13100 #define MMEA1_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 13101 #define MMEA1_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 13102 #define MMEA1_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 13103 #define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 13104 #define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 13105 #define MMEA1_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL 13106 #define MMEA1_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L 13107 #define MMEA1_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L 13108 #define MMEA1_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 13109 #define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 13110 #define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 13111 //MMEA1_ADDRDEC1_RM_SEL_CS23 13112 #define MMEA1_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 13113 #define MMEA1_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 13114 #define MMEA1_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 13115 #define MMEA1_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 13116 #define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 13117 #define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 13118 #define MMEA1_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL 13119 #define MMEA1_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L 13120 #define MMEA1_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L 13121 #define MMEA1_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 13122 #define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 13123 #define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 13124 //MMEA1_ADDRDEC1_RM_SEL_SECCS01 13125 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 13126 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 13127 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 13128 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 13129 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 13130 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 13131 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 13132 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 13133 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 13134 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 13135 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 13136 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 13137 //MMEA1_ADDRDEC1_RM_SEL_SECCS23 13138 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 13139 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 13140 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 13141 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 13142 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 13143 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 13144 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 13145 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 13146 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 13147 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 13148 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 13149 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 13150 //MMEA1_ADDRDEC2_BASE_ADDR_CS0 13151 #define MMEA1_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 13152 #define MMEA1_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 13153 #define MMEA1_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 13154 #define MMEA1_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 13155 //MMEA1_ADDRDEC2_BASE_ADDR_CS1 13156 #define MMEA1_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 13157 #define MMEA1_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 13158 #define MMEA1_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 13159 #define MMEA1_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 13160 //MMEA1_ADDRDEC2_BASE_ADDR_CS2 13161 #define MMEA1_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 13162 #define MMEA1_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 13163 #define MMEA1_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 13164 #define MMEA1_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 13165 //MMEA1_ADDRDEC2_BASE_ADDR_CS3 13166 #define MMEA1_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 13167 #define MMEA1_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 13168 #define MMEA1_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 13169 #define MMEA1_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 13170 //MMEA1_ADDRDEC2_BASE_ADDR_SECCS0 13171 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 13172 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 13173 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 13174 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 13175 //MMEA1_ADDRDEC2_BASE_ADDR_SECCS1 13176 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 13177 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 13178 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 13179 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 13180 //MMEA1_ADDRDEC2_BASE_ADDR_SECCS2 13181 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 13182 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 13183 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 13184 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 13185 //MMEA1_ADDRDEC2_BASE_ADDR_SECCS3 13186 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 13187 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 13188 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 13189 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 13190 //MMEA1_ADDRDEC2_ADDR_MASK_CS01 13191 #define MMEA1_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 13192 #define MMEA1_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 13193 //MMEA1_ADDRDEC2_ADDR_MASK_CS23 13194 #define MMEA1_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 13195 #define MMEA1_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 13196 //MMEA1_ADDRDEC2_ADDR_MASK_SECCS01 13197 #define MMEA1_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 13198 #define MMEA1_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 13199 //MMEA1_ADDRDEC2_ADDR_MASK_SECCS23 13200 #define MMEA1_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 13201 #define MMEA1_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 13202 //MMEA1_ADDRDEC2_ADDR_CFG_CS01 13203 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 13204 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 13205 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 13206 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 13207 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 13208 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 13209 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 13210 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 13211 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 13212 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 13213 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 13214 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 13215 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 13216 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 13217 //MMEA1_ADDRDEC2_ADDR_CFG_CS23 13218 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 13219 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 13220 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 13221 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 13222 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 13223 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 13224 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 13225 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 13226 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 13227 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 13228 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 13229 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 13230 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 13231 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 13232 //MMEA1_ADDRDEC2_ADDR_SEL_CS01 13233 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT 0x0 13234 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT 0x4 13235 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT 0x8 13236 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT 0xc 13237 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT 0x10 13238 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 13239 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 13240 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 13241 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 13242 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 13243 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 13244 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 13245 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 13246 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 13247 //MMEA1_ADDRDEC2_ADDR_SEL_CS23 13248 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT 0x0 13249 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT 0x4 13250 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT 0x8 13251 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT 0xc 13252 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT 0x10 13253 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 13254 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 13255 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 13256 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 13257 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 13258 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 13259 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 13260 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 13261 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 13262 //MMEA1_ADDRDEC2_ADDR_SEL2_CS01 13263 #define MMEA1_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 13264 #define MMEA1_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 13265 //MMEA1_ADDRDEC2_ADDR_SEL2_CS23 13266 #define MMEA1_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 13267 #define MMEA1_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 13268 //MMEA1_ADDRDEC2_COL_SEL_LO_CS01 13269 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT 0x0 13270 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT 0x4 13271 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT 0x8 13272 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT 0xc 13273 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT 0x10 13274 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT 0x14 13275 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT 0x18 13276 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 13277 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 13278 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 13279 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 13280 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 13281 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 13282 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 13283 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 13284 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 13285 //MMEA1_ADDRDEC2_COL_SEL_LO_CS23 13286 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT 0x0 13287 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT 0x4 13288 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT 0x8 13289 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT 0xc 13290 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT 0x10 13291 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT 0x14 13292 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT 0x18 13293 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 13294 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 13295 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 13296 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 13297 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 13298 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 13299 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 13300 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 13301 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 13302 //MMEA1_ADDRDEC2_COL_SEL_HI_CS01 13303 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT 0x0 13304 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT 0x4 13305 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT 0x8 13306 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT 0xc 13307 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT 0x10 13308 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT 0x14 13309 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT 0x18 13310 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 13311 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 13312 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 13313 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 13314 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 13315 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 13316 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 13317 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 13318 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 13319 //MMEA1_ADDRDEC2_COL_SEL_HI_CS23 13320 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT 0x0 13321 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT 0x4 13322 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT 0x8 13323 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT 0xc 13324 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT 0x10 13325 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT 0x14 13326 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT 0x18 13327 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 13328 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 13329 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 13330 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 13331 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 13332 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 13333 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 13334 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 13335 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 13336 //MMEA1_ADDRDEC2_RM_SEL_CS01 13337 #define MMEA1_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT 0x0 13338 #define MMEA1_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT 0x4 13339 #define MMEA1_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT 0x8 13340 #define MMEA1_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 13341 #define MMEA1_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 13342 #define MMEA1_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 13343 #define MMEA1_ADDRDEC2_RM_SEL_CS01__RM0_MASK 0x0000000FL 13344 #define MMEA1_ADDRDEC2_RM_SEL_CS01__RM1_MASK 0x000000F0L 13345 #define MMEA1_ADDRDEC2_RM_SEL_CS01__RM2_MASK 0x00000F00L 13346 #define MMEA1_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 13347 #define MMEA1_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 13348 #define MMEA1_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 13349 //MMEA1_ADDRDEC2_RM_SEL_CS23 13350 #define MMEA1_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT 0x0 13351 #define MMEA1_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT 0x4 13352 #define MMEA1_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT 0x8 13353 #define MMEA1_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 13354 #define MMEA1_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 13355 #define MMEA1_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 13356 #define MMEA1_ADDRDEC2_RM_SEL_CS23__RM0_MASK 0x0000000FL 13357 #define MMEA1_ADDRDEC2_RM_SEL_CS23__RM1_MASK 0x000000F0L 13358 #define MMEA1_ADDRDEC2_RM_SEL_CS23__RM2_MASK 0x00000F00L 13359 #define MMEA1_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 13360 #define MMEA1_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 13361 #define MMEA1_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 13362 //MMEA1_ADDRDEC2_RM_SEL_SECCS01 13363 #define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT 0x0 13364 #define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT 0x4 13365 #define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT 0x8 13366 #define MMEA1_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 13367 #define MMEA1_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 13368 #define MMEA1_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 13369 #define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 13370 #define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 13371 #define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 13372 #define MMEA1_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 13373 #define MMEA1_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 13374 #define MMEA1_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 13375 //MMEA1_ADDRDEC2_RM_SEL_SECCS23 13376 #define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT 0x0 13377 #define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT 0x4 13378 #define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT 0x8 13379 #define MMEA1_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 13380 #define MMEA1_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 13381 #define MMEA1_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 13382 #define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 13383 #define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 13384 #define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 13385 #define MMEA1_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 13386 #define MMEA1_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 13387 #define MMEA1_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 13388 //MMEA1_ADDRNORMDRAM_GLOBAL_CNTL 13389 #define MMEA1_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT 0x14 13390 #define MMEA1_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT 0x15 13391 #define MMEA1_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT 0x16 13392 #define MMEA1_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK 0x00100000L 13393 #define MMEA1_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK 0x00200000L 13394 #define MMEA1_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK 0x00400000L 13395 //MMEA1_ADDRNORMGMI_GLOBAL_CNTL 13396 #define MMEA1_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT 0x14 13397 #define MMEA1_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT 0x15 13398 #define MMEA1_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT 0x16 13399 #define MMEA1_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK 0x00100000L 13400 #define MMEA1_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK 0x00200000L 13401 #define MMEA1_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK 0x00400000L 13402 //MMEA1_IO_RD_CLI2GRP_MAP0 13403 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 13404 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 13405 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 13406 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 13407 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 13408 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 13409 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 13410 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 13411 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 13412 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 13413 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 13414 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 13415 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 13416 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 13417 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 13418 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 13419 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 13420 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 13421 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 13422 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 13423 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 13424 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 13425 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 13426 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 13427 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 13428 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 13429 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 13430 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 13431 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 13432 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 13433 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 13434 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 13435 //MMEA1_IO_RD_CLI2GRP_MAP1 13436 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 13437 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 13438 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 13439 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 13440 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 13441 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 13442 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 13443 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 13444 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 13445 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 13446 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 13447 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 13448 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 13449 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 13450 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 13451 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 13452 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 13453 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 13454 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 13455 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 13456 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 13457 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 13458 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 13459 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 13460 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 13461 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 13462 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 13463 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 13464 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 13465 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 13466 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 13467 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 13468 //MMEA1_IO_WR_CLI2GRP_MAP0 13469 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 13470 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 13471 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 13472 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 13473 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 13474 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 13475 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 13476 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 13477 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 13478 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 13479 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 13480 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 13481 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 13482 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 13483 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 13484 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 13485 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 13486 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 13487 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 13488 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 13489 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 13490 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 13491 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 13492 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 13493 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 13494 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 13495 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 13496 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 13497 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 13498 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 13499 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 13500 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 13501 //MMEA1_IO_WR_CLI2GRP_MAP1 13502 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 13503 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 13504 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 13505 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 13506 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 13507 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 13508 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 13509 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 13510 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 13511 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 13512 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 13513 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 13514 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 13515 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 13516 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 13517 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 13518 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 13519 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 13520 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 13521 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 13522 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 13523 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 13524 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 13525 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 13526 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 13527 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 13528 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 13529 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 13530 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 13531 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 13532 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 13533 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 13534 //MMEA1_IO_RD_COMBINE_FLUSH 13535 #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 13536 #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 13537 #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 13538 #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 13539 #define MMEA1_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT 0x10 13540 #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 13541 #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 13542 #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 13543 #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 13544 #define MMEA1_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK 0x00010000L 13545 //MMEA1_IO_WR_COMBINE_FLUSH 13546 #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 13547 #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 13548 #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 13549 #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 13550 #define MMEA1_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT 0x10 13551 #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 13552 #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 13553 #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 13554 #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 13555 #define MMEA1_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK 0x00010000L 13556 //MMEA1_IO_GROUP_BURST 13557 #define MMEA1_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 13558 #define MMEA1_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 13559 #define MMEA1_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 13560 #define MMEA1_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 13561 #define MMEA1_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL 13562 #define MMEA1_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 13563 #define MMEA1_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 13564 #define MMEA1_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L 13565 //MMEA1_IO_RD_PRI_AGE 13566 #define MMEA1_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 13567 #define MMEA1_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 13568 #define MMEA1_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 13569 #define MMEA1_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 13570 #define MMEA1_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 13571 #define MMEA1_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 13572 #define MMEA1_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 13573 #define MMEA1_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 13574 #define MMEA1_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 13575 #define MMEA1_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 13576 #define MMEA1_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 13577 #define MMEA1_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 13578 #define MMEA1_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 13579 #define MMEA1_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 13580 #define MMEA1_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 13581 #define MMEA1_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 13582 //MMEA1_IO_WR_PRI_AGE 13583 #define MMEA1_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 13584 #define MMEA1_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 13585 #define MMEA1_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 13586 #define MMEA1_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 13587 #define MMEA1_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 13588 #define MMEA1_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 13589 #define MMEA1_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 13590 #define MMEA1_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 13591 #define MMEA1_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 13592 #define MMEA1_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 13593 #define MMEA1_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 13594 #define MMEA1_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 13595 #define MMEA1_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 13596 #define MMEA1_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 13597 #define MMEA1_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 13598 #define MMEA1_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 13599 //MMEA1_IO_RD_PRI_QUEUING 13600 #define MMEA1_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 13601 #define MMEA1_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 13602 #define MMEA1_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 13603 #define MMEA1_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 13604 #define MMEA1_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 13605 #define MMEA1_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 13606 #define MMEA1_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 13607 #define MMEA1_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 13608 //MMEA1_IO_WR_PRI_QUEUING 13609 #define MMEA1_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 13610 #define MMEA1_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 13611 #define MMEA1_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 13612 #define MMEA1_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 13613 #define MMEA1_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 13614 #define MMEA1_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 13615 #define MMEA1_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 13616 #define MMEA1_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 13617 //MMEA1_IO_RD_PRI_FIXED 13618 #define MMEA1_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 13619 #define MMEA1_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 13620 #define MMEA1_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 13621 #define MMEA1_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 13622 #define MMEA1_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 13623 #define MMEA1_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 13624 #define MMEA1_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 13625 #define MMEA1_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 13626 //MMEA1_IO_WR_PRI_FIXED 13627 #define MMEA1_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 13628 #define MMEA1_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 13629 #define MMEA1_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 13630 #define MMEA1_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 13631 #define MMEA1_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 13632 #define MMEA1_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 13633 #define MMEA1_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 13634 #define MMEA1_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 13635 //MMEA1_IO_RD_PRI_URGENCY 13636 #define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 13637 #define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 13638 #define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 13639 #define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 13640 #define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 13641 #define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 13642 #define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 13643 #define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 13644 #define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 13645 #define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 13646 #define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 13647 #define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 13648 #define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 13649 #define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 13650 #define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 13651 #define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 13652 //MMEA1_IO_WR_PRI_URGENCY 13653 #define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 13654 #define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 13655 #define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 13656 #define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 13657 #define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 13658 #define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 13659 #define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 13660 #define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 13661 #define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 13662 #define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 13663 #define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 13664 #define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 13665 #define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 13666 #define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 13667 #define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 13668 #define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 13669 //MMEA1_IO_RD_PRI_URGENCY_MASKING 13670 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 13671 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 13672 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 13673 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 13674 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 13675 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 13676 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 13677 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 13678 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 13679 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 13680 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 13681 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 13682 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 13683 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 13684 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 13685 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 13686 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 13687 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 13688 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 13689 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 13690 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 13691 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 13692 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 13693 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 13694 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 13695 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 13696 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 13697 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 13698 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 13699 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 13700 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 13701 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 13702 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 13703 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 13704 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 13705 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 13706 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 13707 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 13708 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 13709 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 13710 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 13711 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 13712 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 13713 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 13714 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 13715 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 13716 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 13717 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 13718 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 13719 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 13720 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 13721 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 13722 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 13723 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 13724 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 13725 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 13726 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 13727 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 13728 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 13729 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 13730 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 13731 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 13732 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 13733 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 13734 //MMEA1_IO_WR_PRI_URGENCY_MASKING 13735 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 13736 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 13737 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 13738 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 13739 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 13740 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 13741 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 13742 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 13743 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 13744 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 13745 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 13746 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 13747 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 13748 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 13749 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 13750 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 13751 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 13752 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 13753 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 13754 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 13755 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 13756 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 13757 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 13758 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 13759 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 13760 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 13761 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 13762 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 13763 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 13764 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 13765 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 13766 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 13767 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 13768 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 13769 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 13770 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 13771 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 13772 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 13773 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 13774 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 13775 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 13776 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 13777 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 13778 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 13779 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 13780 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 13781 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 13782 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 13783 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 13784 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 13785 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 13786 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 13787 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 13788 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 13789 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 13790 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 13791 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 13792 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 13793 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 13794 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 13795 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 13796 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 13797 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 13798 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 13799 //MMEA1_IO_RD_PRI_QUANT_PRI1 13800 #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 13801 #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 13802 #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 13803 #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 13804 #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 13805 #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 13806 #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 13807 #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 13808 //MMEA1_IO_RD_PRI_QUANT_PRI2 13809 #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 13810 #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 13811 #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 13812 #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 13813 #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 13814 #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 13815 #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 13816 #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 13817 //MMEA1_IO_RD_PRI_QUANT_PRI3 13818 #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 13819 #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 13820 #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 13821 #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 13822 #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 13823 #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 13824 #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 13825 #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 13826 //MMEA1_IO_WR_PRI_QUANT_PRI1 13827 #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 13828 #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 13829 #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 13830 #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 13831 #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 13832 #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 13833 #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 13834 #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 13835 //MMEA1_IO_WR_PRI_QUANT_PRI2 13836 #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 13837 #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 13838 #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 13839 #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 13840 #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 13841 #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 13842 #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 13843 #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 13844 //MMEA1_IO_WR_PRI_QUANT_PRI3 13845 #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 13846 #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 13847 #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 13848 #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 13849 #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 13850 #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 13851 #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 13852 #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 13853 //MMEA1_SDP_ARB_DRAM 13854 #define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 13855 #define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 13856 #define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 13857 #define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 13858 #define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 13859 #define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 13860 #define MMEA1_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 13861 #define MMEA1_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 13862 #define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL 13863 #define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L 13864 #define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L 13865 #define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L 13866 #define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L 13867 #define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L 13868 #define MMEA1_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L 13869 #define MMEA1_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L 13870 //MMEA1_SDP_ARB_GMI 13871 #define MMEA1_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 13872 #define MMEA1_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 13873 #define MMEA1_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT 0x10 13874 #define MMEA1_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT 0x11 13875 #define MMEA1_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT 0x12 13876 #define MMEA1_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT 0x13 13877 #define MMEA1_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT 0x14 13878 #define MMEA1_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 13879 #define MMEA1_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT 0x16 13880 #define MMEA1_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL 13881 #define MMEA1_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L 13882 #define MMEA1_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK 0x00010000L 13883 #define MMEA1_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK 0x00020000L 13884 #define MMEA1_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK 0x00040000L 13885 #define MMEA1_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK 0x00080000L 13886 #define MMEA1_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK 0x00100000L 13887 #define MMEA1_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L 13888 #define MMEA1_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK 0x00400000L 13889 //MMEA1_SDP_ARB_FINAL 13890 #define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 13891 #define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 13892 #define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa 13893 #define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf 13894 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 13895 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 13896 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 13897 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 13898 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 13899 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 13900 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 13901 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 13902 #define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 13903 #define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a 13904 #define MMEA1_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1b 13905 #define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL 13906 #define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L 13907 #define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L 13908 #define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L 13909 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L 13910 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L 13911 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L 13912 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L 13913 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L 13914 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L 13915 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L 13916 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L 13917 #define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L 13918 #define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L 13919 #define MMEA1_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x08000000L 13920 //MMEA1_SDP_DRAM_PRIORITY 13921 #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 13922 #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 13923 #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 13924 #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 13925 #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 13926 #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 13927 #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 13928 #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 13929 #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 13930 #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 13931 #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 13932 #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 13933 #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 13934 #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 13935 #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 13936 #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 13937 //MMEA1_SDP_GMI_PRIORITY 13938 #define MMEA1_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 13939 #define MMEA1_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 13940 #define MMEA1_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 13941 #define MMEA1_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 13942 #define MMEA1_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 13943 #define MMEA1_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 13944 #define MMEA1_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 13945 #define MMEA1_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 13946 #define MMEA1_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 13947 #define MMEA1_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 13948 #define MMEA1_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 13949 #define MMEA1_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 13950 #define MMEA1_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 13951 #define MMEA1_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 13952 #define MMEA1_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 13953 #define MMEA1_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 13954 //MMEA1_SDP_IO_PRIORITY 13955 #define MMEA1_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 13956 #define MMEA1_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 13957 #define MMEA1_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 13958 #define MMEA1_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 13959 #define MMEA1_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 13960 #define MMEA1_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 13961 #define MMEA1_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 13962 #define MMEA1_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 13963 #define MMEA1_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 13964 #define MMEA1_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 13965 #define MMEA1_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 13966 #define MMEA1_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 13967 #define MMEA1_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 13968 #define MMEA1_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 13969 #define MMEA1_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 13970 #define MMEA1_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 13971 //MMEA1_SDP_CREDITS 13972 #define MMEA1_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 13973 #define MMEA1_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 13974 #define MMEA1_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 13975 #define MMEA1_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL 13976 #define MMEA1_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L 13977 #define MMEA1_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L 13978 //MMEA1_SDP_TAG_RESERVE0 13979 #define MMEA1_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 13980 #define MMEA1_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 13981 #define MMEA1_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 13982 #define MMEA1_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 13983 #define MMEA1_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL 13984 #define MMEA1_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L 13985 #define MMEA1_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L 13986 #define MMEA1_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L 13987 //MMEA1_SDP_TAG_RESERVE1 13988 #define MMEA1_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 13989 #define MMEA1_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 13990 #define MMEA1_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 13991 #define MMEA1_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 13992 #define MMEA1_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL 13993 #define MMEA1_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L 13994 #define MMEA1_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L 13995 #define MMEA1_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L 13996 //MMEA1_SDP_VCC_RESERVE0 13997 #define MMEA1_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 13998 #define MMEA1_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 13999 #define MMEA1_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc 14000 #define MMEA1_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 14001 #define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 14002 #define MMEA1_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 14003 #define MMEA1_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 14004 #define MMEA1_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 14005 #define MMEA1_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 14006 #define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 14007 //MMEA1_SDP_VCC_RESERVE1 14008 #define MMEA1_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 14009 #define MMEA1_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 14010 #define MMEA1_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc 14011 #define MMEA1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 14012 #define MMEA1_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 14013 #define MMEA1_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 14014 #define MMEA1_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 14015 #define MMEA1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 14016 //MMEA1_SDP_VCD_RESERVE0 14017 #define MMEA1_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 14018 #define MMEA1_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 14019 #define MMEA1_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc 14020 #define MMEA1_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 14021 #define MMEA1_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 14022 #define MMEA1_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 14023 #define MMEA1_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 14024 #define MMEA1_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 14025 #define MMEA1_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 14026 #define MMEA1_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 14027 //MMEA1_SDP_VCD_RESERVE1 14028 #define MMEA1_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 14029 #define MMEA1_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 14030 #define MMEA1_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc 14031 #define MMEA1_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 14032 #define MMEA1_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 14033 #define MMEA1_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 14034 #define MMEA1_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 14035 #define MMEA1_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 14036 //MMEA1_SDP_REQ_CNTL 14037 #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 14038 #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 14039 #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 14040 #define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 14041 #define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 14042 #define MMEA1_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 14043 #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L 14044 #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L 14045 #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L 14046 #define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L 14047 #define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L 14048 #define MMEA1_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L 14049 //MMEA1_MISC 14050 #define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 14051 #define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 14052 #define MMEA1_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 14053 #define MMEA1_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 14054 #define MMEA1_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 14055 #define MMEA1_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 14056 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 14057 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 14058 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 14059 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 14060 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa 14061 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb 14062 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc 14063 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd 14064 #define MMEA1_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe 14065 #define MMEA1_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf 14066 #define MMEA1_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 14067 #define MMEA1_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 14068 #define MMEA1_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 14069 #define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a 14070 #define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b 14071 #define MMEA1_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c 14072 #define MMEA1_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d 14073 #define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e 14074 #define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f 14075 #define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L 14076 #define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L 14077 #define MMEA1_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L 14078 #define MMEA1_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L 14079 #define MMEA1_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L 14080 #define MMEA1_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L 14081 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L 14082 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L 14083 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L 14084 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L 14085 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L 14086 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L 14087 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L 14088 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L 14089 #define MMEA1_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L 14090 #define MMEA1_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L 14091 #define MMEA1_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L 14092 #define MMEA1_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L 14093 #define MMEA1_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L 14094 #define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L 14095 #define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L 14096 #define MMEA1_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L 14097 #define MMEA1_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L 14098 #define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L 14099 #define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L 14100 //MMEA1_LATENCY_SAMPLING 14101 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 14102 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 14103 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 14104 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 14105 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 14106 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 14107 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 14108 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 14109 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 14110 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 14111 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa 14112 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb 14113 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc 14114 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd 14115 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe 14116 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 14117 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L 14118 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L 14119 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L 14120 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L 14121 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L 14122 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L 14123 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L 14124 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L 14125 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L 14126 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L 14127 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L 14128 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L 14129 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L 14130 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L 14131 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L 14132 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L 14133 //MMEA1_PERFCOUNTER_LO 14134 #define MMEA1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 14135 #define MMEA1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 14136 //MMEA1_PERFCOUNTER_HI 14137 #define MMEA1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 14138 #define MMEA1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 14139 #define MMEA1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 14140 #define MMEA1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 14141 //MMEA1_PERFCOUNTER0_CFG 14142 #define MMEA1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 14143 #define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 14144 #define MMEA1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 14145 #define MMEA1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 14146 #define MMEA1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 14147 #define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 14148 #define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 14149 #define MMEA1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 14150 #define MMEA1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 14151 #define MMEA1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 14152 //MMEA1_PERFCOUNTER1_CFG 14153 #define MMEA1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 14154 #define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 14155 #define MMEA1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 14156 #define MMEA1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 14157 #define MMEA1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 14158 #define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 14159 #define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 14160 #define MMEA1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 14161 #define MMEA1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 14162 #define MMEA1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 14163 //MMEA1_PERFCOUNTER_RSLT_CNTL 14164 #define MMEA1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 14165 #define MMEA1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 14166 #define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 14167 #define MMEA1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 14168 #define MMEA1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 14169 #define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 14170 #define MMEA1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 14171 #define MMEA1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 14172 #define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 14173 #define MMEA1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 14174 #define MMEA1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 14175 #define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 14176 //MMEA1_EDC_CNT 14177 #define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 14178 #define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 14179 #define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 14180 #define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 14181 #define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 14182 #define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa 14183 #define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc 14184 #define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe 14185 #define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 14186 #define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 14187 #define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 14188 #define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 14189 #define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 14190 #define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a 14191 #define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c 14192 #define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 14193 #define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 14194 #define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 14195 #define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 14196 #define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 14197 #define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 14198 #define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L 14199 #define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L 14200 #define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L 14201 #define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L 14202 #define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L 14203 #define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L 14204 #define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L 14205 #define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L 14206 #define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L 14207 //MMEA1_EDC_CNT2 14208 #define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 14209 #define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 14210 #define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 14211 #define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 14212 #define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 14213 #define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa 14214 #define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc 14215 #define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe 14216 #define MMEA1_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10 14217 #define MMEA1_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12 14218 #define MMEA1_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14 14219 #define MMEA1_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16 14220 #define MMEA1_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT 0x18 14221 #define MMEA1_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT 0x1a 14222 #define MMEA1_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT 0x1c 14223 #define MMEA1_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT 0x1e 14224 #define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 14225 #define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 14226 #define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 14227 #define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 14228 #define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 14229 #define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 14230 #define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L 14231 #define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L 14232 #define MMEA1_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L 14233 #define MMEA1_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L 14234 #define MMEA1_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L 14235 #define MMEA1_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L 14236 #define MMEA1_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK 0x03000000L 14237 #define MMEA1_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK 0x0C000000L 14238 #define MMEA1_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK 0x30000000L 14239 #define MMEA1_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK 0xC0000000L 14240 //MMEA1_DSM_CNTL 14241 #define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 14242 #define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 14243 #define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 14244 #define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 14245 #define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 14246 #define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 14247 #define MMEA1_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 14248 #define MMEA1_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 14249 #define MMEA1_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 14250 #define MMEA1_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 14251 #define MMEA1_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 14252 #define MMEA1_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 14253 #define MMEA1_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 14254 #define MMEA1_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 14255 #define MMEA1_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 14256 #define MMEA1_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 14257 #define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 14258 #define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 14259 #define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 14260 #define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 14261 #define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 14262 #define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 14263 #define MMEA1_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 14264 #define MMEA1_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 14265 #define MMEA1_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 14266 #define MMEA1_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 14267 #define MMEA1_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 14268 #define MMEA1_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 14269 #define MMEA1_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 14270 #define MMEA1_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 14271 #define MMEA1_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L 14272 #define MMEA1_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L 14273 //MMEA1_DSM_CNTLA 14274 #define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 14275 #define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 14276 #define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 14277 #define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 14278 #define MMEA1_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 14279 #define MMEA1_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 14280 #define MMEA1_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 14281 #define MMEA1_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 14282 #define MMEA1_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 14283 #define MMEA1_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 14284 #define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 14285 #define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 14286 #define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 14287 #define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 14288 #define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 14289 #define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 14290 #define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 14291 #define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 14292 #define MMEA1_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 14293 #define MMEA1_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 14294 #define MMEA1_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 14295 #define MMEA1_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 14296 #define MMEA1_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 14297 #define MMEA1_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 14298 #define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 14299 #define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 14300 #define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 14301 #define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 14302 //MMEA1_DSM_CNTL2 14303 #define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 14304 #define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 14305 #define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 14306 #define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 14307 #define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 14308 #define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 14309 #define MMEA1_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 14310 #define MMEA1_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb 14311 #define MMEA1_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 14312 #define MMEA1_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe 14313 #define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 14314 #define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 14315 #define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 14316 #define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 14317 #define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 14318 #define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 14319 #define MMEA1_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a 14320 #define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 14321 #define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 14322 #define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 14323 #define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 14324 #define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 14325 #define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 14326 #define MMEA1_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 14327 #define MMEA1_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 14328 #define MMEA1_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 14329 #define MMEA1_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 14330 #define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 14331 #define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 14332 #define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 14333 #define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 14334 #define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L 14335 #define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L 14336 #define MMEA1_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L 14337 //MMEA1_DSM_CNTL2A 14338 #define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 14339 #define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 14340 #define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 14341 #define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 14342 #define MMEA1_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 14343 #define MMEA1_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 14344 #define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 14345 #define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb 14346 #define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 14347 #define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe 14348 #define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 14349 #define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 14350 #define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 14351 #define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 14352 #define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 14353 #define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 14354 #define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 14355 #define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 14356 #define MMEA1_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 14357 #define MMEA1_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 14358 #define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 14359 #define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 14360 #define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 14361 #define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 14362 #define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 14363 #define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 14364 #define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 14365 #define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 14366 //MMEA1_CGTT_CLK_CTRL 14367 #define MMEA1_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 14368 #define MMEA1_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 14369 #define MMEA1_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc 14370 #define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 14371 #define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 14372 #define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 14373 #define MMEA1_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 14374 #define MMEA1_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 14375 #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c 14376 #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d 14377 #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e 14378 #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f 14379 #define MMEA1_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 14380 #define MMEA1_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 14381 #define MMEA1_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L 14382 #define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L 14383 #define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L 14384 #define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L 14385 #define MMEA1_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L 14386 #define MMEA1_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 14387 #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L 14388 #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L 14389 #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L 14390 #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L 14391 //MMEA1_EDC_MODE 14392 #define MMEA1_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 14393 #define MMEA1_EDC_MODE__GATE_FUE__SHIFT 0x11 14394 #define MMEA1_EDC_MODE__DED_MODE__SHIFT 0x14 14395 #define MMEA1_EDC_MODE__PROP_FED__SHIFT 0x1d 14396 #define MMEA1_EDC_MODE__BYPASS__SHIFT 0x1f 14397 #define MMEA1_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L 14398 #define MMEA1_EDC_MODE__GATE_FUE_MASK 0x00020000L 14399 #define MMEA1_EDC_MODE__DED_MODE_MASK 0x00300000L 14400 #define MMEA1_EDC_MODE__PROP_FED_MASK 0x20000000L 14401 #define MMEA1_EDC_MODE__BYPASS_MASK 0x80000000L 14402 //MMEA1_ERR_STATUS 14403 #define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 14404 #define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 14405 #define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 14406 #define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa 14407 #define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb 14408 #define MMEA1_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc 14409 #define MMEA1_ERR_STATUS__FUE_FLAG__SHIFT 0xd 14410 #define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL 14411 #define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L 14412 #define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L 14413 #define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L 14414 #define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L 14415 #define MMEA1_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L 14416 #define MMEA1_ERR_STATUS__FUE_FLAG_MASK 0x00002000L 14417 //MMEA1_MISC2 14418 #define MMEA1_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 14419 #define MMEA1_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 14420 #define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 14421 #define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 14422 #define MMEA1_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc 14423 #define MMEA1_MISC2__RRET_SWAP_MODE__SHIFT 0xd 14424 #define MMEA1_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L 14425 #define MMEA1_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L 14426 #define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL 14427 #define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L 14428 #define MMEA1_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L 14429 #define MMEA1_MISC2__RRET_SWAP_MODE_MASK 0x00002000L 14430 //MMEA1_ADDRDEC_SELECT 14431 #define MMEA1_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0 14432 #define MMEA1_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5 14433 #define MMEA1_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa 14434 #define MMEA1_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf 14435 #define MMEA1_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL 14436 #define MMEA1_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L 14437 #define MMEA1_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L 14438 #define MMEA1_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L 14439 //MMEA1_EDC_CNT3 14440 #define MMEA1_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0 14441 #define MMEA1_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2 14442 #define MMEA1_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4 14443 #define MMEA1_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6 14444 #define MMEA1_EDC_CNT3__IOWR_DATAMEM_DED_COUNT__SHIFT 0x8 14445 #define MMEA1_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0xa 14446 #define MMEA1_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xc 14447 #define MMEA1_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L 14448 #define MMEA1_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL 14449 #define MMEA1_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L 14450 #define MMEA1_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 14451 #define MMEA1_EDC_CNT3__IOWR_DATAMEM_DED_COUNT_MASK 0x00000300L 14452 #define MMEA1_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000C00L 14453 #define MMEA1_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00003000L 14454 14455 14456 // addressBlock: mmhub_ea_mmeadec2 14457 //MMEA2_DRAM_RD_CLI2GRP_MAP0 14458 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 14459 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 14460 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 14461 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 14462 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 14463 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 14464 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 14465 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 14466 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 14467 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 14468 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 14469 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 14470 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 14471 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 14472 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 14473 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 14474 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 14475 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 14476 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 14477 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 14478 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 14479 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 14480 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 14481 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 14482 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 14483 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 14484 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 14485 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 14486 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 14487 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 14488 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 14489 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 14490 //MMEA2_DRAM_RD_CLI2GRP_MAP1 14491 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 14492 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 14493 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 14494 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 14495 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 14496 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 14497 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 14498 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 14499 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 14500 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 14501 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 14502 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 14503 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 14504 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 14505 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 14506 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 14507 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 14508 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 14509 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 14510 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 14511 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 14512 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 14513 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 14514 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 14515 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 14516 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 14517 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 14518 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 14519 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 14520 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 14521 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 14522 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 14523 //MMEA2_DRAM_WR_CLI2GRP_MAP0 14524 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 14525 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 14526 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 14527 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 14528 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 14529 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 14530 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 14531 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 14532 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 14533 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 14534 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 14535 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 14536 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 14537 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 14538 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 14539 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 14540 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 14541 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 14542 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 14543 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 14544 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 14545 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 14546 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 14547 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 14548 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 14549 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 14550 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 14551 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 14552 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 14553 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 14554 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 14555 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 14556 //MMEA2_DRAM_WR_CLI2GRP_MAP1 14557 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 14558 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 14559 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 14560 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 14561 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 14562 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 14563 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 14564 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 14565 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 14566 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 14567 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 14568 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 14569 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 14570 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 14571 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 14572 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 14573 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 14574 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 14575 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 14576 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 14577 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 14578 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 14579 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 14580 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 14581 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 14582 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 14583 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 14584 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 14585 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 14586 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 14587 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 14588 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 14589 //MMEA2_DRAM_RD_GRP2VC_MAP 14590 #define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 14591 #define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 14592 #define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 14593 #define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 14594 #define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 14595 #define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 14596 #define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 14597 #define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 14598 //MMEA2_DRAM_WR_GRP2VC_MAP 14599 #define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 14600 #define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 14601 #define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 14602 #define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 14603 #define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 14604 #define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 14605 #define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 14606 #define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 14607 //MMEA2_DRAM_RD_LAZY 14608 #define MMEA2_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 14609 #define MMEA2_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 14610 #define MMEA2_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 14611 #define MMEA2_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 14612 #define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 14613 #define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 14614 #define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 14615 #define MMEA2_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L 14616 #define MMEA2_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L 14617 #define MMEA2_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L 14618 #define MMEA2_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L 14619 #define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 14620 #define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 14621 #define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 14622 //MMEA2_DRAM_WR_LAZY 14623 #define MMEA2_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 14624 #define MMEA2_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 14625 #define MMEA2_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 14626 #define MMEA2_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 14627 #define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 14628 #define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 14629 #define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 14630 #define MMEA2_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L 14631 #define MMEA2_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L 14632 #define MMEA2_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L 14633 #define MMEA2_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L 14634 #define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 14635 #define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 14636 #define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 14637 //MMEA2_DRAM_RD_CAM_CNTL 14638 #define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 14639 #define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 14640 #define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 14641 #define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 14642 #define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 14643 #define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 14644 #define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 14645 #define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 14646 #define MMEA2_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 14647 #define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 14648 #define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 14649 #define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 14650 #define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 14651 #define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 14652 #define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 14653 #define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 14654 #define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 14655 #define MMEA2_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 14656 //MMEA2_DRAM_WR_CAM_CNTL 14657 #define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 14658 #define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 14659 #define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 14660 #define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 14661 #define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 14662 #define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 14663 #define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 14664 #define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 14665 #define MMEA2_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 14666 #define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 14667 #define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 14668 #define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 14669 #define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 14670 #define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 14671 #define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 14672 #define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 14673 #define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 14674 #define MMEA2_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 14675 //MMEA2_DRAM_PAGE_BURST 14676 #define MMEA2_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 14677 #define MMEA2_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 14678 #define MMEA2_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 14679 #define MMEA2_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 14680 #define MMEA2_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL 14681 #define MMEA2_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 14682 #define MMEA2_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 14683 #define MMEA2_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L 14684 //MMEA2_DRAM_RD_PRI_AGE 14685 #define MMEA2_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 14686 #define MMEA2_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 14687 #define MMEA2_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 14688 #define MMEA2_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 14689 #define MMEA2_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 14690 #define MMEA2_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 14691 #define MMEA2_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 14692 #define MMEA2_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 14693 #define MMEA2_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 14694 #define MMEA2_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 14695 #define MMEA2_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 14696 #define MMEA2_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 14697 #define MMEA2_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 14698 #define MMEA2_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 14699 #define MMEA2_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 14700 #define MMEA2_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 14701 //MMEA2_DRAM_WR_PRI_AGE 14702 #define MMEA2_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 14703 #define MMEA2_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 14704 #define MMEA2_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 14705 #define MMEA2_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 14706 #define MMEA2_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 14707 #define MMEA2_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 14708 #define MMEA2_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 14709 #define MMEA2_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 14710 #define MMEA2_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 14711 #define MMEA2_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 14712 #define MMEA2_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 14713 #define MMEA2_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 14714 #define MMEA2_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 14715 #define MMEA2_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 14716 #define MMEA2_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 14717 #define MMEA2_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 14718 //MMEA2_DRAM_RD_PRI_QUEUING 14719 #define MMEA2_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 14720 #define MMEA2_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 14721 #define MMEA2_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 14722 #define MMEA2_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 14723 #define MMEA2_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 14724 #define MMEA2_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 14725 #define MMEA2_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 14726 #define MMEA2_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 14727 //MMEA2_DRAM_WR_PRI_QUEUING 14728 #define MMEA2_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 14729 #define MMEA2_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 14730 #define MMEA2_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 14731 #define MMEA2_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 14732 #define MMEA2_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 14733 #define MMEA2_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 14734 #define MMEA2_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 14735 #define MMEA2_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 14736 //MMEA2_DRAM_RD_PRI_FIXED 14737 #define MMEA2_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 14738 #define MMEA2_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 14739 #define MMEA2_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 14740 #define MMEA2_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 14741 #define MMEA2_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 14742 #define MMEA2_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 14743 #define MMEA2_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 14744 #define MMEA2_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 14745 //MMEA2_DRAM_WR_PRI_FIXED 14746 #define MMEA2_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 14747 #define MMEA2_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 14748 #define MMEA2_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 14749 #define MMEA2_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 14750 #define MMEA2_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 14751 #define MMEA2_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 14752 #define MMEA2_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 14753 #define MMEA2_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 14754 //MMEA2_DRAM_RD_PRI_URGENCY 14755 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 14756 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 14757 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 14758 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 14759 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 14760 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 14761 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 14762 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 14763 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 14764 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 14765 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 14766 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 14767 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 14768 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 14769 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 14770 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 14771 //MMEA2_DRAM_WR_PRI_URGENCY 14772 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 14773 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 14774 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 14775 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 14776 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 14777 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 14778 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 14779 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 14780 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 14781 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 14782 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 14783 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 14784 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 14785 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 14786 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 14787 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 14788 //MMEA2_DRAM_RD_PRI_QUANT_PRI1 14789 #define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 14790 #define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 14791 #define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 14792 #define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 14793 #define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 14794 #define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 14795 #define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 14796 #define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 14797 //MMEA2_DRAM_RD_PRI_QUANT_PRI2 14798 #define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 14799 #define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 14800 #define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 14801 #define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 14802 #define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 14803 #define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 14804 #define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 14805 #define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 14806 //MMEA2_DRAM_RD_PRI_QUANT_PRI3 14807 #define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 14808 #define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 14809 #define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 14810 #define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 14811 #define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 14812 #define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 14813 #define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 14814 #define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 14815 //MMEA2_DRAM_WR_PRI_QUANT_PRI1 14816 #define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 14817 #define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 14818 #define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 14819 #define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 14820 #define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 14821 #define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 14822 #define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 14823 #define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 14824 //MMEA2_DRAM_WR_PRI_QUANT_PRI2 14825 #define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 14826 #define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 14827 #define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 14828 #define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 14829 #define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 14830 #define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 14831 #define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 14832 #define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 14833 //MMEA2_DRAM_WR_PRI_QUANT_PRI3 14834 #define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 14835 #define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 14836 #define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 14837 #define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 14838 #define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 14839 #define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 14840 #define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 14841 #define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 14842 //MMEA2_GMI_RD_CLI2GRP_MAP0 14843 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 14844 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 14845 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 14846 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 14847 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 14848 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 14849 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 14850 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 14851 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 14852 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 14853 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 14854 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 14855 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 14856 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 14857 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 14858 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 14859 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 14860 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 14861 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 14862 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 14863 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 14864 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 14865 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 14866 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 14867 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 14868 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 14869 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 14870 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 14871 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 14872 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 14873 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 14874 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 14875 //MMEA2_GMI_RD_CLI2GRP_MAP1 14876 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 14877 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 14878 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 14879 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 14880 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 14881 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 14882 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 14883 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 14884 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 14885 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 14886 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 14887 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 14888 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 14889 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 14890 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 14891 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 14892 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 14893 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 14894 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 14895 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 14896 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 14897 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 14898 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 14899 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 14900 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 14901 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 14902 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 14903 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 14904 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 14905 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 14906 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 14907 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 14908 //MMEA2_GMI_WR_CLI2GRP_MAP0 14909 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 14910 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 14911 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 14912 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 14913 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 14914 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 14915 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 14916 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 14917 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 14918 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 14919 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 14920 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 14921 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 14922 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 14923 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 14924 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 14925 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 14926 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 14927 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 14928 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 14929 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 14930 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 14931 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 14932 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 14933 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 14934 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 14935 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 14936 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 14937 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 14938 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 14939 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 14940 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 14941 //MMEA2_GMI_WR_CLI2GRP_MAP1 14942 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 14943 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 14944 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 14945 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 14946 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 14947 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 14948 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 14949 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 14950 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 14951 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 14952 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 14953 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 14954 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 14955 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 14956 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 14957 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 14958 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 14959 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 14960 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 14961 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 14962 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 14963 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 14964 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 14965 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 14966 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 14967 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 14968 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 14969 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 14970 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 14971 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 14972 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 14973 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 14974 //MMEA2_GMI_RD_GRP2VC_MAP 14975 #define MMEA2_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 14976 #define MMEA2_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 14977 #define MMEA2_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 14978 #define MMEA2_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 14979 #define MMEA2_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 14980 #define MMEA2_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 14981 #define MMEA2_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 14982 #define MMEA2_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 14983 //MMEA2_GMI_WR_GRP2VC_MAP 14984 #define MMEA2_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 14985 #define MMEA2_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 14986 #define MMEA2_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 14987 #define MMEA2_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 14988 #define MMEA2_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 14989 #define MMEA2_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 14990 #define MMEA2_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 14991 #define MMEA2_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 14992 //MMEA2_GMI_RD_LAZY 14993 #define MMEA2_GMI_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 14994 #define MMEA2_GMI_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 14995 #define MMEA2_GMI_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 14996 #define MMEA2_GMI_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 14997 #define MMEA2_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 14998 #define MMEA2_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 14999 #define MMEA2_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 15000 #define MMEA2_GMI_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L 15001 #define MMEA2_GMI_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L 15002 #define MMEA2_GMI_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L 15003 #define MMEA2_GMI_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L 15004 #define MMEA2_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 15005 #define MMEA2_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 15006 #define MMEA2_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 15007 //MMEA2_GMI_WR_LAZY 15008 #define MMEA2_GMI_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 15009 #define MMEA2_GMI_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 15010 #define MMEA2_GMI_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 15011 #define MMEA2_GMI_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 15012 #define MMEA2_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 15013 #define MMEA2_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 15014 #define MMEA2_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 15015 #define MMEA2_GMI_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L 15016 #define MMEA2_GMI_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L 15017 #define MMEA2_GMI_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L 15018 #define MMEA2_GMI_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L 15019 #define MMEA2_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 15020 #define MMEA2_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 15021 #define MMEA2_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 15022 //MMEA2_GMI_RD_CAM_CNTL 15023 #define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 15024 #define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 15025 #define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 15026 #define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 15027 #define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 15028 #define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 15029 #define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 15030 #define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 15031 #define MMEA2_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 15032 #define MMEA2_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d 15033 #define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 15034 #define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 15035 #define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 15036 #define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 15037 #define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 15038 #define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 15039 #define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 15040 #define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 15041 #define MMEA2_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 15042 #define MMEA2_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L 15043 //MMEA2_GMI_WR_CAM_CNTL 15044 #define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 15045 #define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 15046 #define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 15047 #define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 15048 #define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 15049 #define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 15050 #define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 15051 #define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 15052 #define MMEA2_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 15053 #define MMEA2_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d 15054 #define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 15055 #define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 15056 #define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 15057 #define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 15058 #define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 15059 #define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 15060 #define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 15061 #define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 15062 #define MMEA2_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 15063 #define MMEA2_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L 15064 //MMEA2_GMI_PAGE_BURST 15065 #define MMEA2_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 15066 #define MMEA2_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 15067 #define MMEA2_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 15068 #define MMEA2_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 15069 #define MMEA2_GMI_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL 15070 #define MMEA2_GMI_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 15071 #define MMEA2_GMI_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 15072 #define MMEA2_GMI_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L 15073 //MMEA2_GMI_RD_PRI_AGE 15074 #define MMEA2_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 15075 #define MMEA2_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 15076 #define MMEA2_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 15077 #define MMEA2_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 15078 #define MMEA2_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 15079 #define MMEA2_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 15080 #define MMEA2_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 15081 #define MMEA2_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 15082 #define MMEA2_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 15083 #define MMEA2_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 15084 #define MMEA2_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 15085 #define MMEA2_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 15086 #define MMEA2_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 15087 #define MMEA2_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 15088 #define MMEA2_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 15089 #define MMEA2_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 15090 //MMEA2_GMI_WR_PRI_AGE 15091 #define MMEA2_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 15092 #define MMEA2_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 15093 #define MMEA2_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 15094 #define MMEA2_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 15095 #define MMEA2_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 15096 #define MMEA2_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 15097 #define MMEA2_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 15098 #define MMEA2_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 15099 #define MMEA2_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 15100 #define MMEA2_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 15101 #define MMEA2_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 15102 #define MMEA2_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 15103 #define MMEA2_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 15104 #define MMEA2_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 15105 #define MMEA2_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 15106 #define MMEA2_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 15107 //MMEA2_GMI_RD_PRI_QUEUING 15108 #define MMEA2_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 15109 #define MMEA2_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 15110 #define MMEA2_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 15111 #define MMEA2_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 15112 #define MMEA2_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 15113 #define MMEA2_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 15114 #define MMEA2_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 15115 #define MMEA2_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 15116 //MMEA2_GMI_WR_PRI_QUEUING 15117 #define MMEA2_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 15118 #define MMEA2_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 15119 #define MMEA2_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 15120 #define MMEA2_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 15121 #define MMEA2_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 15122 #define MMEA2_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 15123 #define MMEA2_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 15124 #define MMEA2_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 15125 //MMEA2_GMI_RD_PRI_FIXED 15126 #define MMEA2_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 15127 #define MMEA2_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 15128 #define MMEA2_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 15129 #define MMEA2_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 15130 #define MMEA2_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 15131 #define MMEA2_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 15132 #define MMEA2_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 15133 #define MMEA2_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 15134 //MMEA2_GMI_WR_PRI_FIXED 15135 #define MMEA2_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 15136 #define MMEA2_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 15137 #define MMEA2_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 15138 #define MMEA2_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 15139 #define MMEA2_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 15140 #define MMEA2_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 15141 #define MMEA2_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 15142 #define MMEA2_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 15143 //MMEA2_GMI_RD_PRI_URGENCY 15144 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 15145 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 15146 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 15147 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 15148 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 15149 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 15150 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 15151 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 15152 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 15153 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 15154 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 15155 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 15156 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 15157 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 15158 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 15159 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 15160 //MMEA2_GMI_WR_PRI_URGENCY 15161 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 15162 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 15163 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 15164 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 15165 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 15166 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 15167 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 15168 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 15169 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 15170 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 15171 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 15172 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 15173 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 15174 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 15175 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 15176 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 15177 //MMEA2_GMI_RD_PRI_URGENCY_MASKING 15178 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 15179 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 15180 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 15181 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 15182 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 15183 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 15184 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 15185 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 15186 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 15187 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 15188 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 15189 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 15190 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 15191 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 15192 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 15193 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 15194 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 15195 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 15196 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 15197 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 15198 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 15199 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 15200 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 15201 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 15202 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 15203 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 15204 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 15205 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 15206 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 15207 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 15208 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 15209 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 15210 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 15211 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 15212 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 15213 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 15214 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 15215 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 15216 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 15217 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 15218 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 15219 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 15220 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 15221 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 15222 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 15223 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 15224 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 15225 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 15226 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 15227 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 15228 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 15229 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 15230 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 15231 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 15232 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 15233 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 15234 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 15235 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 15236 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 15237 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 15238 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 15239 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 15240 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 15241 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 15242 //MMEA2_GMI_WR_PRI_URGENCY_MASKING 15243 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 15244 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 15245 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 15246 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 15247 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 15248 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 15249 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 15250 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 15251 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 15252 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 15253 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 15254 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 15255 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 15256 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 15257 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 15258 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 15259 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 15260 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 15261 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 15262 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 15263 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 15264 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 15265 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 15266 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 15267 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 15268 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 15269 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 15270 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 15271 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 15272 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 15273 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 15274 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 15275 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 15276 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 15277 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 15278 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 15279 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 15280 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 15281 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 15282 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 15283 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 15284 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 15285 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 15286 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 15287 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 15288 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 15289 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 15290 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 15291 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 15292 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 15293 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 15294 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 15295 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 15296 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 15297 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 15298 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 15299 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 15300 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 15301 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 15302 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 15303 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 15304 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 15305 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 15306 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 15307 //MMEA2_GMI_RD_PRI_QUANT_PRI1 15308 #define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 15309 #define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 15310 #define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 15311 #define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 15312 #define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 15313 #define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 15314 #define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 15315 #define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 15316 //MMEA2_GMI_RD_PRI_QUANT_PRI2 15317 #define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 15318 #define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 15319 #define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 15320 #define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 15321 #define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 15322 #define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 15323 #define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 15324 #define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 15325 //MMEA2_GMI_RD_PRI_QUANT_PRI3 15326 #define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 15327 #define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 15328 #define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 15329 #define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 15330 #define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 15331 #define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 15332 #define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 15333 #define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 15334 //MMEA2_GMI_WR_PRI_QUANT_PRI1 15335 #define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 15336 #define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 15337 #define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 15338 #define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 15339 #define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 15340 #define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 15341 #define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 15342 #define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 15343 //MMEA2_GMI_WR_PRI_QUANT_PRI2 15344 #define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 15345 #define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 15346 #define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 15347 #define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 15348 #define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 15349 #define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 15350 #define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 15351 #define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 15352 //MMEA2_GMI_WR_PRI_QUANT_PRI3 15353 #define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 15354 #define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 15355 #define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 15356 #define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 15357 #define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 15358 #define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 15359 #define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 15360 #define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 15361 //MMEA2_ADDRNORM_BASE_ADDR0 15362 #define MMEA2_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 15363 #define MMEA2_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 15364 #define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 15365 #define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x6 15366 #define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 15367 #define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 15368 #define MMEA2_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc 15369 #define MMEA2_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L 15370 #define MMEA2_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 15371 #define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000003CL 15372 #define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x000000C0L 15373 #define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L 15374 #define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L 15375 #define MMEA2_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L 15376 //MMEA2_ADDRNORM_LIMIT_ADDR0 15377 #define MMEA2_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 15378 #define MMEA2_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc 15379 #define MMEA2_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL 15380 #define MMEA2_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L 15381 //MMEA2_ADDRNORM_BASE_ADDR1 15382 #define MMEA2_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 15383 #define MMEA2_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 15384 #define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 15385 #define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x6 15386 #define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 15387 #define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 15388 #define MMEA2_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc 15389 #define MMEA2_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L 15390 #define MMEA2_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 15391 #define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000003CL 15392 #define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x000000C0L 15393 #define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L 15394 #define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L 15395 #define MMEA2_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L 15396 //MMEA2_ADDRNORM_LIMIT_ADDR1 15397 #define MMEA2_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 15398 #define MMEA2_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc 15399 #define MMEA2_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL 15400 #define MMEA2_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L 15401 //MMEA2_ADDRNORM_OFFSET_ADDR1 15402 #define MMEA2_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 15403 #define MMEA2_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 15404 #define MMEA2_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L 15405 #define MMEA2_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L 15406 //MMEA2_ADDRNORM_BASE_ADDR2 15407 #define MMEA2_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT 0x0 15408 #define MMEA2_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT 0x1 15409 #define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT 0x2 15410 #define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT 0x6 15411 #define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT 0x8 15412 #define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT 0x9 15413 #define MMEA2_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT 0xc 15414 #define MMEA2_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK 0x00000001L 15415 #define MMEA2_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 15416 #define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK 0x0000003CL 15417 #define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK 0x000000C0L 15418 #define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK 0x00000100L 15419 #define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK 0x00000E00L 15420 #define MMEA2_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK 0xFFFFF000L 15421 //MMEA2_ADDRNORM_LIMIT_ADDR2 15422 #define MMEA2_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT 0x0 15423 #define MMEA2_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT 0xc 15424 #define MMEA2_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK 0x0000001FL 15425 #define MMEA2_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK 0xFFFFF000L 15426 //MMEA2_ADDRNORM_BASE_ADDR3 15427 #define MMEA2_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT 0x0 15428 #define MMEA2_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT 0x1 15429 #define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT 0x2 15430 #define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT 0x6 15431 #define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT 0x8 15432 #define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT 0x9 15433 #define MMEA2_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT 0xc 15434 #define MMEA2_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK 0x00000001L 15435 #define MMEA2_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 15436 #define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK 0x0000003CL 15437 #define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK 0x000000C0L 15438 #define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK 0x00000100L 15439 #define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK 0x00000E00L 15440 #define MMEA2_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK 0xFFFFF000L 15441 //MMEA2_ADDRNORM_LIMIT_ADDR3 15442 #define MMEA2_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT 0x0 15443 #define MMEA2_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT 0xc 15444 #define MMEA2_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK 0x0000001FL 15445 #define MMEA2_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK 0xFFFFF000L 15446 //MMEA2_ADDRNORM_OFFSET_ADDR3 15447 #define MMEA2_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT 0x0 15448 #define MMEA2_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT 0x14 15449 #define MMEA2_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK 0x00000001L 15450 #define MMEA2_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK 0xFFF00000L 15451 //MMEA2_ADDRNORM_BASE_ADDR4 15452 #define MMEA2_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL__SHIFT 0x0 15453 #define MMEA2_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN__SHIFT 0x1 15454 #define MMEA2_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN__SHIFT 0x2 15455 #define MMEA2_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES__SHIFT 0x6 15456 #define MMEA2_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS__SHIFT 0x8 15457 #define MMEA2_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL__SHIFT 0x9 15458 #define MMEA2_ADDRNORM_BASE_ADDR4__BASE_ADDR__SHIFT 0xc 15459 #define MMEA2_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL_MASK 0x00000001L 15460 #define MMEA2_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 15461 #define MMEA2_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN_MASK 0x0000003CL 15462 #define MMEA2_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES_MASK 0x000000C0L 15463 #define MMEA2_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS_MASK 0x00000100L 15464 #define MMEA2_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL_MASK 0x00000E00L 15465 #define MMEA2_ADDRNORM_BASE_ADDR4__BASE_ADDR_MASK 0xFFFFF000L 15466 //MMEA2_ADDRNORM_LIMIT_ADDR4 15467 #define MMEA2_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID__SHIFT 0x0 15468 #define MMEA2_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR__SHIFT 0xc 15469 #define MMEA2_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID_MASK 0x0000001FL 15470 #define MMEA2_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR_MASK 0xFFFFF000L 15471 //MMEA2_ADDRNORM_BASE_ADDR5 15472 #define MMEA2_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL__SHIFT 0x0 15473 #define MMEA2_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN__SHIFT 0x1 15474 #define MMEA2_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN__SHIFT 0x2 15475 #define MMEA2_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES__SHIFT 0x6 15476 #define MMEA2_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS__SHIFT 0x8 15477 #define MMEA2_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL__SHIFT 0x9 15478 #define MMEA2_ADDRNORM_BASE_ADDR5__BASE_ADDR__SHIFT 0xc 15479 #define MMEA2_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL_MASK 0x00000001L 15480 #define MMEA2_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 15481 #define MMEA2_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN_MASK 0x0000003CL 15482 #define MMEA2_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES_MASK 0x000000C0L 15483 #define MMEA2_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS_MASK 0x00000100L 15484 #define MMEA2_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL_MASK 0x00000E00L 15485 #define MMEA2_ADDRNORM_BASE_ADDR5__BASE_ADDR_MASK 0xFFFFF000L 15486 //MMEA2_ADDRNORM_LIMIT_ADDR5 15487 #define MMEA2_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID__SHIFT 0x0 15488 #define MMEA2_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR__SHIFT 0xc 15489 #define MMEA2_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID_MASK 0x0000001FL 15490 #define MMEA2_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR_MASK 0xFFFFF000L 15491 //MMEA2_ADDRNORM_OFFSET_ADDR5 15492 #define MMEA2_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN__SHIFT 0x0 15493 #define MMEA2_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET__SHIFT 0x14 15494 #define MMEA2_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN_MASK 0x00000001L 15495 #define MMEA2_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_MASK 0xFFF00000L 15496 //MMEA2_ADDRNORMDRAM_HOLE_CNTL 15497 #define MMEA2_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 15498 #define MMEA2_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 15499 #define MMEA2_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L 15500 #define MMEA2_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L 15501 //MMEA2_ADDRNORMGMI_HOLE_CNTL 15502 #define MMEA2_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 15503 #define MMEA2_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 15504 #define MMEA2_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L 15505 #define MMEA2_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L 15506 //MMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG 15507 #define MMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0 15508 #define MMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6 15509 #define MMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL 15510 #define MMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L 15511 //MMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG 15512 #define MMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT 0x0 15513 #define MMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT 0x6 15514 #define MMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK 0x0000003FL 15515 #define MMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK 0x00000FC0L 15516 //MMEA2_ADDRDEC_BANK_CFG 15517 #define MMEA2_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 15518 #define MMEA2_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x6 15519 #define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xc 15520 #define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xf 15521 #define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x12 15522 #define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x13 15523 #define MMEA2_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000003FL 15524 #define MMEA2_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x00000FC0L 15525 #define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00007000L 15526 #define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x00038000L 15527 #define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00040000L 15528 #define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00080000L 15529 //MMEA2_ADDRDEC_MISC_CFG 15530 #define MMEA2_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 15531 #define MMEA2_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 15532 #define MMEA2_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 15533 #define MMEA2_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 15534 #define MMEA2_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 15535 #define MMEA2_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc 15536 #define MMEA2_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11 15537 #define MMEA2_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16 15538 #define MMEA2_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18 15539 #define MMEA2_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a 15540 #define MMEA2_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d 15541 #define MMEA2_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L 15542 #define MMEA2_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L 15543 #define MMEA2_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L 15544 #define MMEA2_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L 15545 #define MMEA2_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L 15546 #define MMEA2_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L 15547 #define MMEA2_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L 15548 #define MMEA2_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L 15549 #define MMEA2_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L 15550 #define MMEA2_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L 15551 #define MMEA2_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L 15552 //MMEA2_ADDRDECDRAM_ADDR_HASH_BANK0 15553 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 15554 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 15555 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe 15556 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L 15557 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL 15558 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L 15559 //MMEA2_ADDRDECDRAM_ADDR_HASH_BANK1 15560 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 15561 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 15562 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe 15563 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L 15564 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL 15565 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L 15566 //MMEA2_ADDRDECDRAM_ADDR_HASH_BANK2 15567 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 15568 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 15569 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe 15570 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L 15571 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL 15572 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L 15573 //MMEA2_ADDRDECDRAM_ADDR_HASH_BANK3 15574 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 15575 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 15576 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe 15577 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L 15578 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL 15579 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L 15580 //MMEA2_ADDRDECDRAM_ADDR_HASH_BANK4 15581 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 15582 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 15583 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe 15584 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L 15585 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL 15586 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L 15587 //MMEA2_ADDRDECDRAM_ADDR_HASH_BANK5 15588 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT 0x0 15589 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR__SHIFT 0x1 15590 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR__SHIFT 0xe 15591 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE_MASK 0x00000001L 15592 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR_MASK 0x00003FFEL 15593 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR_MASK 0xFFFFC000L 15594 //MMEA2_ADDRDECDRAM_ADDR_HASH_PC 15595 #define MMEA2_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 15596 #define MMEA2_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 15597 #define MMEA2_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe 15598 #define MMEA2_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L 15599 #define MMEA2_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL 15600 #define MMEA2_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L 15601 //MMEA2_ADDRDECDRAM_ADDR_HASH_PC2 15602 #define MMEA2_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 15603 #define MMEA2_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000003FL 15604 //MMEA2_ADDRDECDRAM_ADDR_HASH_CS0 15605 #define MMEA2_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 15606 #define MMEA2_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 15607 #define MMEA2_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L 15608 #define MMEA2_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL 15609 //MMEA2_ADDRDECDRAM_ADDR_HASH_CS1 15610 #define MMEA2_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 15611 #define MMEA2_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 15612 #define MMEA2_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L 15613 #define MMEA2_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL 15614 //MMEA2_ADDRDECDRAM_HARVEST_ENABLE 15615 #define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 15616 #define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 15617 #define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 15618 #define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 15619 #define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 15620 #define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 15621 #define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L 15622 #define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L 15623 #define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L 15624 #define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L 15625 #define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L 15626 #define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L 15627 //MMEA2_ADDRDECGMI_ADDR_HASH_BANK0 15628 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 15629 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 15630 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe 15631 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L 15632 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL 15633 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L 15634 //MMEA2_ADDRDECGMI_ADDR_HASH_BANK1 15635 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 15636 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 15637 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe 15638 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L 15639 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL 15640 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L 15641 //MMEA2_ADDRDECGMI_ADDR_HASH_BANK2 15642 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 15643 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 15644 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe 15645 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L 15646 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL 15647 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L 15648 //MMEA2_ADDRDECGMI_ADDR_HASH_BANK3 15649 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 15650 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 15651 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe 15652 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L 15653 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL 15654 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L 15655 //MMEA2_ADDRDECGMI_ADDR_HASH_BANK4 15656 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 15657 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 15658 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe 15659 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L 15660 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL 15661 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L 15662 //MMEA2_ADDRDECGMI_ADDR_HASH_BANK5 15663 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT 0x0 15664 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR__SHIFT 0x1 15665 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR__SHIFT 0xe 15666 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE_MASK 0x00000001L 15667 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR_MASK 0x00003FFEL 15668 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR_MASK 0xFFFFC000L 15669 //MMEA2_ADDRDECGMI_ADDR_HASH_PC 15670 #define MMEA2_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 15671 #define MMEA2_ADDRDECGMI_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 15672 #define MMEA2_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe 15673 #define MMEA2_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L 15674 #define MMEA2_ADDRDECGMI_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL 15675 #define MMEA2_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L 15676 //MMEA2_ADDRDECGMI_ADDR_HASH_PC2 15677 #define MMEA2_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 15678 #define MMEA2_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000003FL 15679 //MMEA2_ADDRDECGMI_ADDR_HASH_CS0 15680 #define MMEA2_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 15681 #define MMEA2_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 15682 #define MMEA2_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L 15683 #define MMEA2_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL 15684 //MMEA2_ADDRDECGMI_ADDR_HASH_CS1 15685 #define MMEA2_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 15686 #define MMEA2_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 15687 #define MMEA2_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L 15688 #define MMEA2_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL 15689 //MMEA2_ADDRDECGMI_HARVEST_ENABLE 15690 #define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 15691 #define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 15692 #define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 15693 #define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 15694 #define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 15695 #define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 15696 #define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L 15697 #define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L 15698 #define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L 15699 #define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L 15700 #define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L 15701 #define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L 15702 //MMEA2_ADDRDEC0_BASE_ADDR_CS0 15703 #define MMEA2_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 15704 #define MMEA2_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 15705 #define MMEA2_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 15706 #define MMEA2_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 15707 //MMEA2_ADDRDEC0_BASE_ADDR_CS1 15708 #define MMEA2_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 15709 #define MMEA2_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 15710 #define MMEA2_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 15711 #define MMEA2_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 15712 //MMEA2_ADDRDEC0_BASE_ADDR_CS2 15713 #define MMEA2_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 15714 #define MMEA2_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 15715 #define MMEA2_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 15716 #define MMEA2_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 15717 //MMEA2_ADDRDEC0_BASE_ADDR_CS3 15718 #define MMEA2_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 15719 #define MMEA2_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 15720 #define MMEA2_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 15721 #define MMEA2_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 15722 //MMEA2_ADDRDEC0_BASE_ADDR_SECCS0 15723 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 15724 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 15725 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 15726 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 15727 //MMEA2_ADDRDEC0_BASE_ADDR_SECCS1 15728 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 15729 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 15730 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 15731 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 15732 //MMEA2_ADDRDEC0_BASE_ADDR_SECCS2 15733 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 15734 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 15735 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 15736 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 15737 //MMEA2_ADDRDEC0_BASE_ADDR_SECCS3 15738 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 15739 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 15740 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 15741 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 15742 //MMEA2_ADDRDEC0_ADDR_MASK_CS01 15743 #define MMEA2_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 15744 #define MMEA2_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 15745 //MMEA2_ADDRDEC0_ADDR_MASK_CS23 15746 #define MMEA2_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 15747 #define MMEA2_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 15748 //MMEA2_ADDRDEC0_ADDR_MASK_SECCS01 15749 #define MMEA2_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 15750 #define MMEA2_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 15751 //MMEA2_ADDRDEC0_ADDR_MASK_SECCS23 15752 #define MMEA2_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 15753 #define MMEA2_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 15754 //MMEA2_ADDRDEC0_ADDR_CFG_CS01 15755 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 15756 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 15757 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 15758 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 15759 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 15760 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 15761 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 15762 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 15763 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 15764 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 15765 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 15766 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 15767 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 15768 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 15769 //MMEA2_ADDRDEC0_ADDR_CFG_CS23 15770 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 15771 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 15772 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 15773 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 15774 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 15775 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 15776 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 15777 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 15778 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 15779 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 15780 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 15781 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 15782 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 15783 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 15784 //MMEA2_ADDRDEC0_ADDR_SEL_CS01 15785 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 15786 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 15787 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 15788 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc 15789 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 15790 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 15791 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 15792 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 15793 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 15794 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 15795 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 15796 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 15797 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 15798 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 15799 //MMEA2_ADDRDEC0_ADDR_SEL_CS23 15800 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 15801 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 15802 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 15803 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc 15804 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 15805 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 15806 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 15807 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 15808 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 15809 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 15810 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 15811 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 15812 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 15813 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 15814 //MMEA2_ADDRDEC0_ADDR_SEL2_CS01 15815 #define MMEA2_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 15816 #define MMEA2_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 15817 //MMEA2_ADDRDEC0_ADDR_SEL2_CS23 15818 #define MMEA2_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 15819 #define MMEA2_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 15820 //MMEA2_ADDRDEC0_COL_SEL_LO_CS01 15821 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 15822 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 15823 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 15824 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc 15825 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 15826 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 15827 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 15828 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 15829 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 15830 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 15831 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 15832 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 15833 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 15834 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 15835 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 15836 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 15837 //MMEA2_ADDRDEC0_COL_SEL_LO_CS23 15838 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 15839 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 15840 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 15841 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc 15842 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 15843 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 15844 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 15845 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 15846 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 15847 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 15848 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 15849 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 15850 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 15851 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 15852 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 15853 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 15854 //MMEA2_ADDRDEC0_COL_SEL_HI_CS01 15855 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 15856 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 15857 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 15858 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc 15859 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 15860 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 15861 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 15862 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 15863 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 15864 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 15865 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 15866 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 15867 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 15868 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 15869 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 15870 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 15871 //MMEA2_ADDRDEC0_COL_SEL_HI_CS23 15872 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 15873 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 15874 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 15875 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc 15876 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 15877 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 15878 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 15879 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 15880 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 15881 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 15882 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 15883 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 15884 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 15885 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 15886 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 15887 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 15888 //MMEA2_ADDRDEC0_RM_SEL_CS01 15889 #define MMEA2_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 15890 #define MMEA2_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 15891 #define MMEA2_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 15892 #define MMEA2_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 15893 #define MMEA2_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 15894 #define MMEA2_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 15895 #define MMEA2_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL 15896 #define MMEA2_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L 15897 #define MMEA2_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L 15898 #define MMEA2_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 15899 #define MMEA2_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 15900 #define MMEA2_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 15901 //MMEA2_ADDRDEC0_RM_SEL_CS23 15902 #define MMEA2_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 15903 #define MMEA2_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 15904 #define MMEA2_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 15905 #define MMEA2_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 15906 #define MMEA2_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 15907 #define MMEA2_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 15908 #define MMEA2_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL 15909 #define MMEA2_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L 15910 #define MMEA2_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L 15911 #define MMEA2_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 15912 #define MMEA2_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 15913 #define MMEA2_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 15914 //MMEA2_ADDRDEC0_RM_SEL_SECCS01 15915 #define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 15916 #define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 15917 #define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 15918 #define MMEA2_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 15919 #define MMEA2_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 15920 #define MMEA2_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 15921 #define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 15922 #define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 15923 #define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 15924 #define MMEA2_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 15925 #define MMEA2_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 15926 #define MMEA2_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 15927 //MMEA2_ADDRDEC0_RM_SEL_SECCS23 15928 #define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 15929 #define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 15930 #define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 15931 #define MMEA2_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 15932 #define MMEA2_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 15933 #define MMEA2_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 15934 #define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 15935 #define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 15936 #define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 15937 #define MMEA2_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 15938 #define MMEA2_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 15939 #define MMEA2_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 15940 //MMEA2_ADDRDEC1_BASE_ADDR_CS0 15941 #define MMEA2_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 15942 #define MMEA2_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 15943 #define MMEA2_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 15944 #define MMEA2_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 15945 //MMEA2_ADDRDEC1_BASE_ADDR_CS1 15946 #define MMEA2_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 15947 #define MMEA2_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 15948 #define MMEA2_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 15949 #define MMEA2_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 15950 //MMEA2_ADDRDEC1_BASE_ADDR_CS2 15951 #define MMEA2_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 15952 #define MMEA2_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 15953 #define MMEA2_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 15954 #define MMEA2_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 15955 //MMEA2_ADDRDEC1_BASE_ADDR_CS3 15956 #define MMEA2_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 15957 #define MMEA2_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 15958 #define MMEA2_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 15959 #define MMEA2_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 15960 //MMEA2_ADDRDEC1_BASE_ADDR_SECCS0 15961 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 15962 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 15963 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 15964 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 15965 //MMEA2_ADDRDEC1_BASE_ADDR_SECCS1 15966 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 15967 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 15968 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 15969 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 15970 //MMEA2_ADDRDEC1_BASE_ADDR_SECCS2 15971 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 15972 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 15973 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 15974 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 15975 //MMEA2_ADDRDEC1_BASE_ADDR_SECCS3 15976 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 15977 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 15978 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 15979 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 15980 //MMEA2_ADDRDEC1_ADDR_MASK_CS01 15981 #define MMEA2_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 15982 #define MMEA2_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 15983 //MMEA2_ADDRDEC1_ADDR_MASK_CS23 15984 #define MMEA2_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 15985 #define MMEA2_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 15986 //MMEA2_ADDRDEC1_ADDR_MASK_SECCS01 15987 #define MMEA2_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 15988 #define MMEA2_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 15989 //MMEA2_ADDRDEC1_ADDR_MASK_SECCS23 15990 #define MMEA2_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 15991 #define MMEA2_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 15992 //MMEA2_ADDRDEC1_ADDR_CFG_CS01 15993 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 15994 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 15995 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 15996 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 15997 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 15998 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 15999 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 16000 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 16001 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 16002 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 16003 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 16004 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 16005 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 16006 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 16007 //MMEA2_ADDRDEC1_ADDR_CFG_CS23 16008 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 16009 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 16010 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 16011 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 16012 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 16013 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 16014 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 16015 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 16016 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 16017 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 16018 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 16019 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 16020 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 16021 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 16022 //MMEA2_ADDRDEC1_ADDR_SEL_CS01 16023 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 16024 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 16025 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 16026 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc 16027 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 16028 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 16029 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 16030 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 16031 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 16032 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 16033 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 16034 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 16035 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 16036 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 16037 //MMEA2_ADDRDEC1_ADDR_SEL_CS23 16038 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 16039 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 16040 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 16041 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc 16042 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 16043 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 16044 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 16045 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 16046 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 16047 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 16048 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 16049 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 16050 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 16051 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 16052 //MMEA2_ADDRDEC1_ADDR_SEL2_CS01 16053 #define MMEA2_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 16054 #define MMEA2_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 16055 //MMEA2_ADDRDEC1_ADDR_SEL2_CS23 16056 #define MMEA2_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 16057 #define MMEA2_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 16058 //MMEA2_ADDRDEC1_COL_SEL_LO_CS01 16059 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 16060 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 16061 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 16062 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc 16063 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 16064 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 16065 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 16066 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 16067 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 16068 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 16069 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 16070 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 16071 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 16072 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 16073 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 16074 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 16075 //MMEA2_ADDRDEC1_COL_SEL_LO_CS23 16076 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 16077 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 16078 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 16079 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc 16080 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 16081 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 16082 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 16083 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 16084 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 16085 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 16086 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 16087 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 16088 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 16089 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 16090 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 16091 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 16092 //MMEA2_ADDRDEC1_COL_SEL_HI_CS01 16093 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 16094 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 16095 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 16096 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc 16097 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 16098 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 16099 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 16100 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 16101 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 16102 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 16103 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 16104 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 16105 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 16106 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 16107 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 16108 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 16109 //MMEA2_ADDRDEC1_COL_SEL_HI_CS23 16110 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 16111 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 16112 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 16113 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc 16114 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 16115 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 16116 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 16117 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 16118 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 16119 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 16120 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 16121 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 16122 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 16123 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 16124 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 16125 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 16126 //MMEA2_ADDRDEC1_RM_SEL_CS01 16127 #define MMEA2_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 16128 #define MMEA2_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 16129 #define MMEA2_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 16130 #define MMEA2_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 16131 #define MMEA2_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 16132 #define MMEA2_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 16133 #define MMEA2_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL 16134 #define MMEA2_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L 16135 #define MMEA2_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L 16136 #define MMEA2_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 16137 #define MMEA2_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 16138 #define MMEA2_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 16139 //MMEA2_ADDRDEC1_RM_SEL_CS23 16140 #define MMEA2_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 16141 #define MMEA2_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 16142 #define MMEA2_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 16143 #define MMEA2_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 16144 #define MMEA2_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 16145 #define MMEA2_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 16146 #define MMEA2_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL 16147 #define MMEA2_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L 16148 #define MMEA2_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L 16149 #define MMEA2_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 16150 #define MMEA2_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 16151 #define MMEA2_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 16152 //MMEA2_ADDRDEC1_RM_SEL_SECCS01 16153 #define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 16154 #define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 16155 #define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 16156 #define MMEA2_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 16157 #define MMEA2_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 16158 #define MMEA2_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 16159 #define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 16160 #define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 16161 #define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 16162 #define MMEA2_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 16163 #define MMEA2_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 16164 #define MMEA2_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 16165 //MMEA2_ADDRDEC1_RM_SEL_SECCS23 16166 #define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 16167 #define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 16168 #define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 16169 #define MMEA2_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 16170 #define MMEA2_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 16171 #define MMEA2_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 16172 #define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 16173 #define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 16174 #define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 16175 #define MMEA2_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 16176 #define MMEA2_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 16177 #define MMEA2_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 16178 //MMEA2_ADDRDEC2_BASE_ADDR_CS0 16179 #define MMEA2_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 16180 #define MMEA2_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 16181 #define MMEA2_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 16182 #define MMEA2_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 16183 //MMEA2_ADDRDEC2_BASE_ADDR_CS1 16184 #define MMEA2_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 16185 #define MMEA2_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 16186 #define MMEA2_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 16187 #define MMEA2_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 16188 //MMEA2_ADDRDEC2_BASE_ADDR_CS2 16189 #define MMEA2_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 16190 #define MMEA2_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 16191 #define MMEA2_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 16192 #define MMEA2_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 16193 //MMEA2_ADDRDEC2_BASE_ADDR_CS3 16194 #define MMEA2_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 16195 #define MMEA2_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 16196 #define MMEA2_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 16197 #define MMEA2_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 16198 //MMEA2_ADDRDEC2_BASE_ADDR_SECCS0 16199 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 16200 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 16201 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 16202 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 16203 //MMEA2_ADDRDEC2_BASE_ADDR_SECCS1 16204 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 16205 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 16206 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 16207 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 16208 //MMEA2_ADDRDEC2_BASE_ADDR_SECCS2 16209 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 16210 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 16211 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 16212 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 16213 //MMEA2_ADDRDEC2_BASE_ADDR_SECCS3 16214 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 16215 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 16216 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 16217 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 16218 //MMEA2_ADDRDEC2_ADDR_MASK_CS01 16219 #define MMEA2_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 16220 #define MMEA2_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 16221 //MMEA2_ADDRDEC2_ADDR_MASK_CS23 16222 #define MMEA2_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 16223 #define MMEA2_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 16224 //MMEA2_ADDRDEC2_ADDR_MASK_SECCS01 16225 #define MMEA2_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 16226 #define MMEA2_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 16227 //MMEA2_ADDRDEC2_ADDR_MASK_SECCS23 16228 #define MMEA2_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 16229 #define MMEA2_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 16230 //MMEA2_ADDRDEC2_ADDR_CFG_CS01 16231 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 16232 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 16233 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 16234 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 16235 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 16236 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 16237 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 16238 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 16239 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 16240 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 16241 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 16242 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 16243 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 16244 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 16245 //MMEA2_ADDRDEC2_ADDR_CFG_CS23 16246 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 16247 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 16248 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 16249 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 16250 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 16251 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 16252 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 16253 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 16254 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 16255 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 16256 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 16257 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 16258 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 16259 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 16260 //MMEA2_ADDRDEC2_ADDR_SEL_CS01 16261 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT 0x0 16262 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT 0x4 16263 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT 0x8 16264 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT 0xc 16265 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT 0x10 16266 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 16267 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 16268 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 16269 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 16270 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 16271 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 16272 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 16273 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 16274 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 16275 //MMEA2_ADDRDEC2_ADDR_SEL_CS23 16276 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT 0x0 16277 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT 0x4 16278 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT 0x8 16279 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT 0xc 16280 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT 0x10 16281 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 16282 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 16283 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 16284 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 16285 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 16286 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 16287 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 16288 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 16289 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 16290 //MMEA2_ADDRDEC2_ADDR_SEL2_CS01 16291 #define MMEA2_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 16292 #define MMEA2_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 16293 //MMEA2_ADDRDEC2_ADDR_SEL2_CS23 16294 #define MMEA2_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 16295 #define MMEA2_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 16296 //MMEA2_ADDRDEC2_COL_SEL_LO_CS01 16297 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT 0x0 16298 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT 0x4 16299 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT 0x8 16300 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT 0xc 16301 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT 0x10 16302 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT 0x14 16303 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT 0x18 16304 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 16305 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 16306 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 16307 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 16308 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 16309 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 16310 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 16311 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 16312 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 16313 //MMEA2_ADDRDEC2_COL_SEL_LO_CS23 16314 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT 0x0 16315 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT 0x4 16316 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT 0x8 16317 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT 0xc 16318 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT 0x10 16319 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT 0x14 16320 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT 0x18 16321 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 16322 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 16323 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 16324 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 16325 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 16326 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 16327 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 16328 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 16329 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 16330 //MMEA2_ADDRDEC2_COL_SEL_HI_CS01 16331 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT 0x0 16332 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT 0x4 16333 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT 0x8 16334 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT 0xc 16335 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT 0x10 16336 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT 0x14 16337 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT 0x18 16338 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 16339 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 16340 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 16341 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 16342 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 16343 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 16344 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 16345 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 16346 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 16347 //MMEA2_ADDRDEC2_COL_SEL_HI_CS23 16348 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT 0x0 16349 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT 0x4 16350 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT 0x8 16351 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT 0xc 16352 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT 0x10 16353 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT 0x14 16354 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT 0x18 16355 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 16356 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 16357 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 16358 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 16359 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 16360 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 16361 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 16362 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 16363 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 16364 //MMEA2_ADDRDEC2_RM_SEL_CS01 16365 #define MMEA2_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT 0x0 16366 #define MMEA2_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT 0x4 16367 #define MMEA2_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT 0x8 16368 #define MMEA2_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 16369 #define MMEA2_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 16370 #define MMEA2_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 16371 #define MMEA2_ADDRDEC2_RM_SEL_CS01__RM0_MASK 0x0000000FL 16372 #define MMEA2_ADDRDEC2_RM_SEL_CS01__RM1_MASK 0x000000F0L 16373 #define MMEA2_ADDRDEC2_RM_SEL_CS01__RM2_MASK 0x00000F00L 16374 #define MMEA2_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 16375 #define MMEA2_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 16376 #define MMEA2_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 16377 //MMEA2_ADDRDEC2_RM_SEL_CS23 16378 #define MMEA2_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT 0x0 16379 #define MMEA2_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT 0x4 16380 #define MMEA2_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT 0x8 16381 #define MMEA2_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 16382 #define MMEA2_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 16383 #define MMEA2_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 16384 #define MMEA2_ADDRDEC2_RM_SEL_CS23__RM0_MASK 0x0000000FL 16385 #define MMEA2_ADDRDEC2_RM_SEL_CS23__RM1_MASK 0x000000F0L 16386 #define MMEA2_ADDRDEC2_RM_SEL_CS23__RM2_MASK 0x00000F00L 16387 #define MMEA2_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 16388 #define MMEA2_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 16389 #define MMEA2_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 16390 //MMEA2_ADDRDEC2_RM_SEL_SECCS01 16391 #define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT 0x0 16392 #define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT 0x4 16393 #define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT 0x8 16394 #define MMEA2_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 16395 #define MMEA2_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 16396 #define MMEA2_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 16397 #define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 16398 #define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 16399 #define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 16400 #define MMEA2_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 16401 #define MMEA2_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 16402 #define MMEA2_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 16403 //MMEA2_ADDRDEC2_RM_SEL_SECCS23 16404 #define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT 0x0 16405 #define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT 0x4 16406 #define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT 0x8 16407 #define MMEA2_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 16408 #define MMEA2_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 16409 #define MMEA2_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 16410 #define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 16411 #define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 16412 #define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 16413 #define MMEA2_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 16414 #define MMEA2_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 16415 #define MMEA2_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 16416 //MMEA2_ADDRNORMDRAM_GLOBAL_CNTL 16417 #define MMEA2_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT 0x14 16418 #define MMEA2_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT 0x15 16419 #define MMEA2_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT 0x16 16420 #define MMEA2_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK 0x00100000L 16421 #define MMEA2_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK 0x00200000L 16422 #define MMEA2_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK 0x00400000L 16423 //MMEA2_ADDRNORMGMI_GLOBAL_CNTL 16424 #define MMEA2_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT 0x14 16425 #define MMEA2_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT 0x15 16426 #define MMEA2_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT 0x16 16427 #define MMEA2_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK 0x00100000L 16428 #define MMEA2_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK 0x00200000L 16429 #define MMEA2_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK 0x00400000L 16430 //MMEA2_IO_RD_CLI2GRP_MAP0 16431 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 16432 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 16433 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 16434 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 16435 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 16436 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 16437 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 16438 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 16439 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 16440 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 16441 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 16442 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 16443 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 16444 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 16445 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 16446 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 16447 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 16448 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 16449 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 16450 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 16451 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 16452 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 16453 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 16454 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 16455 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 16456 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 16457 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 16458 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 16459 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 16460 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 16461 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 16462 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 16463 //MMEA2_IO_RD_CLI2GRP_MAP1 16464 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 16465 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 16466 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 16467 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 16468 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 16469 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 16470 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 16471 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 16472 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 16473 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 16474 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 16475 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 16476 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 16477 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 16478 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 16479 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 16480 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 16481 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 16482 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 16483 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 16484 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 16485 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 16486 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 16487 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 16488 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 16489 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 16490 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 16491 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 16492 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 16493 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 16494 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 16495 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 16496 //MMEA2_IO_WR_CLI2GRP_MAP0 16497 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 16498 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 16499 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 16500 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 16501 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 16502 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 16503 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 16504 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 16505 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 16506 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 16507 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 16508 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 16509 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 16510 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 16511 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 16512 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 16513 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 16514 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 16515 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 16516 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 16517 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 16518 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 16519 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 16520 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 16521 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 16522 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 16523 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 16524 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 16525 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 16526 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 16527 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 16528 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 16529 //MMEA2_IO_WR_CLI2GRP_MAP1 16530 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 16531 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 16532 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 16533 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 16534 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 16535 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 16536 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 16537 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 16538 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 16539 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 16540 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 16541 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 16542 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 16543 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 16544 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 16545 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 16546 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 16547 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 16548 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 16549 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 16550 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 16551 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 16552 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 16553 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 16554 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 16555 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 16556 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 16557 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 16558 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 16559 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 16560 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 16561 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 16562 //MMEA2_IO_RD_COMBINE_FLUSH 16563 #define MMEA2_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 16564 #define MMEA2_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 16565 #define MMEA2_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 16566 #define MMEA2_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 16567 #define MMEA2_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT 0x10 16568 #define MMEA2_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 16569 #define MMEA2_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 16570 #define MMEA2_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 16571 #define MMEA2_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 16572 #define MMEA2_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK 0x00010000L 16573 //MMEA2_IO_WR_COMBINE_FLUSH 16574 #define MMEA2_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 16575 #define MMEA2_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 16576 #define MMEA2_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 16577 #define MMEA2_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 16578 #define MMEA2_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT 0x10 16579 #define MMEA2_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 16580 #define MMEA2_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 16581 #define MMEA2_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 16582 #define MMEA2_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 16583 #define MMEA2_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK 0x00010000L 16584 //MMEA2_IO_GROUP_BURST 16585 #define MMEA2_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 16586 #define MMEA2_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 16587 #define MMEA2_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 16588 #define MMEA2_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 16589 #define MMEA2_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL 16590 #define MMEA2_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 16591 #define MMEA2_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 16592 #define MMEA2_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L 16593 //MMEA2_IO_RD_PRI_AGE 16594 #define MMEA2_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 16595 #define MMEA2_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 16596 #define MMEA2_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 16597 #define MMEA2_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 16598 #define MMEA2_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 16599 #define MMEA2_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 16600 #define MMEA2_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 16601 #define MMEA2_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 16602 #define MMEA2_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 16603 #define MMEA2_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 16604 #define MMEA2_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 16605 #define MMEA2_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 16606 #define MMEA2_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 16607 #define MMEA2_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 16608 #define MMEA2_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 16609 #define MMEA2_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 16610 //MMEA2_IO_WR_PRI_AGE 16611 #define MMEA2_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 16612 #define MMEA2_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 16613 #define MMEA2_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 16614 #define MMEA2_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 16615 #define MMEA2_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 16616 #define MMEA2_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 16617 #define MMEA2_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 16618 #define MMEA2_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 16619 #define MMEA2_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 16620 #define MMEA2_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 16621 #define MMEA2_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 16622 #define MMEA2_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 16623 #define MMEA2_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 16624 #define MMEA2_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 16625 #define MMEA2_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 16626 #define MMEA2_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 16627 //MMEA2_IO_RD_PRI_QUEUING 16628 #define MMEA2_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 16629 #define MMEA2_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 16630 #define MMEA2_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 16631 #define MMEA2_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 16632 #define MMEA2_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 16633 #define MMEA2_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 16634 #define MMEA2_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 16635 #define MMEA2_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 16636 //MMEA2_IO_WR_PRI_QUEUING 16637 #define MMEA2_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 16638 #define MMEA2_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 16639 #define MMEA2_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 16640 #define MMEA2_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 16641 #define MMEA2_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 16642 #define MMEA2_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 16643 #define MMEA2_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 16644 #define MMEA2_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 16645 //MMEA2_IO_RD_PRI_FIXED 16646 #define MMEA2_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 16647 #define MMEA2_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 16648 #define MMEA2_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 16649 #define MMEA2_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 16650 #define MMEA2_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 16651 #define MMEA2_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 16652 #define MMEA2_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 16653 #define MMEA2_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 16654 //MMEA2_IO_WR_PRI_FIXED 16655 #define MMEA2_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 16656 #define MMEA2_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 16657 #define MMEA2_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 16658 #define MMEA2_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 16659 #define MMEA2_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 16660 #define MMEA2_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 16661 #define MMEA2_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 16662 #define MMEA2_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 16663 //MMEA2_IO_RD_PRI_URGENCY 16664 #define MMEA2_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 16665 #define MMEA2_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 16666 #define MMEA2_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 16667 #define MMEA2_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 16668 #define MMEA2_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 16669 #define MMEA2_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 16670 #define MMEA2_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 16671 #define MMEA2_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 16672 #define MMEA2_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 16673 #define MMEA2_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 16674 #define MMEA2_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 16675 #define MMEA2_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 16676 #define MMEA2_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 16677 #define MMEA2_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 16678 #define MMEA2_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 16679 #define MMEA2_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 16680 //MMEA2_IO_WR_PRI_URGENCY 16681 #define MMEA2_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 16682 #define MMEA2_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 16683 #define MMEA2_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 16684 #define MMEA2_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 16685 #define MMEA2_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 16686 #define MMEA2_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 16687 #define MMEA2_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 16688 #define MMEA2_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 16689 #define MMEA2_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 16690 #define MMEA2_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 16691 #define MMEA2_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 16692 #define MMEA2_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 16693 #define MMEA2_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 16694 #define MMEA2_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 16695 #define MMEA2_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 16696 #define MMEA2_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 16697 //MMEA2_IO_RD_PRI_URGENCY_MASKING 16698 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 16699 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 16700 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 16701 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 16702 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 16703 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 16704 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 16705 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 16706 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 16707 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 16708 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 16709 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 16710 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 16711 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 16712 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 16713 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 16714 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 16715 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 16716 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 16717 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 16718 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 16719 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 16720 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 16721 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 16722 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 16723 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 16724 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 16725 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 16726 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 16727 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 16728 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 16729 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 16730 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 16731 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 16732 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 16733 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 16734 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 16735 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 16736 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 16737 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 16738 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 16739 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 16740 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 16741 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 16742 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 16743 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 16744 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 16745 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 16746 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 16747 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 16748 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 16749 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 16750 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 16751 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 16752 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 16753 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 16754 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 16755 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 16756 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 16757 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 16758 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 16759 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 16760 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 16761 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 16762 //MMEA2_IO_WR_PRI_URGENCY_MASKING 16763 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 16764 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 16765 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 16766 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 16767 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 16768 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 16769 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 16770 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 16771 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 16772 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 16773 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 16774 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 16775 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 16776 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 16777 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 16778 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 16779 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 16780 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 16781 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 16782 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 16783 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 16784 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 16785 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 16786 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 16787 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 16788 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 16789 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 16790 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 16791 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 16792 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 16793 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 16794 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 16795 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 16796 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 16797 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 16798 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 16799 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 16800 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 16801 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 16802 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 16803 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 16804 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 16805 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 16806 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 16807 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 16808 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 16809 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 16810 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 16811 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 16812 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 16813 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 16814 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 16815 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 16816 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 16817 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 16818 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 16819 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 16820 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 16821 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 16822 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 16823 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 16824 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 16825 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 16826 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 16827 //MMEA2_IO_RD_PRI_QUANT_PRI1 16828 #define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 16829 #define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 16830 #define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 16831 #define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 16832 #define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 16833 #define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 16834 #define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 16835 #define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 16836 //MMEA2_IO_RD_PRI_QUANT_PRI2 16837 #define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 16838 #define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 16839 #define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 16840 #define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 16841 #define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 16842 #define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 16843 #define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 16844 #define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 16845 //MMEA2_IO_RD_PRI_QUANT_PRI3 16846 #define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 16847 #define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 16848 #define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 16849 #define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 16850 #define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 16851 #define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 16852 #define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 16853 #define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 16854 //MMEA2_IO_WR_PRI_QUANT_PRI1 16855 #define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 16856 #define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 16857 #define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 16858 #define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 16859 #define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 16860 #define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 16861 #define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 16862 #define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 16863 //MMEA2_IO_WR_PRI_QUANT_PRI2 16864 #define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 16865 #define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 16866 #define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 16867 #define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 16868 #define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 16869 #define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 16870 #define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 16871 #define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 16872 //MMEA2_IO_WR_PRI_QUANT_PRI3 16873 #define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 16874 #define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 16875 #define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 16876 #define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 16877 #define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 16878 #define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 16879 #define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 16880 #define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 16881 //MMEA2_SDP_ARB_DRAM 16882 #define MMEA2_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 16883 #define MMEA2_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 16884 #define MMEA2_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 16885 #define MMEA2_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 16886 #define MMEA2_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 16887 #define MMEA2_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 16888 #define MMEA2_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 16889 #define MMEA2_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 16890 #define MMEA2_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL 16891 #define MMEA2_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L 16892 #define MMEA2_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L 16893 #define MMEA2_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L 16894 #define MMEA2_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L 16895 #define MMEA2_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L 16896 #define MMEA2_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L 16897 #define MMEA2_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L 16898 //MMEA2_SDP_ARB_GMI 16899 #define MMEA2_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 16900 #define MMEA2_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 16901 #define MMEA2_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT 0x10 16902 #define MMEA2_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT 0x11 16903 #define MMEA2_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT 0x12 16904 #define MMEA2_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT 0x13 16905 #define MMEA2_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT 0x14 16906 #define MMEA2_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 16907 #define MMEA2_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT 0x16 16908 #define MMEA2_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL 16909 #define MMEA2_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L 16910 #define MMEA2_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK 0x00010000L 16911 #define MMEA2_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK 0x00020000L 16912 #define MMEA2_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK 0x00040000L 16913 #define MMEA2_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK 0x00080000L 16914 #define MMEA2_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK 0x00100000L 16915 #define MMEA2_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L 16916 #define MMEA2_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK 0x00400000L 16917 //MMEA2_SDP_ARB_FINAL 16918 #define MMEA2_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 16919 #define MMEA2_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 16920 #define MMEA2_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa 16921 #define MMEA2_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf 16922 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 16923 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 16924 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 16925 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 16926 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 16927 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 16928 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 16929 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 16930 #define MMEA2_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 16931 #define MMEA2_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a 16932 #define MMEA2_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1b 16933 #define MMEA2_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL 16934 #define MMEA2_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L 16935 #define MMEA2_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L 16936 #define MMEA2_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L 16937 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L 16938 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L 16939 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L 16940 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L 16941 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L 16942 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L 16943 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L 16944 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L 16945 #define MMEA2_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L 16946 #define MMEA2_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L 16947 #define MMEA2_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x08000000L 16948 //MMEA2_SDP_DRAM_PRIORITY 16949 #define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 16950 #define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 16951 #define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 16952 #define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 16953 #define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 16954 #define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 16955 #define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 16956 #define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 16957 #define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 16958 #define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 16959 #define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 16960 #define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 16961 #define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 16962 #define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 16963 #define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 16964 #define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 16965 //MMEA2_SDP_GMI_PRIORITY 16966 #define MMEA2_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 16967 #define MMEA2_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 16968 #define MMEA2_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 16969 #define MMEA2_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 16970 #define MMEA2_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 16971 #define MMEA2_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 16972 #define MMEA2_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 16973 #define MMEA2_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 16974 #define MMEA2_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 16975 #define MMEA2_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 16976 #define MMEA2_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 16977 #define MMEA2_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 16978 #define MMEA2_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 16979 #define MMEA2_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 16980 #define MMEA2_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 16981 #define MMEA2_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 16982 //MMEA2_SDP_IO_PRIORITY 16983 #define MMEA2_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 16984 #define MMEA2_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 16985 #define MMEA2_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 16986 #define MMEA2_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 16987 #define MMEA2_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 16988 #define MMEA2_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 16989 #define MMEA2_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 16990 #define MMEA2_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 16991 #define MMEA2_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 16992 #define MMEA2_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 16993 #define MMEA2_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 16994 #define MMEA2_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 16995 #define MMEA2_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 16996 #define MMEA2_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 16997 #define MMEA2_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 16998 #define MMEA2_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 16999 //MMEA2_SDP_CREDITS 17000 #define MMEA2_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 17001 #define MMEA2_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 17002 #define MMEA2_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 17003 #define MMEA2_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL 17004 #define MMEA2_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L 17005 #define MMEA2_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L 17006 //MMEA2_SDP_TAG_RESERVE0 17007 #define MMEA2_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 17008 #define MMEA2_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 17009 #define MMEA2_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 17010 #define MMEA2_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 17011 #define MMEA2_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL 17012 #define MMEA2_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L 17013 #define MMEA2_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L 17014 #define MMEA2_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L 17015 //MMEA2_SDP_TAG_RESERVE1 17016 #define MMEA2_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 17017 #define MMEA2_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 17018 #define MMEA2_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 17019 #define MMEA2_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 17020 #define MMEA2_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL 17021 #define MMEA2_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L 17022 #define MMEA2_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L 17023 #define MMEA2_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L 17024 //MMEA2_SDP_VCC_RESERVE0 17025 #define MMEA2_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 17026 #define MMEA2_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 17027 #define MMEA2_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc 17028 #define MMEA2_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 17029 #define MMEA2_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 17030 #define MMEA2_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 17031 #define MMEA2_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 17032 #define MMEA2_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 17033 #define MMEA2_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 17034 #define MMEA2_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 17035 //MMEA2_SDP_VCC_RESERVE1 17036 #define MMEA2_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 17037 #define MMEA2_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 17038 #define MMEA2_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc 17039 #define MMEA2_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 17040 #define MMEA2_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 17041 #define MMEA2_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 17042 #define MMEA2_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 17043 #define MMEA2_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 17044 //MMEA2_SDP_VCD_RESERVE0 17045 #define MMEA2_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 17046 #define MMEA2_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 17047 #define MMEA2_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc 17048 #define MMEA2_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 17049 #define MMEA2_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 17050 #define MMEA2_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 17051 #define MMEA2_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 17052 #define MMEA2_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 17053 #define MMEA2_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 17054 #define MMEA2_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 17055 //MMEA2_SDP_VCD_RESERVE1 17056 #define MMEA2_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 17057 #define MMEA2_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 17058 #define MMEA2_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc 17059 #define MMEA2_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 17060 #define MMEA2_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 17061 #define MMEA2_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 17062 #define MMEA2_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 17063 #define MMEA2_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 17064 //MMEA2_SDP_REQ_CNTL 17065 #define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 17066 #define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 17067 #define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 17068 #define MMEA2_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 17069 #define MMEA2_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 17070 #define MMEA2_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 17071 #define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L 17072 #define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L 17073 #define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L 17074 #define MMEA2_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L 17075 #define MMEA2_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L 17076 #define MMEA2_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L 17077 //MMEA2_MISC 17078 #define MMEA2_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 17079 #define MMEA2_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 17080 #define MMEA2_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 17081 #define MMEA2_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 17082 #define MMEA2_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 17083 #define MMEA2_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 17084 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 17085 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 17086 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 17087 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 17088 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa 17089 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb 17090 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc 17091 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd 17092 #define MMEA2_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe 17093 #define MMEA2_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf 17094 #define MMEA2_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 17095 #define MMEA2_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 17096 #define MMEA2_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 17097 #define MMEA2_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a 17098 #define MMEA2_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b 17099 #define MMEA2_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c 17100 #define MMEA2_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d 17101 #define MMEA2_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e 17102 #define MMEA2_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f 17103 #define MMEA2_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L 17104 #define MMEA2_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L 17105 #define MMEA2_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L 17106 #define MMEA2_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L 17107 #define MMEA2_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L 17108 #define MMEA2_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L 17109 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L 17110 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L 17111 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L 17112 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L 17113 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L 17114 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L 17115 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L 17116 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L 17117 #define MMEA2_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L 17118 #define MMEA2_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L 17119 #define MMEA2_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L 17120 #define MMEA2_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L 17121 #define MMEA2_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L 17122 #define MMEA2_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L 17123 #define MMEA2_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L 17124 #define MMEA2_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L 17125 #define MMEA2_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L 17126 #define MMEA2_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L 17127 #define MMEA2_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L 17128 //MMEA2_LATENCY_SAMPLING 17129 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 17130 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 17131 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 17132 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 17133 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 17134 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 17135 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 17136 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 17137 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 17138 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 17139 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa 17140 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb 17141 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc 17142 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd 17143 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe 17144 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 17145 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L 17146 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L 17147 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L 17148 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L 17149 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L 17150 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L 17151 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L 17152 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L 17153 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L 17154 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L 17155 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L 17156 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L 17157 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L 17158 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L 17159 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L 17160 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L 17161 //MMEA2_PERFCOUNTER_LO 17162 #define MMEA2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 17163 #define MMEA2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 17164 //MMEA2_PERFCOUNTER_HI 17165 #define MMEA2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 17166 #define MMEA2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 17167 #define MMEA2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 17168 #define MMEA2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 17169 //MMEA2_PERFCOUNTER0_CFG 17170 #define MMEA2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 17171 #define MMEA2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 17172 #define MMEA2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 17173 #define MMEA2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 17174 #define MMEA2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 17175 #define MMEA2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 17176 #define MMEA2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 17177 #define MMEA2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 17178 #define MMEA2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 17179 #define MMEA2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 17180 //MMEA2_PERFCOUNTER1_CFG 17181 #define MMEA2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 17182 #define MMEA2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 17183 #define MMEA2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 17184 #define MMEA2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 17185 #define MMEA2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 17186 #define MMEA2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 17187 #define MMEA2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 17188 #define MMEA2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 17189 #define MMEA2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 17190 #define MMEA2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 17191 //MMEA2_PERFCOUNTER_RSLT_CNTL 17192 #define MMEA2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 17193 #define MMEA2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 17194 #define MMEA2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 17195 #define MMEA2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 17196 #define MMEA2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 17197 #define MMEA2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 17198 #define MMEA2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 17199 #define MMEA2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 17200 #define MMEA2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 17201 #define MMEA2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 17202 #define MMEA2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 17203 #define MMEA2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 17204 //MMEA2_EDC_CNT 17205 #define MMEA2_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 17206 #define MMEA2_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 17207 #define MMEA2_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 17208 #define MMEA2_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 17209 #define MMEA2_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 17210 #define MMEA2_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa 17211 #define MMEA2_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc 17212 #define MMEA2_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe 17213 #define MMEA2_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 17214 #define MMEA2_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 17215 #define MMEA2_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 17216 #define MMEA2_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 17217 #define MMEA2_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 17218 #define MMEA2_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a 17219 #define MMEA2_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c 17220 #define MMEA2_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 17221 #define MMEA2_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 17222 #define MMEA2_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 17223 #define MMEA2_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 17224 #define MMEA2_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 17225 #define MMEA2_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 17226 #define MMEA2_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L 17227 #define MMEA2_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L 17228 #define MMEA2_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L 17229 #define MMEA2_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L 17230 #define MMEA2_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L 17231 #define MMEA2_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L 17232 #define MMEA2_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L 17233 #define MMEA2_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L 17234 #define MMEA2_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L 17235 //MMEA2_EDC_CNT2 17236 #define MMEA2_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 17237 #define MMEA2_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 17238 #define MMEA2_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 17239 #define MMEA2_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 17240 #define MMEA2_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 17241 #define MMEA2_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa 17242 #define MMEA2_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc 17243 #define MMEA2_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe 17244 #define MMEA2_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10 17245 #define MMEA2_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12 17246 #define MMEA2_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14 17247 #define MMEA2_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16 17248 #define MMEA2_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT 0x18 17249 #define MMEA2_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT 0x1a 17250 #define MMEA2_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT 0x1c 17251 #define MMEA2_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT 0x1e 17252 #define MMEA2_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 17253 #define MMEA2_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 17254 #define MMEA2_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 17255 #define MMEA2_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 17256 #define MMEA2_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 17257 #define MMEA2_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 17258 #define MMEA2_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L 17259 #define MMEA2_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L 17260 #define MMEA2_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L 17261 #define MMEA2_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L 17262 #define MMEA2_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L 17263 #define MMEA2_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L 17264 #define MMEA2_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK 0x03000000L 17265 #define MMEA2_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK 0x0C000000L 17266 #define MMEA2_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK 0x30000000L 17267 #define MMEA2_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK 0xC0000000L 17268 //MMEA2_DSM_CNTL 17269 #define MMEA2_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 17270 #define MMEA2_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 17271 #define MMEA2_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 17272 #define MMEA2_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 17273 #define MMEA2_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 17274 #define MMEA2_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 17275 #define MMEA2_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 17276 #define MMEA2_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 17277 #define MMEA2_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 17278 #define MMEA2_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 17279 #define MMEA2_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 17280 #define MMEA2_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 17281 #define MMEA2_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 17282 #define MMEA2_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 17283 #define MMEA2_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 17284 #define MMEA2_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 17285 #define MMEA2_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 17286 #define MMEA2_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 17287 #define MMEA2_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 17288 #define MMEA2_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 17289 #define MMEA2_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 17290 #define MMEA2_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 17291 #define MMEA2_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 17292 #define MMEA2_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 17293 #define MMEA2_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 17294 #define MMEA2_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 17295 #define MMEA2_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 17296 #define MMEA2_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 17297 #define MMEA2_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 17298 #define MMEA2_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 17299 #define MMEA2_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L 17300 #define MMEA2_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L 17301 //MMEA2_DSM_CNTLA 17302 #define MMEA2_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 17303 #define MMEA2_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 17304 #define MMEA2_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 17305 #define MMEA2_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 17306 #define MMEA2_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 17307 #define MMEA2_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 17308 #define MMEA2_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 17309 #define MMEA2_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 17310 #define MMEA2_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 17311 #define MMEA2_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 17312 #define MMEA2_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 17313 #define MMEA2_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 17314 #define MMEA2_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 17315 #define MMEA2_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 17316 #define MMEA2_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 17317 #define MMEA2_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 17318 #define MMEA2_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 17319 #define MMEA2_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 17320 #define MMEA2_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 17321 #define MMEA2_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 17322 #define MMEA2_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 17323 #define MMEA2_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 17324 #define MMEA2_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 17325 #define MMEA2_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 17326 #define MMEA2_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 17327 #define MMEA2_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 17328 #define MMEA2_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 17329 #define MMEA2_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 17330 //MMEA2_DSM_CNTL2 17331 #define MMEA2_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 17332 #define MMEA2_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 17333 #define MMEA2_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 17334 #define MMEA2_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 17335 #define MMEA2_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 17336 #define MMEA2_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 17337 #define MMEA2_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 17338 #define MMEA2_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb 17339 #define MMEA2_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 17340 #define MMEA2_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe 17341 #define MMEA2_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 17342 #define MMEA2_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 17343 #define MMEA2_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 17344 #define MMEA2_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 17345 #define MMEA2_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 17346 #define MMEA2_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 17347 #define MMEA2_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a 17348 #define MMEA2_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 17349 #define MMEA2_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 17350 #define MMEA2_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 17351 #define MMEA2_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 17352 #define MMEA2_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 17353 #define MMEA2_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 17354 #define MMEA2_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 17355 #define MMEA2_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 17356 #define MMEA2_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 17357 #define MMEA2_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 17358 #define MMEA2_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 17359 #define MMEA2_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 17360 #define MMEA2_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 17361 #define MMEA2_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 17362 #define MMEA2_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L 17363 #define MMEA2_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L 17364 #define MMEA2_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L 17365 //MMEA2_DSM_CNTL2A 17366 #define MMEA2_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 17367 #define MMEA2_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 17368 #define MMEA2_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 17369 #define MMEA2_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 17370 #define MMEA2_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 17371 #define MMEA2_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 17372 #define MMEA2_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 17373 #define MMEA2_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb 17374 #define MMEA2_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 17375 #define MMEA2_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe 17376 #define MMEA2_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 17377 #define MMEA2_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 17378 #define MMEA2_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 17379 #define MMEA2_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 17380 #define MMEA2_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 17381 #define MMEA2_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 17382 #define MMEA2_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 17383 #define MMEA2_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 17384 #define MMEA2_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 17385 #define MMEA2_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 17386 #define MMEA2_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 17387 #define MMEA2_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 17388 #define MMEA2_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 17389 #define MMEA2_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 17390 #define MMEA2_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 17391 #define MMEA2_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 17392 #define MMEA2_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 17393 #define MMEA2_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 17394 //MMEA2_CGTT_CLK_CTRL 17395 #define MMEA2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 17396 #define MMEA2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 17397 #define MMEA2_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc 17398 #define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 17399 #define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 17400 #define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 17401 #define MMEA2_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 17402 #define MMEA2_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 17403 #define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c 17404 #define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d 17405 #define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e 17406 #define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f 17407 #define MMEA2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 17408 #define MMEA2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 17409 #define MMEA2_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L 17410 #define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L 17411 #define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L 17412 #define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L 17413 #define MMEA2_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L 17414 #define MMEA2_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 17415 #define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L 17416 #define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L 17417 #define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L 17418 #define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L 17419 //MMEA2_EDC_MODE 17420 #define MMEA2_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 17421 #define MMEA2_EDC_MODE__GATE_FUE__SHIFT 0x11 17422 #define MMEA2_EDC_MODE__DED_MODE__SHIFT 0x14 17423 #define MMEA2_EDC_MODE__PROP_FED__SHIFT 0x1d 17424 #define MMEA2_EDC_MODE__BYPASS__SHIFT 0x1f 17425 #define MMEA2_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L 17426 #define MMEA2_EDC_MODE__GATE_FUE_MASK 0x00020000L 17427 #define MMEA2_EDC_MODE__DED_MODE_MASK 0x00300000L 17428 #define MMEA2_EDC_MODE__PROP_FED_MASK 0x20000000L 17429 #define MMEA2_EDC_MODE__BYPASS_MASK 0x80000000L 17430 //MMEA2_ERR_STATUS 17431 #define MMEA2_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 17432 #define MMEA2_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 17433 #define MMEA2_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 17434 #define MMEA2_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa 17435 #define MMEA2_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb 17436 #define MMEA2_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc 17437 #define MMEA2_ERR_STATUS__FUE_FLAG__SHIFT 0xd 17438 #define MMEA2_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL 17439 #define MMEA2_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L 17440 #define MMEA2_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L 17441 #define MMEA2_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L 17442 #define MMEA2_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L 17443 #define MMEA2_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L 17444 #define MMEA2_ERR_STATUS__FUE_FLAG_MASK 0x00002000L 17445 //MMEA2_MISC2 17446 #define MMEA2_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 17447 #define MMEA2_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 17448 #define MMEA2_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 17449 #define MMEA2_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 17450 #define MMEA2_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc 17451 #define MMEA2_MISC2__RRET_SWAP_MODE__SHIFT 0xd 17452 #define MMEA2_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L 17453 #define MMEA2_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L 17454 #define MMEA2_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL 17455 #define MMEA2_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L 17456 #define MMEA2_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L 17457 #define MMEA2_MISC2__RRET_SWAP_MODE_MASK 0x00002000L 17458 //MMEA2_ADDRDEC_SELECT 17459 #define MMEA2_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0 17460 #define MMEA2_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5 17461 #define MMEA2_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa 17462 #define MMEA2_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf 17463 #define MMEA2_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL 17464 #define MMEA2_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L 17465 #define MMEA2_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L 17466 #define MMEA2_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L 17467 //MMEA2_EDC_CNT3 17468 #define MMEA2_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0 17469 #define MMEA2_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2 17470 #define MMEA2_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4 17471 #define MMEA2_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6 17472 #define MMEA2_EDC_CNT3__IOWR_DATAMEM_DED_COUNT__SHIFT 0x8 17473 #define MMEA2_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0xa 17474 #define MMEA2_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xc 17475 #define MMEA2_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L 17476 #define MMEA2_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL 17477 #define MMEA2_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L 17478 #define MMEA2_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 17479 #define MMEA2_EDC_CNT3__IOWR_DATAMEM_DED_COUNT_MASK 0x00000300L 17480 #define MMEA2_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000C00L 17481 #define MMEA2_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00003000L 17482 17483 17484 // addressBlock: mmhub_ea_mmeadec3 17485 //MMEA3_DRAM_RD_CLI2GRP_MAP0 17486 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 17487 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 17488 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 17489 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 17490 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 17491 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 17492 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 17493 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 17494 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 17495 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 17496 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 17497 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 17498 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 17499 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 17500 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 17501 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 17502 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 17503 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 17504 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 17505 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 17506 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 17507 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 17508 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 17509 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 17510 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 17511 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 17512 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 17513 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 17514 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 17515 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 17516 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 17517 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 17518 //MMEA3_DRAM_RD_CLI2GRP_MAP1 17519 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 17520 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 17521 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 17522 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 17523 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 17524 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 17525 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 17526 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 17527 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 17528 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 17529 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 17530 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 17531 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 17532 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 17533 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 17534 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 17535 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 17536 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 17537 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 17538 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 17539 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 17540 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 17541 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 17542 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 17543 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 17544 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 17545 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 17546 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 17547 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 17548 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 17549 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 17550 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 17551 //MMEA3_DRAM_WR_CLI2GRP_MAP0 17552 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 17553 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 17554 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 17555 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 17556 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 17557 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 17558 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 17559 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 17560 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 17561 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 17562 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 17563 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 17564 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 17565 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 17566 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 17567 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 17568 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 17569 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 17570 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 17571 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 17572 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 17573 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 17574 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 17575 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 17576 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 17577 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 17578 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 17579 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 17580 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 17581 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 17582 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 17583 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 17584 //MMEA3_DRAM_WR_CLI2GRP_MAP1 17585 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 17586 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 17587 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 17588 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 17589 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 17590 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 17591 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 17592 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 17593 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 17594 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 17595 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 17596 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 17597 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 17598 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 17599 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 17600 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 17601 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 17602 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 17603 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 17604 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 17605 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 17606 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 17607 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 17608 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 17609 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 17610 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 17611 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 17612 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 17613 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 17614 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 17615 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 17616 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 17617 //MMEA3_DRAM_RD_GRP2VC_MAP 17618 #define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 17619 #define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 17620 #define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 17621 #define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 17622 #define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 17623 #define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 17624 #define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 17625 #define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 17626 //MMEA3_DRAM_WR_GRP2VC_MAP 17627 #define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 17628 #define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 17629 #define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 17630 #define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 17631 #define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 17632 #define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 17633 #define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 17634 #define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 17635 //MMEA3_DRAM_RD_LAZY 17636 #define MMEA3_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 17637 #define MMEA3_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 17638 #define MMEA3_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 17639 #define MMEA3_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 17640 #define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 17641 #define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 17642 #define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 17643 #define MMEA3_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L 17644 #define MMEA3_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L 17645 #define MMEA3_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L 17646 #define MMEA3_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L 17647 #define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 17648 #define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 17649 #define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 17650 //MMEA3_DRAM_WR_LAZY 17651 #define MMEA3_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 17652 #define MMEA3_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 17653 #define MMEA3_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 17654 #define MMEA3_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 17655 #define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 17656 #define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 17657 #define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 17658 #define MMEA3_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L 17659 #define MMEA3_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L 17660 #define MMEA3_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L 17661 #define MMEA3_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L 17662 #define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 17663 #define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 17664 #define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 17665 //MMEA3_DRAM_RD_CAM_CNTL 17666 #define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 17667 #define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 17668 #define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 17669 #define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 17670 #define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 17671 #define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 17672 #define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 17673 #define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 17674 #define MMEA3_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 17675 #define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 17676 #define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 17677 #define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 17678 #define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 17679 #define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 17680 #define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 17681 #define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 17682 #define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 17683 #define MMEA3_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 17684 //MMEA3_DRAM_WR_CAM_CNTL 17685 #define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 17686 #define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 17687 #define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 17688 #define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 17689 #define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 17690 #define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 17691 #define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 17692 #define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 17693 #define MMEA3_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 17694 #define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 17695 #define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 17696 #define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 17697 #define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 17698 #define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 17699 #define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 17700 #define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 17701 #define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 17702 #define MMEA3_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 17703 //MMEA3_DRAM_PAGE_BURST 17704 #define MMEA3_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 17705 #define MMEA3_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 17706 #define MMEA3_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 17707 #define MMEA3_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 17708 #define MMEA3_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL 17709 #define MMEA3_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 17710 #define MMEA3_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 17711 #define MMEA3_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L 17712 //MMEA3_DRAM_RD_PRI_AGE 17713 #define MMEA3_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 17714 #define MMEA3_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 17715 #define MMEA3_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 17716 #define MMEA3_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 17717 #define MMEA3_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 17718 #define MMEA3_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 17719 #define MMEA3_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 17720 #define MMEA3_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 17721 #define MMEA3_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 17722 #define MMEA3_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 17723 #define MMEA3_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 17724 #define MMEA3_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 17725 #define MMEA3_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 17726 #define MMEA3_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 17727 #define MMEA3_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 17728 #define MMEA3_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 17729 //MMEA3_DRAM_WR_PRI_AGE 17730 #define MMEA3_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 17731 #define MMEA3_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 17732 #define MMEA3_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 17733 #define MMEA3_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 17734 #define MMEA3_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 17735 #define MMEA3_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 17736 #define MMEA3_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 17737 #define MMEA3_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 17738 #define MMEA3_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 17739 #define MMEA3_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 17740 #define MMEA3_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 17741 #define MMEA3_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 17742 #define MMEA3_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 17743 #define MMEA3_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 17744 #define MMEA3_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 17745 #define MMEA3_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 17746 //MMEA3_DRAM_RD_PRI_QUEUING 17747 #define MMEA3_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 17748 #define MMEA3_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 17749 #define MMEA3_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 17750 #define MMEA3_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 17751 #define MMEA3_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 17752 #define MMEA3_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 17753 #define MMEA3_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 17754 #define MMEA3_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 17755 //MMEA3_DRAM_WR_PRI_QUEUING 17756 #define MMEA3_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 17757 #define MMEA3_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 17758 #define MMEA3_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 17759 #define MMEA3_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 17760 #define MMEA3_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 17761 #define MMEA3_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 17762 #define MMEA3_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 17763 #define MMEA3_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 17764 //MMEA3_DRAM_RD_PRI_FIXED 17765 #define MMEA3_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 17766 #define MMEA3_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 17767 #define MMEA3_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 17768 #define MMEA3_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 17769 #define MMEA3_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 17770 #define MMEA3_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 17771 #define MMEA3_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 17772 #define MMEA3_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 17773 //MMEA3_DRAM_WR_PRI_FIXED 17774 #define MMEA3_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 17775 #define MMEA3_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 17776 #define MMEA3_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 17777 #define MMEA3_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 17778 #define MMEA3_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 17779 #define MMEA3_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 17780 #define MMEA3_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 17781 #define MMEA3_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 17782 //MMEA3_DRAM_RD_PRI_URGENCY 17783 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 17784 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 17785 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 17786 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 17787 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 17788 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 17789 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 17790 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 17791 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 17792 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 17793 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 17794 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 17795 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 17796 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 17797 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 17798 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 17799 //MMEA3_DRAM_WR_PRI_URGENCY 17800 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 17801 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 17802 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 17803 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 17804 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 17805 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 17806 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 17807 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 17808 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 17809 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 17810 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 17811 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 17812 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 17813 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 17814 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 17815 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 17816 //MMEA3_DRAM_RD_PRI_QUANT_PRI1 17817 #define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 17818 #define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 17819 #define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 17820 #define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 17821 #define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 17822 #define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 17823 #define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 17824 #define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 17825 //MMEA3_DRAM_RD_PRI_QUANT_PRI2 17826 #define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 17827 #define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 17828 #define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 17829 #define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 17830 #define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 17831 #define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 17832 #define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 17833 #define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 17834 //MMEA3_DRAM_RD_PRI_QUANT_PRI3 17835 #define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 17836 #define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 17837 #define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 17838 #define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 17839 #define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 17840 #define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 17841 #define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 17842 #define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 17843 //MMEA3_DRAM_WR_PRI_QUANT_PRI1 17844 #define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 17845 #define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 17846 #define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 17847 #define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 17848 #define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 17849 #define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 17850 #define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 17851 #define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 17852 //MMEA3_DRAM_WR_PRI_QUANT_PRI2 17853 #define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 17854 #define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 17855 #define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 17856 #define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 17857 #define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 17858 #define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 17859 #define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 17860 #define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 17861 //MMEA3_DRAM_WR_PRI_QUANT_PRI3 17862 #define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 17863 #define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 17864 #define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 17865 #define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 17866 #define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 17867 #define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 17868 #define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 17869 #define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 17870 //MMEA3_GMI_RD_CLI2GRP_MAP0 17871 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 17872 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 17873 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 17874 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 17875 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 17876 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 17877 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 17878 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 17879 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 17880 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 17881 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 17882 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 17883 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 17884 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 17885 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 17886 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 17887 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 17888 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 17889 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 17890 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 17891 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 17892 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 17893 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 17894 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 17895 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 17896 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 17897 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 17898 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 17899 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 17900 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 17901 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 17902 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 17903 //MMEA3_GMI_RD_CLI2GRP_MAP1 17904 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 17905 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 17906 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 17907 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 17908 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 17909 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 17910 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 17911 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 17912 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 17913 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 17914 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 17915 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 17916 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 17917 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 17918 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 17919 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 17920 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 17921 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 17922 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 17923 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 17924 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 17925 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 17926 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 17927 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 17928 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 17929 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 17930 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 17931 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 17932 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 17933 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 17934 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 17935 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 17936 //MMEA3_GMI_WR_CLI2GRP_MAP0 17937 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 17938 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 17939 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 17940 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 17941 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 17942 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 17943 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 17944 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 17945 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 17946 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 17947 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 17948 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 17949 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 17950 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 17951 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 17952 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 17953 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 17954 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 17955 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 17956 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 17957 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 17958 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 17959 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 17960 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 17961 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 17962 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 17963 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 17964 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 17965 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 17966 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 17967 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 17968 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 17969 //MMEA3_GMI_WR_CLI2GRP_MAP1 17970 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 17971 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 17972 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 17973 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 17974 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 17975 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 17976 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 17977 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 17978 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 17979 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 17980 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 17981 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 17982 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 17983 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 17984 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 17985 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 17986 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 17987 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 17988 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 17989 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 17990 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 17991 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 17992 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 17993 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 17994 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 17995 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 17996 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 17997 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 17998 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 17999 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 18000 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 18001 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 18002 //MMEA3_GMI_RD_GRP2VC_MAP 18003 #define MMEA3_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 18004 #define MMEA3_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 18005 #define MMEA3_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 18006 #define MMEA3_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 18007 #define MMEA3_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 18008 #define MMEA3_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 18009 #define MMEA3_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 18010 #define MMEA3_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 18011 //MMEA3_GMI_WR_GRP2VC_MAP 18012 #define MMEA3_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 18013 #define MMEA3_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 18014 #define MMEA3_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 18015 #define MMEA3_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 18016 #define MMEA3_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 18017 #define MMEA3_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 18018 #define MMEA3_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 18019 #define MMEA3_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 18020 //MMEA3_GMI_RD_LAZY 18021 #define MMEA3_GMI_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 18022 #define MMEA3_GMI_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 18023 #define MMEA3_GMI_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 18024 #define MMEA3_GMI_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 18025 #define MMEA3_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 18026 #define MMEA3_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 18027 #define MMEA3_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 18028 #define MMEA3_GMI_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L 18029 #define MMEA3_GMI_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L 18030 #define MMEA3_GMI_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L 18031 #define MMEA3_GMI_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L 18032 #define MMEA3_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 18033 #define MMEA3_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 18034 #define MMEA3_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 18035 //MMEA3_GMI_WR_LAZY 18036 #define MMEA3_GMI_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 18037 #define MMEA3_GMI_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 18038 #define MMEA3_GMI_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 18039 #define MMEA3_GMI_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 18040 #define MMEA3_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 18041 #define MMEA3_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 18042 #define MMEA3_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 18043 #define MMEA3_GMI_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L 18044 #define MMEA3_GMI_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L 18045 #define MMEA3_GMI_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L 18046 #define MMEA3_GMI_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L 18047 #define MMEA3_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 18048 #define MMEA3_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 18049 #define MMEA3_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 18050 //MMEA3_GMI_RD_CAM_CNTL 18051 #define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 18052 #define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 18053 #define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 18054 #define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 18055 #define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 18056 #define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 18057 #define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 18058 #define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 18059 #define MMEA3_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 18060 #define MMEA3_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d 18061 #define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 18062 #define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 18063 #define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 18064 #define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 18065 #define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 18066 #define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 18067 #define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 18068 #define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 18069 #define MMEA3_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 18070 #define MMEA3_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L 18071 //MMEA3_GMI_WR_CAM_CNTL 18072 #define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 18073 #define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 18074 #define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 18075 #define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 18076 #define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 18077 #define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 18078 #define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 18079 #define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 18080 #define MMEA3_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 18081 #define MMEA3_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d 18082 #define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 18083 #define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 18084 #define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 18085 #define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 18086 #define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 18087 #define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 18088 #define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 18089 #define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 18090 #define MMEA3_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 18091 #define MMEA3_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L 18092 //MMEA3_GMI_PAGE_BURST 18093 #define MMEA3_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 18094 #define MMEA3_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 18095 #define MMEA3_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 18096 #define MMEA3_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 18097 #define MMEA3_GMI_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL 18098 #define MMEA3_GMI_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 18099 #define MMEA3_GMI_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 18100 #define MMEA3_GMI_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L 18101 //MMEA3_GMI_RD_PRI_AGE 18102 #define MMEA3_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 18103 #define MMEA3_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 18104 #define MMEA3_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 18105 #define MMEA3_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 18106 #define MMEA3_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 18107 #define MMEA3_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 18108 #define MMEA3_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 18109 #define MMEA3_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 18110 #define MMEA3_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 18111 #define MMEA3_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 18112 #define MMEA3_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 18113 #define MMEA3_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 18114 #define MMEA3_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 18115 #define MMEA3_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 18116 #define MMEA3_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 18117 #define MMEA3_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 18118 //MMEA3_GMI_WR_PRI_AGE 18119 #define MMEA3_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 18120 #define MMEA3_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 18121 #define MMEA3_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 18122 #define MMEA3_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 18123 #define MMEA3_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 18124 #define MMEA3_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 18125 #define MMEA3_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 18126 #define MMEA3_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 18127 #define MMEA3_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 18128 #define MMEA3_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 18129 #define MMEA3_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 18130 #define MMEA3_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 18131 #define MMEA3_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 18132 #define MMEA3_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 18133 #define MMEA3_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 18134 #define MMEA3_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 18135 //MMEA3_GMI_RD_PRI_QUEUING 18136 #define MMEA3_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 18137 #define MMEA3_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 18138 #define MMEA3_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 18139 #define MMEA3_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 18140 #define MMEA3_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 18141 #define MMEA3_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 18142 #define MMEA3_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 18143 #define MMEA3_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 18144 //MMEA3_GMI_WR_PRI_QUEUING 18145 #define MMEA3_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 18146 #define MMEA3_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 18147 #define MMEA3_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 18148 #define MMEA3_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 18149 #define MMEA3_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 18150 #define MMEA3_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 18151 #define MMEA3_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 18152 #define MMEA3_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 18153 //MMEA3_GMI_RD_PRI_FIXED 18154 #define MMEA3_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 18155 #define MMEA3_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 18156 #define MMEA3_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 18157 #define MMEA3_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 18158 #define MMEA3_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 18159 #define MMEA3_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 18160 #define MMEA3_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 18161 #define MMEA3_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 18162 //MMEA3_GMI_WR_PRI_FIXED 18163 #define MMEA3_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 18164 #define MMEA3_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 18165 #define MMEA3_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 18166 #define MMEA3_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 18167 #define MMEA3_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 18168 #define MMEA3_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 18169 #define MMEA3_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 18170 #define MMEA3_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 18171 //MMEA3_GMI_RD_PRI_URGENCY 18172 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 18173 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 18174 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 18175 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 18176 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 18177 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 18178 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 18179 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 18180 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 18181 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 18182 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 18183 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 18184 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 18185 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 18186 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 18187 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 18188 //MMEA3_GMI_WR_PRI_URGENCY 18189 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 18190 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 18191 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 18192 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 18193 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 18194 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 18195 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 18196 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 18197 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 18198 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 18199 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 18200 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 18201 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 18202 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 18203 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 18204 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 18205 //MMEA3_GMI_RD_PRI_URGENCY_MASKING 18206 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 18207 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 18208 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 18209 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 18210 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 18211 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 18212 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 18213 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 18214 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 18215 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 18216 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 18217 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 18218 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 18219 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 18220 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 18221 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 18222 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 18223 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 18224 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 18225 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 18226 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 18227 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 18228 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 18229 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 18230 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 18231 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 18232 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 18233 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 18234 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 18235 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 18236 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 18237 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 18238 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 18239 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 18240 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 18241 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 18242 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 18243 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 18244 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 18245 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 18246 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 18247 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 18248 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 18249 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 18250 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 18251 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 18252 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 18253 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 18254 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 18255 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 18256 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 18257 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 18258 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 18259 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 18260 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 18261 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 18262 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 18263 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 18264 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 18265 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 18266 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 18267 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 18268 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 18269 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 18270 //MMEA3_GMI_WR_PRI_URGENCY_MASKING 18271 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 18272 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 18273 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 18274 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 18275 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 18276 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 18277 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 18278 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 18279 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 18280 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 18281 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 18282 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 18283 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 18284 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 18285 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 18286 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 18287 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 18288 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 18289 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 18290 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 18291 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 18292 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 18293 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 18294 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 18295 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 18296 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 18297 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 18298 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 18299 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 18300 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 18301 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 18302 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 18303 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 18304 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 18305 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 18306 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 18307 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 18308 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 18309 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 18310 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 18311 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 18312 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 18313 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 18314 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 18315 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 18316 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 18317 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 18318 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 18319 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 18320 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 18321 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 18322 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 18323 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 18324 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 18325 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 18326 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 18327 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 18328 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 18329 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 18330 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 18331 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 18332 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 18333 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 18334 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 18335 //MMEA3_GMI_RD_PRI_QUANT_PRI1 18336 #define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 18337 #define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 18338 #define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 18339 #define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 18340 #define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 18341 #define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 18342 #define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 18343 #define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 18344 //MMEA3_GMI_RD_PRI_QUANT_PRI2 18345 #define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 18346 #define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 18347 #define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 18348 #define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 18349 #define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 18350 #define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 18351 #define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 18352 #define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 18353 //MMEA3_GMI_RD_PRI_QUANT_PRI3 18354 #define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 18355 #define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 18356 #define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 18357 #define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 18358 #define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 18359 #define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 18360 #define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 18361 #define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 18362 //MMEA3_GMI_WR_PRI_QUANT_PRI1 18363 #define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 18364 #define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 18365 #define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 18366 #define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 18367 #define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 18368 #define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 18369 #define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 18370 #define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 18371 //MMEA3_GMI_WR_PRI_QUANT_PRI2 18372 #define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 18373 #define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 18374 #define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 18375 #define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 18376 #define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 18377 #define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 18378 #define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 18379 #define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 18380 //MMEA3_GMI_WR_PRI_QUANT_PRI3 18381 #define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 18382 #define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 18383 #define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 18384 #define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 18385 #define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 18386 #define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 18387 #define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 18388 #define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 18389 //MMEA3_ADDRNORM_BASE_ADDR0 18390 #define MMEA3_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 18391 #define MMEA3_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 18392 #define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 18393 #define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x6 18394 #define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 18395 #define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 18396 #define MMEA3_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc 18397 #define MMEA3_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L 18398 #define MMEA3_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 18399 #define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000003CL 18400 #define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x000000C0L 18401 #define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L 18402 #define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L 18403 #define MMEA3_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L 18404 //MMEA3_ADDRNORM_LIMIT_ADDR0 18405 #define MMEA3_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 18406 #define MMEA3_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc 18407 #define MMEA3_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL 18408 #define MMEA3_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L 18409 //MMEA3_ADDRNORM_BASE_ADDR1 18410 #define MMEA3_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 18411 #define MMEA3_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 18412 #define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 18413 #define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x6 18414 #define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 18415 #define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 18416 #define MMEA3_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc 18417 #define MMEA3_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L 18418 #define MMEA3_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 18419 #define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000003CL 18420 #define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x000000C0L 18421 #define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L 18422 #define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L 18423 #define MMEA3_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L 18424 //MMEA3_ADDRNORM_LIMIT_ADDR1 18425 #define MMEA3_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 18426 #define MMEA3_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc 18427 #define MMEA3_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL 18428 #define MMEA3_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L 18429 //MMEA3_ADDRNORM_OFFSET_ADDR1 18430 #define MMEA3_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 18431 #define MMEA3_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 18432 #define MMEA3_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L 18433 #define MMEA3_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L 18434 //MMEA3_ADDRNORM_BASE_ADDR2 18435 #define MMEA3_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT 0x0 18436 #define MMEA3_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT 0x1 18437 #define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT 0x2 18438 #define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT 0x6 18439 #define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT 0x8 18440 #define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT 0x9 18441 #define MMEA3_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT 0xc 18442 #define MMEA3_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK 0x00000001L 18443 #define MMEA3_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 18444 #define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK 0x0000003CL 18445 #define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK 0x000000C0L 18446 #define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK 0x00000100L 18447 #define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK 0x00000E00L 18448 #define MMEA3_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK 0xFFFFF000L 18449 //MMEA3_ADDRNORM_LIMIT_ADDR2 18450 #define MMEA3_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT 0x0 18451 #define MMEA3_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT 0xc 18452 #define MMEA3_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK 0x0000001FL 18453 #define MMEA3_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK 0xFFFFF000L 18454 //MMEA3_ADDRNORM_BASE_ADDR3 18455 #define MMEA3_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT 0x0 18456 #define MMEA3_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT 0x1 18457 #define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT 0x2 18458 #define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT 0x6 18459 #define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT 0x8 18460 #define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT 0x9 18461 #define MMEA3_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT 0xc 18462 #define MMEA3_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK 0x00000001L 18463 #define MMEA3_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 18464 #define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK 0x0000003CL 18465 #define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK 0x000000C0L 18466 #define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK 0x00000100L 18467 #define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK 0x00000E00L 18468 #define MMEA3_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK 0xFFFFF000L 18469 //MMEA3_ADDRNORM_LIMIT_ADDR3 18470 #define MMEA3_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT 0x0 18471 #define MMEA3_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT 0xc 18472 #define MMEA3_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK 0x0000001FL 18473 #define MMEA3_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK 0xFFFFF000L 18474 //MMEA3_ADDRNORM_OFFSET_ADDR3 18475 #define MMEA3_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT 0x0 18476 #define MMEA3_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT 0x14 18477 #define MMEA3_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK 0x00000001L 18478 #define MMEA3_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK 0xFFF00000L 18479 //MMEA3_ADDRNORM_BASE_ADDR4 18480 #define MMEA3_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL__SHIFT 0x0 18481 #define MMEA3_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN__SHIFT 0x1 18482 #define MMEA3_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN__SHIFT 0x2 18483 #define MMEA3_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES__SHIFT 0x6 18484 #define MMEA3_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS__SHIFT 0x8 18485 #define MMEA3_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL__SHIFT 0x9 18486 #define MMEA3_ADDRNORM_BASE_ADDR4__BASE_ADDR__SHIFT 0xc 18487 #define MMEA3_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL_MASK 0x00000001L 18488 #define MMEA3_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 18489 #define MMEA3_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN_MASK 0x0000003CL 18490 #define MMEA3_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES_MASK 0x000000C0L 18491 #define MMEA3_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS_MASK 0x00000100L 18492 #define MMEA3_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL_MASK 0x00000E00L 18493 #define MMEA3_ADDRNORM_BASE_ADDR4__BASE_ADDR_MASK 0xFFFFF000L 18494 //MMEA3_ADDRNORM_LIMIT_ADDR4 18495 #define MMEA3_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID__SHIFT 0x0 18496 #define MMEA3_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR__SHIFT 0xc 18497 #define MMEA3_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID_MASK 0x0000001FL 18498 #define MMEA3_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR_MASK 0xFFFFF000L 18499 //MMEA3_ADDRNORM_BASE_ADDR5 18500 #define MMEA3_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL__SHIFT 0x0 18501 #define MMEA3_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN__SHIFT 0x1 18502 #define MMEA3_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN__SHIFT 0x2 18503 #define MMEA3_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES__SHIFT 0x6 18504 #define MMEA3_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS__SHIFT 0x8 18505 #define MMEA3_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL__SHIFT 0x9 18506 #define MMEA3_ADDRNORM_BASE_ADDR5__BASE_ADDR__SHIFT 0xc 18507 #define MMEA3_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL_MASK 0x00000001L 18508 #define MMEA3_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 18509 #define MMEA3_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN_MASK 0x0000003CL 18510 #define MMEA3_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES_MASK 0x000000C0L 18511 #define MMEA3_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS_MASK 0x00000100L 18512 #define MMEA3_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL_MASK 0x00000E00L 18513 #define MMEA3_ADDRNORM_BASE_ADDR5__BASE_ADDR_MASK 0xFFFFF000L 18514 //MMEA3_ADDRNORM_LIMIT_ADDR5 18515 #define MMEA3_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID__SHIFT 0x0 18516 #define MMEA3_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR__SHIFT 0xc 18517 #define MMEA3_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID_MASK 0x0000001FL 18518 #define MMEA3_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR_MASK 0xFFFFF000L 18519 //MMEA3_ADDRNORM_OFFSET_ADDR5 18520 #define MMEA3_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN__SHIFT 0x0 18521 #define MMEA3_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET__SHIFT 0x14 18522 #define MMEA3_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN_MASK 0x00000001L 18523 #define MMEA3_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_MASK 0xFFF00000L 18524 //MMEA3_ADDRNORMDRAM_HOLE_CNTL 18525 #define MMEA3_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 18526 #define MMEA3_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 18527 #define MMEA3_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L 18528 #define MMEA3_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L 18529 //MMEA3_ADDRNORMGMI_HOLE_CNTL 18530 #define MMEA3_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 18531 #define MMEA3_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 18532 #define MMEA3_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L 18533 #define MMEA3_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L 18534 //MMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG 18535 #define MMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0 18536 #define MMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6 18537 #define MMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL 18538 #define MMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L 18539 //MMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG 18540 #define MMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT 0x0 18541 #define MMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT 0x6 18542 #define MMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK 0x0000003FL 18543 #define MMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK 0x00000FC0L 18544 //MMEA3_ADDRDEC_BANK_CFG 18545 #define MMEA3_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 18546 #define MMEA3_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x6 18547 #define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xc 18548 #define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xf 18549 #define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x12 18550 #define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x13 18551 #define MMEA3_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000003FL 18552 #define MMEA3_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x00000FC0L 18553 #define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00007000L 18554 #define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x00038000L 18555 #define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00040000L 18556 #define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00080000L 18557 //MMEA3_ADDRDEC_MISC_CFG 18558 #define MMEA3_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 18559 #define MMEA3_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 18560 #define MMEA3_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 18561 #define MMEA3_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 18562 #define MMEA3_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 18563 #define MMEA3_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc 18564 #define MMEA3_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11 18565 #define MMEA3_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16 18566 #define MMEA3_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18 18567 #define MMEA3_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a 18568 #define MMEA3_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d 18569 #define MMEA3_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L 18570 #define MMEA3_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L 18571 #define MMEA3_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L 18572 #define MMEA3_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L 18573 #define MMEA3_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L 18574 #define MMEA3_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L 18575 #define MMEA3_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L 18576 #define MMEA3_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L 18577 #define MMEA3_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L 18578 #define MMEA3_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L 18579 #define MMEA3_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L 18580 //MMEA3_ADDRDECDRAM_ADDR_HASH_BANK0 18581 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 18582 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 18583 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe 18584 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L 18585 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL 18586 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L 18587 //MMEA3_ADDRDECDRAM_ADDR_HASH_BANK1 18588 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 18589 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 18590 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe 18591 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L 18592 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL 18593 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L 18594 //MMEA3_ADDRDECDRAM_ADDR_HASH_BANK2 18595 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 18596 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 18597 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe 18598 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L 18599 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL 18600 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L 18601 //MMEA3_ADDRDECDRAM_ADDR_HASH_BANK3 18602 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 18603 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 18604 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe 18605 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L 18606 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL 18607 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L 18608 //MMEA3_ADDRDECDRAM_ADDR_HASH_BANK4 18609 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 18610 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 18611 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe 18612 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L 18613 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL 18614 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L 18615 //MMEA3_ADDRDECDRAM_ADDR_HASH_BANK5 18616 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT 0x0 18617 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR__SHIFT 0x1 18618 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR__SHIFT 0xe 18619 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE_MASK 0x00000001L 18620 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR_MASK 0x00003FFEL 18621 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR_MASK 0xFFFFC000L 18622 //MMEA3_ADDRDECDRAM_ADDR_HASH_PC 18623 #define MMEA3_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 18624 #define MMEA3_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 18625 #define MMEA3_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe 18626 #define MMEA3_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L 18627 #define MMEA3_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL 18628 #define MMEA3_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L 18629 //MMEA3_ADDRDECDRAM_ADDR_HASH_PC2 18630 #define MMEA3_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 18631 #define MMEA3_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000003FL 18632 //MMEA3_ADDRDECDRAM_ADDR_HASH_CS0 18633 #define MMEA3_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 18634 #define MMEA3_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 18635 #define MMEA3_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L 18636 #define MMEA3_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL 18637 //MMEA3_ADDRDECDRAM_ADDR_HASH_CS1 18638 #define MMEA3_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 18639 #define MMEA3_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 18640 #define MMEA3_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L 18641 #define MMEA3_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL 18642 //MMEA3_ADDRDECDRAM_HARVEST_ENABLE 18643 #define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 18644 #define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 18645 #define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 18646 #define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 18647 #define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 18648 #define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 18649 #define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L 18650 #define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L 18651 #define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L 18652 #define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L 18653 #define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L 18654 #define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L 18655 //MMEA3_ADDRDECGMI_ADDR_HASH_BANK0 18656 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 18657 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 18658 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe 18659 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L 18660 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL 18661 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L 18662 //MMEA3_ADDRDECGMI_ADDR_HASH_BANK1 18663 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 18664 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 18665 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe 18666 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L 18667 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL 18668 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L 18669 //MMEA3_ADDRDECGMI_ADDR_HASH_BANK2 18670 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 18671 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 18672 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe 18673 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L 18674 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL 18675 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L 18676 //MMEA3_ADDRDECGMI_ADDR_HASH_BANK3 18677 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 18678 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 18679 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe 18680 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L 18681 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL 18682 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L 18683 //MMEA3_ADDRDECGMI_ADDR_HASH_BANK4 18684 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 18685 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 18686 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe 18687 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L 18688 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL 18689 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L 18690 //MMEA3_ADDRDECGMI_ADDR_HASH_BANK5 18691 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT 0x0 18692 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR__SHIFT 0x1 18693 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR__SHIFT 0xe 18694 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE_MASK 0x00000001L 18695 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR_MASK 0x00003FFEL 18696 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR_MASK 0xFFFFC000L 18697 //MMEA3_ADDRDECGMI_ADDR_HASH_PC 18698 #define MMEA3_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 18699 #define MMEA3_ADDRDECGMI_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 18700 #define MMEA3_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe 18701 #define MMEA3_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L 18702 #define MMEA3_ADDRDECGMI_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL 18703 #define MMEA3_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L 18704 //MMEA3_ADDRDECGMI_ADDR_HASH_PC2 18705 #define MMEA3_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 18706 #define MMEA3_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000003FL 18707 //MMEA3_ADDRDECGMI_ADDR_HASH_CS0 18708 #define MMEA3_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 18709 #define MMEA3_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 18710 #define MMEA3_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L 18711 #define MMEA3_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL 18712 //MMEA3_ADDRDECGMI_ADDR_HASH_CS1 18713 #define MMEA3_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 18714 #define MMEA3_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 18715 #define MMEA3_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L 18716 #define MMEA3_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL 18717 //MMEA3_ADDRDECGMI_HARVEST_ENABLE 18718 #define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 18719 #define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 18720 #define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 18721 #define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 18722 #define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 18723 #define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 18724 #define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L 18725 #define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L 18726 #define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L 18727 #define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L 18728 #define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L 18729 #define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L 18730 //MMEA3_ADDRDEC0_BASE_ADDR_CS0 18731 #define MMEA3_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 18732 #define MMEA3_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 18733 #define MMEA3_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 18734 #define MMEA3_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 18735 //MMEA3_ADDRDEC0_BASE_ADDR_CS1 18736 #define MMEA3_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 18737 #define MMEA3_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 18738 #define MMEA3_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 18739 #define MMEA3_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 18740 //MMEA3_ADDRDEC0_BASE_ADDR_CS2 18741 #define MMEA3_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 18742 #define MMEA3_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 18743 #define MMEA3_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 18744 #define MMEA3_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 18745 //MMEA3_ADDRDEC0_BASE_ADDR_CS3 18746 #define MMEA3_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 18747 #define MMEA3_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 18748 #define MMEA3_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 18749 #define MMEA3_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 18750 //MMEA3_ADDRDEC0_BASE_ADDR_SECCS0 18751 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 18752 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 18753 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 18754 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 18755 //MMEA3_ADDRDEC0_BASE_ADDR_SECCS1 18756 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 18757 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 18758 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 18759 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 18760 //MMEA3_ADDRDEC0_BASE_ADDR_SECCS2 18761 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 18762 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 18763 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 18764 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 18765 //MMEA3_ADDRDEC0_BASE_ADDR_SECCS3 18766 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 18767 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 18768 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 18769 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 18770 //MMEA3_ADDRDEC0_ADDR_MASK_CS01 18771 #define MMEA3_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 18772 #define MMEA3_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 18773 //MMEA3_ADDRDEC0_ADDR_MASK_CS23 18774 #define MMEA3_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 18775 #define MMEA3_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 18776 //MMEA3_ADDRDEC0_ADDR_MASK_SECCS01 18777 #define MMEA3_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 18778 #define MMEA3_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 18779 //MMEA3_ADDRDEC0_ADDR_MASK_SECCS23 18780 #define MMEA3_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 18781 #define MMEA3_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 18782 //MMEA3_ADDRDEC0_ADDR_CFG_CS01 18783 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 18784 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 18785 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 18786 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 18787 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 18788 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 18789 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 18790 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 18791 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 18792 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 18793 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 18794 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 18795 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 18796 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 18797 //MMEA3_ADDRDEC0_ADDR_CFG_CS23 18798 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 18799 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 18800 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 18801 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 18802 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 18803 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 18804 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 18805 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 18806 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 18807 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 18808 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 18809 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 18810 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 18811 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 18812 //MMEA3_ADDRDEC0_ADDR_SEL_CS01 18813 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 18814 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 18815 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 18816 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc 18817 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 18818 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 18819 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 18820 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 18821 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 18822 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 18823 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 18824 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 18825 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 18826 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 18827 //MMEA3_ADDRDEC0_ADDR_SEL_CS23 18828 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 18829 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 18830 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 18831 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc 18832 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 18833 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 18834 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 18835 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 18836 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 18837 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 18838 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 18839 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 18840 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 18841 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 18842 //MMEA3_ADDRDEC0_ADDR_SEL2_CS01 18843 #define MMEA3_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 18844 #define MMEA3_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 18845 //MMEA3_ADDRDEC0_ADDR_SEL2_CS23 18846 #define MMEA3_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 18847 #define MMEA3_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 18848 //MMEA3_ADDRDEC0_COL_SEL_LO_CS01 18849 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 18850 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 18851 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 18852 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc 18853 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 18854 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 18855 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 18856 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 18857 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 18858 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 18859 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 18860 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 18861 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 18862 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 18863 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 18864 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 18865 //MMEA3_ADDRDEC0_COL_SEL_LO_CS23 18866 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 18867 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 18868 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 18869 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc 18870 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 18871 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 18872 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 18873 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 18874 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 18875 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 18876 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 18877 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 18878 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 18879 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 18880 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 18881 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 18882 //MMEA3_ADDRDEC0_COL_SEL_HI_CS01 18883 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 18884 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 18885 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 18886 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc 18887 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 18888 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 18889 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 18890 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 18891 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 18892 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 18893 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 18894 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 18895 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 18896 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 18897 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 18898 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 18899 //MMEA3_ADDRDEC0_COL_SEL_HI_CS23 18900 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 18901 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 18902 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 18903 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc 18904 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 18905 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 18906 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 18907 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 18908 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 18909 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 18910 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 18911 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 18912 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 18913 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 18914 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 18915 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 18916 //MMEA3_ADDRDEC0_RM_SEL_CS01 18917 #define MMEA3_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 18918 #define MMEA3_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 18919 #define MMEA3_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 18920 #define MMEA3_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 18921 #define MMEA3_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 18922 #define MMEA3_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 18923 #define MMEA3_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL 18924 #define MMEA3_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L 18925 #define MMEA3_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L 18926 #define MMEA3_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 18927 #define MMEA3_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 18928 #define MMEA3_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 18929 //MMEA3_ADDRDEC0_RM_SEL_CS23 18930 #define MMEA3_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 18931 #define MMEA3_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 18932 #define MMEA3_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 18933 #define MMEA3_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 18934 #define MMEA3_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 18935 #define MMEA3_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 18936 #define MMEA3_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL 18937 #define MMEA3_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L 18938 #define MMEA3_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L 18939 #define MMEA3_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 18940 #define MMEA3_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 18941 #define MMEA3_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 18942 //MMEA3_ADDRDEC0_RM_SEL_SECCS01 18943 #define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 18944 #define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 18945 #define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 18946 #define MMEA3_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 18947 #define MMEA3_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 18948 #define MMEA3_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 18949 #define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 18950 #define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 18951 #define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 18952 #define MMEA3_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 18953 #define MMEA3_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 18954 #define MMEA3_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 18955 //MMEA3_ADDRDEC0_RM_SEL_SECCS23 18956 #define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 18957 #define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 18958 #define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 18959 #define MMEA3_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 18960 #define MMEA3_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 18961 #define MMEA3_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 18962 #define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 18963 #define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 18964 #define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 18965 #define MMEA3_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 18966 #define MMEA3_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 18967 #define MMEA3_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 18968 //MMEA3_ADDRDEC1_BASE_ADDR_CS0 18969 #define MMEA3_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 18970 #define MMEA3_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 18971 #define MMEA3_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 18972 #define MMEA3_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 18973 //MMEA3_ADDRDEC1_BASE_ADDR_CS1 18974 #define MMEA3_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 18975 #define MMEA3_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 18976 #define MMEA3_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 18977 #define MMEA3_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 18978 //MMEA3_ADDRDEC1_BASE_ADDR_CS2 18979 #define MMEA3_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 18980 #define MMEA3_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 18981 #define MMEA3_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 18982 #define MMEA3_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 18983 //MMEA3_ADDRDEC1_BASE_ADDR_CS3 18984 #define MMEA3_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 18985 #define MMEA3_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 18986 #define MMEA3_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 18987 #define MMEA3_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 18988 //MMEA3_ADDRDEC1_BASE_ADDR_SECCS0 18989 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 18990 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 18991 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 18992 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 18993 //MMEA3_ADDRDEC1_BASE_ADDR_SECCS1 18994 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 18995 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 18996 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 18997 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 18998 //MMEA3_ADDRDEC1_BASE_ADDR_SECCS2 18999 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 19000 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 19001 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 19002 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 19003 //MMEA3_ADDRDEC1_BASE_ADDR_SECCS3 19004 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 19005 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 19006 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 19007 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 19008 //MMEA3_ADDRDEC1_ADDR_MASK_CS01 19009 #define MMEA3_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 19010 #define MMEA3_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 19011 //MMEA3_ADDRDEC1_ADDR_MASK_CS23 19012 #define MMEA3_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 19013 #define MMEA3_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 19014 //MMEA3_ADDRDEC1_ADDR_MASK_SECCS01 19015 #define MMEA3_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 19016 #define MMEA3_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 19017 //MMEA3_ADDRDEC1_ADDR_MASK_SECCS23 19018 #define MMEA3_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 19019 #define MMEA3_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 19020 //MMEA3_ADDRDEC1_ADDR_CFG_CS01 19021 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 19022 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 19023 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 19024 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 19025 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 19026 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 19027 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 19028 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 19029 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 19030 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 19031 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 19032 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 19033 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 19034 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 19035 //MMEA3_ADDRDEC1_ADDR_CFG_CS23 19036 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 19037 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 19038 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 19039 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 19040 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 19041 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 19042 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 19043 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 19044 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 19045 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 19046 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 19047 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 19048 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 19049 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 19050 //MMEA3_ADDRDEC1_ADDR_SEL_CS01 19051 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 19052 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 19053 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 19054 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc 19055 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 19056 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 19057 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 19058 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 19059 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 19060 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 19061 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 19062 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 19063 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 19064 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 19065 //MMEA3_ADDRDEC1_ADDR_SEL_CS23 19066 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 19067 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 19068 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 19069 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc 19070 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 19071 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 19072 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 19073 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 19074 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 19075 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 19076 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 19077 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 19078 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 19079 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 19080 //MMEA3_ADDRDEC1_ADDR_SEL2_CS01 19081 #define MMEA3_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 19082 #define MMEA3_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 19083 //MMEA3_ADDRDEC1_ADDR_SEL2_CS23 19084 #define MMEA3_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 19085 #define MMEA3_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 19086 //MMEA3_ADDRDEC1_COL_SEL_LO_CS01 19087 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 19088 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 19089 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 19090 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc 19091 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 19092 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 19093 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 19094 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 19095 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 19096 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 19097 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 19098 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 19099 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 19100 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 19101 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 19102 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 19103 //MMEA3_ADDRDEC1_COL_SEL_LO_CS23 19104 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 19105 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 19106 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 19107 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc 19108 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 19109 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 19110 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 19111 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 19112 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 19113 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 19114 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 19115 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 19116 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 19117 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 19118 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 19119 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 19120 //MMEA3_ADDRDEC1_COL_SEL_HI_CS01 19121 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 19122 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 19123 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 19124 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc 19125 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 19126 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 19127 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 19128 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 19129 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 19130 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 19131 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 19132 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 19133 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 19134 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 19135 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 19136 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 19137 //MMEA3_ADDRDEC1_COL_SEL_HI_CS23 19138 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 19139 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 19140 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 19141 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc 19142 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 19143 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 19144 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 19145 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 19146 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 19147 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 19148 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 19149 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 19150 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 19151 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 19152 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 19153 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 19154 //MMEA3_ADDRDEC1_RM_SEL_CS01 19155 #define MMEA3_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 19156 #define MMEA3_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 19157 #define MMEA3_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 19158 #define MMEA3_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 19159 #define MMEA3_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 19160 #define MMEA3_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 19161 #define MMEA3_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL 19162 #define MMEA3_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L 19163 #define MMEA3_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L 19164 #define MMEA3_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 19165 #define MMEA3_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 19166 #define MMEA3_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 19167 //MMEA3_ADDRDEC1_RM_SEL_CS23 19168 #define MMEA3_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 19169 #define MMEA3_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 19170 #define MMEA3_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 19171 #define MMEA3_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 19172 #define MMEA3_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 19173 #define MMEA3_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 19174 #define MMEA3_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL 19175 #define MMEA3_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L 19176 #define MMEA3_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L 19177 #define MMEA3_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 19178 #define MMEA3_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 19179 #define MMEA3_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 19180 //MMEA3_ADDRDEC1_RM_SEL_SECCS01 19181 #define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 19182 #define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 19183 #define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 19184 #define MMEA3_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 19185 #define MMEA3_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 19186 #define MMEA3_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 19187 #define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 19188 #define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 19189 #define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 19190 #define MMEA3_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 19191 #define MMEA3_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 19192 #define MMEA3_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 19193 //MMEA3_ADDRDEC1_RM_SEL_SECCS23 19194 #define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 19195 #define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 19196 #define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 19197 #define MMEA3_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 19198 #define MMEA3_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 19199 #define MMEA3_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 19200 #define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 19201 #define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 19202 #define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 19203 #define MMEA3_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 19204 #define MMEA3_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 19205 #define MMEA3_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 19206 //MMEA3_ADDRDEC2_BASE_ADDR_CS0 19207 #define MMEA3_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 19208 #define MMEA3_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 19209 #define MMEA3_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 19210 #define MMEA3_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 19211 //MMEA3_ADDRDEC2_BASE_ADDR_CS1 19212 #define MMEA3_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 19213 #define MMEA3_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 19214 #define MMEA3_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 19215 #define MMEA3_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 19216 //MMEA3_ADDRDEC2_BASE_ADDR_CS2 19217 #define MMEA3_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 19218 #define MMEA3_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 19219 #define MMEA3_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 19220 #define MMEA3_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 19221 //MMEA3_ADDRDEC2_BASE_ADDR_CS3 19222 #define MMEA3_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 19223 #define MMEA3_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 19224 #define MMEA3_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 19225 #define MMEA3_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 19226 //MMEA3_ADDRDEC2_BASE_ADDR_SECCS0 19227 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 19228 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 19229 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 19230 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 19231 //MMEA3_ADDRDEC2_BASE_ADDR_SECCS1 19232 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 19233 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 19234 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 19235 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 19236 //MMEA3_ADDRDEC2_BASE_ADDR_SECCS2 19237 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 19238 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 19239 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 19240 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 19241 //MMEA3_ADDRDEC2_BASE_ADDR_SECCS3 19242 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 19243 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 19244 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 19245 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 19246 //MMEA3_ADDRDEC2_ADDR_MASK_CS01 19247 #define MMEA3_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 19248 #define MMEA3_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 19249 //MMEA3_ADDRDEC2_ADDR_MASK_CS23 19250 #define MMEA3_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 19251 #define MMEA3_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 19252 //MMEA3_ADDRDEC2_ADDR_MASK_SECCS01 19253 #define MMEA3_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 19254 #define MMEA3_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 19255 //MMEA3_ADDRDEC2_ADDR_MASK_SECCS23 19256 #define MMEA3_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 19257 #define MMEA3_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 19258 //MMEA3_ADDRDEC2_ADDR_CFG_CS01 19259 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 19260 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 19261 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 19262 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 19263 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 19264 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 19265 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 19266 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 19267 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 19268 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 19269 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 19270 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 19271 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 19272 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 19273 //MMEA3_ADDRDEC2_ADDR_CFG_CS23 19274 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 19275 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 19276 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 19277 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 19278 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 19279 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 19280 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 19281 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 19282 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 19283 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 19284 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 19285 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 19286 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 19287 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 19288 //MMEA3_ADDRDEC2_ADDR_SEL_CS01 19289 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT 0x0 19290 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT 0x4 19291 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT 0x8 19292 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT 0xc 19293 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT 0x10 19294 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 19295 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 19296 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 19297 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 19298 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 19299 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 19300 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 19301 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 19302 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 19303 //MMEA3_ADDRDEC2_ADDR_SEL_CS23 19304 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT 0x0 19305 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT 0x4 19306 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT 0x8 19307 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT 0xc 19308 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT 0x10 19309 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 19310 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 19311 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 19312 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 19313 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 19314 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 19315 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 19316 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 19317 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 19318 //MMEA3_ADDRDEC2_ADDR_SEL2_CS01 19319 #define MMEA3_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 19320 #define MMEA3_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 19321 //MMEA3_ADDRDEC2_ADDR_SEL2_CS23 19322 #define MMEA3_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 19323 #define MMEA3_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 19324 //MMEA3_ADDRDEC2_COL_SEL_LO_CS01 19325 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT 0x0 19326 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT 0x4 19327 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT 0x8 19328 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT 0xc 19329 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT 0x10 19330 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT 0x14 19331 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT 0x18 19332 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 19333 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 19334 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 19335 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 19336 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 19337 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 19338 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 19339 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 19340 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 19341 //MMEA3_ADDRDEC2_COL_SEL_LO_CS23 19342 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT 0x0 19343 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT 0x4 19344 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT 0x8 19345 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT 0xc 19346 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT 0x10 19347 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT 0x14 19348 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT 0x18 19349 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 19350 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 19351 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 19352 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 19353 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 19354 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 19355 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 19356 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 19357 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 19358 //MMEA3_ADDRDEC2_COL_SEL_HI_CS01 19359 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT 0x0 19360 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT 0x4 19361 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT 0x8 19362 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT 0xc 19363 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT 0x10 19364 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT 0x14 19365 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT 0x18 19366 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 19367 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 19368 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 19369 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 19370 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 19371 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 19372 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 19373 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 19374 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 19375 //MMEA3_ADDRDEC2_COL_SEL_HI_CS23 19376 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT 0x0 19377 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT 0x4 19378 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT 0x8 19379 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT 0xc 19380 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT 0x10 19381 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT 0x14 19382 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT 0x18 19383 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 19384 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 19385 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 19386 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 19387 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 19388 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 19389 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 19390 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 19391 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 19392 //MMEA3_ADDRDEC2_RM_SEL_CS01 19393 #define MMEA3_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT 0x0 19394 #define MMEA3_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT 0x4 19395 #define MMEA3_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT 0x8 19396 #define MMEA3_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 19397 #define MMEA3_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 19398 #define MMEA3_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 19399 #define MMEA3_ADDRDEC2_RM_SEL_CS01__RM0_MASK 0x0000000FL 19400 #define MMEA3_ADDRDEC2_RM_SEL_CS01__RM1_MASK 0x000000F0L 19401 #define MMEA3_ADDRDEC2_RM_SEL_CS01__RM2_MASK 0x00000F00L 19402 #define MMEA3_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 19403 #define MMEA3_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 19404 #define MMEA3_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 19405 //MMEA3_ADDRDEC2_RM_SEL_CS23 19406 #define MMEA3_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT 0x0 19407 #define MMEA3_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT 0x4 19408 #define MMEA3_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT 0x8 19409 #define MMEA3_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 19410 #define MMEA3_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 19411 #define MMEA3_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 19412 #define MMEA3_ADDRDEC2_RM_SEL_CS23__RM0_MASK 0x0000000FL 19413 #define MMEA3_ADDRDEC2_RM_SEL_CS23__RM1_MASK 0x000000F0L 19414 #define MMEA3_ADDRDEC2_RM_SEL_CS23__RM2_MASK 0x00000F00L 19415 #define MMEA3_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 19416 #define MMEA3_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 19417 #define MMEA3_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 19418 //MMEA3_ADDRDEC2_RM_SEL_SECCS01 19419 #define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT 0x0 19420 #define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT 0x4 19421 #define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT 0x8 19422 #define MMEA3_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 19423 #define MMEA3_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 19424 #define MMEA3_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 19425 #define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 19426 #define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 19427 #define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 19428 #define MMEA3_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 19429 #define MMEA3_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 19430 #define MMEA3_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 19431 //MMEA3_ADDRDEC2_RM_SEL_SECCS23 19432 #define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT 0x0 19433 #define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT 0x4 19434 #define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT 0x8 19435 #define MMEA3_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 19436 #define MMEA3_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 19437 #define MMEA3_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 19438 #define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 19439 #define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 19440 #define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 19441 #define MMEA3_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 19442 #define MMEA3_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 19443 #define MMEA3_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 19444 //MMEA3_ADDRNORMDRAM_GLOBAL_CNTL 19445 #define MMEA3_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT 0x14 19446 #define MMEA3_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT 0x15 19447 #define MMEA3_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT 0x16 19448 #define MMEA3_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK 0x00100000L 19449 #define MMEA3_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK 0x00200000L 19450 #define MMEA3_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK 0x00400000L 19451 //MMEA3_ADDRNORMGMI_GLOBAL_CNTL 19452 #define MMEA3_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT 0x14 19453 #define MMEA3_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT 0x15 19454 #define MMEA3_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT 0x16 19455 #define MMEA3_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK 0x00100000L 19456 #define MMEA3_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK 0x00200000L 19457 #define MMEA3_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK 0x00400000L 19458 //MMEA3_IO_RD_CLI2GRP_MAP0 19459 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 19460 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 19461 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 19462 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 19463 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 19464 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 19465 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 19466 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 19467 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 19468 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 19469 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 19470 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 19471 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 19472 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 19473 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 19474 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 19475 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 19476 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 19477 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 19478 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 19479 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 19480 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 19481 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 19482 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 19483 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 19484 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 19485 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 19486 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 19487 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 19488 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 19489 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 19490 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 19491 //MMEA3_IO_RD_CLI2GRP_MAP1 19492 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 19493 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 19494 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 19495 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 19496 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 19497 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 19498 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 19499 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 19500 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 19501 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 19502 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 19503 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 19504 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 19505 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 19506 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 19507 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 19508 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 19509 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 19510 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 19511 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 19512 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 19513 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 19514 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 19515 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 19516 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 19517 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 19518 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 19519 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 19520 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 19521 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 19522 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 19523 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 19524 //MMEA3_IO_WR_CLI2GRP_MAP0 19525 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 19526 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 19527 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 19528 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 19529 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 19530 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 19531 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 19532 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 19533 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 19534 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 19535 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 19536 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 19537 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 19538 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 19539 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 19540 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 19541 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 19542 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 19543 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 19544 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 19545 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 19546 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 19547 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 19548 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 19549 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 19550 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 19551 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 19552 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 19553 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 19554 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 19555 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 19556 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 19557 //MMEA3_IO_WR_CLI2GRP_MAP1 19558 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 19559 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 19560 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 19561 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 19562 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 19563 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 19564 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 19565 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 19566 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 19567 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 19568 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 19569 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 19570 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 19571 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 19572 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 19573 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 19574 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 19575 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 19576 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 19577 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 19578 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 19579 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 19580 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 19581 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 19582 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 19583 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 19584 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 19585 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 19586 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 19587 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 19588 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 19589 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 19590 //MMEA3_IO_RD_COMBINE_FLUSH 19591 #define MMEA3_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 19592 #define MMEA3_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 19593 #define MMEA3_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 19594 #define MMEA3_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 19595 #define MMEA3_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT 0x10 19596 #define MMEA3_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 19597 #define MMEA3_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 19598 #define MMEA3_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 19599 #define MMEA3_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 19600 #define MMEA3_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK 0x00010000L 19601 //MMEA3_IO_WR_COMBINE_FLUSH 19602 #define MMEA3_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 19603 #define MMEA3_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 19604 #define MMEA3_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 19605 #define MMEA3_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 19606 #define MMEA3_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT 0x10 19607 #define MMEA3_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 19608 #define MMEA3_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 19609 #define MMEA3_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 19610 #define MMEA3_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 19611 #define MMEA3_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK 0x00010000L 19612 //MMEA3_IO_GROUP_BURST 19613 #define MMEA3_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 19614 #define MMEA3_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 19615 #define MMEA3_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 19616 #define MMEA3_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 19617 #define MMEA3_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL 19618 #define MMEA3_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 19619 #define MMEA3_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 19620 #define MMEA3_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L 19621 //MMEA3_IO_RD_PRI_AGE 19622 #define MMEA3_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 19623 #define MMEA3_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 19624 #define MMEA3_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 19625 #define MMEA3_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 19626 #define MMEA3_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 19627 #define MMEA3_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 19628 #define MMEA3_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 19629 #define MMEA3_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 19630 #define MMEA3_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 19631 #define MMEA3_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 19632 #define MMEA3_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 19633 #define MMEA3_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 19634 #define MMEA3_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 19635 #define MMEA3_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 19636 #define MMEA3_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 19637 #define MMEA3_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 19638 //MMEA3_IO_WR_PRI_AGE 19639 #define MMEA3_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 19640 #define MMEA3_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 19641 #define MMEA3_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 19642 #define MMEA3_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 19643 #define MMEA3_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 19644 #define MMEA3_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 19645 #define MMEA3_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 19646 #define MMEA3_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 19647 #define MMEA3_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 19648 #define MMEA3_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 19649 #define MMEA3_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 19650 #define MMEA3_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 19651 #define MMEA3_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 19652 #define MMEA3_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 19653 #define MMEA3_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 19654 #define MMEA3_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 19655 //MMEA3_IO_RD_PRI_QUEUING 19656 #define MMEA3_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 19657 #define MMEA3_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 19658 #define MMEA3_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 19659 #define MMEA3_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 19660 #define MMEA3_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 19661 #define MMEA3_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 19662 #define MMEA3_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 19663 #define MMEA3_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 19664 //MMEA3_IO_WR_PRI_QUEUING 19665 #define MMEA3_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 19666 #define MMEA3_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 19667 #define MMEA3_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 19668 #define MMEA3_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 19669 #define MMEA3_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 19670 #define MMEA3_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 19671 #define MMEA3_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 19672 #define MMEA3_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 19673 //MMEA3_IO_RD_PRI_FIXED 19674 #define MMEA3_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 19675 #define MMEA3_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 19676 #define MMEA3_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 19677 #define MMEA3_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 19678 #define MMEA3_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 19679 #define MMEA3_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 19680 #define MMEA3_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 19681 #define MMEA3_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 19682 //MMEA3_IO_WR_PRI_FIXED 19683 #define MMEA3_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 19684 #define MMEA3_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 19685 #define MMEA3_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 19686 #define MMEA3_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 19687 #define MMEA3_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 19688 #define MMEA3_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 19689 #define MMEA3_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 19690 #define MMEA3_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 19691 //MMEA3_IO_RD_PRI_URGENCY 19692 #define MMEA3_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 19693 #define MMEA3_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 19694 #define MMEA3_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 19695 #define MMEA3_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 19696 #define MMEA3_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 19697 #define MMEA3_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 19698 #define MMEA3_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 19699 #define MMEA3_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 19700 #define MMEA3_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 19701 #define MMEA3_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 19702 #define MMEA3_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 19703 #define MMEA3_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 19704 #define MMEA3_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 19705 #define MMEA3_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 19706 #define MMEA3_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 19707 #define MMEA3_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 19708 //MMEA3_IO_WR_PRI_URGENCY 19709 #define MMEA3_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 19710 #define MMEA3_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 19711 #define MMEA3_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 19712 #define MMEA3_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 19713 #define MMEA3_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 19714 #define MMEA3_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 19715 #define MMEA3_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 19716 #define MMEA3_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 19717 #define MMEA3_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 19718 #define MMEA3_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 19719 #define MMEA3_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 19720 #define MMEA3_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 19721 #define MMEA3_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 19722 #define MMEA3_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 19723 #define MMEA3_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 19724 #define MMEA3_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 19725 //MMEA3_IO_RD_PRI_URGENCY_MASKING 19726 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 19727 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 19728 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 19729 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 19730 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 19731 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 19732 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 19733 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 19734 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 19735 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 19736 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 19737 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 19738 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 19739 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 19740 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 19741 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 19742 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 19743 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 19744 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 19745 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 19746 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 19747 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 19748 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 19749 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 19750 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 19751 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 19752 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 19753 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 19754 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 19755 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 19756 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 19757 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 19758 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 19759 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 19760 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 19761 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 19762 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 19763 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 19764 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 19765 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 19766 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 19767 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 19768 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 19769 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 19770 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 19771 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 19772 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 19773 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 19774 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 19775 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 19776 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 19777 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 19778 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 19779 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 19780 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 19781 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 19782 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 19783 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 19784 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 19785 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 19786 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 19787 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 19788 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 19789 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 19790 //MMEA3_IO_WR_PRI_URGENCY_MASKING 19791 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 19792 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 19793 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 19794 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 19795 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 19796 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 19797 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 19798 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 19799 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 19800 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 19801 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 19802 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 19803 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 19804 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 19805 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 19806 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 19807 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 19808 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 19809 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 19810 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 19811 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 19812 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 19813 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 19814 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 19815 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 19816 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 19817 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 19818 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 19819 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 19820 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 19821 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 19822 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 19823 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 19824 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 19825 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 19826 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 19827 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 19828 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 19829 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 19830 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 19831 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 19832 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 19833 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 19834 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 19835 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 19836 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 19837 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 19838 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 19839 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 19840 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 19841 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 19842 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 19843 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 19844 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 19845 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 19846 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 19847 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 19848 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 19849 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 19850 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 19851 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 19852 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 19853 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 19854 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 19855 //MMEA3_IO_RD_PRI_QUANT_PRI1 19856 #define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 19857 #define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 19858 #define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 19859 #define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 19860 #define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 19861 #define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 19862 #define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 19863 #define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 19864 //MMEA3_IO_RD_PRI_QUANT_PRI2 19865 #define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 19866 #define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 19867 #define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 19868 #define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 19869 #define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 19870 #define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 19871 #define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 19872 #define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 19873 //MMEA3_IO_RD_PRI_QUANT_PRI3 19874 #define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 19875 #define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 19876 #define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 19877 #define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 19878 #define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 19879 #define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 19880 #define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 19881 #define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 19882 //MMEA3_IO_WR_PRI_QUANT_PRI1 19883 #define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 19884 #define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 19885 #define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 19886 #define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 19887 #define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 19888 #define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 19889 #define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 19890 #define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 19891 //MMEA3_IO_WR_PRI_QUANT_PRI2 19892 #define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 19893 #define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 19894 #define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 19895 #define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 19896 #define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 19897 #define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 19898 #define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 19899 #define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 19900 //MMEA3_IO_WR_PRI_QUANT_PRI3 19901 #define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 19902 #define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 19903 #define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 19904 #define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 19905 #define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 19906 #define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 19907 #define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 19908 #define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 19909 //MMEA3_SDP_ARB_DRAM 19910 #define MMEA3_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 19911 #define MMEA3_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 19912 #define MMEA3_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 19913 #define MMEA3_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 19914 #define MMEA3_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 19915 #define MMEA3_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 19916 #define MMEA3_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 19917 #define MMEA3_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 19918 #define MMEA3_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL 19919 #define MMEA3_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L 19920 #define MMEA3_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L 19921 #define MMEA3_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L 19922 #define MMEA3_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L 19923 #define MMEA3_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L 19924 #define MMEA3_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L 19925 #define MMEA3_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L 19926 //MMEA3_SDP_ARB_GMI 19927 #define MMEA3_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 19928 #define MMEA3_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 19929 #define MMEA3_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT 0x10 19930 #define MMEA3_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT 0x11 19931 #define MMEA3_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT 0x12 19932 #define MMEA3_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT 0x13 19933 #define MMEA3_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT 0x14 19934 #define MMEA3_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 19935 #define MMEA3_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT 0x16 19936 #define MMEA3_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL 19937 #define MMEA3_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L 19938 #define MMEA3_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK 0x00010000L 19939 #define MMEA3_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK 0x00020000L 19940 #define MMEA3_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK 0x00040000L 19941 #define MMEA3_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK 0x00080000L 19942 #define MMEA3_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK 0x00100000L 19943 #define MMEA3_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L 19944 #define MMEA3_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK 0x00400000L 19945 //MMEA3_SDP_ARB_FINAL 19946 #define MMEA3_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 19947 #define MMEA3_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 19948 #define MMEA3_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa 19949 #define MMEA3_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf 19950 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 19951 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 19952 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 19953 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 19954 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 19955 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 19956 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 19957 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 19958 #define MMEA3_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 19959 #define MMEA3_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a 19960 #define MMEA3_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1b 19961 #define MMEA3_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL 19962 #define MMEA3_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L 19963 #define MMEA3_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L 19964 #define MMEA3_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L 19965 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L 19966 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L 19967 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L 19968 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L 19969 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L 19970 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L 19971 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L 19972 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L 19973 #define MMEA3_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L 19974 #define MMEA3_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L 19975 #define MMEA3_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x08000000L 19976 //MMEA3_SDP_DRAM_PRIORITY 19977 #define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 19978 #define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 19979 #define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 19980 #define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 19981 #define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 19982 #define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 19983 #define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 19984 #define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 19985 #define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 19986 #define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 19987 #define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 19988 #define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 19989 #define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 19990 #define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 19991 #define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 19992 #define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 19993 //MMEA3_SDP_GMI_PRIORITY 19994 #define MMEA3_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 19995 #define MMEA3_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 19996 #define MMEA3_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 19997 #define MMEA3_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 19998 #define MMEA3_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 19999 #define MMEA3_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 20000 #define MMEA3_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 20001 #define MMEA3_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 20002 #define MMEA3_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 20003 #define MMEA3_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 20004 #define MMEA3_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 20005 #define MMEA3_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 20006 #define MMEA3_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 20007 #define MMEA3_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 20008 #define MMEA3_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 20009 #define MMEA3_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 20010 //MMEA3_SDP_IO_PRIORITY 20011 #define MMEA3_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 20012 #define MMEA3_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 20013 #define MMEA3_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 20014 #define MMEA3_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 20015 #define MMEA3_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 20016 #define MMEA3_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 20017 #define MMEA3_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 20018 #define MMEA3_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 20019 #define MMEA3_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 20020 #define MMEA3_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 20021 #define MMEA3_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 20022 #define MMEA3_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 20023 #define MMEA3_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 20024 #define MMEA3_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 20025 #define MMEA3_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 20026 #define MMEA3_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 20027 //MMEA3_SDP_CREDITS 20028 #define MMEA3_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 20029 #define MMEA3_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 20030 #define MMEA3_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 20031 #define MMEA3_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL 20032 #define MMEA3_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L 20033 #define MMEA3_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L 20034 //MMEA3_SDP_TAG_RESERVE0 20035 #define MMEA3_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 20036 #define MMEA3_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 20037 #define MMEA3_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 20038 #define MMEA3_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 20039 #define MMEA3_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL 20040 #define MMEA3_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L 20041 #define MMEA3_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L 20042 #define MMEA3_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L 20043 //MMEA3_SDP_TAG_RESERVE1 20044 #define MMEA3_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 20045 #define MMEA3_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 20046 #define MMEA3_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 20047 #define MMEA3_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 20048 #define MMEA3_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL 20049 #define MMEA3_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L 20050 #define MMEA3_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L 20051 #define MMEA3_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L 20052 //MMEA3_SDP_VCC_RESERVE0 20053 #define MMEA3_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 20054 #define MMEA3_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 20055 #define MMEA3_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc 20056 #define MMEA3_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 20057 #define MMEA3_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 20058 #define MMEA3_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 20059 #define MMEA3_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 20060 #define MMEA3_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 20061 #define MMEA3_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 20062 #define MMEA3_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 20063 //MMEA3_SDP_VCC_RESERVE1 20064 #define MMEA3_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 20065 #define MMEA3_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 20066 #define MMEA3_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc 20067 #define MMEA3_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 20068 #define MMEA3_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 20069 #define MMEA3_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 20070 #define MMEA3_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 20071 #define MMEA3_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 20072 //MMEA3_SDP_VCD_RESERVE0 20073 #define MMEA3_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 20074 #define MMEA3_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 20075 #define MMEA3_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc 20076 #define MMEA3_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 20077 #define MMEA3_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 20078 #define MMEA3_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 20079 #define MMEA3_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 20080 #define MMEA3_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 20081 #define MMEA3_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 20082 #define MMEA3_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 20083 //MMEA3_SDP_VCD_RESERVE1 20084 #define MMEA3_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 20085 #define MMEA3_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 20086 #define MMEA3_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc 20087 #define MMEA3_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 20088 #define MMEA3_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 20089 #define MMEA3_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 20090 #define MMEA3_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 20091 #define MMEA3_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 20092 //MMEA3_SDP_REQ_CNTL 20093 #define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 20094 #define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 20095 #define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 20096 #define MMEA3_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 20097 #define MMEA3_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 20098 #define MMEA3_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 20099 #define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L 20100 #define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L 20101 #define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L 20102 #define MMEA3_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L 20103 #define MMEA3_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L 20104 #define MMEA3_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L 20105 //MMEA3_MISC 20106 #define MMEA3_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 20107 #define MMEA3_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 20108 #define MMEA3_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 20109 #define MMEA3_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 20110 #define MMEA3_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 20111 #define MMEA3_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 20112 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 20113 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 20114 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 20115 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 20116 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa 20117 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb 20118 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc 20119 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd 20120 #define MMEA3_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe 20121 #define MMEA3_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf 20122 #define MMEA3_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 20123 #define MMEA3_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 20124 #define MMEA3_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 20125 #define MMEA3_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a 20126 #define MMEA3_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b 20127 #define MMEA3_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c 20128 #define MMEA3_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d 20129 #define MMEA3_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e 20130 #define MMEA3_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f 20131 #define MMEA3_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L 20132 #define MMEA3_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L 20133 #define MMEA3_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L 20134 #define MMEA3_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L 20135 #define MMEA3_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L 20136 #define MMEA3_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L 20137 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L 20138 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L 20139 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L 20140 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L 20141 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L 20142 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L 20143 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L 20144 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L 20145 #define MMEA3_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L 20146 #define MMEA3_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L 20147 #define MMEA3_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L 20148 #define MMEA3_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L 20149 #define MMEA3_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L 20150 #define MMEA3_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L 20151 #define MMEA3_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L 20152 #define MMEA3_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L 20153 #define MMEA3_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L 20154 #define MMEA3_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L 20155 #define MMEA3_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L 20156 //MMEA3_LATENCY_SAMPLING 20157 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 20158 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 20159 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 20160 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 20161 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 20162 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 20163 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 20164 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 20165 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 20166 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 20167 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa 20168 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb 20169 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc 20170 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd 20171 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe 20172 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 20173 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L 20174 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L 20175 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L 20176 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L 20177 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L 20178 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L 20179 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L 20180 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L 20181 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L 20182 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L 20183 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L 20184 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L 20185 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L 20186 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L 20187 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L 20188 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L 20189 //MMEA3_PERFCOUNTER_LO 20190 #define MMEA3_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 20191 #define MMEA3_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 20192 //MMEA3_PERFCOUNTER_HI 20193 #define MMEA3_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 20194 #define MMEA3_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 20195 #define MMEA3_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 20196 #define MMEA3_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 20197 //MMEA3_PERFCOUNTER0_CFG 20198 #define MMEA3_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 20199 #define MMEA3_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 20200 #define MMEA3_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 20201 #define MMEA3_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 20202 #define MMEA3_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 20203 #define MMEA3_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 20204 #define MMEA3_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 20205 #define MMEA3_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 20206 #define MMEA3_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 20207 #define MMEA3_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 20208 //MMEA3_PERFCOUNTER1_CFG 20209 #define MMEA3_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 20210 #define MMEA3_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 20211 #define MMEA3_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 20212 #define MMEA3_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 20213 #define MMEA3_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 20214 #define MMEA3_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 20215 #define MMEA3_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 20216 #define MMEA3_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 20217 #define MMEA3_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 20218 #define MMEA3_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 20219 //MMEA3_PERFCOUNTER_RSLT_CNTL 20220 #define MMEA3_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 20221 #define MMEA3_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 20222 #define MMEA3_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 20223 #define MMEA3_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 20224 #define MMEA3_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 20225 #define MMEA3_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 20226 #define MMEA3_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 20227 #define MMEA3_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 20228 #define MMEA3_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 20229 #define MMEA3_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 20230 #define MMEA3_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 20231 #define MMEA3_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 20232 //MMEA3_EDC_CNT 20233 #define MMEA3_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 20234 #define MMEA3_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 20235 #define MMEA3_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 20236 #define MMEA3_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 20237 #define MMEA3_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 20238 #define MMEA3_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa 20239 #define MMEA3_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc 20240 #define MMEA3_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe 20241 #define MMEA3_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 20242 #define MMEA3_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 20243 #define MMEA3_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 20244 #define MMEA3_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 20245 #define MMEA3_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 20246 #define MMEA3_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a 20247 #define MMEA3_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c 20248 #define MMEA3_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 20249 #define MMEA3_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 20250 #define MMEA3_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 20251 #define MMEA3_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 20252 #define MMEA3_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 20253 #define MMEA3_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 20254 #define MMEA3_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L 20255 #define MMEA3_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L 20256 #define MMEA3_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L 20257 #define MMEA3_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L 20258 #define MMEA3_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L 20259 #define MMEA3_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L 20260 #define MMEA3_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L 20261 #define MMEA3_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L 20262 #define MMEA3_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L 20263 //MMEA3_EDC_CNT2 20264 #define MMEA3_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 20265 #define MMEA3_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 20266 #define MMEA3_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 20267 #define MMEA3_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 20268 #define MMEA3_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 20269 #define MMEA3_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa 20270 #define MMEA3_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc 20271 #define MMEA3_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe 20272 #define MMEA3_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10 20273 #define MMEA3_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12 20274 #define MMEA3_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14 20275 #define MMEA3_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16 20276 #define MMEA3_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT 0x18 20277 #define MMEA3_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT 0x1a 20278 #define MMEA3_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT 0x1c 20279 #define MMEA3_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT 0x1e 20280 #define MMEA3_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 20281 #define MMEA3_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 20282 #define MMEA3_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 20283 #define MMEA3_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 20284 #define MMEA3_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 20285 #define MMEA3_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 20286 #define MMEA3_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L 20287 #define MMEA3_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L 20288 #define MMEA3_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L 20289 #define MMEA3_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L 20290 #define MMEA3_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L 20291 #define MMEA3_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L 20292 #define MMEA3_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK 0x03000000L 20293 #define MMEA3_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK 0x0C000000L 20294 #define MMEA3_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK 0x30000000L 20295 #define MMEA3_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK 0xC0000000L 20296 //MMEA3_DSM_CNTL 20297 #define MMEA3_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 20298 #define MMEA3_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 20299 #define MMEA3_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 20300 #define MMEA3_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 20301 #define MMEA3_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 20302 #define MMEA3_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 20303 #define MMEA3_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 20304 #define MMEA3_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 20305 #define MMEA3_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 20306 #define MMEA3_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 20307 #define MMEA3_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 20308 #define MMEA3_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 20309 #define MMEA3_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 20310 #define MMEA3_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 20311 #define MMEA3_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 20312 #define MMEA3_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 20313 #define MMEA3_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 20314 #define MMEA3_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 20315 #define MMEA3_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 20316 #define MMEA3_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 20317 #define MMEA3_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 20318 #define MMEA3_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 20319 #define MMEA3_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 20320 #define MMEA3_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 20321 #define MMEA3_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 20322 #define MMEA3_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 20323 #define MMEA3_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 20324 #define MMEA3_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 20325 #define MMEA3_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 20326 #define MMEA3_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 20327 #define MMEA3_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L 20328 #define MMEA3_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L 20329 //MMEA3_DSM_CNTLA 20330 #define MMEA3_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 20331 #define MMEA3_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 20332 #define MMEA3_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 20333 #define MMEA3_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 20334 #define MMEA3_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 20335 #define MMEA3_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 20336 #define MMEA3_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 20337 #define MMEA3_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 20338 #define MMEA3_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 20339 #define MMEA3_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 20340 #define MMEA3_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 20341 #define MMEA3_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 20342 #define MMEA3_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 20343 #define MMEA3_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 20344 #define MMEA3_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 20345 #define MMEA3_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 20346 #define MMEA3_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 20347 #define MMEA3_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 20348 #define MMEA3_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 20349 #define MMEA3_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 20350 #define MMEA3_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 20351 #define MMEA3_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 20352 #define MMEA3_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 20353 #define MMEA3_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 20354 #define MMEA3_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 20355 #define MMEA3_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 20356 #define MMEA3_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 20357 #define MMEA3_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 20358 //MMEA3_DSM_CNTL2 20359 #define MMEA3_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 20360 #define MMEA3_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 20361 #define MMEA3_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 20362 #define MMEA3_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 20363 #define MMEA3_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 20364 #define MMEA3_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 20365 #define MMEA3_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 20366 #define MMEA3_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb 20367 #define MMEA3_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 20368 #define MMEA3_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe 20369 #define MMEA3_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 20370 #define MMEA3_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 20371 #define MMEA3_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 20372 #define MMEA3_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 20373 #define MMEA3_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 20374 #define MMEA3_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 20375 #define MMEA3_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a 20376 #define MMEA3_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 20377 #define MMEA3_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 20378 #define MMEA3_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 20379 #define MMEA3_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 20380 #define MMEA3_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 20381 #define MMEA3_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 20382 #define MMEA3_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 20383 #define MMEA3_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 20384 #define MMEA3_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 20385 #define MMEA3_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 20386 #define MMEA3_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 20387 #define MMEA3_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 20388 #define MMEA3_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 20389 #define MMEA3_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 20390 #define MMEA3_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L 20391 #define MMEA3_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L 20392 #define MMEA3_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L 20393 //MMEA3_DSM_CNTL2A 20394 #define MMEA3_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 20395 #define MMEA3_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 20396 #define MMEA3_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 20397 #define MMEA3_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 20398 #define MMEA3_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 20399 #define MMEA3_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 20400 #define MMEA3_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 20401 #define MMEA3_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb 20402 #define MMEA3_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 20403 #define MMEA3_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe 20404 #define MMEA3_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 20405 #define MMEA3_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 20406 #define MMEA3_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 20407 #define MMEA3_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 20408 #define MMEA3_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 20409 #define MMEA3_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 20410 #define MMEA3_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 20411 #define MMEA3_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 20412 #define MMEA3_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 20413 #define MMEA3_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 20414 #define MMEA3_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 20415 #define MMEA3_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 20416 #define MMEA3_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 20417 #define MMEA3_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 20418 #define MMEA3_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 20419 #define MMEA3_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 20420 #define MMEA3_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 20421 #define MMEA3_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 20422 //MMEA3_CGTT_CLK_CTRL 20423 #define MMEA3_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 20424 #define MMEA3_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 20425 #define MMEA3_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc 20426 #define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 20427 #define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 20428 #define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 20429 #define MMEA3_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 20430 #define MMEA3_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 20431 #define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c 20432 #define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d 20433 #define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e 20434 #define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f 20435 #define MMEA3_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 20436 #define MMEA3_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 20437 #define MMEA3_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L 20438 #define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L 20439 #define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L 20440 #define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L 20441 #define MMEA3_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L 20442 #define MMEA3_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 20443 #define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L 20444 #define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L 20445 #define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L 20446 #define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L 20447 //MMEA3_EDC_MODE 20448 #define MMEA3_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 20449 #define MMEA3_EDC_MODE__GATE_FUE__SHIFT 0x11 20450 #define MMEA3_EDC_MODE__DED_MODE__SHIFT 0x14 20451 #define MMEA3_EDC_MODE__PROP_FED__SHIFT 0x1d 20452 #define MMEA3_EDC_MODE__BYPASS__SHIFT 0x1f 20453 #define MMEA3_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L 20454 #define MMEA3_EDC_MODE__GATE_FUE_MASK 0x00020000L 20455 #define MMEA3_EDC_MODE__DED_MODE_MASK 0x00300000L 20456 #define MMEA3_EDC_MODE__PROP_FED_MASK 0x20000000L 20457 #define MMEA3_EDC_MODE__BYPASS_MASK 0x80000000L 20458 //MMEA3_ERR_STATUS 20459 #define MMEA3_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 20460 #define MMEA3_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 20461 #define MMEA3_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 20462 #define MMEA3_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa 20463 #define MMEA3_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb 20464 #define MMEA3_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc 20465 #define MMEA3_ERR_STATUS__FUE_FLAG__SHIFT 0xd 20466 #define MMEA3_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL 20467 #define MMEA3_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L 20468 #define MMEA3_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L 20469 #define MMEA3_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L 20470 #define MMEA3_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L 20471 #define MMEA3_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L 20472 #define MMEA3_ERR_STATUS__FUE_FLAG_MASK 0x00002000L 20473 //MMEA3_MISC2 20474 #define MMEA3_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 20475 #define MMEA3_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 20476 #define MMEA3_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 20477 #define MMEA3_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 20478 #define MMEA3_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc 20479 #define MMEA3_MISC2__RRET_SWAP_MODE__SHIFT 0xd 20480 #define MMEA3_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L 20481 #define MMEA3_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L 20482 #define MMEA3_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL 20483 #define MMEA3_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L 20484 #define MMEA3_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L 20485 #define MMEA3_MISC2__RRET_SWAP_MODE_MASK 0x00002000L 20486 //MMEA3_ADDRDEC_SELECT 20487 #define MMEA3_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0 20488 #define MMEA3_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5 20489 #define MMEA3_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa 20490 #define MMEA3_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf 20491 #define MMEA3_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL 20492 #define MMEA3_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L 20493 #define MMEA3_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L 20494 #define MMEA3_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L 20495 //MMEA3_EDC_CNT3 20496 #define MMEA3_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0 20497 #define MMEA3_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2 20498 #define MMEA3_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4 20499 #define MMEA3_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6 20500 #define MMEA3_EDC_CNT3__IOWR_DATAMEM_DED_COUNT__SHIFT 0x8 20501 #define MMEA3_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0xa 20502 #define MMEA3_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xc 20503 #define MMEA3_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L 20504 #define MMEA3_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL 20505 #define MMEA3_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L 20506 #define MMEA3_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 20507 #define MMEA3_EDC_CNT3__IOWR_DATAMEM_DED_COUNT_MASK 0x00000300L 20508 #define MMEA3_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000C00L 20509 #define MMEA3_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00003000L 20510 20511 20512 // addressBlock: mmhub_ea_mmeadec4 20513 //MMEA4_DRAM_RD_CLI2GRP_MAP0 20514 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 20515 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 20516 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 20517 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 20518 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 20519 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 20520 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 20521 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 20522 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 20523 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 20524 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 20525 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 20526 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 20527 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 20528 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 20529 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 20530 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 20531 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 20532 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 20533 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 20534 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 20535 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 20536 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 20537 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 20538 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 20539 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 20540 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 20541 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 20542 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 20543 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 20544 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 20545 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 20546 //MMEA4_DRAM_RD_CLI2GRP_MAP1 20547 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 20548 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 20549 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 20550 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 20551 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 20552 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 20553 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 20554 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 20555 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 20556 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 20557 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 20558 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 20559 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 20560 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 20561 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 20562 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 20563 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 20564 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 20565 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 20566 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 20567 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 20568 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 20569 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 20570 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 20571 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 20572 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 20573 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 20574 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 20575 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 20576 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 20577 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 20578 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 20579 //MMEA4_DRAM_WR_CLI2GRP_MAP0 20580 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 20581 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 20582 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 20583 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 20584 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 20585 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 20586 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 20587 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 20588 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 20589 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 20590 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 20591 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 20592 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 20593 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 20594 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 20595 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 20596 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 20597 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 20598 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 20599 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 20600 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 20601 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 20602 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 20603 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 20604 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 20605 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 20606 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 20607 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 20608 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 20609 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 20610 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 20611 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 20612 //MMEA4_DRAM_WR_CLI2GRP_MAP1 20613 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 20614 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 20615 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 20616 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 20617 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 20618 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 20619 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 20620 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 20621 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 20622 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 20623 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 20624 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 20625 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 20626 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 20627 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 20628 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 20629 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 20630 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 20631 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 20632 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 20633 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 20634 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 20635 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 20636 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 20637 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 20638 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 20639 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 20640 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 20641 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 20642 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 20643 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 20644 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 20645 //MMEA4_DRAM_RD_GRP2VC_MAP 20646 #define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 20647 #define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 20648 #define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 20649 #define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 20650 #define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 20651 #define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 20652 #define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 20653 #define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 20654 //MMEA4_DRAM_WR_GRP2VC_MAP 20655 #define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 20656 #define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 20657 #define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 20658 #define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 20659 #define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 20660 #define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 20661 #define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 20662 #define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 20663 //MMEA4_DRAM_RD_LAZY 20664 #define MMEA4_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 20665 #define MMEA4_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 20666 #define MMEA4_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 20667 #define MMEA4_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 20668 #define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 20669 #define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 20670 #define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 20671 #define MMEA4_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L 20672 #define MMEA4_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L 20673 #define MMEA4_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L 20674 #define MMEA4_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L 20675 #define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 20676 #define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 20677 #define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 20678 //MMEA4_DRAM_WR_LAZY 20679 #define MMEA4_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 20680 #define MMEA4_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 20681 #define MMEA4_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 20682 #define MMEA4_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 20683 #define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 20684 #define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 20685 #define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 20686 #define MMEA4_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L 20687 #define MMEA4_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L 20688 #define MMEA4_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L 20689 #define MMEA4_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L 20690 #define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 20691 #define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 20692 #define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 20693 //MMEA4_DRAM_RD_CAM_CNTL 20694 #define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 20695 #define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 20696 #define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 20697 #define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 20698 #define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 20699 #define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 20700 #define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 20701 #define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 20702 #define MMEA4_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 20703 #define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 20704 #define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 20705 #define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 20706 #define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 20707 #define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 20708 #define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 20709 #define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 20710 #define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 20711 #define MMEA4_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 20712 //MMEA4_DRAM_WR_CAM_CNTL 20713 #define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 20714 #define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 20715 #define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 20716 #define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 20717 #define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 20718 #define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 20719 #define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 20720 #define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 20721 #define MMEA4_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 20722 #define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 20723 #define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 20724 #define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 20725 #define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 20726 #define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 20727 #define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 20728 #define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 20729 #define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 20730 #define MMEA4_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 20731 //MMEA4_DRAM_PAGE_BURST 20732 #define MMEA4_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 20733 #define MMEA4_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 20734 #define MMEA4_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 20735 #define MMEA4_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 20736 #define MMEA4_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL 20737 #define MMEA4_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 20738 #define MMEA4_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 20739 #define MMEA4_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L 20740 //MMEA4_DRAM_RD_PRI_AGE 20741 #define MMEA4_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 20742 #define MMEA4_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 20743 #define MMEA4_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 20744 #define MMEA4_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 20745 #define MMEA4_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 20746 #define MMEA4_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 20747 #define MMEA4_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 20748 #define MMEA4_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 20749 #define MMEA4_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 20750 #define MMEA4_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 20751 #define MMEA4_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 20752 #define MMEA4_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 20753 #define MMEA4_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 20754 #define MMEA4_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 20755 #define MMEA4_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 20756 #define MMEA4_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 20757 //MMEA4_DRAM_WR_PRI_AGE 20758 #define MMEA4_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 20759 #define MMEA4_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 20760 #define MMEA4_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 20761 #define MMEA4_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 20762 #define MMEA4_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 20763 #define MMEA4_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 20764 #define MMEA4_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 20765 #define MMEA4_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 20766 #define MMEA4_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 20767 #define MMEA4_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 20768 #define MMEA4_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 20769 #define MMEA4_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 20770 #define MMEA4_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 20771 #define MMEA4_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 20772 #define MMEA4_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 20773 #define MMEA4_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 20774 //MMEA4_DRAM_RD_PRI_QUEUING 20775 #define MMEA4_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 20776 #define MMEA4_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 20777 #define MMEA4_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 20778 #define MMEA4_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 20779 #define MMEA4_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 20780 #define MMEA4_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 20781 #define MMEA4_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 20782 #define MMEA4_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 20783 //MMEA4_DRAM_WR_PRI_QUEUING 20784 #define MMEA4_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 20785 #define MMEA4_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 20786 #define MMEA4_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 20787 #define MMEA4_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 20788 #define MMEA4_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 20789 #define MMEA4_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 20790 #define MMEA4_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 20791 #define MMEA4_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 20792 //MMEA4_DRAM_RD_PRI_FIXED 20793 #define MMEA4_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 20794 #define MMEA4_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 20795 #define MMEA4_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 20796 #define MMEA4_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 20797 #define MMEA4_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 20798 #define MMEA4_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 20799 #define MMEA4_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 20800 #define MMEA4_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 20801 //MMEA4_DRAM_WR_PRI_FIXED 20802 #define MMEA4_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 20803 #define MMEA4_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 20804 #define MMEA4_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 20805 #define MMEA4_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 20806 #define MMEA4_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 20807 #define MMEA4_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 20808 #define MMEA4_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 20809 #define MMEA4_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 20810 //MMEA4_DRAM_RD_PRI_URGENCY 20811 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 20812 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 20813 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 20814 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 20815 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 20816 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 20817 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 20818 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 20819 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 20820 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 20821 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 20822 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 20823 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 20824 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 20825 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 20826 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 20827 //MMEA4_DRAM_WR_PRI_URGENCY 20828 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 20829 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 20830 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 20831 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 20832 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 20833 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 20834 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 20835 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 20836 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 20837 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 20838 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 20839 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 20840 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 20841 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 20842 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 20843 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 20844 //MMEA4_DRAM_RD_PRI_QUANT_PRI1 20845 #define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 20846 #define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 20847 #define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 20848 #define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 20849 #define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 20850 #define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 20851 #define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 20852 #define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 20853 //MMEA4_DRAM_RD_PRI_QUANT_PRI2 20854 #define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 20855 #define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 20856 #define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 20857 #define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 20858 #define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 20859 #define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 20860 #define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 20861 #define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 20862 //MMEA4_DRAM_RD_PRI_QUANT_PRI3 20863 #define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 20864 #define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 20865 #define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 20866 #define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 20867 #define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 20868 #define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 20869 #define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 20870 #define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 20871 //MMEA4_DRAM_WR_PRI_QUANT_PRI1 20872 #define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 20873 #define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 20874 #define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 20875 #define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 20876 #define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 20877 #define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 20878 #define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 20879 #define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 20880 //MMEA4_DRAM_WR_PRI_QUANT_PRI2 20881 #define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 20882 #define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 20883 #define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 20884 #define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 20885 #define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 20886 #define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 20887 #define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 20888 #define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 20889 //MMEA4_DRAM_WR_PRI_QUANT_PRI3 20890 #define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 20891 #define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 20892 #define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 20893 #define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 20894 #define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 20895 #define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 20896 #define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 20897 #define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 20898 //MMEA4_GMI_RD_CLI2GRP_MAP0 20899 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 20900 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 20901 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 20902 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 20903 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 20904 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 20905 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 20906 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 20907 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 20908 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 20909 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 20910 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 20911 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 20912 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 20913 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 20914 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 20915 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 20916 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 20917 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 20918 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 20919 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 20920 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 20921 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 20922 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 20923 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 20924 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 20925 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 20926 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 20927 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 20928 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 20929 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 20930 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 20931 //MMEA4_GMI_RD_CLI2GRP_MAP1 20932 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 20933 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 20934 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 20935 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 20936 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 20937 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 20938 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 20939 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 20940 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 20941 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 20942 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 20943 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 20944 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 20945 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 20946 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 20947 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 20948 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 20949 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 20950 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 20951 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 20952 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 20953 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 20954 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 20955 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 20956 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 20957 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 20958 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 20959 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 20960 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 20961 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 20962 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 20963 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 20964 //MMEA4_GMI_WR_CLI2GRP_MAP0 20965 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 20966 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 20967 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 20968 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 20969 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 20970 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 20971 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 20972 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 20973 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 20974 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 20975 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 20976 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 20977 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 20978 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 20979 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 20980 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 20981 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 20982 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 20983 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 20984 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 20985 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 20986 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 20987 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 20988 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 20989 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 20990 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 20991 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 20992 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 20993 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 20994 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 20995 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 20996 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 20997 //MMEA4_GMI_WR_CLI2GRP_MAP1 20998 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 20999 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 21000 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 21001 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 21002 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 21003 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 21004 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 21005 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 21006 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 21007 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 21008 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 21009 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 21010 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 21011 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 21012 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 21013 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 21014 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 21015 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 21016 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 21017 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 21018 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 21019 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 21020 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 21021 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 21022 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 21023 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 21024 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 21025 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 21026 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 21027 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 21028 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 21029 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 21030 //MMEA4_GMI_RD_GRP2VC_MAP 21031 #define MMEA4_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 21032 #define MMEA4_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 21033 #define MMEA4_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 21034 #define MMEA4_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 21035 #define MMEA4_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 21036 #define MMEA4_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 21037 #define MMEA4_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 21038 #define MMEA4_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 21039 //MMEA4_GMI_WR_GRP2VC_MAP 21040 #define MMEA4_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 21041 #define MMEA4_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 21042 #define MMEA4_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 21043 #define MMEA4_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 21044 #define MMEA4_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 21045 #define MMEA4_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 21046 #define MMEA4_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 21047 #define MMEA4_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 21048 //MMEA4_GMI_RD_LAZY 21049 #define MMEA4_GMI_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 21050 #define MMEA4_GMI_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 21051 #define MMEA4_GMI_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 21052 #define MMEA4_GMI_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 21053 #define MMEA4_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 21054 #define MMEA4_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 21055 #define MMEA4_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 21056 #define MMEA4_GMI_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L 21057 #define MMEA4_GMI_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L 21058 #define MMEA4_GMI_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L 21059 #define MMEA4_GMI_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L 21060 #define MMEA4_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 21061 #define MMEA4_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 21062 #define MMEA4_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 21063 //MMEA4_GMI_WR_LAZY 21064 #define MMEA4_GMI_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 21065 #define MMEA4_GMI_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 21066 #define MMEA4_GMI_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 21067 #define MMEA4_GMI_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 21068 #define MMEA4_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 21069 #define MMEA4_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 21070 #define MMEA4_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 21071 #define MMEA4_GMI_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L 21072 #define MMEA4_GMI_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L 21073 #define MMEA4_GMI_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L 21074 #define MMEA4_GMI_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L 21075 #define MMEA4_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 21076 #define MMEA4_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 21077 #define MMEA4_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 21078 //MMEA4_GMI_RD_CAM_CNTL 21079 #define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 21080 #define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 21081 #define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 21082 #define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 21083 #define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 21084 #define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 21085 #define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 21086 #define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 21087 #define MMEA4_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 21088 #define MMEA4_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d 21089 #define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 21090 #define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 21091 #define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 21092 #define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 21093 #define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 21094 #define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 21095 #define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 21096 #define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 21097 #define MMEA4_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 21098 #define MMEA4_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L 21099 //MMEA4_GMI_WR_CAM_CNTL 21100 #define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 21101 #define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 21102 #define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 21103 #define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 21104 #define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 21105 #define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 21106 #define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 21107 #define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 21108 #define MMEA4_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 21109 #define MMEA4_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d 21110 #define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 21111 #define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 21112 #define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 21113 #define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 21114 #define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 21115 #define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 21116 #define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 21117 #define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 21118 #define MMEA4_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 21119 #define MMEA4_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L 21120 //MMEA4_GMI_PAGE_BURST 21121 #define MMEA4_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 21122 #define MMEA4_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 21123 #define MMEA4_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 21124 #define MMEA4_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 21125 #define MMEA4_GMI_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL 21126 #define MMEA4_GMI_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 21127 #define MMEA4_GMI_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 21128 #define MMEA4_GMI_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L 21129 //MMEA4_GMI_RD_PRI_AGE 21130 #define MMEA4_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 21131 #define MMEA4_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 21132 #define MMEA4_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 21133 #define MMEA4_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 21134 #define MMEA4_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 21135 #define MMEA4_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 21136 #define MMEA4_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 21137 #define MMEA4_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 21138 #define MMEA4_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 21139 #define MMEA4_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 21140 #define MMEA4_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 21141 #define MMEA4_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 21142 #define MMEA4_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 21143 #define MMEA4_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 21144 #define MMEA4_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 21145 #define MMEA4_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 21146 //MMEA4_GMI_WR_PRI_AGE 21147 #define MMEA4_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 21148 #define MMEA4_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 21149 #define MMEA4_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 21150 #define MMEA4_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 21151 #define MMEA4_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 21152 #define MMEA4_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 21153 #define MMEA4_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 21154 #define MMEA4_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 21155 #define MMEA4_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 21156 #define MMEA4_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 21157 #define MMEA4_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 21158 #define MMEA4_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 21159 #define MMEA4_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 21160 #define MMEA4_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 21161 #define MMEA4_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 21162 #define MMEA4_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 21163 //MMEA4_GMI_RD_PRI_QUEUING 21164 #define MMEA4_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 21165 #define MMEA4_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 21166 #define MMEA4_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 21167 #define MMEA4_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 21168 #define MMEA4_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 21169 #define MMEA4_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 21170 #define MMEA4_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 21171 #define MMEA4_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 21172 //MMEA4_GMI_WR_PRI_QUEUING 21173 #define MMEA4_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 21174 #define MMEA4_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 21175 #define MMEA4_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 21176 #define MMEA4_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 21177 #define MMEA4_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 21178 #define MMEA4_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 21179 #define MMEA4_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 21180 #define MMEA4_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 21181 //MMEA4_GMI_RD_PRI_FIXED 21182 #define MMEA4_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 21183 #define MMEA4_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 21184 #define MMEA4_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 21185 #define MMEA4_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 21186 #define MMEA4_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 21187 #define MMEA4_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 21188 #define MMEA4_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 21189 #define MMEA4_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 21190 //MMEA4_GMI_WR_PRI_FIXED 21191 #define MMEA4_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 21192 #define MMEA4_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 21193 #define MMEA4_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 21194 #define MMEA4_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 21195 #define MMEA4_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 21196 #define MMEA4_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 21197 #define MMEA4_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 21198 #define MMEA4_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 21199 //MMEA4_GMI_RD_PRI_URGENCY 21200 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 21201 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 21202 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 21203 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 21204 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 21205 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 21206 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 21207 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 21208 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 21209 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 21210 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 21211 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 21212 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 21213 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 21214 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 21215 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 21216 //MMEA4_GMI_WR_PRI_URGENCY 21217 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 21218 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 21219 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 21220 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 21221 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 21222 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 21223 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 21224 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 21225 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 21226 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 21227 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 21228 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 21229 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 21230 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 21231 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 21232 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 21233 //MMEA4_GMI_RD_PRI_URGENCY_MASKING 21234 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 21235 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 21236 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 21237 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 21238 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 21239 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 21240 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 21241 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 21242 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 21243 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 21244 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 21245 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 21246 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 21247 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 21248 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 21249 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 21250 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 21251 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 21252 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 21253 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 21254 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 21255 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 21256 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 21257 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 21258 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 21259 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 21260 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 21261 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 21262 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 21263 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 21264 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 21265 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 21266 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 21267 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 21268 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 21269 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 21270 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 21271 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 21272 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 21273 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 21274 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 21275 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 21276 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 21277 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 21278 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 21279 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 21280 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 21281 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 21282 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 21283 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 21284 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 21285 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 21286 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 21287 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 21288 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 21289 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 21290 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 21291 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 21292 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 21293 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 21294 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 21295 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 21296 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 21297 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 21298 //MMEA4_GMI_WR_PRI_URGENCY_MASKING 21299 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 21300 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 21301 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 21302 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 21303 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 21304 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 21305 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 21306 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 21307 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 21308 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 21309 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 21310 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 21311 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 21312 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 21313 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 21314 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 21315 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 21316 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 21317 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 21318 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 21319 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 21320 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 21321 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 21322 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 21323 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 21324 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 21325 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 21326 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 21327 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 21328 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 21329 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 21330 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 21331 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 21332 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 21333 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 21334 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 21335 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 21336 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 21337 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 21338 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 21339 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 21340 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 21341 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 21342 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 21343 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 21344 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 21345 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 21346 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 21347 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 21348 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 21349 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 21350 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 21351 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 21352 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 21353 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 21354 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 21355 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 21356 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 21357 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 21358 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 21359 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 21360 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 21361 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 21362 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 21363 //MMEA4_GMI_RD_PRI_QUANT_PRI1 21364 #define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 21365 #define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 21366 #define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 21367 #define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 21368 #define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 21369 #define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 21370 #define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 21371 #define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 21372 //MMEA4_GMI_RD_PRI_QUANT_PRI2 21373 #define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 21374 #define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 21375 #define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 21376 #define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 21377 #define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 21378 #define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 21379 #define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 21380 #define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 21381 //MMEA4_GMI_RD_PRI_QUANT_PRI3 21382 #define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 21383 #define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 21384 #define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 21385 #define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 21386 #define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 21387 #define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 21388 #define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 21389 #define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 21390 //MMEA4_GMI_WR_PRI_QUANT_PRI1 21391 #define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 21392 #define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 21393 #define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 21394 #define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 21395 #define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 21396 #define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 21397 #define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 21398 #define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 21399 //MMEA4_GMI_WR_PRI_QUANT_PRI2 21400 #define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 21401 #define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 21402 #define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 21403 #define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 21404 #define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 21405 #define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 21406 #define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 21407 #define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 21408 //MMEA4_GMI_WR_PRI_QUANT_PRI3 21409 #define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 21410 #define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 21411 #define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 21412 #define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 21413 #define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 21414 #define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 21415 #define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 21416 #define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 21417 //MMEA4_ADDRNORM_BASE_ADDR0 21418 #define MMEA4_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 21419 #define MMEA4_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 21420 #define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 21421 #define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x6 21422 #define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 21423 #define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 21424 #define MMEA4_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc 21425 #define MMEA4_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L 21426 #define MMEA4_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 21427 #define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000003CL 21428 #define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x000000C0L 21429 #define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L 21430 #define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L 21431 #define MMEA4_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L 21432 //MMEA4_ADDRNORM_LIMIT_ADDR0 21433 #define MMEA4_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 21434 #define MMEA4_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc 21435 #define MMEA4_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL 21436 #define MMEA4_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L 21437 //MMEA4_ADDRNORM_BASE_ADDR1 21438 #define MMEA4_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 21439 #define MMEA4_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 21440 #define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 21441 #define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x6 21442 #define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 21443 #define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 21444 #define MMEA4_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc 21445 #define MMEA4_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L 21446 #define MMEA4_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 21447 #define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000003CL 21448 #define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x000000C0L 21449 #define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L 21450 #define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L 21451 #define MMEA4_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L 21452 //MMEA4_ADDRNORM_LIMIT_ADDR1 21453 #define MMEA4_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 21454 #define MMEA4_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc 21455 #define MMEA4_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL 21456 #define MMEA4_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L 21457 //MMEA4_ADDRNORM_OFFSET_ADDR1 21458 #define MMEA4_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 21459 #define MMEA4_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 21460 #define MMEA4_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L 21461 #define MMEA4_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L 21462 //MMEA4_ADDRNORM_BASE_ADDR2 21463 #define MMEA4_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT 0x0 21464 #define MMEA4_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT 0x1 21465 #define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT 0x2 21466 #define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT 0x6 21467 #define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT 0x8 21468 #define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT 0x9 21469 #define MMEA4_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT 0xc 21470 #define MMEA4_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK 0x00000001L 21471 #define MMEA4_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 21472 #define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK 0x0000003CL 21473 #define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK 0x000000C0L 21474 #define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK 0x00000100L 21475 #define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK 0x00000E00L 21476 #define MMEA4_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK 0xFFFFF000L 21477 //MMEA4_ADDRNORM_LIMIT_ADDR2 21478 #define MMEA4_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT 0x0 21479 #define MMEA4_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT 0xc 21480 #define MMEA4_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK 0x0000001FL 21481 #define MMEA4_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK 0xFFFFF000L 21482 //MMEA4_ADDRNORM_BASE_ADDR3 21483 #define MMEA4_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT 0x0 21484 #define MMEA4_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT 0x1 21485 #define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT 0x2 21486 #define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT 0x6 21487 #define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT 0x8 21488 #define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT 0x9 21489 #define MMEA4_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT 0xc 21490 #define MMEA4_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK 0x00000001L 21491 #define MMEA4_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 21492 #define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK 0x0000003CL 21493 #define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK 0x000000C0L 21494 #define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK 0x00000100L 21495 #define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK 0x00000E00L 21496 #define MMEA4_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK 0xFFFFF000L 21497 //MMEA4_ADDRNORM_LIMIT_ADDR3 21498 #define MMEA4_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT 0x0 21499 #define MMEA4_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT 0xc 21500 #define MMEA4_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK 0x0000001FL 21501 #define MMEA4_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK 0xFFFFF000L 21502 //MMEA4_ADDRNORM_OFFSET_ADDR3 21503 #define MMEA4_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT 0x0 21504 #define MMEA4_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT 0x14 21505 #define MMEA4_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK 0x00000001L 21506 #define MMEA4_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK 0xFFF00000L 21507 //MMEA4_ADDRNORM_BASE_ADDR4 21508 #define MMEA4_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL__SHIFT 0x0 21509 #define MMEA4_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN__SHIFT 0x1 21510 #define MMEA4_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN__SHIFT 0x2 21511 #define MMEA4_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES__SHIFT 0x6 21512 #define MMEA4_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS__SHIFT 0x8 21513 #define MMEA4_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL__SHIFT 0x9 21514 #define MMEA4_ADDRNORM_BASE_ADDR4__BASE_ADDR__SHIFT 0xc 21515 #define MMEA4_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL_MASK 0x00000001L 21516 #define MMEA4_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 21517 #define MMEA4_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN_MASK 0x0000003CL 21518 #define MMEA4_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES_MASK 0x000000C0L 21519 #define MMEA4_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS_MASK 0x00000100L 21520 #define MMEA4_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL_MASK 0x00000E00L 21521 #define MMEA4_ADDRNORM_BASE_ADDR4__BASE_ADDR_MASK 0xFFFFF000L 21522 //MMEA4_ADDRNORM_LIMIT_ADDR4 21523 #define MMEA4_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID__SHIFT 0x0 21524 #define MMEA4_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR__SHIFT 0xc 21525 #define MMEA4_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID_MASK 0x0000001FL 21526 #define MMEA4_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR_MASK 0xFFFFF000L 21527 //MMEA4_ADDRNORM_BASE_ADDR5 21528 #define MMEA4_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL__SHIFT 0x0 21529 #define MMEA4_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN__SHIFT 0x1 21530 #define MMEA4_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN__SHIFT 0x2 21531 #define MMEA4_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES__SHIFT 0x6 21532 #define MMEA4_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS__SHIFT 0x8 21533 #define MMEA4_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL__SHIFT 0x9 21534 #define MMEA4_ADDRNORM_BASE_ADDR5__BASE_ADDR__SHIFT 0xc 21535 #define MMEA4_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL_MASK 0x00000001L 21536 #define MMEA4_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 21537 #define MMEA4_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN_MASK 0x0000003CL 21538 #define MMEA4_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES_MASK 0x000000C0L 21539 #define MMEA4_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS_MASK 0x00000100L 21540 #define MMEA4_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL_MASK 0x00000E00L 21541 #define MMEA4_ADDRNORM_BASE_ADDR5__BASE_ADDR_MASK 0xFFFFF000L 21542 //MMEA4_ADDRNORM_LIMIT_ADDR5 21543 #define MMEA4_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID__SHIFT 0x0 21544 #define MMEA4_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR__SHIFT 0xc 21545 #define MMEA4_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID_MASK 0x0000001FL 21546 #define MMEA4_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR_MASK 0xFFFFF000L 21547 //MMEA4_ADDRNORM_OFFSET_ADDR5 21548 #define MMEA4_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN__SHIFT 0x0 21549 #define MMEA4_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET__SHIFT 0x14 21550 #define MMEA4_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN_MASK 0x00000001L 21551 #define MMEA4_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_MASK 0xFFF00000L 21552 //MMEA4_ADDRNORMDRAM_HOLE_CNTL 21553 #define MMEA4_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 21554 #define MMEA4_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 21555 #define MMEA4_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L 21556 #define MMEA4_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L 21557 //MMEA4_ADDRNORMGMI_HOLE_CNTL 21558 #define MMEA4_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 21559 #define MMEA4_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 21560 #define MMEA4_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L 21561 #define MMEA4_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L 21562 //MMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG 21563 #define MMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0 21564 #define MMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6 21565 #define MMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL 21566 #define MMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L 21567 //MMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG 21568 #define MMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT 0x0 21569 #define MMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT 0x6 21570 #define MMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK 0x0000003FL 21571 #define MMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK 0x00000FC0L 21572 //MMEA4_ADDRDEC_BANK_CFG 21573 #define MMEA4_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 21574 #define MMEA4_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x6 21575 #define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xc 21576 #define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xf 21577 #define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x12 21578 #define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x13 21579 #define MMEA4_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000003FL 21580 #define MMEA4_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x00000FC0L 21581 #define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00007000L 21582 #define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x00038000L 21583 #define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00040000L 21584 #define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00080000L 21585 //MMEA4_ADDRDEC_MISC_CFG 21586 #define MMEA4_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 21587 #define MMEA4_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 21588 #define MMEA4_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 21589 #define MMEA4_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 21590 #define MMEA4_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 21591 #define MMEA4_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc 21592 #define MMEA4_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11 21593 #define MMEA4_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16 21594 #define MMEA4_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18 21595 #define MMEA4_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a 21596 #define MMEA4_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d 21597 #define MMEA4_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L 21598 #define MMEA4_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L 21599 #define MMEA4_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L 21600 #define MMEA4_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L 21601 #define MMEA4_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L 21602 #define MMEA4_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L 21603 #define MMEA4_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L 21604 #define MMEA4_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L 21605 #define MMEA4_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L 21606 #define MMEA4_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L 21607 #define MMEA4_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L 21608 //MMEA4_ADDRDECDRAM_ADDR_HASH_BANK0 21609 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 21610 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 21611 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe 21612 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L 21613 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL 21614 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L 21615 //MMEA4_ADDRDECDRAM_ADDR_HASH_BANK1 21616 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 21617 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 21618 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe 21619 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L 21620 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL 21621 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L 21622 //MMEA4_ADDRDECDRAM_ADDR_HASH_BANK2 21623 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 21624 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 21625 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe 21626 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L 21627 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL 21628 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L 21629 //MMEA4_ADDRDECDRAM_ADDR_HASH_BANK3 21630 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 21631 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 21632 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe 21633 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L 21634 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL 21635 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L 21636 //MMEA4_ADDRDECDRAM_ADDR_HASH_BANK4 21637 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 21638 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 21639 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe 21640 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L 21641 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL 21642 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L 21643 //MMEA4_ADDRDECDRAM_ADDR_HASH_BANK5 21644 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT 0x0 21645 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR__SHIFT 0x1 21646 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR__SHIFT 0xe 21647 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE_MASK 0x00000001L 21648 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR_MASK 0x00003FFEL 21649 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR_MASK 0xFFFFC000L 21650 //MMEA4_ADDRDECDRAM_ADDR_HASH_PC 21651 #define MMEA4_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 21652 #define MMEA4_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 21653 #define MMEA4_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe 21654 #define MMEA4_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L 21655 #define MMEA4_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL 21656 #define MMEA4_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L 21657 //MMEA4_ADDRDECDRAM_ADDR_HASH_PC2 21658 #define MMEA4_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 21659 #define MMEA4_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000003FL 21660 //MMEA4_ADDRDECDRAM_ADDR_HASH_CS0 21661 #define MMEA4_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 21662 #define MMEA4_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 21663 #define MMEA4_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L 21664 #define MMEA4_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL 21665 //MMEA4_ADDRDECDRAM_ADDR_HASH_CS1 21666 #define MMEA4_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 21667 #define MMEA4_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 21668 #define MMEA4_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L 21669 #define MMEA4_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL 21670 //MMEA4_ADDRDECDRAM_HARVEST_ENABLE 21671 #define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 21672 #define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 21673 #define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 21674 #define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 21675 #define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 21676 #define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 21677 #define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L 21678 #define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L 21679 #define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L 21680 #define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L 21681 #define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L 21682 #define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L 21683 //MMEA4_ADDRDECGMI_ADDR_HASH_BANK0 21684 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 21685 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 21686 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe 21687 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L 21688 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL 21689 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L 21690 //MMEA4_ADDRDECGMI_ADDR_HASH_BANK1 21691 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 21692 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 21693 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe 21694 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L 21695 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL 21696 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L 21697 //MMEA4_ADDRDECGMI_ADDR_HASH_BANK2 21698 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 21699 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 21700 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe 21701 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L 21702 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL 21703 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L 21704 //MMEA4_ADDRDECGMI_ADDR_HASH_BANK3 21705 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 21706 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 21707 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe 21708 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L 21709 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL 21710 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L 21711 //MMEA4_ADDRDECGMI_ADDR_HASH_BANK4 21712 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 21713 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 21714 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe 21715 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L 21716 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL 21717 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L 21718 //MMEA4_ADDRDECGMI_ADDR_HASH_BANK5 21719 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT 0x0 21720 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR__SHIFT 0x1 21721 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR__SHIFT 0xe 21722 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE_MASK 0x00000001L 21723 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR_MASK 0x00003FFEL 21724 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR_MASK 0xFFFFC000L 21725 //MMEA4_ADDRDECGMI_ADDR_HASH_PC 21726 #define MMEA4_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 21727 #define MMEA4_ADDRDECGMI_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 21728 #define MMEA4_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe 21729 #define MMEA4_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L 21730 #define MMEA4_ADDRDECGMI_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL 21731 #define MMEA4_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L 21732 //MMEA4_ADDRDECGMI_ADDR_HASH_PC2 21733 #define MMEA4_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 21734 #define MMEA4_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000003FL 21735 //MMEA4_ADDRDECGMI_ADDR_HASH_CS0 21736 #define MMEA4_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 21737 #define MMEA4_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 21738 #define MMEA4_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L 21739 #define MMEA4_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL 21740 //MMEA4_ADDRDECGMI_ADDR_HASH_CS1 21741 #define MMEA4_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 21742 #define MMEA4_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 21743 #define MMEA4_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L 21744 #define MMEA4_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL 21745 //MMEA4_ADDRDECGMI_HARVEST_ENABLE 21746 #define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 21747 #define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 21748 #define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 21749 #define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 21750 #define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 21751 #define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 21752 #define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L 21753 #define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L 21754 #define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L 21755 #define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L 21756 #define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L 21757 #define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L 21758 //MMEA4_ADDRDEC0_BASE_ADDR_CS0 21759 #define MMEA4_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 21760 #define MMEA4_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 21761 #define MMEA4_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 21762 #define MMEA4_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 21763 //MMEA4_ADDRDEC0_BASE_ADDR_CS1 21764 #define MMEA4_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 21765 #define MMEA4_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 21766 #define MMEA4_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 21767 #define MMEA4_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 21768 //MMEA4_ADDRDEC0_BASE_ADDR_CS2 21769 #define MMEA4_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 21770 #define MMEA4_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 21771 #define MMEA4_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 21772 #define MMEA4_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 21773 //MMEA4_ADDRDEC0_BASE_ADDR_CS3 21774 #define MMEA4_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 21775 #define MMEA4_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 21776 #define MMEA4_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 21777 #define MMEA4_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 21778 //MMEA4_ADDRDEC0_BASE_ADDR_SECCS0 21779 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 21780 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 21781 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 21782 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 21783 //MMEA4_ADDRDEC0_BASE_ADDR_SECCS1 21784 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 21785 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 21786 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 21787 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 21788 //MMEA4_ADDRDEC0_BASE_ADDR_SECCS2 21789 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 21790 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 21791 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 21792 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 21793 //MMEA4_ADDRDEC0_BASE_ADDR_SECCS3 21794 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 21795 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 21796 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 21797 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 21798 //MMEA4_ADDRDEC0_ADDR_MASK_CS01 21799 #define MMEA4_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 21800 #define MMEA4_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 21801 //MMEA4_ADDRDEC0_ADDR_MASK_CS23 21802 #define MMEA4_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 21803 #define MMEA4_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 21804 //MMEA4_ADDRDEC0_ADDR_MASK_SECCS01 21805 #define MMEA4_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 21806 #define MMEA4_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 21807 //MMEA4_ADDRDEC0_ADDR_MASK_SECCS23 21808 #define MMEA4_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 21809 #define MMEA4_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 21810 //MMEA4_ADDRDEC0_ADDR_CFG_CS01 21811 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 21812 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 21813 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 21814 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 21815 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 21816 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 21817 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 21818 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 21819 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 21820 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 21821 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 21822 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 21823 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 21824 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 21825 //MMEA4_ADDRDEC0_ADDR_CFG_CS23 21826 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 21827 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 21828 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 21829 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 21830 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 21831 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 21832 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 21833 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 21834 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 21835 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 21836 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 21837 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 21838 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 21839 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 21840 //MMEA4_ADDRDEC0_ADDR_SEL_CS01 21841 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 21842 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 21843 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 21844 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc 21845 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 21846 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 21847 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 21848 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 21849 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 21850 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 21851 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 21852 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 21853 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 21854 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 21855 //MMEA4_ADDRDEC0_ADDR_SEL_CS23 21856 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 21857 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 21858 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 21859 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc 21860 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 21861 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 21862 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 21863 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 21864 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 21865 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 21866 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 21867 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 21868 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 21869 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 21870 //MMEA4_ADDRDEC0_ADDR_SEL2_CS01 21871 #define MMEA4_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 21872 #define MMEA4_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 21873 //MMEA4_ADDRDEC0_ADDR_SEL2_CS23 21874 #define MMEA4_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 21875 #define MMEA4_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 21876 //MMEA4_ADDRDEC0_COL_SEL_LO_CS01 21877 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 21878 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 21879 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 21880 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc 21881 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 21882 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 21883 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 21884 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 21885 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 21886 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 21887 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 21888 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 21889 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 21890 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 21891 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 21892 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 21893 //MMEA4_ADDRDEC0_COL_SEL_LO_CS23 21894 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 21895 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 21896 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 21897 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc 21898 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 21899 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 21900 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 21901 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 21902 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 21903 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 21904 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 21905 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 21906 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 21907 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 21908 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 21909 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 21910 //MMEA4_ADDRDEC0_COL_SEL_HI_CS01 21911 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 21912 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 21913 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 21914 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc 21915 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 21916 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 21917 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 21918 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 21919 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 21920 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 21921 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 21922 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 21923 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 21924 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 21925 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 21926 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 21927 //MMEA4_ADDRDEC0_COL_SEL_HI_CS23 21928 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 21929 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 21930 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 21931 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc 21932 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 21933 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 21934 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 21935 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 21936 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 21937 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 21938 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 21939 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 21940 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 21941 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 21942 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 21943 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 21944 //MMEA4_ADDRDEC0_RM_SEL_CS01 21945 #define MMEA4_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 21946 #define MMEA4_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 21947 #define MMEA4_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 21948 #define MMEA4_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 21949 #define MMEA4_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 21950 #define MMEA4_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 21951 #define MMEA4_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL 21952 #define MMEA4_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L 21953 #define MMEA4_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L 21954 #define MMEA4_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 21955 #define MMEA4_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 21956 #define MMEA4_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 21957 //MMEA4_ADDRDEC0_RM_SEL_CS23 21958 #define MMEA4_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 21959 #define MMEA4_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 21960 #define MMEA4_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 21961 #define MMEA4_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 21962 #define MMEA4_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 21963 #define MMEA4_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 21964 #define MMEA4_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL 21965 #define MMEA4_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L 21966 #define MMEA4_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L 21967 #define MMEA4_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 21968 #define MMEA4_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 21969 #define MMEA4_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 21970 //MMEA4_ADDRDEC0_RM_SEL_SECCS01 21971 #define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 21972 #define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 21973 #define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 21974 #define MMEA4_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 21975 #define MMEA4_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 21976 #define MMEA4_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 21977 #define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 21978 #define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 21979 #define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 21980 #define MMEA4_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 21981 #define MMEA4_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 21982 #define MMEA4_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 21983 //MMEA4_ADDRDEC0_RM_SEL_SECCS23 21984 #define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 21985 #define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 21986 #define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 21987 #define MMEA4_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 21988 #define MMEA4_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 21989 #define MMEA4_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 21990 #define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 21991 #define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 21992 #define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 21993 #define MMEA4_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 21994 #define MMEA4_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 21995 #define MMEA4_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 21996 //MMEA4_ADDRDEC1_BASE_ADDR_CS0 21997 #define MMEA4_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 21998 #define MMEA4_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 21999 #define MMEA4_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 22000 #define MMEA4_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 22001 //MMEA4_ADDRDEC1_BASE_ADDR_CS1 22002 #define MMEA4_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 22003 #define MMEA4_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 22004 #define MMEA4_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 22005 #define MMEA4_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 22006 //MMEA4_ADDRDEC1_BASE_ADDR_CS2 22007 #define MMEA4_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 22008 #define MMEA4_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 22009 #define MMEA4_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 22010 #define MMEA4_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 22011 //MMEA4_ADDRDEC1_BASE_ADDR_CS3 22012 #define MMEA4_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 22013 #define MMEA4_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 22014 #define MMEA4_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 22015 #define MMEA4_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 22016 //MMEA4_ADDRDEC1_BASE_ADDR_SECCS0 22017 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 22018 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 22019 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 22020 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 22021 //MMEA4_ADDRDEC1_BASE_ADDR_SECCS1 22022 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 22023 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 22024 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 22025 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 22026 //MMEA4_ADDRDEC1_BASE_ADDR_SECCS2 22027 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 22028 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 22029 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 22030 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 22031 //MMEA4_ADDRDEC1_BASE_ADDR_SECCS3 22032 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 22033 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 22034 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 22035 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 22036 //MMEA4_ADDRDEC1_ADDR_MASK_CS01 22037 #define MMEA4_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 22038 #define MMEA4_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 22039 //MMEA4_ADDRDEC1_ADDR_MASK_CS23 22040 #define MMEA4_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 22041 #define MMEA4_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 22042 //MMEA4_ADDRDEC1_ADDR_MASK_SECCS01 22043 #define MMEA4_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 22044 #define MMEA4_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 22045 //MMEA4_ADDRDEC1_ADDR_MASK_SECCS23 22046 #define MMEA4_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 22047 #define MMEA4_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 22048 //MMEA4_ADDRDEC1_ADDR_CFG_CS01 22049 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 22050 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 22051 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 22052 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 22053 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 22054 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 22055 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 22056 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 22057 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 22058 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 22059 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 22060 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 22061 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 22062 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 22063 //MMEA4_ADDRDEC1_ADDR_CFG_CS23 22064 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 22065 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 22066 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 22067 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 22068 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 22069 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 22070 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 22071 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 22072 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 22073 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 22074 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 22075 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 22076 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 22077 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 22078 //MMEA4_ADDRDEC1_ADDR_SEL_CS01 22079 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 22080 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 22081 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 22082 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc 22083 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 22084 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 22085 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 22086 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 22087 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 22088 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 22089 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 22090 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 22091 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 22092 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 22093 //MMEA4_ADDRDEC1_ADDR_SEL_CS23 22094 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 22095 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 22096 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 22097 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc 22098 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 22099 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 22100 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 22101 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 22102 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 22103 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 22104 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 22105 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 22106 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 22107 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 22108 //MMEA4_ADDRDEC1_ADDR_SEL2_CS01 22109 #define MMEA4_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 22110 #define MMEA4_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 22111 //MMEA4_ADDRDEC1_ADDR_SEL2_CS23 22112 #define MMEA4_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 22113 #define MMEA4_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 22114 //MMEA4_ADDRDEC1_COL_SEL_LO_CS01 22115 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 22116 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 22117 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 22118 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc 22119 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 22120 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 22121 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 22122 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 22123 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 22124 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 22125 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 22126 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 22127 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 22128 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 22129 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 22130 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 22131 //MMEA4_ADDRDEC1_COL_SEL_LO_CS23 22132 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 22133 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 22134 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 22135 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc 22136 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 22137 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 22138 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 22139 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 22140 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 22141 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 22142 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 22143 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 22144 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 22145 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 22146 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 22147 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 22148 //MMEA4_ADDRDEC1_COL_SEL_HI_CS01 22149 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 22150 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 22151 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 22152 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc 22153 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 22154 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 22155 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 22156 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 22157 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 22158 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 22159 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 22160 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 22161 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 22162 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 22163 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 22164 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 22165 //MMEA4_ADDRDEC1_COL_SEL_HI_CS23 22166 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 22167 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 22168 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 22169 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc 22170 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 22171 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 22172 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 22173 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 22174 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 22175 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 22176 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 22177 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 22178 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 22179 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 22180 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 22181 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 22182 //MMEA4_ADDRDEC1_RM_SEL_CS01 22183 #define MMEA4_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 22184 #define MMEA4_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 22185 #define MMEA4_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 22186 #define MMEA4_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 22187 #define MMEA4_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 22188 #define MMEA4_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 22189 #define MMEA4_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL 22190 #define MMEA4_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L 22191 #define MMEA4_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L 22192 #define MMEA4_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 22193 #define MMEA4_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 22194 #define MMEA4_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 22195 //MMEA4_ADDRDEC1_RM_SEL_CS23 22196 #define MMEA4_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 22197 #define MMEA4_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 22198 #define MMEA4_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 22199 #define MMEA4_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 22200 #define MMEA4_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 22201 #define MMEA4_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 22202 #define MMEA4_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL 22203 #define MMEA4_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L 22204 #define MMEA4_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L 22205 #define MMEA4_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 22206 #define MMEA4_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 22207 #define MMEA4_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 22208 //MMEA4_ADDRDEC1_RM_SEL_SECCS01 22209 #define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 22210 #define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 22211 #define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 22212 #define MMEA4_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 22213 #define MMEA4_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 22214 #define MMEA4_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 22215 #define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 22216 #define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 22217 #define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 22218 #define MMEA4_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 22219 #define MMEA4_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 22220 #define MMEA4_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 22221 //MMEA4_ADDRDEC1_RM_SEL_SECCS23 22222 #define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 22223 #define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 22224 #define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 22225 #define MMEA4_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 22226 #define MMEA4_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 22227 #define MMEA4_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 22228 #define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 22229 #define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 22230 #define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 22231 #define MMEA4_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 22232 #define MMEA4_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 22233 #define MMEA4_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 22234 //MMEA4_ADDRDEC2_BASE_ADDR_CS0 22235 #define MMEA4_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 22236 #define MMEA4_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 22237 #define MMEA4_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 22238 #define MMEA4_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 22239 //MMEA4_ADDRDEC2_BASE_ADDR_CS1 22240 #define MMEA4_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 22241 #define MMEA4_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 22242 #define MMEA4_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 22243 #define MMEA4_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 22244 //MMEA4_ADDRDEC2_BASE_ADDR_CS2 22245 #define MMEA4_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 22246 #define MMEA4_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 22247 #define MMEA4_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 22248 #define MMEA4_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 22249 //MMEA4_ADDRDEC2_BASE_ADDR_CS3 22250 #define MMEA4_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 22251 #define MMEA4_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 22252 #define MMEA4_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 22253 #define MMEA4_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 22254 //MMEA4_ADDRDEC2_BASE_ADDR_SECCS0 22255 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 22256 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 22257 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 22258 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 22259 //MMEA4_ADDRDEC2_BASE_ADDR_SECCS1 22260 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 22261 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 22262 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 22263 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 22264 //MMEA4_ADDRDEC2_BASE_ADDR_SECCS2 22265 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 22266 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 22267 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 22268 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 22269 //MMEA4_ADDRDEC2_BASE_ADDR_SECCS3 22270 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 22271 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 22272 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 22273 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 22274 //MMEA4_ADDRDEC2_ADDR_MASK_CS01 22275 #define MMEA4_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 22276 #define MMEA4_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 22277 //MMEA4_ADDRDEC2_ADDR_MASK_CS23 22278 #define MMEA4_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 22279 #define MMEA4_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 22280 //MMEA4_ADDRDEC2_ADDR_MASK_SECCS01 22281 #define MMEA4_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 22282 #define MMEA4_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 22283 //MMEA4_ADDRDEC2_ADDR_MASK_SECCS23 22284 #define MMEA4_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 22285 #define MMEA4_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 22286 //MMEA4_ADDRDEC2_ADDR_CFG_CS01 22287 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 22288 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 22289 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 22290 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 22291 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 22292 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 22293 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 22294 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 22295 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 22296 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 22297 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 22298 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 22299 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 22300 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 22301 //MMEA4_ADDRDEC2_ADDR_CFG_CS23 22302 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 22303 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 22304 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 22305 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 22306 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 22307 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 22308 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 22309 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 22310 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 22311 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 22312 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 22313 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 22314 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 22315 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 22316 //MMEA4_ADDRDEC2_ADDR_SEL_CS01 22317 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT 0x0 22318 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT 0x4 22319 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT 0x8 22320 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT 0xc 22321 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT 0x10 22322 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 22323 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 22324 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 22325 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 22326 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 22327 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 22328 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 22329 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 22330 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 22331 //MMEA4_ADDRDEC2_ADDR_SEL_CS23 22332 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT 0x0 22333 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT 0x4 22334 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT 0x8 22335 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT 0xc 22336 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT 0x10 22337 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 22338 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 22339 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 22340 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 22341 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 22342 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 22343 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 22344 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 22345 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 22346 //MMEA4_ADDRDEC2_ADDR_SEL2_CS01 22347 #define MMEA4_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 22348 #define MMEA4_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 22349 //MMEA4_ADDRDEC2_ADDR_SEL2_CS23 22350 #define MMEA4_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 22351 #define MMEA4_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 22352 //MMEA4_ADDRDEC2_COL_SEL_LO_CS01 22353 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT 0x0 22354 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT 0x4 22355 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT 0x8 22356 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT 0xc 22357 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT 0x10 22358 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT 0x14 22359 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT 0x18 22360 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 22361 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 22362 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 22363 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 22364 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 22365 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 22366 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 22367 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 22368 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 22369 //MMEA4_ADDRDEC2_COL_SEL_LO_CS23 22370 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT 0x0 22371 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT 0x4 22372 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT 0x8 22373 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT 0xc 22374 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT 0x10 22375 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT 0x14 22376 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT 0x18 22377 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 22378 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 22379 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 22380 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 22381 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 22382 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 22383 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 22384 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 22385 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 22386 //MMEA4_ADDRDEC2_COL_SEL_HI_CS01 22387 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT 0x0 22388 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT 0x4 22389 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT 0x8 22390 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT 0xc 22391 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT 0x10 22392 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT 0x14 22393 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT 0x18 22394 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 22395 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 22396 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 22397 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 22398 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 22399 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 22400 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 22401 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 22402 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 22403 //MMEA4_ADDRDEC2_COL_SEL_HI_CS23 22404 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT 0x0 22405 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT 0x4 22406 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT 0x8 22407 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT 0xc 22408 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT 0x10 22409 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT 0x14 22410 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT 0x18 22411 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 22412 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 22413 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 22414 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 22415 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 22416 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 22417 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 22418 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 22419 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 22420 //MMEA4_ADDRDEC2_RM_SEL_CS01 22421 #define MMEA4_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT 0x0 22422 #define MMEA4_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT 0x4 22423 #define MMEA4_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT 0x8 22424 #define MMEA4_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 22425 #define MMEA4_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 22426 #define MMEA4_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 22427 #define MMEA4_ADDRDEC2_RM_SEL_CS01__RM0_MASK 0x0000000FL 22428 #define MMEA4_ADDRDEC2_RM_SEL_CS01__RM1_MASK 0x000000F0L 22429 #define MMEA4_ADDRDEC2_RM_SEL_CS01__RM2_MASK 0x00000F00L 22430 #define MMEA4_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 22431 #define MMEA4_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 22432 #define MMEA4_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 22433 //MMEA4_ADDRDEC2_RM_SEL_CS23 22434 #define MMEA4_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT 0x0 22435 #define MMEA4_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT 0x4 22436 #define MMEA4_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT 0x8 22437 #define MMEA4_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 22438 #define MMEA4_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 22439 #define MMEA4_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 22440 #define MMEA4_ADDRDEC2_RM_SEL_CS23__RM0_MASK 0x0000000FL 22441 #define MMEA4_ADDRDEC2_RM_SEL_CS23__RM1_MASK 0x000000F0L 22442 #define MMEA4_ADDRDEC2_RM_SEL_CS23__RM2_MASK 0x00000F00L 22443 #define MMEA4_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 22444 #define MMEA4_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 22445 #define MMEA4_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 22446 //MMEA4_ADDRDEC2_RM_SEL_SECCS01 22447 #define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT 0x0 22448 #define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT 0x4 22449 #define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT 0x8 22450 #define MMEA4_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 22451 #define MMEA4_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 22452 #define MMEA4_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 22453 #define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 22454 #define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 22455 #define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 22456 #define MMEA4_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 22457 #define MMEA4_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 22458 #define MMEA4_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 22459 //MMEA4_ADDRDEC2_RM_SEL_SECCS23 22460 #define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT 0x0 22461 #define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT 0x4 22462 #define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT 0x8 22463 #define MMEA4_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 22464 #define MMEA4_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 22465 #define MMEA4_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 22466 #define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 22467 #define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 22468 #define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 22469 #define MMEA4_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 22470 #define MMEA4_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 22471 #define MMEA4_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 22472 //MMEA4_ADDRNORMDRAM_GLOBAL_CNTL 22473 #define MMEA4_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT 0x14 22474 #define MMEA4_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT 0x15 22475 #define MMEA4_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT 0x16 22476 #define MMEA4_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK 0x00100000L 22477 #define MMEA4_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK 0x00200000L 22478 #define MMEA4_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK 0x00400000L 22479 //MMEA4_ADDRNORMGMI_GLOBAL_CNTL 22480 #define MMEA4_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT 0x14 22481 #define MMEA4_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT 0x15 22482 #define MMEA4_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT 0x16 22483 #define MMEA4_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK 0x00100000L 22484 #define MMEA4_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK 0x00200000L 22485 #define MMEA4_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK 0x00400000L 22486 //MMEA4_IO_RD_CLI2GRP_MAP0 22487 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 22488 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 22489 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 22490 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 22491 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 22492 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 22493 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 22494 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 22495 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 22496 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 22497 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 22498 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 22499 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 22500 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 22501 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 22502 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 22503 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 22504 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 22505 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 22506 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 22507 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 22508 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 22509 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 22510 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 22511 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 22512 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 22513 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 22514 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 22515 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 22516 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 22517 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 22518 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 22519 //MMEA4_IO_RD_CLI2GRP_MAP1 22520 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 22521 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 22522 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 22523 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 22524 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 22525 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 22526 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 22527 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 22528 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 22529 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 22530 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 22531 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 22532 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 22533 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 22534 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 22535 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 22536 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 22537 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 22538 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 22539 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 22540 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 22541 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 22542 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 22543 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 22544 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 22545 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 22546 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 22547 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 22548 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 22549 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 22550 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 22551 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 22552 //MMEA4_IO_WR_CLI2GRP_MAP0 22553 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 22554 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 22555 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 22556 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 22557 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 22558 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 22559 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 22560 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 22561 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 22562 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 22563 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 22564 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 22565 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 22566 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 22567 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 22568 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 22569 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 22570 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 22571 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 22572 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 22573 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 22574 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 22575 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 22576 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 22577 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 22578 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 22579 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 22580 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 22581 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 22582 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 22583 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 22584 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 22585 //MMEA4_IO_WR_CLI2GRP_MAP1 22586 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 22587 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 22588 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 22589 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 22590 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 22591 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 22592 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 22593 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 22594 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 22595 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 22596 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 22597 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 22598 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 22599 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 22600 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 22601 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 22602 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 22603 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 22604 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 22605 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 22606 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 22607 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 22608 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 22609 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 22610 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 22611 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 22612 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 22613 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 22614 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 22615 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 22616 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 22617 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 22618 //MMEA4_IO_RD_COMBINE_FLUSH 22619 #define MMEA4_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 22620 #define MMEA4_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 22621 #define MMEA4_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 22622 #define MMEA4_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 22623 #define MMEA4_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT 0x10 22624 #define MMEA4_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 22625 #define MMEA4_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 22626 #define MMEA4_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 22627 #define MMEA4_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 22628 #define MMEA4_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK 0x00010000L 22629 //MMEA4_IO_WR_COMBINE_FLUSH 22630 #define MMEA4_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 22631 #define MMEA4_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 22632 #define MMEA4_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 22633 #define MMEA4_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 22634 #define MMEA4_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT 0x10 22635 #define MMEA4_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 22636 #define MMEA4_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 22637 #define MMEA4_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 22638 #define MMEA4_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 22639 #define MMEA4_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK 0x00010000L 22640 //MMEA4_IO_GROUP_BURST 22641 #define MMEA4_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 22642 #define MMEA4_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 22643 #define MMEA4_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 22644 #define MMEA4_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 22645 #define MMEA4_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL 22646 #define MMEA4_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 22647 #define MMEA4_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 22648 #define MMEA4_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L 22649 //MMEA4_IO_RD_PRI_AGE 22650 #define MMEA4_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 22651 #define MMEA4_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 22652 #define MMEA4_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 22653 #define MMEA4_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 22654 #define MMEA4_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 22655 #define MMEA4_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 22656 #define MMEA4_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 22657 #define MMEA4_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 22658 #define MMEA4_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 22659 #define MMEA4_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 22660 #define MMEA4_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 22661 #define MMEA4_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 22662 #define MMEA4_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 22663 #define MMEA4_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 22664 #define MMEA4_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 22665 #define MMEA4_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 22666 //MMEA4_IO_WR_PRI_AGE 22667 #define MMEA4_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 22668 #define MMEA4_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 22669 #define MMEA4_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 22670 #define MMEA4_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 22671 #define MMEA4_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 22672 #define MMEA4_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 22673 #define MMEA4_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 22674 #define MMEA4_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 22675 #define MMEA4_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 22676 #define MMEA4_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 22677 #define MMEA4_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 22678 #define MMEA4_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 22679 #define MMEA4_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 22680 #define MMEA4_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 22681 #define MMEA4_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 22682 #define MMEA4_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 22683 //MMEA4_IO_RD_PRI_QUEUING 22684 #define MMEA4_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 22685 #define MMEA4_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 22686 #define MMEA4_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 22687 #define MMEA4_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 22688 #define MMEA4_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 22689 #define MMEA4_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 22690 #define MMEA4_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 22691 #define MMEA4_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 22692 //MMEA4_IO_WR_PRI_QUEUING 22693 #define MMEA4_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 22694 #define MMEA4_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 22695 #define MMEA4_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 22696 #define MMEA4_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 22697 #define MMEA4_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 22698 #define MMEA4_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 22699 #define MMEA4_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 22700 #define MMEA4_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 22701 //MMEA4_IO_RD_PRI_FIXED 22702 #define MMEA4_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 22703 #define MMEA4_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 22704 #define MMEA4_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 22705 #define MMEA4_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 22706 #define MMEA4_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 22707 #define MMEA4_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 22708 #define MMEA4_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 22709 #define MMEA4_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 22710 //MMEA4_IO_WR_PRI_FIXED 22711 #define MMEA4_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 22712 #define MMEA4_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 22713 #define MMEA4_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 22714 #define MMEA4_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 22715 #define MMEA4_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 22716 #define MMEA4_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 22717 #define MMEA4_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 22718 #define MMEA4_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 22719 //MMEA4_IO_RD_PRI_URGENCY 22720 #define MMEA4_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 22721 #define MMEA4_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 22722 #define MMEA4_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 22723 #define MMEA4_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 22724 #define MMEA4_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 22725 #define MMEA4_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 22726 #define MMEA4_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 22727 #define MMEA4_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 22728 #define MMEA4_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 22729 #define MMEA4_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 22730 #define MMEA4_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 22731 #define MMEA4_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 22732 #define MMEA4_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 22733 #define MMEA4_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 22734 #define MMEA4_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 22735 #define MMEA4_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 22736 //MMEA4_IO_WR_PRI_URGENCY 22737 #define MMEA4_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 22738 #define MMEA4_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 22739 #define MMEA4_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 22740 #define MMEA4_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 22741 #define MMEA4_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 22742 #define MMEA4_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 22743 #define MMEA4_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 22744 #define MMEA4_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 22745 #define MMEA4_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 22746 #define MMEA4_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 22747 #define MMEA4_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 22748 #define MMEA4_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 22749 #define MMEA4_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 22750 #define MMEA4_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 22751 #define MMEA4_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 22752 #define MMEA4_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 22753 //MMEA4_IO_RD_PRI_URGENCY_MASKING 22754 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 22755 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 22756 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 22757 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 22758 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 22759 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 22760 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 22761 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 22762 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 22763 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 22764 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 22765 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 22766 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 22767 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 22768 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 22769 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 22770 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 22771 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 22772 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 22773 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 22774 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 22775 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 22776 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 22777 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 22778 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 22779 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 22780 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 22781 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 22782 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 22783 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 22784 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 22785 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 22786 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 22787 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 22788 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 22789 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 22790 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 22791 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 22792 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 22793 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 22794 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 22795 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 22796 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 22797 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 22798 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 22799 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 22800 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 22801 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 22802 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 22803 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 22804 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 22805 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 22806 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 22807 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 22808 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 22809 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 22810 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 22811 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 22812 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 22813 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 22814 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 22815 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 22816 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 22817 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 22818 //MMEA4_IO_WR_PRI_URGENCY_MASKING 22819 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 22820 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 22821 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 22822 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 22823 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 22824 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 22825 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 22826 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 22827 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 22828 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 22829 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 22830 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 22831 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 22832 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 22833 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 22834 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 22835 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 22836 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 22837 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 22838 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 22839 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 22840 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 22841 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 22842 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 22843 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 22844 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 22845 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 22846 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 22847 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 22848 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 22849 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 22850 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 22851 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 22852 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 22853 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 22854 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 22855 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 22856 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 22857 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 22858 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 22859 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 22860 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 22861 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 22862 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 22863 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 22864 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 22865 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 22866 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 22867 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 22868 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 22869 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 22870 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 22871 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 22872 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 22873 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 22874 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 22875 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 22876 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 22877 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 22878 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 22879 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 22880 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 22881 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 22882 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 22883 //MMEA4_IO_RD_PRI_QUANT_PRI1 22884 #define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 22885 #define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 22886 #define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 22887 #define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 22888 #define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 22889 #define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 22890 #define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 22891 #define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 22892 //MMEA4_IO_RD_PRI_QUANT_PRI2 22893 #define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 22894 #define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 22895 #define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 22896 #define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 22897 #define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 22898 #define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 22899 #define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 22900 #define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 22901 //MMEA4_IO_RD_PRI_QUANT_PRI3 22902 #define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 22903 #define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 22904 #define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 22905 #define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 22906 #define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 22907 #define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 22908 #define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 22909 #define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 22910 //MMEA4_IO_WR_PRI_QUANT_PRI1 22911 #define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 22912 #define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 22913 #define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 22914 #define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 22915 #define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 22916 #define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 22917 #define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 22918 #define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 22919 //MMEA4_IO_WR_PRI_QUANT_PRI2 22920 #define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 22921 #define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 22922 #define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 22923 #define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 22924 #define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 22925 #define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 22926 #define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 22927 #define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 22928 //MMEA4_IO_WR_PRI_QUANT_PRI3 22929 #define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 22930 #define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 22931 #define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 22932 #define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 22933 #define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 22934 #define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 22935 #define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 22936 #define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 22937 //MMEA4_SDP_ARB_DRAM 22938 #define MMEA4_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 22939 #define MMEA4_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 22940 #define MMEA4_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 22941 #define MMEA4_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 22942 #define MMEA4_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 22943 #define MMEA4_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 22944 #define MMEA4_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 22945 #define MMEA4_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 22946 #define MMEA4_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL 22947 #define MMEA4_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L 22948 #define MMEA4_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L 22949 #define MMEA4_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L 22950 #define MMEA4_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L 22951 #define MMEA4_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L 22952 #define MMEA4_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L 22953 #define MMEA4_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L 22954 //MMEA4_SDP_ARB_GMI 22955 #define MMEA4_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 22956 #define MMEA4_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 22957 #define MMEA4_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT 0x10 22958 #define MMEA4_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT 0x11 22959 #define MMEA4_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT 0x12 22960 #define MMEA4_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT 0x13 22961 #define MMEA4_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT 0x14 22962 #define MMEA4_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 22963 #define MMEA4_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT 0x16 22964 #define MMEA4_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL 22965 #define MMEA4_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L 22966 #define MMEA4_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK 0x00010000L 22967 #define MMEA4_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK 0x00020000L 22968 #define MMEA4_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK 0x00040000L 22969 #define MMEA4_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK 0x00080000L 22970 #define MMEA4_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK 0x00100000L 22971 #define MMEA4_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L 22972 #define MMEA4_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK 0x00400000L 22973 //MMEA4_SDP_ARB_FINAL 22974 #define MMEA4_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 22975 #define MMEA4_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 22976 #define MMEA4_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa 22977 #define MMEA4_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf 22978 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 22979 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 22980 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 22981 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 22982 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 22983 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 22984 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 22985 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 22986 #define MMEA4_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 22987 #define MMEA4_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a 22988 #define MMEA4_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1b 22989 #define MMEA4_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL 22990 #define MMEA4_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L 22991 #define MMEA4_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L 22992 #define MMEA4_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L 22993 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L 22994 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L 22995 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L 22996 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L 22997 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L 22998 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L 22999 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L 23000 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L 23001 #define MMEA4_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L 23002 #define MMEA4_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L 23003 #define MMEA4_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x08000000L 23004 //MMEA4_SDP_DRAM_PRIORITY 23005 #define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 23006 #define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 23007 #define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 23008 #define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 23009 #define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 23010 #define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 23011 #define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 23012 #define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 23013 #define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 23014 #define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 23015 #define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 23016 #define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 23017 #define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 23018 #define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 23019 #define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 23020 #define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 23021 //MMEA4_SDP_GMI_PRIORITY 23022 #define MMEA4_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 23023 #define MMEA4_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 23024 #define MMEA4_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 23025 #define MMEA4_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 23026 #define MMEA4_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 23027 #define MMEA4_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 23028 #define MMEA4_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 23029 #define MMEA4_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 23030 #define MMEA4_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 23031 #define MMEA4_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 23032 #define MMEA4_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 23033 #define MMEA4_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 23034 #define MMEA4_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 23035 #define MMEA4_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 23036 #define MMEA4_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 23037 #define MMEA4_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 23038 //MMEA4_SDP_IO_PRIORITY 23039 #define MMEA4_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 23040 #define MMEA4_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 23041 #define MMEA4_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 23042 #define MMEA4_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 23043 #define MMEA4_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 23044 #define MMEA4_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 23045 #define MMEA4_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 23046 #define MMEA4_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 23047 #define MMEA4_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 23048 #define MMEA4_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 23049 #define MMEA4_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 23050 #define MMEA4_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 23051 #define MMEA4_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 23052 #define MMEA4_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 23053 #define MMEA4_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 23054 #define MMEA4_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 23055 //MMEA4_SDP_CREDITS 23056 #define MMEA4_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 23057 #define MMEA4_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 23058 #define MMEA4_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 23059 #define MMEA4_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL 23060 #define MMEA4_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L 23061 #define MMEA4_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L 23062 //MMEA4_SDP_TAG_RESERVE0 23063 #define MMEA4_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 23064 #define MMEA4_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 23065 #define MMEA4_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 23066 #define MMEA4_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 23067 #define MMEA4_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL 23068 #define MMEA4_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L 23069 #define MMEA4_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L 23070 #define MMEA4_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L 23071 //MMEA4_SDP_TAG_RESERVE1 23072 #define MMEA4_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 23073 #define MMEA4_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 23074 #define MMEA4_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 23075 #define MMEA4_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 23076 #define MMEA4_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL 23077 #define MMEA4_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L 23078 #define MMEA4_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L 23079 #define MMEA4_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L 23080 //MMEA4_SDP_VCC_RESERVE0 23081 #define MMEA4_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 23082 #define MMEA4_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 23083 #define MMEA4_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc 23084 #define MMEA4_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 23085 #define MMEA4_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 23086 #define MMEA4_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 23087 #define MMEA4_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 23088 #define MMEA4_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 23089 #define MMEA4_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 23090 #define MMEA4_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 23091 //MMEA4_SDP_VCC_RESERVE1 23092 #define MMEA4_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 23093 #define MMEA4_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 23094 #define MMEA4_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc 23095 #define MMEA4_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 23096 #define MMEA4_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 23097 #define MMEA4_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 23098 #define MMEA4_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 23099 #define MMEA4_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 23100 //MMEA4_SDP_VCD_RESERVE0 23101 #define MMEA4_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 23102 #define MMEA4_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 23103 #define MMEA4_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc 23104 #define MMEA4_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 23105 #define MMEA4_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 23106 #define MMEA4_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 23107 #define MMEA4_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 23108 #define MMEA4_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 23109 #define MMEA4_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 23110 #define MMEA4_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 23111 //MMEA4_SDP_VCD_RESERVE1 23112 #define MMEA4_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 23113 #define MMEA4_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 23114 #define MMEA4_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc 23115 #define MMEA4_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 23116 #define MMEA4_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 23117 #define MMEA4_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 23118 #define MMEA4_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 23119 #define MMEA4_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 23120 //MMEA4_SDP_REQ_CNTL 23121 #define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 23122 #define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 23123 #define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 23124 #define MMEA4_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 23125 #define MMEA4_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 23126 #define MMEA4_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 23127 #define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L 23128 #define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L 23129 #define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L 23130 #define MMEA4_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L 23131 #define MMEA4_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L 23132 #define MMEA4_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L 23133 //MMEA4_MISC 23134 #define MMEA4_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 23135 #define MMEA4_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 23136 #define MMEA4_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 23137 #define MMEA4_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 23138 #define MMEA4_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 23139 #define MMEA4_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 23140 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 23141 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 23142 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 23143 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 23144 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa 23145 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb 23146 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc 23147 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd 23148 #define MMEA4_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe 23149 #define MMEA4_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf 23150 #define MMEA4_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 23151 #define MMEA4_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 23152 #define MMEA4_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 23153 #define MMEA4_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a 23154 #define MMEA4_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b 23155 #define MMEA4_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c 23156 #define MMEA4_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d 23157 #define MMEA4_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e 23158 #define MMEA4_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f 23159 #define MMEA4_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L 23160 #define MMEA4_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L 23161 #define MMEA4_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L 23162 #define MMEA4_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L 23163 #define MMEA4_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L 23164 #define MMEA4_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L 23165 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L 23166 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L 23167 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L 23168 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L 23169 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L 23170 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L 23171 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L 23172 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L 23173 #define MMEA4_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L 23174 #define MMEA4_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L 23175 #define MMEA4_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L 23176 #define MMEA4_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L 23177 #define MMEA4_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L 23178 #define MMEA4_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L 23179 #define MMEA4_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L 23180 #define MMEA4_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L 23181 #define MMEA4_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L 23182 #define MMEA4_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L 23183 #define MMEA4_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L 23184 //MMEA4_LATENCY_SAMPLING 23185 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 23186 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 23187 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 23188 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 23189 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 23190 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 23191 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 23192 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 23193 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 23194 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 23195 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa 23196 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb 23197 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc 23198 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd 23199 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe 23200 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 23201 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L 23202 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L 23203 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L 23204 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L 23205 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L 23206 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L 23207 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L 23208 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L 23209 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L 23210 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L 23211 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L 23212 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L 23213 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L 23214 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L 23215 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L 23216 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L 23217 //MMEA4_PERFCOUNTER_LO 23218 #define MMEA4_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 23219 #define MMEA4_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 23220 //MMEA4_PERFCOUNTER_HI 23221 #define MMEA4_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 23222 #define MMEA4_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 23223 #define MMEA4_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 23224 #define MMEA4_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 23225 //MMEA4_PERFCOUNTER0_CFG 23226 #define MMEA4_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 23227 #define MMEA4_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 23228 #define MMEA4_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 23229 #define MMEA4_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 23230 #define MMEA4_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 23231 #define MMEA4_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 23232 #define MMEA4_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 23233 #define MMEA4_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 23234 #define MMEA4_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 23235 #define MMEA4_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 23236 //MMEA4_PERFCOUNTER1_CFG 23237 #define MMEA4_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 23238 #define MMEA4_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 23239 #define MMEA4_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 23240 #define MMEA4_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 23241 #define MMEA4_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 23242 #define MMEA4_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 23243 #define MMEA4_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 23244 #define MMEA4_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 23245 #define MMEA4_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 23246 #define MMEA4_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 23247 //MMEA4_PERFCOUNTER_RSLT_CNTL 23248 #define MMEA4_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 23249 #define MMEA4_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 23250 #define MMEA4_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 23251 #define MMEA4_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 23252 #define MMEA4_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 23253 #define MMEA4_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 23254 #define MMEA4_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 23255 #define MMEA4_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 23256 #define MMEA4_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 23257 #define MMEA4_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 23258 #define MMEA4_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 23259 #define MMEA4_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 23260 //MMEA4_EDC_CNT 23261 #define MMEA4_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 23262 #define MMEA4_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 23263 #define MMEA4_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 23264 #define MMEA4_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 23265 #define MMEA4_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 23266 #define MMEA4_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa 23267 #define MMEA4_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc 23268 #define MMEA4_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe 23269 #define MMEA4_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 23270 #define MMEA4_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 23271 #define MMEA4_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 23272 #define MMEA4_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 23273 #define MMEA4_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 23274 #define MMEA4_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a 23275 #define MMEA4_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c 23276 #define MMEA4_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 23277 #define MMEA4_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 23278 #define MMEA4_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 23279 #define MMEA4_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 23280 #define MMEA4_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 23281 #define MMEA4_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 23282 #define MMEA4_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L 23283 #define MMEA4_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L 23284 #define MMEA4_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L 23285 #define MMEA4_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L 23286 #define MMEA4_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L 23287 #define MMEA4_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L 23288 #define MMEA4_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L 23289 #define MMEA4_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L 23290 #define MMEA4_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L 23291 //MMEA4_EDC_CNT2 23292 #define MMEA4_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 23293 #define MMEA4_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 23294 #define MMEA4_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 23295 #define MMEA4_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 23296 #define MMEA4_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 23297 #define MMEA4_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa 23298 #define MMEA4_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc 23299 #define MMEA4_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe 23300 #define MMEA4_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10 23301 #define MMEA4_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12 23302 #define MMEA4_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14 23303 #define MMEA4_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16 23304 #define MMEA4_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT 0x18 23305 #define MMEA4_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT 0x1a 23306 #define MMEA4_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT 0x1c 23307 #define MMEA4_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT 0x1e 23308 #define MMEA4_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 23309 #define MMEA4_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 23310 #define MMEA4_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 23311 #define MMEA4_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 23312 #define MMEA4_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 23313 #define MMEA4_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 23314 #define MMEA4_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L 23315 #define MMEA4_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L 23316 #define MMEA4_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L 23317 #define MMEA4_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L 23318 #define MMEA4_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L 23319 #define MMEA4_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L 23320 #define MMEA4_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK 0x03000000L 23321 #define MMEA4_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK 0x0C000000L 23322 #define MMEA4_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK 0x30000000L 23323 #define MMEA4_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK 0xC0000000L 23324 //MMEA4_DSM_CNTL 23325 #define MMEA4_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 23326 #define MMEA4_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 23327 #define MMEA4_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 23328 #define MMEA4_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 23329 #define MMEA4_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 23330 #define MMEA4_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 23331 #define MMEA4_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 23332 #define MMEA4_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 23333 #define MMEA4_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 23334 #define MMEA4_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 23335 #define MMEA4_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 23336 #define MMEA4_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 23337 #define MMEA4_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 23338 #define MMEA4_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 23339 #define MMEA4_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 23340 #define MMEA4_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 23341 #define MMEA4_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 23342 #define MMEA4_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 23343 #define MMEA4_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 23344 #define MMEA4_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 23345 #define MMEA4_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 23346 #define MMEA4_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 23347 #define MMEA4_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 23348 #define MMEA4_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 23349 #define MMEA4_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 23350 #define MMEA4_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 23351 #define MMEA4_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 23352 #define MMEA4_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 23353 #define MMEA4_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 23354 #define MMEA4_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 23355 #define MMEA4_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L 23356 #define MMEA4_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L 23357 //MMEA4_DSM_CNTLA 23358 #define MMEA4_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 23359 #define MMEA4_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 23360 #define MMEA4_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 23361 #define MMEA4_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 23362 #define MMEA4_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 23363 #define MMEA4_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 23364 #define MMEA4_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 23365 #define MMEA4_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 23366 #define MMEA4_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 23367 #define MMEA4_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 23368 #define MMEA4_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 23369 #define MMEA4_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 23370 #define MMEA4_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 23371 #define MMEA4_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 23372 #define MMEA4_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 23373 #define MMEA4_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 23374 #define MMEA4_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 23375 #define MMEA4_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 23376 #define MMEA4_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 23377 #define MMEA4_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 23378 #define MMEA4_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 23379 #define MMEA4_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 23380 #define MMEA4_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 23381 #define MMEA4_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 23382 #define MMEA4_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 23383 #define MMEA4_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 23384 #define MMEA4_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 23385 #define MMEA4_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 23386 //MMEA4_DSM_CNTL2 23387 #define MMEA4_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 23388 #define MMEA4_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 23389 #define MMEA4_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 23390 #define MMEA4_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 23391 #define MMEA4_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 23392 #define MMEA4_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 23393 #define MMEA4_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 23394 #define MMEA4_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb 23395 #define MMEA4_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 23396 #define MMEA4_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe 23397 #define MMEA4_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 23398 #define MMEA4_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 23399 #define MMEA4_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 23400 #define MMEA4_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 23401 #define MMEA4_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 23402 #define MMEA4_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 23403 #define MMEA4_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a 23404 #define MMEA4_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 23405 #define MMEA4_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 23406 #define MMEA4_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 23407 #define MMEA4_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 23408 #define MMEA4_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 23409 #define MMEA4_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 23410 #define MMEA4_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 23411 #define MMEA4_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 23412 #define MMEA4_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 23413 #define MMEA4_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 23414 #define MMEA4_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 23415 #define MMEA4_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 23416 #define MMEA4_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 23417 #define MMEA4_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 23418 #define MMEA4_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L 23419 #define MMEA4_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L 23420 #define MMEA4_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L 23421 //MMEA4_DSM_CNTL2A 23422 #define MMEA4_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 23423 #define MMEA4_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 23424 #define MMEA4_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 23425 #define MMEA4_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 23426 #define MMEA4_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 23427 #define MMEA4_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 23428 #define MMEA4_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 23429 #define MMEA4_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb 23430 #define MMEA4_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 23431 #define MMEA4_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe 23432 #define MMEA4_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 23433 #define MMEA4_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 23434 #define MMEA4_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 23435 #define MMEA4_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 23436 #define MMEA4_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 23437 #define MMEA4_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 23438 #define MMEA4_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 23439 #define MMEA4_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 23440 #define MMEA4_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 23441 #define MMEA4_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 23442 #define MMEA4_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 23443 #define MMEA4_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 23444 #define MMEA4_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 23445 #define MMEA4_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 23446 #define MMEA4_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 23447 #define MMEA4_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 23448 #define MMEA4_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 23449 #define MMEA4_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 23450 //MMEA4_CGTT_CLK_CTRL 23451 #define MMEA4_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 23452 #define MMEA4_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 23453 #define MMEA4_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc 23454 #define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 23455 #define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 23456 #define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 23457 #define MMEA4_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 23458 #define MMEA4_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 23459 #define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c 23460 #define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d 23461 #define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e 23462 #define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f 23463 #define MMEA4_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 23464 #define MMEA4_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 23465 #define MMEA4_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L 23466 #define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L 23467 #define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L 23468 #define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L 23469 #define MMEA4_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L 23470 #define MMEA4_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 23471 #define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L 23472 #define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L 23473 #define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L 23474 #define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L 23475 //MMEA4_EDC_MODE 23476 #define MMEA4_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 23477 #define MMEA4_EDC_MODE__GATE_FUE__SHIFT 0x11 23478 #define MMEA4_EDC_MODE__DED_MODE__SHIFT 0x14 23479 #define MMEA4_EDC_MODE__PROP_FED__SHIFT 0x1d 23480 #define MMEA4_EDC_MODE__BYPASS__SHIFT 0x1f 23481 #define MMEA4_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L 23482 #define MMEA4_EDC_MODE__GATE_FUE_MASK 0x00020000L 23483 #define MMEA4_EDC_MODE__DED_MODE_MASK 0x00300000L 23484 #define MMEA4_EDC_MODE__PROP_FED_MASK 0x20000000L 23485 #define MMEA4_EDC_MODE__BYPASS_MASK 0x80000000L 23486 //MMEA4_ERR_STATUS 23487 #define MMEA4_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 23488 #define MMEA4_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 23489 #define MMEA4_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 23490 #define MMEA4_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa 23491 #define MMEA4_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb 23492 #define MMEA4_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc 23493 #define MMEA4_ERR_STATUS__FUE_FLAG__SHIFT 0xd 23494 #define MMEA4_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL 23495 #define MMEA4_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L 23496 #define MMEA4_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L 23497 #define MMEA4_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L 23498 #define MMEA4_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L 23499 #define MMEA4_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L 23500 #define MMEA4_ERR_STATUS__FUE_FLAG_MASK 0x00002000L 23501 //MMEA4_MISC2 23502 #define MMEA4_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 23503 #define MMEA4_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 23504 #define MMEA4_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 23505 #define MMEA4_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 23506 #define MMEA4_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc 23507 #define MMEA4_MISC2__RRET_SWAP_MODE__SHIFT 0xd 23508 #define MMEA4_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L 23509 #define MMEA4_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L 23510 #define MMEA4_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL 23511 #define MMEA4_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L 23512 #define MMEA4_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L 23513 #define MMEA4_MISC2__RRET_SWAP_MODE_MASK 0x00002000L 23514 //MMEA4_ADDRDEC_SELECT 23515 #define MMEA4_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0 23516 #define MMEA4_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5 23517 #define MMEA4_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa 23518 #define MMEA4_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf 23519 #define MMEA4_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL 23520 #define MMEA4_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L 23521 #define MMEA4_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L 23522 #define MMEA4_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L 23523 //MMEA4_EDC_CNT3 23524 #define MMEA4_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0 23525 #define MMEA4_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2 23526 #define MMEA4_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4 23527 #define MMEA4_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6 23528 #define MMEA4_EDC_CNT3__IOWR_DATAMEM_DED_COUNT__SHIFT 0x8 23529 #define MMEA4_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0xa 23530 #define MMEA4_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xc 23531 #define MMEA4_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L 23532 #define MMEA4_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL 23533 #define MMEA4_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L 23534 #define MMEA4_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 23535 #define MMEA4_EDC_CNT3__IOWR_DATAMEM_DED_COUNT_MASK 0x00000300L 23536 #define MMEA4_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000C00L 23537 #define MMEA4_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00003000L 23538 23539 23540 // addressBlock: mmhub_pctldec0 23541 //PCTL0_CTRL 23542 #define PCTL0_CTRL__PG_ENABLE__SHIFT 0x0 23543 #define PCTL0_CTRL__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x1 23544 #define PCTL0_CTRL__STCTRL_RSMU_IDLE_THRESHOLD__SHIFT 0x4 23545 #define PCTL0_CTRL__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT 0xb 23546 #define PCTL0_CTRL__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x10 23547 #define PCTL0_CTRL__OVR_EA0_SDP_PARTACK__SHIFT 0x11 23548 #define PCTL0_CTRL__OVR_EA1_SDP_PARTACK__SHIFT 0x12 23549 #define PCTL0_CTRL__OVR_EA2_SDP_PARTACK__SHIFT 0x13 23550 #define PCTL0_CTRL__OVR_EA3_SDP_PARTACK__SHIFT 0x14 23551 #define PCTL0_CTRL__OVR_EA4_SDP_PARTACK__SHIFT 0x15 23552 #define PCTL0_CTRL__OVR_EA0_SDP_FULLACK__SHIFT 0x16 23553 #define PCTL0_CTRL__OVR_EA1_SDP_FULLACK__SHIFT 0x17 23554 #define PCTL0_CTRL__OVR_EA2_SDP_FULLACK__SHIFT 0x18 23555 #define PCTL0_CTRL__OVR_EA3_SDP_FULLACK__SHIFT 0x19 23556 #define PCTL0_CTRL__OVR_EA4_SDP_FULLACK__SHIFT 0x1a 23557 #define PCTL0_CTRL__PGFSM_CMD_STATUS__SHIFT 0x1b 23558 #define PCTL0_CTRL__PG_ENABLE_MASK 0x00000001L 23559 #define PCTL0_CTRL__ALLOW_DEEP_SLEEP_MODE_MASK 0x0000000EL 23560 #define PCTL0_CTRL__STCTRL_RSMU_IDLE_THRESHOLD_MASK 0x000007F0L 23561 #define PCTL0_CTRL__STCTRL_DAGB_IDLE_THRESHOLD_MASK 0x0000F800L 23562 #define PCTL0_CTRL__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x00010000L 23563 #define PCTL0_CTRL__OVR_EA0_SDP_PARTACK_MASK 0x00020000L 23564 #define PCTL0_CTRL__OVR_EA1_SDP_PARTACK_MASK 0x00040000L 23565 #define PCTL0_CTRL__OVR_EA2_SDP_PARTACK_MASK 0x00080000L 23566 #define PCTL0_CTRL__OVR_EA3_SDP_PARTACK_MASK 0x00100000L 23567 #define PCTL0_CTRL__OVR_EA4_SDP_PARTACK_MASK 0x00200000L 23568 #define PCTL0_CTRL__OVR_EA0_SDP_FULLACK_MASK 0x00400000L 23569 #define PCTL0_CTRL__OVR_EA1_SDP_FULLACK_MASK 0x00800000L 23570 #define PCTL0_CTRL__OVR_EA2_SDP_FULLACK_MASK 0x01000000L 23571 #define PCTL0_CTRL__OVR_EA3_SDP_FULLACK_MASK 0x02000000L 23572 #define PCTL0_CTRL__OVR_EA4_SDP_FULLACK_MASK 0x04000000L 23573 #define PCTL0_CTRL__PGFSM_CMD_STATUS_MASK 0x18000000L 23574 //PCTL0_MMHUB_DEEPSLEEP_IB 23575 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS0__SHIFT 0x0 23576 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS1__SHIFT 0x1 23577 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS2__SHIFT 0x2 23578 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS3__SHIFT 0x3 23579 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS4__SHIFT 0x4 23580 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS5__SHIFT 0x5 23581 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS6__SHIFT 0x6 23582 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS7__SHIFT 0x7 23583 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS8__SHIFT 0x8 23584 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS9__SHIFT 0x9 23585 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS10__SHIFT 0xa 23586 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS11__SHIFT 0xb 23587 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS12__SHIFT 0xc 23588 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS13__SHIFT 0xd 23589 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS14__SHIFT 0xe 23590 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS15__SHIFT 0xf 23591 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS16__SHIFT 0x10 23592 #define PCTL0_MMHUB_DEEPSLEEP_IB__SETCLEAR__SHIFT 0x1f 23593 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS0_MASK 0x00000001L 23594 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS1_MASK 0x00000002L 23595 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS2_MASK 0x00000004L 23596 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS3_MASK 0x00000008L 23597 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS4_MASK 0x00000010L 23598 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS5_MASK 0x00000020L 23599 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS6_MASK 0x00000040L 23600 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS7_MASK 0x00000080L 23601 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS8_MASK 0x00000100L 23602 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS9_MASK 0x00000200L 23603 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS10_MASK 0x00000400L 23604 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS11_MASK 0x00000800L 23605 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS12_MASK 0x00001000L 23606 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS13_MASK 0x00002000L 23607 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS14_MASK 0x00004000L 23608 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS15_MASK 0x00008000L 23609 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS16_MASK 0x00010000L 23610 #define PCTL0_MMHUB_DEEPSLEEP_IB__SETCLEAR_MASK 0x80000000L 23611 //PCTL0_MMHUB_DEEPSLEEP_OVERRIDE 23612 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT 0x0 23613 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT 0x1 23614 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT 0x2 23615 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT 0x3 23616 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT 0x4 23617 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT 0x5 23618 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT 0x6 23619 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT 0x7 23620 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT 0x8 23621 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT 0x9 23622 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT 0xa 23623 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT 0xb 23624 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT 0xc 23625 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT 0xd 23626 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT 0xe 23627 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT 0xf 23628 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT 0x10 23629 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB__SHIFT 0x11 23630 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK 0x00000001L 23631 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK 0x00000002L 23632 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK 0x00000004L 23633 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK 0x00000008L 23634 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK 0x00000010L 23635 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK 0x00000020L 23636 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK 0x00000040L 23637 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK 0x00000080L 23638 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK 0x00000100L 23639 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK 0x00000200L 23640 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK 0x00000400L 23641 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK 0x00000800L 23642 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK 0x00001000L 23643 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK 0x00002000L 23644 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK 0x00004000L 23645 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK 0x00008000L 23646 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK 0x00010000L 23647 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB_MASK 0x00020000L 23648 //PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB 23649 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0__SHIFT 0x0 23650 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1__SHIFT 0x1 23651 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2__SHIFT 0x2 23652 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3__SHIFT 0x3 23653 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4__SHIFT 0x4 23654 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5__SHIFT 0x5 23655 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6__SHIFT 0x6 23656 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7__SHIFT 0x7 23657 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8__SHIFT 0x8 23658 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9__SHIFT 0x9 23659 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10__SHIFT 0xa 23660 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11__SHIFT 0xb 23661 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12__SHIFT 0xc 23662 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13__SHIFT 0xd 23663 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14__SHIFT 0xe 23664 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15__SHIFT 0xf 23665 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16__SHIFT 0x10 23666 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0_MASK 0x00000001L 23667 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1_MASK 0x00000002L 23668 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2_MASK 0x00000004L 23669 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3_MASK 0x00000008L 23670 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4_MASK 0x00000010L 23671 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5_MASK 0x00000020L 23672 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6_MASK 0x00000040L 23673 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7_MASK 0x00000080L 23674 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8_MASK 0x00000100L 23675 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9_MASK 0x00000200L 23676 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10_MASK 0x00000400L 23677 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11_MASK 0x00000800L 23678 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12_MASK 0x00001000L 23679 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13_MASK 0x00002000L 23680 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14_MASK 0x00004000L 23681 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15_MASK 0x00008000L 23682 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16_MASK 0x00010000L 23683 //PCTL0_PG_IGNORE_DEEPSLEEP 23684 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS0__SHIFT 0x0 23685 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS1__SHIFT 0x1 23686 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS2__SHIFT 0x2 23687 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS3__SHIFT 0x3 23688 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS4__SHIFT 0x4 23689 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS5__SHIFT 0x5 23690 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS6__SHIFT 0x6 23691 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS7__SHIFT 0x7 23692 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS8__SHIFT 0x8 23693 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS9__SHIFT 0x9 23694 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS10__SHIFT 0xa 23695 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS11__SHIFT 0xb 23696 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS12__SHIFT 0xc 23697 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS13__SHIFT 0xd 23698 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS14__SHIFT 0xe 23699 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS15__SHIFT 0xf 23700 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS16__SHIFT 0x10 23701 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS_ATHUB__SHIFT 0x11 23702 #define PCTL0_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT 0x12 23703 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS0_MASK 0x00000001L 23704 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS1_MASK 0x00000002L 23705 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS2_MASK 0x00000004L 23706 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS3_MASK 0x00000008L 23707 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS4_MASK 0x00000010L 23708 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS5_MASK 0x00000020L 23709 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS6_MASK 0x00000040L 23710 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS7_MASK 0x00000080L 23711 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS8_MASK 0x00000100L 23712 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS9_MASK 0x00000200L 23713 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS10_MASK 0x00000400L 23714 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS11_MASK 0x00000800L 23715 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS12_MASK 0x00001000L 23716 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS13_MASK 0x00002000L 23717 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS14_MASK 0x00004000L 23718 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS15_MASK 0x00008000L 23719 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS16_MASK 0x00010000L 23720 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS_ATHUB_MASK 0x00020000L 23721 #define PCTL0_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK 0x00040000L 23722 //PCTL0_PG_IGNORE_DEEPSLEEP_IB 23723 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS0__SHIFT 0x0 23724 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS1__SHIFT 0x1 23725 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS2__SHIFT 0x2 23726 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS3__SHIFT 0x3 23727 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS4__SHIFT 0x4 23728 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS5__SHIFT 0x5 23729 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS6__SHIFT 0x6 23730 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS7__SHIFT 0x7 23731 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS8__SHIFT 0x8 23732 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS9__SHIFT 0x9 23733 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS10__SHIFT 0xa 23734 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS11__SHIFT 0xb 23735 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS12__SHIFT 0xc 23736 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS13__SHIFT 0xd 23737 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS14__SHIFT 0xe 23738 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS15__SHIFT 0xf 23739 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS16__SHIFT 0x10 23740 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__ALLIPS__SHIFT 0x11 23741 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS0_MASK 0x00000001L 23742 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS1_MASK 0x00000002L 23743 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS2_MASK 0x00000004L 23744 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS3_MASK 0x00000008L 23745 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS4_MASK 0x00000010L 23746 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS5_MASK 0x00000020L 23747 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS6_MASK 0x00000040L 23748 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS7_MASK 0x00000080L 23749 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS8_MASK 0x00000100L 23750 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS9_MASK 0x00000200L 23751 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS10_MASK 0x00000400L 23752 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS11_MASK 0x00000800L 23753 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS12_MASK 0x00001000L 23754 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS13_MASK 0x00002000L 23755 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS14_MASK 0x00004000L 23756 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS15_MASK 0x00008000L 23757 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS16_MASK 0x00010000L 23758 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__ALLIPS_MASK 0x00020000L 23759 //PCTL0_SLICE0_CFG_DAGB_BUSY 23760 #define PCTL0_SLICE0_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0 23761 #define PCTL0_SLICE0_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL 23762 //PCTL0_SLICE0_CFG_DS_ALLOW 23763 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS0__SHIFT 0x0 23764 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS1__SHIFT 0x1 23765 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS2__SHIFT 0x2 23766 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS3__SHIFT 0x3 23767 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS4__SHIFT 0x4 23768 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS5__SHIFT 0x5 23769 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS6__SHIFT 0x6 23770 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS7__SHIFT 0x7 23771 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS8__SHIFT 0x8 23772 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS9__SHIFT 0x9 23773 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS10__SHIFT 0xa 23774 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS11__SHIFT 0xb 23775 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS12__SHIFT 0xc 23776 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS13__SHIFT 0xd 23777 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS14__SHIFT 0xe 23778 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS15__SHIFT 0xf 23779 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS16__SHIFT 0x10 23780 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS0_MASK 0x00000001L 23781 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS1_MASK 0x00000002L 23782 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS2_MASK 0x00000004L 23783 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS3_MASK 0x00000008L 23784 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS4_MASK 0x00000010L 23785 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS5_MASK 0x00000020L 23786 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS6_MASK 0x00000040L 23787 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS7_MASK 0x00000080L 23788 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS8_MASK 0x00000100L 23789 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS9_MASK 0x00000200L 23790 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS10_MASK 0x00000400L 23791 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS11_MASK 0x00000800L 23792 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS12_MASK 0x00001000L 23793 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS13_MASK 0x00002000L 23794 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS14_MASK 0x00004000L 23795 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS15_MASK 0x00008000L 23796 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS16_MASK 0x00010000L 23797 //PCTL0_SLICE0_CFG_DS_ALLOW_IB 23798 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 23799 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 23800 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 23801 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 23802 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 23803 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 23804 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 23805 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 23806 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 23807 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 23808 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa 23809 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb 23810 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc 23811 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd 23812 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe 23813 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf 23814 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 23815 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L 23816 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L 23817 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L 23818 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L 23819 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L 23820 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L 23821 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L 23822 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L 23823 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L 23824 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L 23825 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L 23826 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L 23827 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L 23828 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L 23829 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L 23830 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L 23831 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L 23832 //PCTL0_SLICE1_CFG_DAGB_BUSY 23833 #define PCTL0_SLICE1_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0 23834 #define PCTL0_SLICE1_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL 23835 //PCTL0_SLICE1_CFG_DS_ALLOW 23836 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS0__SHIFT 0x0 23837 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS1__SHIFT 0x1 23838 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS2__SHIFT 0x2 23839 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS3__SHIFT 0x3 23840 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS4__SHIFT 0x4 23841 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS5__SHIFT 0x5 23842 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS6__SHIFT 0x6 23843 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS7__SHIFT 0x7 23844 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS8__SHIFT 0x8 23845 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS9__SHIFT 0x9 23846 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS10__SHIFT 0xa 23847 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS11__SHIFT 0xb 23848 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS12__SHIFT 0xc 23849 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS13__SHIFT 0xd 23850 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS14__SHIFT 0xe 23851 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS15__SHIFT 0xf 23852 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS16__SHIFT 0x10 23853 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS0_MASK 0x00000001L 23854 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS1_MASK 0x00000002L 23855 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS2_MASK 0x00000004L 23856 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS3_MASK 0x00000008L 23857 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS4_MASK 0x00000010L 23858 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS5_MASK 0x00000020L 23859 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS6_MASK 0x00000040L 23860 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS7_MASK 0x00000080L 23861 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS8_MASK 0x00000100L 23862 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS9_MASK 0x00000200L 23863 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS10_MASK 0x00000400L 23864 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS11_MASK 0x00000800L 23865 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS12_MASK 0x00001000L 23866 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS13_MASK 0x00002000L 23867 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS14_MASK 0x00004000L 23868 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS15_MASK 0x00008000L 23869 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS16_MASK 0x00010000L 23870 //PCTL0_SLICE1_CFG_DS_ALLOW_IB 23871 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 23872 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 23873 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 23874 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 23875 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 23876 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 23877 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 23878 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 23879 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 23880 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 23881 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa 23882 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb 23883 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc 23884 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd 23885 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe 23886 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf 23887 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 23888 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L 23889 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L 23890 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L 23891 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L 23892 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L 23893 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L 23894 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L 23895 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L 23896 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L 23897 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L 23898 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L 23899 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L 23900 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L 23901 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L 23902 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L 23903 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L 23904 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L 23905 //PCTL0_SLICE2_CFG_DAGB_BUSY 23906 #define PCTL0_SLICE2_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0 23907 #define PCTL0_SLICE2_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL 23908 //PCTL0_SLICE2_CFG_DS_ALLOW 23909 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS0__SHIFT 0x0 23910 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS1__SHIFT 0x1 23911 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS2__SHIFT 0x2 23912 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS3__SHIFT 0x3 23913 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS4__SHIFT 0x4 23914 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS5__SHIFT 0x5 23915 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS6__SHIFT 0x6 23916 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS7__SHIFT 0x7 23917 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS8__SHIFT 0x8 23918 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS9__SHIFT 0x9 23919 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS10__SHIFT 0xa 23920 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS11__SHIFT 0xb 23921 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS12__SHIFT 0xc 23922 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS13__SHIFT 0xd 23923 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS14__SHIFT 0xe 23924 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS15__SHIFT 0xf 23925 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS16__SHIFT 0x10 23926 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS0_MASK 0x00000001L 23927 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS1_MASK 0x00000002L 23928 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS2_MASK 0x00000004L 23929 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS3_MASK 0x00000008L 23930 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS4_MASK 0x00000010L 23931 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS5_MASK 0x00000020L 23932 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS6_MASK 0x00000040L 23933 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS7_MASK 0x00000080L 23934 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS8_MASK 0x00000100L 23935 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS9_MASK 0x00000200L 23936 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS10_MASK 0x00000400L 23937 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS11_MASK 0x00000800L 23938 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS12_MASK 0x00001000L 23939 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS13_MASK 0x00002000L 23940 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS14_MASK 0x00004000L 23941 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS15_MASK 0x00008000L 23942 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS16_MASK 0x00010000L 23943 //PCTL0_SLICE2_CFG_DS_ALLOW_IB 23944 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 23945 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 23946 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 23947 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 23948 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 23949 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 23950 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 23951 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 23952 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 23953 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 23954 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa 23955 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb 23956 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc 23957 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd 23958 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe 23959 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf 23960 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 23961 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L 23962 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L 23963 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L 23964 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L 23965 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L 23966 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L 23967 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L 23968 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L 23969 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L 23970 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L 23971 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L 23972 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L 23973 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L 23974 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L 23975 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L 23976 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L 23977 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L 23978 //PCTL0_SLICE3_CFG_DAGB_BUSY 23979 #define PCTL0_SLICE3_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0 23980 #define PCTL0_SLICE3_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL 23981 //PCTL0_SLICE3_CFG_DS_ALLOW 23982 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS0__SHIFT 0x0 23983 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS1__SHIFT 0x1 23984 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS2__SHIFT 0x2 23985 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS3__SHIFT 0x3 23986 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS4__SHIFT 0x4 23987 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS5__SHIFT 0x5 23988 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS6__SHIFT 0x6 23989 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS7__SHIFT 0x7 23990 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS8__SHIFT 0x8 23991 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS9__SHIFT 0x9 23992 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS10__SHIFT 0xa 23993 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS11__SHIFT 0xb 23994 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS12__SHIFT 0xc 23995 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS13__SHIFT 0xd 23996 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS14__SHIFT 0xe 23997 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS15__SHIFT 0xf 23998 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS16__SHIFT 0x10 23999 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS0_MASK 0x00000001L 24000 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS1_MASK 0x00000002L 24001 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS2_MASK 0x00000004L 24002 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS3_MASK 0x00000008L 24003 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS4_MASK 0x00000010L 24004 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS5_MASK 0x00000020L 24005 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS6_MASK 0x00000040L 24006 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS7_MASK 0x00000080L 24007 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS8_MASK 0x00000100L 24008 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS9_MASK 0x00000200L 24009 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS10_MASK 0x00000400L 24010 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS11_MASK 0x00000800L 24011 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS12_MASK 0x00001000L 24012 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS13_MASK 0x00002000L 24013 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS14_MASK 0x00004000L 24014 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS15_MASK 0x00008000L 24015 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS16_MASK 0x00010000L 24016 //PCTL0_SLICE3_CFG_DS_ALLOW_IB 24017 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 24018 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 24019 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 24020 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 24021 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 24022 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 24023 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 24024 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 24025 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 24026 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 24027 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa 24028 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb 24029 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc 24030 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd 24031 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe 24032 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf 24033 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 24034 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L 24035 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L 24036 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L 24037 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L 24038 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L 24039 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L 24040 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L 24041 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L 24042 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L 24043 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L 24044 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L 24045 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L 24046 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L 24047 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L 24048 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L 24049 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L 24050 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L 24051 //PCTL0_SLICE4_CFG_DAGB_BUSY 24052 #define PCTL0_SLICE4_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0 24053 #define PCTL0_SLICE4_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL 24054 //PCTL0_SLICE4_CFG_DS_ALLOW 24055 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS0__SHIFT 0x0 24056 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS1__SHIFT 0x1 24057 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS2__SHIFT 0x2 24058 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS3__SHIFT 0x3 24059 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS4__SHIFT 0x4 24060 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS5__SHIFT 0x5 24061 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS6__SHIFT 0x6 24062 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS7__SHIFT 0x7 24063 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS8__SHIFT 0x8 24064 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS9__SHIFT 0x9 24065 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS10__SHIFT 0xa 24066 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS11__SHIFT 0xb 24067 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS12__SHIFT 0xc 24068 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS13__SHIFT 0xd 24069 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS14__SHIFT 0xe 24070 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS15__SHIFT 0xf 24071 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS16__SHIFT 0x10 24072 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS0_MASK 0x00000001L 24073 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS1_MASK 0x00000002L 24074 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS2_MASK 0x00000004L 24075 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS3_MASK 0x00000008L 24076 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS4_MASK 0x00000010L 24077 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS5_MASK 0x00000020L 24078 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS6_MASK 0x00000040L 24079 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS7_MASK 0x00000080L 24080 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS8_MASK 0x00000100L 24081 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS9_MASK 0x00000200L 24082 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS10_MASK 0x00000400L 24083 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS11_MASK 0x00000800L 24084 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS12_MASK 0x00001000L 24085 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS13_MASK 0x00002000L 24086 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS14_MASK 0x00004000L 24087 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS15_MASK 0x00008000L 24088 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS16_MASK 0x00010000L 24089 //PCTL0_SLICE4_CFG_DS_ALLOW_IB 24090 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 24091 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 24092 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 24093 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 24094 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 24095 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 24096 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 24097 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 24098 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 24099 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 24100 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa 24101 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb 24102 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc 24103 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd 24104 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe 24105 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf 24106 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 24107 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L 24108 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L 24109 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L 24110 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L 24111 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L 24112 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L 24113 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L 24114 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L 24115 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L 24116 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L 24117 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L 24118 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L 24119 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L 24120 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L 24121 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L 24122 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L 24123 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L 24124 //PCTL0_UTCL2_MISC 24125 #define PCTL0_UTCL2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xb 24126 #define PCTL0_UTCL2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xc 24127 #define PCTL0_UTCL2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xf 24128 #define PCTL0_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10 24129 #define PCTL0_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 24130 #define PCTL0_UTCL2_MISC__RD_TIMER_ENABLE__SHIFT 0x12 24131 #define PCTL0_UTCL2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000800L 24132 #define PCTL0_UTCL2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00007000L 24133 #define PCTL0_UTCL2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00008000L 24134 #define PCTL0_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00010000L 24135 #define PCTL0_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L 24136 #define PCTL0_UTCL2_MISC__RD_TIMER_ENABLE_MASK 0x00040000L 24137 //PCTL0_SLICE0_MISC 24138 #define PCTL0_SLICE0_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa 24139 #define PCTL0_SLICE0_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb 24140 #define PCTL0_SLICE0_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe 24141 #define PCTL0_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf 24142 #define PCTL0_SLICE0_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 24143 #define PCTL0_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 24144 #define PCTL0_SLICE0_MISC__RD_TIMER_ENABLE__SHIFT 0x12 24145 #define PCTL0_SLICE0_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L 24146 #define PCTL0_SLICE0_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L 24147 #define PCTL0_SLICE0_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L 24148 #define PCTL0_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L 24149 #define PCTL0_SLICE0_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L 24150 #define PCTL0_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L 24151 #define PCTL0_SLICE0_MISC__RD_TIMER_ENABLE_MASK 0x00040000L 24152 //PCTL0_SLICE1_MISC 24153 #define PCTL0_SLICE1_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa 24154 #define PCTL0_SLICE1_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb 24155 #define PCTL0_SLICE1_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe 24156 #define PCTL0_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf 24157 #define PCTL0_SLICE1_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 24158 #define PCTL0_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 24159 #define PCTL0_SLICE1_MISC__RD_TIMER_ENABLE__SHIFT 0x12 24160 #define PCTL0_SLICE1_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L 24161 #define PCTL0_SLICE1_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L 24162 #define PCTL0_SLICE1_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L 24163 #define PCTL0_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L 24164 #define PCTL0_SLICE1_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L 24165 #define PCTL0_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L 24166 #define PCTL0_SLICE1_MISC__RD_TIMER_ENABLE_MASK 0x00040000L 24167 //PCTL0_SLICE2_MISC 24168 #define PCTL0_SLICE2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa 24169 #define PCTL0_SLICE2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb 24170 #define PCTL0_SLICE2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe 24171 #define PCTL0_SLICE2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf 24172 #define PCTL0_SLICE2_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 24173 #define PCTL0_SLICE2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 24174 #define PCTL0_SLICE2_MISC__RD_TIMER_ENABLE__SHIFT 0x12 24175 #define PCTL0_SLICE2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L 24176 #define PCTL0_SLICE2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L 24177 #define PCTL0_SLICE2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L 24178 #define PCTL0_SLICE2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L 24179 #define PCTL0_SLICE2_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L 24180 #define PCTL0_SLICE2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L 24181 #define PCTL0_SLICE2_MISC__RD_TIMER_ENABLE_MASK 0x00040000L 24182 //PCTL0_SLICE3_MISC 24183 #define PCTL0_SLICE3_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa 24184 #define PCTL0_SLICE3_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb 24185 #define PCTL0_SLICE3_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe 24186 #define PCTL0_SLICE3_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf 24187 #define PCTL0_SLICE3_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 24188 #define PCTL0_SLICE3_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 24189 #define PCTL0_SLICE3_MISC__RD_TIMER_ENABLE__SHIFT 0x12 24190 #define PCTL0_SLICE3_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L 24191 #define PCTL0_SLICE3_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L 24192 #define PCTL0_SLICE3_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L 24193 #define PCTL0_SLICE3_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L 24194 #define PCTL0_SLICE3_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L 24195 #define PCTL0_SLICE3_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L 24196 #define PCTL0_SLICE3_MISC__RD_TIMER_ENABLE_MASK 0x00040000L 24197 //PCTL0_SLICE4_MISC 24198 #define PCTL0_SLICE4_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa 24199 #define PCTL0_SLICE4_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb 24200 #define PCTL0_SLICE4_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe 24201 #define PCTL0_SLICE4_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf 24202 #define PCTL0_SLICE4_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 24203 #define PCTL0_SLICE4_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 24204 #define PCTL0_SLICE4_MISC__RD_TIMER_ENABLE__SHIFT 0x12 24205 #define PCTL0_SLICE4_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L 24206 #define PCTL0_SLICE4_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L 24207 #define PCTL0_SLICE4_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L 24208 #define PCTL0_SLICE4_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L 24209 #define PCTL0_SLICE4_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L 24210 #define PCTL0_SLICE4_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L 24211 #define PCTL0_SLICE4_MISC__RD_TIMER_ENABLE_MASK 0x00040000L 24212 //PCTL0_UTCL2_RENG_EXECUTE 24213 #define PCTL0_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 24214 #define PCTL0_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 24215 #define PCTL0_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 24216 #define PCTL0_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xd 24217 #define PCTL0_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L 24218 #define PCTL0_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 24219 #define PCTL0_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00001FFCL 24220 #define PCTL0_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x00FFE000L 24221 //PCTL0_SLICE0_RENG_EXECUTE 24222 #define PCTL0_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 24223 #define PCTL0_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 24224 #define PCTL0_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 24225 #define PCTL0_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc 24226 #define PCTL0_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L 24227 #define PCTL0_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 24228 #define PCTL0_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL 24229 #define PCTL0_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L 24230 //PCTL0_SLICE1_RENG_EXECUTE 24231 #define PCTL0_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 24232 #define PCTL0_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 24233 #define PCTL0_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 24234 #define PCTL0_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc 24235 #define PCTL0_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L 24236 #define PCTL0_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 24237 #define PCTL0_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL 24238 #define PCTL0_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L 24239 //PCTL0_SLICE2_RENG_EXECUTE 24240 #define PCTL0_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 24241 #define PCTL0_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 24242 #define PCTL0_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 24243 #define PCTL0_SLICE2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc 24244 #define PCTL0_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L 24245 #define PCTL0_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 24246 #define PCTL0_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL 24247 #define PCTL0_SLICE2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L 24248 //PCTL0_SLICE3_RENG_EXECUTE 24249 #define PCTL0_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 24250 #define PCTL0_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 24251 #define PCTL0_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 24252 #define PCTL0_SLICE3_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc 24253 #define PCTL0_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L 24254 #define PCTL0_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 24255 #define PCTL0_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL 24256 #define PCTL0_SLICE3_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L 24257 //PCTL0_SLICE4_RENG_EXECUTE 24258 #define PCTL0_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 24259 #define PCTL0_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 24260 #define PCTL0_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 24261 #define PCTL0_SLICE4_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc 24262 #define PCTL0_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L 24263 #define PCTL0_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 24264 #define PCTL0_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL 24265 #define PCTL0_SLICE4_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L 24266 //PCTL0_UTCL2_RENG_RAM_INDEX 24267 #define PCTL0_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 24268 #define PCTL0_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000007FFL 24269 //PCTL0_UTCL2_RENG_RAM_DATA 24270 #define PCTL0_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 24271 #define PCTL0_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 24272 //PCTL0_SLICE0_RENG_RAM_INDEX 24273 #define PCTL0_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 24274 #define PCTL0_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL 24275 //PCTL0_SLICE0_RENG_RAM_DATA 24276 #define PCTL0_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 24277 #define PCTL0_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 24278 //PCTL0_SLICE1_RENG_RAM_INDEX 24279 #define PCTL0_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 24280 #define PCTL0_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL 24281 //PCTL0_SLICE1_RENG_RAM_DATA 24282 #define PCTL0_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 24283 #define PCTL0_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 24284 //PCTL0_SLICE2_RENG_RAM_INDEX 24285 #define PCTL0_SLICE2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 24286 #define PCTL0_SLICE2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL 24287 //PCTL0_SLICE2_RENG_RAM_DATA 24288 #define PCTL0_SLICE2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 24289 #define PCTL0_SLICE2_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 24290 //PCTL0_SLICE3_RENG_RAM_INDEX 24291 #define PCTL0_SLICE3_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 24292 #define PCTL0_SLICE3_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL 24293 //PCTL0_SLICE3_RENG_RAM_DATA 24294 #define PCTL0_SLICE3_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 24295 #define PCTL0_SLICE3_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 24296 //PCTL0_SLICE4_RENG_RAM_INDEX 24297 #define PCTL0_SLICE4_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 24298 #define PCTL0_SLICE4_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL 24299 //PCTL0_SLICE4_RENG_RAM_DATA 24300 #define PCTL0_SLICE4_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 24301 #define PCTL0_SLICE4_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 24302 //PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 24303 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 24304 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 24305 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 24306 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 24307 //PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 24308 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 24309 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 24310 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 24311 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 24312 //PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 24313 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 24314 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 24315 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 24316 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 24317 //PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 24318 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 24319 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 24320 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 24321 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 24322 //PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 24323 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 24324 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 24325 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 24326 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 24327 //PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 24328 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 24329 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 24330 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 24331 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 24332 //PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 24333 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 24334 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 24335 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 24336 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 24337 //PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 24338 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 24339 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 24340 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 24341 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 24342 //PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 24343 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 24344 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 24345 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 24346 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 24347 //PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 24348 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 24349 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 24350 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 24351 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 24352 //PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 24353 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 24354 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 24355 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 24356 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 24357 //PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 24358 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 24359 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 24360 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 24361 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 24362 //PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 24363 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 24364 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 24365 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 24366 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 24367 //PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 24368 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 24369 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 24370 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 24371 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 24372 //PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 24373 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 24374 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 24375 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 24376 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 24377 //PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 24378 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 24379 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 24380 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 24381 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 24382 //PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 24383 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 24384 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 24385 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 24386 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 24387 //PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 24388 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 24389 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 24390 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 24391 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 24392 //PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 24393 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 24394 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 24395 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 24396 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 24397 //PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 24398 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 24399 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 24400 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 24401 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 24402 //PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 24403 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 24404 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 24405 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 24406 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 24407 //PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0 24408 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 24409 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 24410 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 24411 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 24412 //PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1 24413 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 24414 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 24415 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 24416 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 24417 //PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2 24418 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 24419 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 24420 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 24421 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 24422 //PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3 24423 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 24424 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 24425 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 24426 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 24427 //PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4 24428 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 24429 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 24430 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 24431 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 24432 //PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0 24433 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 24434 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 24435 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 24436 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 24437 //PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1 24438 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 24439 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 24440 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 24441 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 24442 //PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0 24443 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 24444 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 24445 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 24446 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 24447 //PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1 24448 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 24449 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 24450 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 24451 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 24452 //PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2 24453 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 24454 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 24455 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 24456 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 24457 //PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3 24458 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 24459 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 24460 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 24461 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 24462 //PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4 24463 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 24464 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 24465 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 24466 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 24467 //PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0 24468 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 24469 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 24470 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 24471 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 24472 //PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1 24473 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 24474 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 24475 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 24476 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 24477 //PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0 24478 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 24479 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 24480 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 24481 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 24482 //PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1 24483 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 24484 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 24485 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 24486 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 24487 //PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2 24488 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 24489 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 24490 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 24491 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 24492 //PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3 24493 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 24494 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 24495 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 24496 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 24497 //PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4 24498 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 24499 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 24500 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 24501 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 24502 //PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0 24503 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 24504 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 24505 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 24506 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 24507 //PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1 24508 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 24509 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 24510 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 24511 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 24512 24513 24514 // addressBlock: mmhub_l1tlb_vml1dec 24515 //VML1_0_MC_VM_MX_L1_TLB0_STATUS 24516 #define VML1_0_MC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT 0x0 24517 #define VML1_0_MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 24518 #define VML1_0_MC_VM_MX_L1_TLB0_STATUS__BUSY_MASK 0x00000001L 24519 #define VML1_0_MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 24520 //VML1_0_MC_VM_MX_L1_TLB1_STATUS 24521 #define VML1_0_MC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT 0x0 24522 #define VML1_0_MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 24523 #define VML1_0_MC_VM_MX_L1_TLB1_STATUS__BUSY_MASK 0x00000001L 24524 #define VML1_0_MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 24525 //VML1_0_MC_VM_MX_L1_TLB2_STATUS 24526 #define VML1_0_MC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT 0x0 24527 #define VML1_0_MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 24528 #define VML1_0_MC_VM_MX_L1_TLB2_STATUS__BUSY_MASK 0x00000001L 24529 #define VML1_0_MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 24530 //VML1_0_MC_VM_MX_L1_TLB3_STATUS 24531 #define VML1_0_MC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT 0x0 24532 #define VML1_0_MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 24533 #define VML1_0_MC_VM_MX_L1_TLB3_STATUS__BUSY_MASK 0x00000001L 24534 #define VML1_0_MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 24535 //VML1_0_MC_VM_MX_L1_TLB4_STATUS 24536 #define VML1_0_MC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT 0x0 24537 #define VML1_0_MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 24538 #define VML1_0_MC_VM_MX_L1_TLB4_STATUS__BUSY_MASK 0x00000001L 24539 #define VML1_0_MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 24540 //VML1_0_MC_VM_MX_L1_TLB5_STATUS 24541 #define VML1_0_MC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT 0x0 24542 #define VML1_0_MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 24543 #define VML1_0_MC_VM_MX_L1_TLB5_STATUS__BUSY_MASK 0x00000001L 24544 #define VML1_0_MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 24545 //VML1_0_MC_VM_MX_L1_TLB6_STATUS 24546 #define VML1_0_MC_VM_MX_L1_TLB6_STATUS__BUSY__SHIFT 0x0 24547 #define VML1_0_MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 24548 #define VML1_0_MC_VM_MX_L1_TLB6_STATUS__BUSY_MASK 0x00000001L 24549 #define VML1_0_MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 24550 //VML1_0_MC_VM_MX_L1_TLB7_STATUS 24551 #define VML1_0_MC_VM_MX_L1_TLB7_STATUS__BUSY__SHIFT 0x0 24552 #define VML1_0_MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 24553 #define VML1_0_MC_VM_MX_L1_TLB7_STATUS__BUSY_MASK 0x00000001L 24554 #define VML1_0_MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 24555 24556 24557 // addressBlock: mmhub_l1tlb_vml1pldec 24558 //VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG 24559 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 24560 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 24561 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 24562 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 24563 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 24564 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 24565 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 24566 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 24567 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 24568 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 24569 //VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG 24570 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 24571 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 24572 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 24573 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 24574 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 24575 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 24576 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 24577 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 24578 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 24579 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 24580 //VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG 24581 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 24582 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 24583 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 24584 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 24585 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 24586 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 24587 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 24588 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 24589 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 24590 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 24591 //VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG 24592 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 24593 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 24594 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 24595 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 24596 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 24597 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 24598 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 24599 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 24600 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 24601 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 24602 //VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 24603 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 24604 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 24605 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 24606 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 24607 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 24608 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 24609 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 24610 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 24611 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 24612 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 24613 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 24614 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 24615 24616 24617 // addressBlock: mmhub_l1tlb_vml1prdec 24618 //VML1PR0_MC_VM_MX_L1_PERFCOUNTER_LO 24619 #define VML1PR0_MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 24620 #define VML1PR0_MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 24621 //VML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI 24622 #define VML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 24623 #define VML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 24624 #define VML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 24625 #define VML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 24626 24627 24628 // addressBlock: mmhub_utcl2_atcl2dec 24629 //ATCL2_0_ATC_L2_CNTL 24630 #define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 24631 #define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3 24632 #define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6 24633 #define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7 24634 #define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS__SHIFT 0x8 24635 #define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS__SHIFT 0xb 24636 #define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0xe 24637 #define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0xf 24638 #define ATCL2_0_ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x10 24639 #define ATCL2_0_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0x13 24640 #define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L 24641 #define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L 24642 #define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L 24643 #define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L 24644 #define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS_MASK 0x00000300L 24645 #define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS_MASK 0x00001800L 24646 #define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00004000L 24647 #define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00008000L 24648 #define ATCL2_0_ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00070000L 24649 #define ATCL2_0_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00080000L 24650 //ATCL2_0_ATC_L2_CNTL2 24651 #define ATCL2_0_ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 24652 #define ATCL2_0_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6 24653 #define ATCL2_0_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8 24654 #define ATCL2_0_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9 24655 #define ATCL2_0_ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc 24656 #define ATCL2_0_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf 24657 #define ATCL2_0_ATC_L2_CNTL2__L2_BIGK_FRAGMENT_SIZE__SHIFT 0x15 24658 #define ATCL2_0_ATC_L2_CNTL2__L2_4K_BIGK_SWAP_ENABLE__SHIFT 0x1b 24659 #define ATCL2_0_ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL 24660 #define ATCL2_0_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L 24661 #define ATCL2_0_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000100L 24662 #define ATCL2_0_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00000E00L 24663 #define ATCL2_0_ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00007000L 24664 #define ATCL2_0_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x001F8000L 24665 #define ATCL2_0_ATC_L2_CNTL2__L2_BIGK_FRAGMENT_SIZE_MASK 0x07E00000L 24666 #define ATCL2_0_ATC_L2_CNTL2__L2_4K_BIGK_SWAP_ENABLE_MASK 0x08000000L 24667 //ATCL2_0_ATC_L2_CACHE_DATA0 24668 #define ATCL2_0_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 24669 #define ATCL2_0_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 24670 #define ATCL2_0_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 24671 #define ATCL2_0_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x17 24672 #define ATCL2_0_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L 24673 #define ATCL2_0_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L 24674 #define ATCL2_0_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x007FFFFCL 24675 #define ATCL2_0_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x07800000L 24676 //ATCL2_0_ATC_L2_CACHE_DATA1 24677 #define ATCL2_0_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 24678 #define ATCL2_0_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL 24679 //ATCL2_0_ATC_L2_CACHE_DATA2 24680 #define ATCL2_0_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 24681 #define ATCL2_0_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL 24682 //ATCL2_0_ATC_L2_CNTL3 24683 #define ATCL2_0_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x0 24684 #define ATCL2_0_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x3 24685 #define ATCL2_0_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT 0x9 24686 #define ATCL2_0_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x00000007L 24687 #define ATCL2_0_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x000001F8L 24688 #define ATCL2_0_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK 0x00000E00L 24689 //ATCL2_0_ATC_L2_STATUS 24690 #define ATCL2_0_ATC_L2_STATUS__BUSY__SHIFT 0x0 24691 #define ATCL2_0_ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1 24692 #define ATCL2_0_ATC_L2_STATUS__BUSY_MASK 0x00000001L 24693 #define ATCL2_0_ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x7FFFFFFEL 24694 //ATCL2_0_ATC_L2_STATUS2 24695 #define ATCL2_0_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x0 24696 #define ATCL2_0_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x8 24697 #define ATCL2_0_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000FFL 24698 #define ATCL2_0_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000FF00L 24699 //ATCL2_0_ATC_L2_STATUS3 24700 #define ATCL2_0_ATC_L2_STATUS3__BUSY__SHIFT 0x0 24701 #define ATCL2_0_ATC_L2_STATUS3__PARITY_ERROR_INFO__SHIFT 0x1 24702 #define ATCL2_0_ATC_L2_STATUS3__BUSY_MASK 0x00000001L 24703 #define ATCL2_0_ATC_L2_STATUS3__PARITY_ERROR_INFO_MASK 0x7FFFFFFEL 24704 //ATCL2_0_ATC_L2_MISC_CG 24705 #define ATCL2_0_ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6 24706 #define ATCL2_0_ATC_L2_MISC_CG__ENABLE__SHIFT 0x12 24707 #define ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 24708 #define ATCL2_0_ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L 24709 #define ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L 24710 #define ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L 24711 //ATCL2_0_ATC_L2_MEM_POWER_LS 24712 #define ATCL2_0_ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 24713 #define ATCL2_0_ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 24714 #define ATCL2_0_ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL 24715 #define ATCL2_0_ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L 24716 //ATCL2_0_ATC_L2_CGTT_CLK_CTRL 24717 #define ATCL2_0_ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 24718 #define ATCL2_0_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 24719 #define ATCL2_0_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf 24720 #define ATCL2_0_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 24721 #define ATCL2_0_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 24722 #define ATCL2_0_ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 24723 #define ATCL2_0_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 24724 #define ATCL2_0_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L 24725 #define ATCL2_0_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L 24726 #define ATCL2_0_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L 24727 //ATCL2_0_ATC_L2_CACHE_4K_DSM_INDEX 24728 #define ATCL2_0_ATC_L2_CACHE_4K_DSM_INDEX__INDEX__SHIFT 0x0 24729 #define ATCL2_0_ATC_L2_CACHE_4K_DSM_INDEX__INDEX_MASK 0x000000FFL 24730 //ATCL2_0_ATC_L2_CACHE_2M_DSM_INDEX 24731 #define ATCL2_0_ATC_L2_CACHE_2M_DSM_INDEX__INDEX__SHIFT 0x0 24732 #define ATCL2_0_ATC_L2_CACHE_2M_DSM_INDEX__INDEX_MASK 0x000000FFL 24733 //ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL 24734 #define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY__SHIFT 0x0 24735 #define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 24736 #define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 24737 #define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 24738 #define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb 24739 #define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS__SHIFT 0xc 24740 #define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT__SHIFT 0xd 24741 #define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT__SHIFT 0xf 24742 #define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE__SHIFT 0x11 24743 #define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY_MASK 0x0000003FL 24744 #define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L 24745 #define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L 24746 #define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L 24747 #define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L 24748 #define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS_MASK 0x00001000L 24749 #define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT_MASK 0x00006000L 24750 #define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT_MASK 0x00018000L 24751 #define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE_MASK 0x00020000L 24752 //ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL 24753 #define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY__SHIFT 0x0 24754 #define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 24755 #define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 24756 #define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 24757 #define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb 24758 #define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS__SHIFT 0xc 24759 #define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT__SHIFT 0xd 24760 #define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT__SHIFT 0xf 24761 #define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE__SHIFT 0x11 24762 #define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY_MASK 0x0000003FL 24763 #define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L 24764 #define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L 24765 #define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L 24766 #define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L 24767 #define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS_MASK 0x00001000L 24768 #define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT_MASK 0x00006000L 24769 #define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT_MASK 0x00018000L 24770 #define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE_MASK 0x00020000L 24771 //ATCL2_0_ATC_L2_CNTL4 24772 #define ATCL2_0_ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x0 24773 #define ATCL2_0_ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0xa 24774 #define ATCL2_0_ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000003FFL 24775 #define ATCL2_0_ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000FFC00L 24776 //ATCL2_0_ATC_L2_MM_GROUP_RT_CLASSES 24777 #define ATCL2_0_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS__SHIFT 0x0 24778 #define ATCL2_0_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS_MASK 0xFFFFFFFFL 24779 24780 24781 // addressBlock: mmhub_utcl2_vml2pfdec 24782 //VML2PF0_VM_L2_CNTL 24783 #define VML2PF0_VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 24784 #define VML2PF0_VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 24785 #define VML2PF0_VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 24786 #define VML2PF0_VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 24787 #define VML2PF0_VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 24788 #define VML2PF0_VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 24789 #define VML2PF0_VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa 24790 #define VML2PF0_VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb 24791 #define VML2PF0_VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc 24792 #define VML2PF0_VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf 24793 #define VML2PF0_VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 24794 #define VML2PF0_VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 24795 #define VML2PF0_VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 24796 #define VML2PF0_VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a 24797 #define VML2PF0_VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L 24798 #define VML2PF0_VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L 24799 #define VML2PF0_VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL 24800 #define VML2PF0_VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L 24801 #define VML2PF0_VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L 24802 #define VML2PF0_VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L 24803 #define VML2PF0_VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L 24804 #define VML2PF0_VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L 24805 #define VML2PF0_VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L 24806 #define VML2PF0_VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L 24807 #define VML2PF0_VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L 24808 #define VML2PF0_VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L 24809 #define VML2PF0_VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L 24810 #define VML2PF0_VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L 24811 //VML2PF0_VM_L2_CNTL2 24812 #define VML2PF0_VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 24813 #define VML2PF0_VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 24814 #define VML2PF0_VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 24815 #define VML2PF0_VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 24816 #define VML2PF0_VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 24817 #define VML2PF0_VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a 24818 #define VML2PF0_VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c 24819 #define VML2PF0_VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L 24820 #define VML2PF0_VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L 24821 #define VML2PF0_VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L 24822 #define VML2PF0_VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L 24823 #define VML2PF0_VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L 24824 #define VML2PF0_VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L 24825 #define VML2PF0_VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L 24826 //VML2PF0_VM_L2_CNTL3 24827 #define VML2PF0_VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 24828 #define VML2PF0_VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 24829 #define VML2PF0_VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 24830 #define VML2PF0_VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf 24831 #define VML2PF0_VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 24832 #define VML2PF0_VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 24833 #define VML2PF0_VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 24834 #define VML2PF0_VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c 24835 #define VML2PF0_VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d 24836 #define VML2PF0_VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e 24837 #define VML2PF0_VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f 24838 #define VML2PF0_VM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL 24839 #define VML2PF0_VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L 24840 #define VML2PF0_VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L 24841 #define VML2PF0_VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L 24842 #define VML2PF0_VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L 24843 #define VML2PF0_VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L 24844 #define VML2PF0_VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L 24845 #define VML2PF0_VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L 24846 #define VML2PF0_VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L 24847 #define VML2PF0_VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L 24848 #define VML2PF0_VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L 24849 //VML2PF0_VM_L2_STATUS 24850 #define VML2PF0_VM_L2_STATUS__L2_BUSY__SHIFT 0x0 24851 #define VML2PF0_VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 24852 #define VML2PF0_VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 24853 #define VML2PF0_VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 24854 #define VML2PF0_VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 24855 #define VML2PF0_VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 24856 #define VML2PF0_VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 24857 #define VML2PF0_VM_L2_STATUS__L2_BUSY_MASK 0x00000001L 24858 #define VML2PF0_VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL 24859 #define VML2PF0_VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L 24860 #define VML2PF0_VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L 24861 #define VML2PF0_VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L 24862 #define VML2PF0_VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L 24863 #define VML2PF0_VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L 24864 //VML2PF0_VM_DUMMY_PAGE_FAULT_CNTL 24865 #define VML2PF0_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 24866 #define VML2PF0_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 24867 #define VML2PF0_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 24868 #define VML2PF0_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L 24869 #define VML2PF0_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L 24870 #define VML2PF0_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL 24871 //VML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_LO32 24872 #define VML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 24873 #define VML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 24874 //VML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_HI32 24875 #define VML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0 24876 #define VML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL 24877 //VML2PF0_VM_L2_PROTECTION_FAULT_CNTL 24878 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 24879 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 24880 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 24881 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 24882 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 24883 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 24884 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 24885 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 24886 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 24887 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 24888 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 24889 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb 24890 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 24891 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd 24892 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d 24893 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e 24894 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f 24895 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L 24896 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L 24897 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L 24898 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L 24899 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L 24900 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L 24901 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L 24902 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L 24903 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L 24904 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L 24905 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 24906 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L 24907 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 24908 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L 24909 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L 24910 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L 24911 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L 24912 //VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2 24913 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 24914 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 24915 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 24916 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 24917 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 24918 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL 24919 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L 24920 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L 24921 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L 24922 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L 24923 //VML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL3 24924 #define VML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 24925 #define VML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL 24926 //VML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL4 24927 #define VML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 24928 #define VML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL 24929 //VML2PF0_VM_L2_PROTECTION_FAULT_STATUS 24930 #define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 24931 #define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1 24932 #define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4 24933 #define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8 24934 #define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9 24935 #define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12 24936 #define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13 24937 #define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14 24938 #define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18 24939 #define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19 24940 #define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L 24941 #define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL 24942 #define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L 24943 #define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L 24944 #define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L 24945 #define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L 24946 #define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L 24947 #define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L 24948 #define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L 24949 #define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L 24950 //VML2PF0_VM_L2_PROTECTION_FAULT_ADDR_LO32 24951 #define VML2PF0_VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 24952 #define VML2PF0_VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 24953 //VML2PF0_VM_L2_PROTECTION_FAULT_ADDR_HI32 24954 #define VML2PF0_VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 24955 #define VML2PF0_VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL 24956 //VML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 24957 #define VML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 24958 #define VML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 24959 //VML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 24960 #define VML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0 24961 #define VML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL 24962 //VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 24963 #define VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 24964 #define VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 24965 //VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 24966 #define VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 24967 #define VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 24968 //VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 24969 #define VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 24970 #define VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 24971 //VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 24972 #define VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 24973 #define VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 24974 //VML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 24975 #define VML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 24976 #define VML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL 24977 //VML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 24978 #define VML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0 24979 #define VML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL 24980 //VML2PF0_VM_L2_CNTL4 24981 #define VML2PF0_VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 24982 #define VML2PF0_VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 24983 #define VML2PF0_VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 24984 #define VML2PF0_VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 24985 #define VML2PF0_VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 24986 #define VML2PF0_VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c 24987 #define VML2PF0_VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL 24988 #define VML2PF0_VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L 24989 #define VML2PF0_VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L 24990 #define VML2PF0_VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L 24991 #define VML2PF0_VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L 24992 #define VML2PF0_VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L 24993 //VML2PF0_VM_L2_MM_GROUP_RT_CLASSES 24994 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 24995 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 24996 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 24997 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 24998 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 24999 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 25000 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 25001 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 25002 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 25003 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 25004 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa 25005 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb 25006 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc 25007 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd 25008 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe 25009 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf 25010 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 25011 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 25012 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 25013 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 25014 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 25015 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 25016 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 25017 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 25018 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 25019 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 25020 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a 25021 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b 25022 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c 25023 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d 25024 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e 25025 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f 25026 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L 25027 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L 25028 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L 25029 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L 25030 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L 25031 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L 25032 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L 25033 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L 25034 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L 25035 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L 25036 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L 25037 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L 25038 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L 25039 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L 25040 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L 25041 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L 25042 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L 25043 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L 25044 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L 25045 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L 25046 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L 25047 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L 25048 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L 25049 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L 25050 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L 25051 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L 25052 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L 25053 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L 25054 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L 25055 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L 25056 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L 25057 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L 25058 //VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID 25059 #define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 25060 #define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa 25061 #define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 25062 #define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 25063 #define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 25064 #define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL 25065 #define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L 25066 #define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L 25067 #define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L 25068 #define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L 25069 //VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2 25070 #define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 25071 #define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa 25072 #define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 25073 #define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 25074 #define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 25075 #define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL 25076 #define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L 25077 #define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L 25078 #define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L 25079 #define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L 25080 //VML2PF0_VM_L2_CACHE_PARITY_CNTL 25081 #define VML2PF0_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 25082 #define VML2PF0_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 25083 #define VML2PF0_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 25084 #define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 25085 #define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 25086 #define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 25087 #define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 25088 #define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 25089 #define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc 25090 #define VML2PF0_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L 25091 #define VML2PF0_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L 25092 #define VML2PF0_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L 25093 #define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L 25094 #define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L 25095 #define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L 25096 #define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L 25097 #define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L 25098 #define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L 25099 //VML2PF0_VM_L2_CGTT_CLK_CTRL 25100 #define VML2PF0_VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 25101 #define VML2PF0_VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 25102 #define VML2PF0_VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf 25103 #define VML2PF0_VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 25104 #define VML2PF0_VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 25105 #define VML2PF0_VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 25106 #define VML2PF0_VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 25107 #define VML2PF0_VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L 25108 #define VML2PF0_VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L 25109 #define VML2PF0_VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L 25110 25111 25112 // addressBlock: mmhub_utcl2_vml2vcdec 25113 //VML2VC0_VM_CONTEXT0_CNTL 25114 #define VML2VC0_VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 25115 #define VML2VC0_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 25116 #define VML2VC0_VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 25117 #define VML2VC0_VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 25118 #define VML2VC0_VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 25119 #define VML2VC0_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 25120 #define VML2VC0_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 25121 #define VML2VC0_VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 25122 #define VML2VC0_VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 25123 #define VML2VC0_VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 25124 #define VML2VC0_VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 25125 #define VML2VC0_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 25126 #define VML2VC0_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 25127 #define VML2VC0_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 25128 #define VML2VC0_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 25129 #define VML2VC0_VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 25130 #define VML2VC0_VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 25131 #define VML2VC0_VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 25132 #define VML2VC0_VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 25133 #define VML2VC0_VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 25134 #define VML2VC0_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 25135 #define VML2VC0_VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 25136 #define VML2VC0_VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 25137 #define VML2VC0_VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 25138 #define VML2VC0_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 25139 #define VML2VC0_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 25140 #define VML2VC0_VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 25141 #define VML2VC0_VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 25142 #define VML2VC0_VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 25143 #define VML2VC0_VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 25144 #define VML2VC0_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 25145 #define VML2VC0_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 25146 #define VML2VC0_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 25147 #define VML2VC0_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 25148 #define VML2VC0_VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 25149 #define VML2VC0_VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 25150 #define VML2VC0_VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 25151 #define VML2VC0_VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 25152 //VML2VC0_VM_CONTEXT1_CNTL 25153 #define VML2VC0_VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 25154 #define VML2VC0_VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 25155 #define VML2VC0_VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 25156 #define VML2VC0_VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 25157 #define VML2VC0_VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 25158 #define VML2VC0_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 25159 #define VML2VC0_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 25160 #define VML2VC0_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 25161 #define VML2VC0_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 25162 #define VML2VC0_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 25163 #define VML2VC0_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 25164 #define VML2VC0_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 25165 #define VML2VC0_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 25166 #define VML2VC0_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 25167 #define VML2VC0_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 25168 #define VML2VC0_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 25169 #define VML2VC0_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 25170 #define VML2VC0_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 25171 #define VML2VC0_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 25172 #define VML2VC0_VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 25173 #define VML2VC0_VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 25174 #define VML2VC0_VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 25175 #define VML2VC0_VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 25176 #define VML2VC0_VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 25177 #define VML2VC0_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 25178 #define VML2VC0_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 25179 #define VML2VC0_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 25180 #define VML2VC0_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 25181 #define VML2VC0_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 25182 #define VML2VC0_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 25183 #define VML2VC0_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 25184 #define VML2VC0_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 25185 #define VML2VC0_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 25186 #define VML2VC0_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 25187 #define VML2VC0_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 25188 #define VML2VC0_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 25189 #define VML2VC0_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 25190 #define VML2VC0_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 25191 //VML2VC0_VM_CONTEXT2_CNTL 25192 #define VML2VC0_VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 25193 #define VML2VC0_VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 25194 #define VML2VC0_VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 25195 #define VML2VC0_VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 25196 #define VML2VC0_VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 25197 #define VML2VC0_VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 25198 #define VML2VC0_VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 25199 #define VML2VC0_VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 25200 #define VML2VC0_VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 25201 #define VML2VC0_VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 25202 #define VML2VC0_VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 25203 #define VML2VC0_VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 25204 #define VML2VC0_VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 25205 #define VML2VC0_VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 25206 #define VML2VC0_VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 25207 #define VML2VC0_VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 25208 #define VML2VC0_VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 25209 #define VML2VC0_VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 25210 #define VML2VC0_VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 25211 #define VML2VC0_VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 25212 #define VML2VC0_VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 25213 #define VML2VC0_VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 25214 #define VML2VC0_VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 25215 #define VML2VC0_VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 25216 #define VML2VC0_VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 25217 #define VML2VC0_VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 25218 #define VML2VC0_VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 25219 #define VML2VC0_VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 25220 #define VML2VC0_VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 25221 #define VML2VC0_VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 25222 #define VML2VC0_VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 25223 #define VML2VC0_VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 25224 #define VML2VC0_VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 25225 #define VML2VC0_VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 25226 #define VML2VC0_VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 25227 #define VML2VC0_VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 25228 #define VML2VC0_VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 25229 #define VML2VC0_VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 25230 //VML2VC0_VM_CONTEXT3_CNTL 25231 #define VML2VC0_VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 25232 #define VML2VC0_VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 25233 #define VML2VC0_VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 25234 #define VML2VC0_VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 25235 #define VML2VC0_VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 25236 #define VML2VC0_VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 25237 #define VML2VC0_VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 25238 #define VML2VC0_VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 25239 #define VML2VC0_VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 25240 #define VML2VC0_VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 25241 #define VML2VC0_VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 25242 #define VML2VC0_VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 25243 #define VML2VC0_VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 25244 #define VML2VC0_VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 25245 #define VML2VC0_VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 25246 #define VML2VC0_VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 25247 #define VML2VC0_VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 25248 #define VML2VC0_VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 25249 #define VML2VC0_VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 25250 #define VML2VC0_VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 25251 #define VML2VC0_VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 25252 #define VML2VC0_VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 25253 #define VML2VC0_VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 25254 #define VML2VC0_VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 25255 #define VML2VC0_VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 25256 #define VML2VC0_VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 25257 #define VML2VC0_VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 25258 #define VML2VC0_VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 25259 #define VML2VC0_VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 25260 #define VML2VC0_VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 25261 #define VML2VC0_VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 25262 #define VML2VC0_VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 25263 #define VML2VC0_VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 25264 #define VML2VC0_VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 25265 #define VML2VC0_VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 25266 #define VML2VC0_VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 25267 #define VML2VC0_VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 25268 #define VML2VC0_VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 25269 //VML2VC0_VM_CONTEXT4_CNTL 25270 #define VML2VC0_VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 25271 #define VML2VC0_VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 25272 #define VML2VC0_VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 25273 #define VML2VC0_VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 25274 #define VML2VC0_VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 25275 #define VML2VC0_VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 25276 #define VML2VC0_VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 25277 #define VML2VC0_VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 25278 #define VML2VC0_VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 25279 #define VML2VC0_VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 25280 #define VML2VC0_VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 25281 #define VML2VC0_VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 25282 #define VML2VC0_VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 25283 #define VML2VC0_VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 25284 #define VML2VC0_VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 25285 #define VML2VC0_VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 25286 #define VML2VC0_VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 25287 #define VML2VC0_VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 25288 #define VML2VC0_VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 25289 #define VML2VC0_VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 25290 #define VML2VC0_VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 25291 #define VML2VC0_VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 25292 #define VML2VC0_VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 25293 #define VML2VC0_VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 25294 #define VML2VC0_VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 25295 #define VML2VC0_VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 25296 #define VML2VC0_VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 25297 #define VML2VC0_VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 25298 #define VML2VC0_VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 25299 #define VML2VC0_VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 25300 #define VML2VC0_VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 25301 #define VML2VC0_VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 25302 #define VML2VC0_VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 25303 #define VML2VC0_VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 25304 #define VML2VC0_VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 25305 #define VML2VC0_VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 25306 #define VML2VC0_VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 25307 #define VML2VC0_VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 25308 //VML2VC0_VM_CONTEXT5_CNTL 25309 #define VML2VC0_VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 25310 #define VML2VC0_VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 25311 #define VML2VC0_VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 25312 #define VML2VC0_VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 25313 #define VML2VC0_VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 25314 #define VML2VC0_VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 25315 #define VML2VC0_VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 25316 #define VML2VC0_VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 25317 #define VML2VC0_VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 25318 #define VML2VC0_VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 25319 #define VML2VC0_VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 25320 #define VML2VC0_VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 25321 #define VML2VC0_VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 25322 #define VML2VC0_VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 25323 #define VML2VC0_VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 25324 #define VML2VC0_VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 25325 #define VML2VC0_VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 25326 #define VML2VC0_VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 25327 #define VML2VC0_VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 25328 #define VML2VC0_VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 25329 #define VML2VC0_VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 25330 #define VML2VC0_VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 25331 #define VML2VC0_VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 25332 #define VML2VC0_VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 25333 #define VML2VC0_VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 25334 #define VML2VC0_VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 25335 #define VML2VC0_VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 25336 #define VML2VC0_VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 25337 #define VML2VC0_VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 25338 #define VML2VC0_VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 25339 #define VML2VC0_VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 25340 #define VML2VC0_VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 25341 #define VML2VC0_VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 25342 #define VML2VC0_VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 25343 #define VML2VC0_VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 25344 #define VML2VC0_VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 25345 #define VML2VC0_VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 25346 #define VML2VC0_VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 25347 //VML2VC0_VM_CONTEXT6_CNTL 25348 #define VML2VC0_VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 25349 #define VML2VC0_VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 25350 #define VML2VC0_VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 25351 #define VML2VC0_VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 25352 #define VML2VC0_VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 25353 #define VML2VC0_VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 25354 #define VML2VC0_VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 25355 #define VML2VC0_VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 25356 #define VML2VC0_VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 25357 #define VML2VC0_VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 25358 #define VML2VC0_VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 25359 #define VML2VC0_VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 25360 #define VML2VC0_VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 25361 #define VML2VC0_VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 25362 #define VML2VC0_VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 25363 #define VML2VC0_VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 25364 #define VML2VC0_VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 25365 #define VML2VC0_VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 25366 #define VML2VC0_VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 25367 #define VML2VC0_VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 25368 #define VML2VC0_VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 25369 #define VML2VC0_VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 25370 #define VML2VC0_VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 25371 #define VML2VC0_VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 25372 #define VML2VC0_VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 25373 #define VML2VC0_VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 25374 #define VML2VC0_VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 25375 #define VML2VC0_VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 25376 #define VML2VC0_VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 25377 #define VML2VC0_VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 25378 #define VML2VC0_VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 25379 #define VML2VC0_VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 25380 #define VML2VC0_VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 25381 #define VML2VC0_VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 25382 #define VML2VC0_VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 25383 #define VML2VC0_VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 25384 #define VML2VC0_VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 25385 #define VML2VC0_VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 25386 //VML2VC0_VM_CONTEXT7_CNTL 25387 #define VML2VC0_VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 25388 #define VML2VC0_VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 25389 #define VML2VC0_VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 25390 #define VML2VC0_VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 25391 #define VML2VC0_VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 25392 #define VML2VC0_VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 25393 #define VML2VC0_VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 25394 #define VML2VC0_VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 25395 #define VML2VC0_VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 25396 #define VML2VC0_VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 25397 #define VML2VC0_VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 25398 #define VML2VC0_VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 25399 #define VML2VC0_VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 25400 #define VML2VC0_VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 25401 #define VML2VC0_VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 25402 #define VML2VC0_VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 25403 #define VML2VC0_VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 25404 #define VML2VC0_VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 25405 #define VML2VC0_VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 25406 #define VML2VC0_VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 25407 #define VML2VC0_VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 25408 #define VML2VC0_VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 25409 #define VML2VC0_VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 25410 #define VML2VC0_VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 25411 #define VML2VC0_VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 25412 #define VML2VC0_VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 25413 #define VML2VC0_VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 25414 #define VML2VC0_VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 25415 #define VML2VC0_VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 25416 #define VML2VC0_VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 25417 #define VML2VC0_VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 25418 #define VML2VC0_VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 25419 #define VML2VC0_VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 25420 #define VML2VC0_VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 25421 #define VML2VC0_VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 25422 #define VML2VC0_VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 25423 #define VML2VC0_VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 25424 #define VML2VC0_VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 25425 //VML2VC0_VM_CONTEXT8_CNTL 25426 #define VML2VC0_VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 25427 #define VML2VC0_VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 25428 #define VML2VC0_VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 25429 #define VML2VC0_VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 25430 #define VML2VC0_VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 25431 #define VML2VC0_VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 25432 #define VML2VC0_VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 25433 #define VML2VC0_VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 25434 #define VML2VC0_VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 25435 #define VML2VC0_VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 25436 #define VML2VC0_VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 25437 #define VML2VC0_VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 25438 #define VML2VC0_VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 25439 #define VML2VC0_VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 25440 #define VML2VC0_VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 25441 #define VML2VC0_VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 25442 #define VML2VC0_VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 25443 #define VML2VC0_VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 25444 #define VML2VC0_VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 25445 #define VML2VC0_VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 25446 #define VML2VC0_VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 25447 #define VML2VC0_VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 25448 #define VML2VC0_VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 25449 #define VML2VC0_VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 25450 #define VML2VC0_VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 25451 #define VML2VC0_VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 25452 #define VML2VC0_VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 25453 #define VML2VC0_VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 25454 #define VML2VC0_VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 25455 #define VML2VC0_VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 25456 #define VML2VC0_VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 25457 #define VML2VC0_VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 25458 #define VML2VC0_VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 25459 #define VML2VC0_VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 25460 #define VML2VC0_VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 25461 #define VML2VC0_VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 25462 #define VML2VC0_VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 25463 #define VML2VC0_VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 25464 //VML2VC0_VM_CONTEXT9_CNTL 25465 #define VML2VC0_VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 25466 #define VML2VC0_VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 25467 #define VML2VC0_VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 25468 #define VML2VC0_VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 25469 #define VML2VC0_VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 25470 #define VML2VC0_VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 25471 #define VML2VC0_VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 25472 #define VML2VC0_VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 25473 #define VML2VC0_VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 25474 #define VML2VC0_VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 25475 #define VML2VC0_VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 25476 #define VML2VC0_VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 25477 #define VML2VC0_VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 25478 #define VML2VC0_VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 25479 #define VML2VC0_VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 25480 #define VML2VC0_VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 25481 #define VML2VC0_VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 25482 #define VML2VC0_VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 25483 #define VML2VC0_VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 25484 #define VML2VC0_VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 25485 #define VML2VC0_VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 25486 #define VML2VC0_VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 25487 #define VML2VC0_VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 25488 #define VML2VC0_VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 25489 #define VML2VC0_VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 25490 #define VML2VC0_VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 25491 #define VML2VC0_VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 25492 #define VML2VC0_VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 25493 #define VML2VC0_VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 25494 #define VML2VC0_VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 25495 #define VML2VC0_VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 25496 #define VML2VC0_VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 25497 #define VML2VC0_VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 25498 #define VML2VC0_VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 25499 #define VML2VC0_VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 25500 #define VML2VC0_VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 25501 #define VML2VC0_VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 25502 #define VML2VC0_VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 25503 //VML2VC0_VM_CONTEXT10_CNTL 25504 #define VML2VC0_VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 25505 #define VML2VC0_VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 25506 #define VML2VC0_VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 25507 #define VML2VC0_VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 25508 #define VML2VC0_VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 25509 #define VML2VC0_VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 25510 #define VML2VC0_VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 25511 #define VML2VC0_VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 25512 #define VML2VC0_VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 25513 #define VML2VC0_VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 25514 #define VML2VC0_VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 25515 #define VML2VC0_VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 25516 #define VML2VC0_VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 25517 #define VML2VC0_VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 25518 #define VML2VC0_VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 25519 #define VML2VC0_VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 25520 #define VML2VC0_VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 25521 #define VML2VC0_VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 25522 #define VML2VC0_VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 25523 #define VML2VC0_VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 25524 #define VML2VC0_VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 25525 #define VML2VC0_VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 25526 #define VML2VC0_VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 25527 #define VML2VC0_VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 25528 #define VML2VC0_VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 25529 #define VML2VC0_VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 25530 #define VML2VC0_VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 25531 #define VML2VC0_VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 25532 #define VML2VC0_VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 25533 #define VML2VC0_VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 25534 #define VML2VC0_VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 25535 #define VML2VC0_VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 25536 #define VML2VC0_VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 25537 #define VML2VC0_VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 25538 #define VML2VC0_VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 25539 #define VML2VC0_VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 25540 #define VML2VC0_VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 25541 #define VML2VC0_VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 25542 //VML2VC0_VM_CONTEXT11_CNTL 25543 #define VML2VC0_VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 25544 #define VML2VC0_VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 25545 #define VML2VC0_VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 25546 #define VML2VC0_VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 25547 #define VML2VC0_VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 25548 #define VML2VC0_VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 25549 #define VML2VC0_VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 25550 #define VML2VC0_VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 25551 #define VML2VC0_VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 25552 #define VML2VC0_VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 25553 #define VML2VC0_VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 25554 #define VML2VC0_VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 25555 #define VML2VC0_VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 25556 #define VML2VC0_VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 25557 #define VML2VC0_VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 25558 #define VML2VC0_VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 25559 #define VML2VC0_VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 25560 #define VML2VC0_VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 25561 #define VML2VC0_VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 25562 #define VML2VC0_VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 25563 #define VML2VC0_VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 25564 #define VML2VC0_VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 25565 #define VML2VC0_VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 25566 #define VML2VC0_VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 25567 #define VML2VC0_VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 25568 #define VML2VC0_VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 25569 #define VML2VC0_VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 25570 #define VML2VC0_VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 25571 #define VML2VC0_VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 25572 #define VML2VC0_VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 25573 #define VML2VC0_VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 25574 #define VML2VC0_VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 25575 #define VML2VC0_VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 25576 #define VML2VC0_VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 25577 #define VML2VC0_VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 25578 #define VML2VC0_VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 25579 #define VML2VC0_VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 25580 #define VML2VC0_VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 25581 //VML2VC0_VM_CONTEXT12_CNTL 25582 #define VML2VC0_VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 25583 #define VML2VC0_VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 25584 #define VML2VC0_VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 25585 #define VML2VC0_VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 25586 #define VML2VC0_VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 25587 #define VML2VC0_VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 25588 #define VML2VC0_VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 25589 #define VML2VC0_VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 25590 #define VML2VC0_VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 25591 #define VML2VC0_VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 25592 #define VML2VC0_VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 25593 #define VML2VC0_VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 25594 #define VML2VC0_VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 25595 #define VML2VC0_VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 25596 #define VML2VC0_VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 25597 #define VML2VC0_VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 25598 #define VML2VC0_VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 25599 #define VML2VC0_VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 25600 #define VML2VC0_VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 25601 #define VML2VC0_VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 25602 #define VML2VC0_VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 25603 #define VML2VC0_VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 25604 #define VML2VC0_VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 25605 #define VML2VC0_VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 25606 #define VML2VC0_VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 25607 #define VML2VC0_VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 25608 #define VML2VC0_VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 25609 #define VML2VC0_VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 25610 #define VML2VC0_VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 25611 #define VML2VC0_VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 25612 #define VML2VC0_VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 25613 #define VML2VC0_VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 25614 #define VML2VC0_VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 25615 #define VML2VC0_VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 25616 #define VML2VC0_VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 25617 #define VML2VC0_VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 25618 #define VML2VC0_VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 25619 #define VML2VC0_VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 25620 //VML2VC0_VM_CONTEXT13_CNTL 25621 #define VML2VC0_VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 25622 #define VML2VC0_VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 25623 #define VML2VC0_VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 25624 #define VML2VC0_VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 25625 #define VML2VC0_VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 25626 #define VML2VC0_VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 25627 #define VML2VC0_VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 25628 #define VML2VC0_VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 25629 #define VML2VC0_VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 25630 #define VML2VC0_VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 25631 #define VML2VC0_VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 25632 #define VML2VC0_VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 25633 #define VML2VC0_VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 25634 #define VML2VC0_VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 25635 #define VML2VC0_VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 25636 #define VML2VC0_VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 25637 #define VML2VC0_VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 25638 #define VML2VC0_VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 25639 #define VML2VC0_VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 25640 #define VML2VC0_VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 25641 #define VML2VC0_VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 25642 #define VML2VC0_VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 25643 #define VML2VC0_VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 25644 #define VML2VC0_VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 25645 #define VML2VC0_VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 25646 #define VML2VC0_VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 25647 #define VML2VC0_VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 25648 #define VML2VC0_VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 25649 #define VML2VC0_VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 25650 #define VML2VC0_VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 25651 #define VML2VC0_VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 25652 #define VML2VC0_VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 25653 #define VML2VC0_VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 25654 #define VML2VC0_VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 25655 #define VML2VC0_VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 25656 #define VML2VC0_VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 25657 #define VML2VC0_VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 25658 #define VML2VC0_VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 25659 //VML2VC0_VM_CONTEXT14_CNTL 25660 #define VML2VC0_VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 25661 #define VML2VC0_VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 25662 #define VML2VC0_VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 25663 #define VML2VC0_VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 25664 #define VML2VC0_VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 25665 #define VML2VC0_VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 25666 #define VML2VC0_VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 25667 #define VML2VC0_VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 25668 #define VML2VC0_VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 25669 #define VML2VC0_VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 25670 #define VML2VC0_VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 25671 #define VML2VC0_VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 25672 #define VML2VC0_VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 25673 #define VML2VC0_VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 25674 #define VML2VC0_VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 25675 #define VML2VC0_VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 25676 #define VML2VC0_VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 25677 #define VML2VC0_VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 25678 #define VML2VC0_VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 25679 #define VML2VC0_VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 25680 #define VML2VC0_VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 25681 #define VML2VC0_VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 25682 #define VML2VC0_VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 25683 #define VML2VC0_VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 25684 #define VML2VC0_VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 25685 #define VML2VC0_VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 25686 #define VML2VC0_VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 25687 #define VML2VC0_VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 25688 #define VML2VC0_VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 25689 #define VML2VC0_VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 25690 #define VML2VC0_VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 25691 #define VML2VC0_VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 25692 #define VML2VC0_VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 25693 #define VML2VC0_VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 25694 #define VML2VC0_VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 25695 #define VML2VC0_VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 25696 #define VML2VC0_VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 25697 #define VML2VC0_VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 25698 //VML2VC0_VM_CONTEXT15_CNTL 25699 #define VML2VC0_VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 25700 #define VML2VC0_VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 25701 #define VML2VC0_VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 25702 #define VML2VC0_VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 25703 #define VML2VC0_VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 25704 #define VML2VC0_VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 25705 #define VML2VC0_VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 25706 #define VML2VC0_VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 25707 #define VML2VC0_VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 25708 #define VML2VC0_VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 25709 #define VML2VC0_VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 25710 #define VML2VC0_VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 25711 #define VML2VC0_VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 25712 #define VML2VC0_VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 25713 #define VML2VC0_VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 25714 #define VML2VC0_VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 25715 #define VML2VC0_VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 25716 #define VML2VC0_VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 25717 #define VML2VC0_VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 25718 #define VML2VC0_VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 25719 #define VML2VC0_VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 25720 #define VML2VC0_VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 25721 #define VML2VC0_VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 25722 #define VML2VC0_VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 25723 #define VML2VC0_VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 25724 #define VML2VC0_VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 25725 #define VML2VC0_VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 25726 #define VML2VC0_VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 25727 #define VML2VC0_VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 25728 #define VML2VC0_VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 25729 #define VML2VC0_VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 25730 #define VML2VC0_VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 25731 #define VML2VC0_VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 25732 #define VML2VC0_VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 25733 #define VML2VC0_VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 25734 #define VML2VC0_VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 25735 #define VML2VC0_VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 25736 #define VML2VC0_VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 25737 //VML2VC0_VM_CONTEXTS_DISABLE 25738 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 25739 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 25740 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 25741 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 25742 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 25743 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 25744 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 25745 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 25746 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 25747 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 25748 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa 25749 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb 25750 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc 25751 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd 25752 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe 25753 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf 25754 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L 25755 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L 25756 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L 25757 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L 25758 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L 25759 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L 25760 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L 25761 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L 25762 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L 25763 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L 25764 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L 25765 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L 25766 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L 25767 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L 25768 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L 25769 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L 25770 //VML2VC0_VM_INVALIDATE_ENG0_SEM 25771 #define VML2VC0_VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 25772 #define VML2VC0_VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L 25773 //VML2VC0_VM_INVALIDATE_ENG1_SEM 25774 #define VML2VC0_VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 25775 #define VML2VC0_VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L 25776 //VML2VC0_VM_INVALIDATE_ENG2_SEM 25777 #define VML2VC0_VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 25778 #define VML2VC0_VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L 25779 //VML2VC0_VM_INVALIDATE_ENG3_SEM 25780 #define VML2VC0_VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 25781 #define VML2VC0_VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L 25782 //VML2VC0_VM_INVALIDATE_ENG4_SEM 25783 #define VML2VC0_VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 25784 #define VML2VC0_VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L 25785 //VML2VC0_VM_INVALIDATE_ENG5_SEM 25786 #define VML2VC0_VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 25787 #define VML2VC0_VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L 25788 //VML2VC0_VM_INVALIDATE_ENG6_SEM 25789 #define VML2VC0_VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 25790 #define VML2VC0_VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L 25791 //VML2VC0_VM_INVALIDATE_ENG7_SEM 25792 #define VML2VC0_VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 25793 #define VML2VC0_VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L 25794 //VML2VC0_VM_INVALIDATE_ENG8_SEM 25795 #define VML2VC0_VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 25796 #define VML2VC0_VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L 25797 //VML2VC0_VM_INVALIDATE_ENG9_SEM 25798 #define VML2VC0_VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 25799 #define VML2VC0_VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L 25800 //VML2VC0_VM_INVALIDATE_ENG10_SEM 25801 #define VML2VC0_VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 25802 #define VML2VC0_VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L 25803 //VML2VC0_VM_INVALIDATE_ENG11_SEM 25804 #define VML2VC0_VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 25805 #define VML2VC0_VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L 25806 //VML2VC0_VM_INVALIDATE_ENG12_SEM 25807 #define VML2VC0_VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 25808 #define VML2VC0_VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L 25809 //VML2VC0_VM_INVALIDATE_ENG13_SEM 25810 #define VML2VC0_VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 25811 #define VML2VC0_VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L 25812 //VML2VC0_VM_INVALIDATE_ENG14_SEM 25813 #define VML2VC0_VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 25814 #define VML2VC0_VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L 25815 //VML2VC0_VM_INVALIDATE_ENG15_SEM 25816 #define VML2VC0_VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 25817 #define VML2VC0_VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L 25818 //VML2VC0_VM_INVALIDATE_ENG16_SEM 25819 #define VML2VC0_VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 25820 #define VML2VC0_VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L 25821 //VML2VC0_VM_INVALIDATE_ENG17_SEM 25822 #define VML2VC0_VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 25823 #define VML2VC0_VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L 25824 //VML2VC0_VM_INVALIDATE_ENG0_REQ 25825 #define VML2VC0_VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 25826 #define VML2VC0_VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 25827 #define VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 25828 #define VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 25829 #define VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 25830 #define VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 25831 #define VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 25832 #define VML2VC0_VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 25833 #define VML2VC0_VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 25834 #define VML2VC0_VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00030000L 25835 #define VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 25836 #define VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 25837 #define VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 25838 #define VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 25839 #define VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 25840 #define VML2VC0_VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 25841 //VML2VC0_VM_INVALIDATE_ENG1_REQ 25842 #define VML2VC0_VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 25843 #define VML2VC0_VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 25844 #define VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 25845 #define VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 25846 #define VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 25847 #define VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 25848 #define VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 25849 #define VML2VC0_VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 25850 #define VML2VC0_VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 25851 #define VML2VC0_VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00030000L 25852 #define VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 25853 #define VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 25854 #define VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 25855 #define VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 25856 #define VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 25857 #define VML2VC0_VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 25858 //VML2VC0_VM_INVALIDATE_ENG2_REQ 25859 #define VML2VC0_VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 25860 #define VML2VC0_VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 25861 #define VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 25862 #define VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 25863 #define VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 25864 #define VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 25865 #define VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 25866 #define VML2VC0_VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 25867 #define VML2VC0_VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 25868 #define VML2VC0_VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00030000L 25869 #define VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 25870 #define VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 25871 #define VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 25872 #define VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 25873 #define VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 25874 #define VML2VC0_VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 25875 //VML2VC0_VM_INVALIDATE_ENG3_REQ 25876 #define VML2VC0_VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 25877 #define VML2VC0_VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 25878 #define VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 25879 #define VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 25880 #define VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 25881 #define VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 25882 #define VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 25883 #define VML2VC0_VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 25884 #define VML2VC0_VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 25885 #define VML2VC0_VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00030000L 25886 #define VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 25887 #define VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 25888 #define VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 25889 #define VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 25890 #define VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 25891 #define VML2VC0_VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 25892 //VML2VC0_VM_INVALIDATE_ENG4_REQ 25893 #define VML2VC0_VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 25894 #define VML2VC0_VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 25895 #define VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 25896 #define VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 25897 #define VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 25898 #define VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 25899 #define VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 25900 #define VML2VC0_VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 25901 #define VML2VC0_VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 25902 #define VML2VC0_VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00030000L 25903 #define VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 25904 #define VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 25905 #define VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 25906 #define VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 25907 #define VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 25908 #define VML2VC0_VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 25909 //VML2VC0_VM_INVALIDATE_ENG5_REQ 25910 #define VML2VC0_VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 25911 #define VML2VC0_VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 25912 #define VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 25913 #define VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 25914 #define VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 25915 #define VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 25916 #define VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 25917 #define VML2VC0_VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 25918 #define VML2VC0_VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 25919 #define VML2VC0_VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00030000L 25920 #define VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 25921 #define VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 25922 #define VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 25923 #define VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 25924 #define VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 25925 #define VML2VC0_VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 25926 //VML2VC0_VM_INVALIDATE_ENG6_REQ 25927 #define VML2VC0_VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 25928 #define VML2VC0_VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 25929 #define VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 25930 #define VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 25931 #define VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 25932 #define VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 25933 #define VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 25934 #define VML2VC0_VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 25935 #define VML2VC0_VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 25936 #define VML2VC0_VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00030000L 25937 #define VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 25938 #define VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 25939 #define VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 25940 #define VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 25941 #define VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 25942 #define VML2VC0_VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 25943 //VML2VC0_VM_INVALIDATE_ENG7_REQ 25944 #define VML2VC0_VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 25945 #define VML2VC0_VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 25946 #define VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 25947 #define VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 25948 #define VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 25949 #define VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 25950 #define VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 25951 #define VML2VC0_VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 25952 #define VML2VC0_VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 25953 #define VML2VC0_VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00030000L 25954 #define VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 25955 #define VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 25956 #define VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 25957 #define VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 25958 #define VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 25959 #define VML2VC0_VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 25960 //VML2VC0_VM_INVALIDATE_ENG8_REQ 25961 #define VML2VC0_VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 25962 #define VML2VC0_VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 25963 #define VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 25964 #define VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 25965 #define VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 25966 #define VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 25967 #define VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 25968 #define VML2VC0_VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 25969 #define VML2VC0_VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 25970 #define VML2VC0_VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00030000L 25971 #define VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 25972 #define VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 25973 #define VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 25974 #define VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 25975 #define VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 25976 #define VML2VC0_VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 25977 //VML2VC0_VM_INVALIDATE_ENG9_REQ 25978 #define VML2VC0_VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 25979 #define VML2VC0_VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 25980 #define VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 25981 #define VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 25982 #define VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 25983 #define VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 25984 #define VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 25985 #define VML2VC0_VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 25986 #define VML2VC0_VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 25987 #define VML2VC0_VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00030000L 25988 #define VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 25989 #define VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 25990 #define VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 25991 #define VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 25992 #define VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 25993 #define VML2VC0_VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 25994 //VML2VC0_VM_INVALIDATE_ENG10_REQ 25995 #define VML2VC0_VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 25996 #define VML2VC0_VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 25997 #define VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 25998 #define VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 25999 #define VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 26000 #define VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 26001 #define VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 26002 #define VML2VC0_VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 26003 #define VML2VC0_VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 26004 #define VML2VC0_VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00030000L 26005 #define VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 26006 #define VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 26007 #define VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 26008 #define VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 26009 #define VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 26010 #define VML2VC0_VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 26011 //VML2VC0_VM_INVALIDATE_ENG11_REQ 26012 #define VML2VC0_VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 26013 #define VML2VC0_VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 26014 #define VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 26015 #define VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 26016 #define VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 26017 #define VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 26018 #define VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 26019 #define VML2VC0_VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 26020 #define VML2VC0_VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 26021 #define VML2VC0_VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00030000L 26022 #define VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 26023 #define VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 26024 #define VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 26025 #define VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 26026 #define VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 26027 #define VML2VC0_VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 26028 //VML2VC0_VM_INVALIDATE_ENG12_REQ 26029 #define VML2VC0_VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 26030 #define VML2VC0_VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 26031 #define VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 26032 #define VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 26033 #define VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 26034 #define VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 26035 #define VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 26036 #define VML2VC0_VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 26037 #define VML2VC0_VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 26038 #define VML2VC0_VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00030000L 26039 #define VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 26040 #define VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 26041 #define VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 26042 #define VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 26043 #define VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 26044 #define VML2VC0_VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 26045 //VML2VC0_VM_INVALIDATE_ENG13_REQ 26046 #define VML2VC0_VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 26047 #define VML2VC0_VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 26048 #define VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 26049 #define VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 26050 #define VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 26051 #define VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 26052 #define VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 26053 #define VML2VC0_VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 26054 #define VML2VC0_VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 26055 #define VML2VC0_VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00030000L 26056 #define VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 26057 #define VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 26058 #define VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 26059 #define VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 26060 #define VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 26061 #define VML2VC0_VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 26062 //VML2VC0_VM_INVALIDATE_ENG14_REQ 26063 #define VML2VC0_VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 26064 #define VML2VC0_VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 26065 #define VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 26066 #define VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 26067 #define VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 26068 #define VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 26069 #define VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 26070 #define VML2VC0_VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 26071 #define VML2VC0_VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 26072 #define VML2VC0_VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00030000L 26073 #define VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 26074 #define VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 26075 #define VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 26076 #define VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 26077 #define VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 26078 #define VML2VC0_VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 26079 //VML2VC0_VM_INVALIDATE_ENG15_REQ 26080 #define VML2VC0_VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 26081 #define VML2VC0_VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 26082 #define VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 26083 #define VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 26084 #define VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 26085 #define VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 26086 #define VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 26087 #define VML2VC0_VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 26088 #define VML2VC0_VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 26089 #define VML2VC0_VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00030000L 26090 #define VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 26091 #define VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 26092 #define VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 26093 #define VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 26094 #define VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 26095 #define VML2VC0_VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 26096 //VML2VC0_VM_INVALIDATE_ENG16_REQ 26097 #define VML2VC0_VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 26098 #define VML2VC0_VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 26099 #define VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 26100 #define VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 26101 #define VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 26102 #define VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 26103 #define VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 26104 #define VML2VC0_VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 26105 #define VML2VC0_VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 26106 #define VML2VC0_VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00030000L 26107 #define VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 26108 #define VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 26109 #define VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 26110 #define VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 26111 #define VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 26112 #define VML2VC0_VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 26113 //VML2VC0_VM_INVALIDATE_ENG17_REQ 26114 #define VML2VC0_VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 26115 #define VML2VC0_VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 26116 #define VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 26117 #define VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 26118 #define VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 26119 #define VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 26120 #define VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 26121 #define VML2VC0_VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 26122 #define VML2VC0_VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 26123 #define VML2VC0_VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00030000L 26124 #define VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 26125 #define VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 26126 #define VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 26127 #define VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 26128 #define VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 26129 #define VML2VC0_VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 26130 //VML2VC0_VM_INVALIDATE_ENG0_ACK 26131 #define VML2VC0_VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 26132 #define VML2VC0_VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 26133 #define VML2VC0_VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 26134 #define VML2VC0_VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L 26135 //VML2VC0_VM_INVALIDATE_ENG1_ACK 26136 #define VML2VC0_VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 26137 #define VML2VC0_VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 26138 #define VML2VC0_VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 26139 #define VML2VC0_VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L 26140 //VML2VC0_VM_INVALIDATE_ENG2_ACK 26141 #define VML2VC0_VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 26142 #define VML2VC0_VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 26143 #define VML2VC0_VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 26144 #define VML2VC0_VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L 26145 //VML2VC0_VM_INVALIDATE_ENG3_ACK 26146 #define VML2VC0_VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 26147 #define VML2VC0_VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 26148 #define VML2VC0_VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 26149 #define VML2VC0_VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L 26150 //VML2VC0_VM_INVALIDATE_ENG4_ACK 26151 #define VML2VC0_VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 26152 #define VML2VC0_VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 26153 #define VML2VC0_VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 26154 #define VML2VC0_VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L 26155 //VML2VC0_VM_INVALIDATE_ENG5_ACK 26156 #define VML2VC0_VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 26157 #define VML2VC0_VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 26158 #define VML2VC0_VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 26159 #define VML2VC0_VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L 26160 //VML2VC0_VM_INVALIDATE_ENG6_ACK 26161 #define VML2VC0_VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 26162 #define VML2VC0_VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 26163 #define VML2VC0_VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 26164 #define VML2VC0_VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L 26165 //VML2VC0_VM_INVALIDATE_ENG7_ACK 26166 #define VML2VC0_VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 26167 #define VML2VC0_VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 26168 #define VML2VC0_VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 26169 #define VML2VC0_VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L 26170 //VML2VC0_VM_INVALIDATE_ENG8_ACK 26171 #define VML2VC0_VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 26172 #define VML2VC0_VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 26173 #define VML2VC0_VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 26174 #define VML2VC0_VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L 26175 //VML2VC0_VM_INVALIDATE_ENG9_ACK 26176 #define VML2VC0_VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 26177 #define VML2VC0_VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 26178 #define VML2VC0_VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 26179 #define VML2VC0_VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L 26180 //VML2VC0_VM_INVALIDATE_ENG10_ACK 26181 #define VML2VC0_VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 26182 #define VML2VC0_VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 26183 #define VML2VC0_VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 26184 #define VML2VC0_VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L 26185 //VML2VC0_VM_INVALIDATE_ENG11_ACK 26186 #define VML2VC0_VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 26187 #define VML2VC0_VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 26188 #define VML2VC0_VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 26189 #define VML2VC0_VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L 26190 //VML2VC0_VM_INVALIDATE_ENG12_ACK 26191 #define VML2VC0_VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 26192 #define VML2VC0_VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 26193 #define VML2VC0_VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 26194 #define VML2VC0_VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L 26195 //VML2VC0_VM_INVALIDATE_ENG13_ACK 26196 #define VML2VC0_VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 26197 #define VML2VC0_VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 26198 #define VML2VC0_VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 26199 #define VML2VC0_VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L 26200 //VML2VC0_VM_INVALIDATE_ENG14_ACK 26201 #define VML2VC0_VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 26202 #define VML2VC0_VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 26203 #define VML2VC0_VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 26204 #define VML2VC0_VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L 26205 //VML2VC0_VM_INVALIDATE_ENG15_ACK 26206 #define VML2VC0_VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 26207 #define VML2VC0_VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 26208 #define VML2VC0_VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 26209 #define VML2VC0_VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L 26210 //VML2VC0_VM_INVALIDATE_ENG16_ACK 26211 #define VML2VC0_VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 26212 #define VML2VC0_VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 26213 #define VML2VC0_VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 26214 #define VML2VC0_VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L 26215 //VML2VC0_VM_INVALIDATE_ENG17_ACK 26216 #define VML2VC0_VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 26217 #define VML2VC0_VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 26218 #define VML2VC0_VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 26219 #define VML2VC0_VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L 26220 //VML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32 26221 #define VML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 26222 #define VML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 26223 #define VML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 26224 #define VML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 26225 //VML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32 26226 #define VML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 26227 #define VML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 26228 //VML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 26229 #define VML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 26230 #define VML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 26231 #define VML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 26232 #define VML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 26233 //VML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32 26234 #define VML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 26235 #define VML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 26236 //VML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32 26237 #define VML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 26238 #define VML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 26239 #define VML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 26240 #define VML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 26241 //VML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32 26242 #define VML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 26243 #define VML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 26244 //VML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32 26245 #define VML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 26246 #define VML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 26247 #define VML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 26248 #define VML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 26249 //VML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32 26250 #define VML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 26251 #define VML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 26252 //VML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32 26253 #define VML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 26254 #define VML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 26255 #define VML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 26256 #define VML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 26257 //VML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32 26258 #define VML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 26259 #define VML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 26260 //VML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32 26261 #define VML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 26262 #define VML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 26263 #define VML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 26264 #define VML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 26265 //VML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32 26266 #define VML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 26267 #define VML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 26268 //VML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32 26269 #define VML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 26270 #define VML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 26271 #define VML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 26272 #define VML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 26273 //VML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32 26274 #define VML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 26275 #define VML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 26276 //VML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32 26277 #define VML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 26278 #define VML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 26279 #define VML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 26280 #define VML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 26281 //VML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32 26282 #define VML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 26283 #define VML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 26284 //VML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32 26285 #define VML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 26286 #define VML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 26287 #define VML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 26288 #define VML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 26289 //VML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32 26290 #define VML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 26291 #define VML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 26292 //VML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32 26293 #define VML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 26294 #define VML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 26295 #define VML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 26296 #define VML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 26297 //VML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32 26298 #define VML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 26299 #define VML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 26300 //VML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32 26301 #define VML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 26302 #define VML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 26303 #define VML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 26304 #define VML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 26305 //VML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32 26306 #define VML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 26307 #define VML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 26308 //VML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32 26309 #define VML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 26310 #define VML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 26311 #define VML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 26312 #define VML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 26313 //VML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32 26314 #define VML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 26315 #define VML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 26316 //VML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32 26317 #define VML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 26318 #define VML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 26319 #define VML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 26320 #define VML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 26321 //VML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32 26322 #define VML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 26323 #define VML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 26324 //VML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32 26325 #define VML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 26326 #define VML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 26327 #define VML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 26328 #define VML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 26329 //VML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32 26330 #define VML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 26331 #define VML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 26332 //VML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32 26333 #define VML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 26334 #define VML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 26335 #define VML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 26336 #define VML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 26337 //VML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32 26338 #define VML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 26339 #define VML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 26340 //VML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32 26341 #define VML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 26342 #define VML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 26343 #define VML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 26344 #define VML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 26345 //VML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32 26346 #define VML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 26347 #define VML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 26348 //VML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 26349 #define VML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 26350 #define VML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 26351 #define VML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 26352 #define VML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 26353 //VML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 26354 #define VML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 26355 #define VML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 26356 //VML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32 26357 #define VML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 26358 #define VML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 26359 #define VML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 26360 #define VML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 26361 //VML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32 26362 #define VML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 26363 #define VML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 26364 //VML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 26365 #define VML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 26366 #define VML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 26367 //VML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 26368 #define VML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 26369 #define VML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 26370 //VML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 26371 #define VML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 26372 #define VML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 26373 //VML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 26374 #define VML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 26375 #define VML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 26376 //VML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 26377 #define VML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 26378 #define VML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 26379 //VML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 26380 #define VML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 26381 #define VML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 26382 //VML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 26383 #define VML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 26384 #define VML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 26385 //VML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 26386 #define VML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 26387 #define VML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 26388 //VML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 26389 #define VML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 26390 #define VML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 26391 //VML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 26392 #define VML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 26393 #define VML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 26394 //VML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 26395 #define VML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 26396 #define VML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 26397 //VML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 26398 #define VML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 26399 #define VML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 26400 //VML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 26401 #define VML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 26402 #define VML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 26403 //VML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 26404 #define VML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 26405 #define VML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 26406 //VML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 26407 #define VML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 26408 #define VML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 26409 //VML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 26410 #define VML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 26411 #define VML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 26412 //VML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 26413 #define VML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 26414 #define VML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 26415 //VML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 26416 #define VML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 26417 #define VML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 26418 //VML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 26419 #define VML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 26420 #define VML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 26421 //VML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 26422 #define VML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 26423 #define VML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 26424 //VML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 26425 #define VML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 26426 #define VML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 26427 //VML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 26428 #define VML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 26429 #define VML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 26430 //VML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 26431 #define VML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 26432 #define VML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 26433 //VML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 26434 #define VML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 26435 #define VML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 26436 //VML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 26437 #define VML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 26438 #define VML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 26439 //VML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 26440 #define VML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 26441 #define VML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 26442 //VML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 26443 #define VML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 26444 #define VML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 26445 //VML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 26446 #define VML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 26447 #define VML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 26448 //VML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 26449 #define VML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 26450 #define VML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 26451 //VML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 26452 #define VML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 26453 #define VML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 26454 //VML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 26455 #define VML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 26456 #define VML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 26457 //VML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 26458 #define VML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 26459 #define VML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 26460 //VML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 26461 #define VML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 26462 #define VML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 26463 //VML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 26464 #define VML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 26465 #define VML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 26466 //VML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 26467 #define VML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 26468 #define VML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 26469 //VML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 26470 #define VML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 26471 #define VML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 26472 //VML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 26473 #define VML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 26474 #define VML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 26475 //VML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 26476 #define VML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 26477 #define VML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 26478 //VML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 26479 #define VML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 26480 #define VML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 26481 //VML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 26482 #define VML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 26483 #define VML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 26484 //VML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 26485 #define VML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 26486 #define VML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 26487 //VML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 26488 #define VML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 26489 #define VML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 26490 //VML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 26491 #define VML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 26492 #define VML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 26493 //VML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 26494 #define VML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 26495 #define VML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 26496 //VML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 26497 #define VML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 26498 #define VML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 26499 //VML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 26500 #define VML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 26501 #define VML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 26502 //VML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 26503 #define VML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 26504 #define VML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 26505 //VML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 26506 #define VML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 26507 #define VML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 26508 //VML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 26509 #define VML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 26510 #define VML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 26511 //VML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 26512 #define VML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 26513 #define VML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 26514 //VML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 26515 #define VML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 26516 #define VML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 26517 //VML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 26518 #define VML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 26519 #define VML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 26520 //VML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 26521 #define VML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 26522 #define VML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 26523 //VML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 26524 #define VML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 26525 #define VML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 26526 //VML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 26527 #define VML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 26528 #define VML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 26529 //VML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 26530 #define VML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 26531 #define VML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 26532 //VML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 26533 #define VML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 26534 #define VML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 26535 //VML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 26536 #define VML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 26537 #define VML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 26538 //VML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 26539 #define VML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 26540 #define VML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 26541 //VML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 26542 #define VML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 26543 #define VML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 26544 //VML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 26545 #define VML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 26546 #define VML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 26547 //VML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 26548 #define VML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 26549 #define VML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 26550 //VML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 26551 #define VML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 26552 #define VML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 26553 //VML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 26554 #define VML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 26555 #define VML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 26556 //VML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 26557 #define VML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 26558 #define VML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 26559 //VML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 26560 #define VML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 26561 #define VML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 26562 //VML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 26563 #define VML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 26564 #define VML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 26565 //VML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 26566 #define VML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 26567 #define VML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 26568 //VML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 26569 #define VML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 26570 #define VML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 26571 //VML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 26572 #define VML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 26573 #define VML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 26574 //VML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 26575 #define VML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 26576 #define VML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 26577 //VML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 26578 #define VML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 26579 #define VML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 26580 //VML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 26581 #define VML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 26582 #define VML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 26583 //VML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 26584 #define VML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 26585 #define VML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 26586 //VML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 26587 #define VML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 26588 #define VML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 26589 //VML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 26590 #define VML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 26591 #define VML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 26592 //VML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 26593 #define VML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 26594 #define VML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 26595 //VML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 26596 #define VML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 26597 #define VML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 26598 //VML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 26599 #define VML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 26600 #define VML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 26601 //VML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 26602 #define VML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 26603 #define VML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 26604 //VML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 26605 #define VML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 26606 #define VML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 26607 //VML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 26608 #define VML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 26609 #define VML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 26610 //VML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 26611 #define VML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 26612 #define VML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 26613 //VML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 26614 #define VML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 26615 #define VML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 26616 //VML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 26617 #define VML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 26618 #define VML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 26619 //VML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 26620 #define VML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 26621 #define VML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 26622 //VML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 26623 #define VML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 26624 #define VML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 26625 //VML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 26626 #define VML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 26627 #define VML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 26628 //VML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 26629 #define VML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 26630 #define VML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 26631 //VML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 26632 #define VML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 26633 #define VML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 26634 //VML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 26635 #define VML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 26636 #define VML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 26637 //VML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 26638 #define VML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 26639 #define VML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 26640 //VML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 26641 #define VML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 26642 #define VML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 26643 //VML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 26644 #define VML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 26645 #define VML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 26646 //VML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 26647 #define VML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 26648 #define VML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 26649 //VML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 26650 #define VML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 26651 #define VML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 26652 26653 26654 // addressBlock: mmhub_utcl2_vmsharedpfdec 26655 //VMSHAREDPF0_MC_VM_NB_MMIOBASE 26656 #define VMSHAREDPF0_MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0 26657 #define VMSHAREDPF0_MC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL 26658 //VMSHAREDPF0_MC_VM_NB_MMIOLIMIT 26659 #define VMSHAREDPF0_MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 26660 #define VMSHAREDPF0_MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL 26661 //VMSHAREDPF0_MC_VM_NB_PCI_CTRL 26662 #define VMSHAREDPF0_MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17 26663 #define VMSHAREDPF0_MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L 26664 //VMSHAREDPF0_MC_VM_NB_PCI_ARB 26665 #define VMSHAREDPF0_MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 26666 #define VMSHAREDPF0_MC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L 26667 //VMSHAREDPF0_MC_VM_NB_TOP_OF_DRAM_SLOT1 26668 #define VMSHAREDPF0_MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 26669 #define VMSHAREDPF0_MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L 26670 //VMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2 26671 #define VMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 26672 #define VMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 26673 #define VMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L 26674 #define VMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L 26675 //VMSHAREDPF0_MC_VM_NB_UPPER_TOP_OF_DRAM2 26676 #define VMSHAREDPF0_MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 26677 #define VMSHAREDPF0_MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x00000FFFL 26678 //VMSHAREDPF0_MC_VM_FB_OFFSET 26679 #define VMSHAREDPF0_MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 26680 #define VMSHAREDPF0_MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL 26681 //VMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 26682 #define VMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 26683 #define VMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL 26684 //VMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 26685 #define VMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 26686 #define VMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL 26687 //VMSHAREDPF0_MC_VM_STEERING 26688 #define VMSHAREDPF0_MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 26689 #define VMSHAREDPF0_MC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L 26690 //VMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ 26691 #define VMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 26692 #define VMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f 26693 #define VMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 26694 #define VMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L 26695 //VMSHAREDPF0_MC_MEM_POWER_LS 26696 #define VMSHAREDPF0_MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 26697 #define VMSHAREDPF0_MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 26698 #define VMSHAREDPF0_MC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL 26699 #define VMSHAREDPF0_MC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L 26700 //VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_START 26701 #define VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 26702 #define VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL 26703 //VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_END 26704 #define VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 26705 #define VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL 26706 //VMSHAREDPF0_MC_VM_APT_CNTL 26707 #define VMSHAREDPF0_MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 26708 #define VMSHAREDPF0_MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 26709 #define VMSHAREDPF0_MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L 26710 #define VMSHAREDPF0_MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L 26711 //VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_START 26712 #define VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0 26713 #define VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL 26714 //VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_END 26715 #define VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0 26716 #define VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL 26717 //VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 26718 #define VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 26719 #define VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L 26720 //VMSHAREDPF0_MC_VM_XGMI_LFB_CNTL 26721 #define VMSHAREDPF0_MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT 0x0 26722 #define VMSHAREDPF0_MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT 0x4 26723 #define VMSHAREDPF0_MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK 0x0000000FL 26724 #define VMSHAREDPF0_MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK 0x000000F0L 26725 //VMSHAREDPF0_MC_VM_XGMI_LFB_SIZE 26726 #define VMSHAREDPF0_MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT 0x0 26727 #define VMSHAREDPF0_MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK 0x0001FFFFL 26728 //VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL 26729 #define VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE__SHIFT 0x0 26730 #define VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE_MASK 0x00000001L 26731 //MC_VM_XGMI_LFB_CNTL 26732 #define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT 0x0 26733 #define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT 0x3 26734 #define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK 0x00000007L 26735 #define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK 0x00000038L 26736 //MC_VM_XGMI_LFB_SIZE 26737 #define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT 0x0 26738 #define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK 0x0000FFFFL 26739 26740 26741 // addressBlock: mmhub_utcl2_vmsharedvcdec 26742 //VMSHAREDVC0_MC_VM_FB_LOCATION_BASE 26743 #define VMSHAREDVC0_MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 26744 #define VMSHAREDVC0_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL 26745 //VMSHAREDVC0_MC_VM_FB_LOCATION_TOP 26746 #define VMSHAREDVC0_MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 26747 #define VMSHAREDVC0_MC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL 26748 //VMSHAREDVC0_MC_VM_AGP_TOP 26749 #define VMSHAREDVC0_MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 26750 #define VMSHAREDVC0_MC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL 26751 //VMSHAREDVC0_MC_VM_AGP_BOT 26752 #define VMSHAREDVC0_MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 26753 #define VMSHAREDVC0_MC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL 26754 //VMSHAREDVC0_MC_VM_AGP_BASE 26755 #define VMSHAREDVC0_MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 26756 #define VMSHAREDVC0_MC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL 26757 //VMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR 26758 #define VMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0 26759 #define VMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL 26760 //VMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 26761 #define VMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0 26762 #define VMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL 26763 //VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL 26764 #define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 26765 #define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 26766 #define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 26767 #define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 26768 #define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 26769 #define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb 26770 #define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT 0xd 26771 #define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L 26772 #define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L 26773 #define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L 26774 #define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L 26775 #define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L 26776 #define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00001800L 26777 #define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK 0x00002000L 26778 26779 26780 // addressBlock: mmhub_utcl2_vmsharedhvdec 26781 //VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0 26782 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 26783 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 26784 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL 26785 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L 26786 //VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1 26787 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 26788 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 26789 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL 26790 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L 26791 //VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2 26792 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 26793 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 26794 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL 26795 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L 26796 //VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3 26797 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 26798 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 26799 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL 26800 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L 26801 //VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4 26802 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 26803 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 26804 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL 26805 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L 26806 //VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5 26807 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 26808 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 26809 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL 26810 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L 26811 //VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6 26812 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 26813 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 26814 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL 26815 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L 26816 //VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7 26817 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 26818 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 26819 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL 26820 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L 26821 //VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8 26822 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0 26823 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10 26824 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL 26825 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L 26826 //VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9 26827 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0 26828 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10 26829 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL 26830 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L 26831 //VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10 26832 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0 26833 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10 26834 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL 26835 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L 26836 //VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11 26837 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0 26838 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10 26839 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL 26840 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L 26841 //VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12 26842 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0 26843 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10 26844 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL 26845 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L 26846 //VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13 26847 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0 26848 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10 26849 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL 26850 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L 26851 //VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14 26852 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0 26853 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10 26854 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL 26855 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L 26856 //VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15 26857 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0 26858 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10 26859 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL 26860 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L 26861 //VMSHAREDHV0_VM_IOMMU_MMIO_CNTRL_1 26862 #define VMSHAREDHV0_VM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT 0x8 26863 #define VMSHAREDHV0_VM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK 0x00000100L 26864 //VMSHAREDHV0_MC_VM_MARC_BASE_LO_0 26865 #define VMSHAREDHV0_MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc 26866 #define VMSHAREDHV0_MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L 26867 //VMSHAREDHV0_MC_VM_MARC_BASE_LO_1 26868 #define VMSHAREDHV0_MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc 26869 #define VMSHAREDHV0_MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L 26870 //VMSHAREDHV0_MC_VM_MARC_BASE_LO_2 26871 #define VMSHAREDHV0_MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc 26872 #define VMSHAREDHV0_MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L 26873 //VMSHAREDHV0_MC_VM_MARC_BASE_LO_3 26874 #define VMSHAREDHV0_MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc 26875 #define VMSHAREDHV0_MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L 26876 //VMSHAREDHV0_MC_VM_MARC_BASE_HI_0 26877 #define VMSHAREDHV0_MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0 26878 #define VMSHAREDHV0_MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL 26879 //VMSHAREDHV0_MC_VM_MARC_BASE_HI_1 26880 #define VMSHAREDHV0_MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0 26881 #define VMSHAREDHV0_MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL 26882 //VMSHAREDHV0_MC_VM_MARC_BASE_HI_2 26883 #define VMSHAREDHV0_MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0 26884 #define VMSHAREDHV0_MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL 26885 //VMSHAREDHV0_MC_VM_MARC_BASE_HI_3 26886 #define VMSHAREDHV0_MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0 26887 #define VMSHAREDHV0_MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL 26888 //VMSHAREDHV0_MC_VM_MARC_RELOC_LO_0 26889 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0 26890 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1 26891 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc 26892 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L 26893 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L 26894 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L 26895 //VMSHAREDHV0_MC_VM_MARC_RELOC_LO_1 26896 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0 26897 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1 26898 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc 26899 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L 26900 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L 26901 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L 26902 //VMSHAREDHV0_MC_VM_MARC_RELOC_LO_2 26903 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0 26904 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1 26905 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc 26906 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L 26907 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L 26908 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L 26909 //VMSHAREDHV0_MC_VM_MARC_RELOC_LO_3 26910 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0 26911 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1 26912 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc 26913 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L 26914 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L 26915 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L 26916 //VMSHAREDHV0_MC_VM_MARC_RELOC_HI_0 26917 #define VMSHAREDHV0_MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0 26918 #define VMSHAREDHV0_MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL 26919 //VMSHAREDHV0_MC_VM_MARC_RELOC_HI_1 26920 #define VMSHAREDHV0_MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0 26921 #define VMSHAREDHV0_MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL 26922 //VMSHAREDHV0_MC_VM_MARC_RELOC_HI_2 26923 #define VMSHAREDHV0_MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0 26924 #define VMSHAREDHV0_MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL 26925 //VMSHAREDHV0_MC_VM_MARC_RELOC_HI_3 26926 #define VMSHAREDHV0_MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0 26927 #define VMSHAREDHV0_MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL 26928 //VMSHAREDHV0_MC_VM_MARC_LEN_LO_0 26929 #define VMSHAREDHV0_MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc 26930 #define VMSHAREDHV0_MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L 26931 //VMSHAREDHV0_MC_VM_MARC_LEN_LO_1 26932 #define VMSHAREDHV0_MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc 26933 #define VMSHAREDHV0_MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L 26934 //VMSHAREDHV0_MC_VM_MARC_LEN_LO_2 26935 #define VMSHAREDHV0_MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc 26936 #define VMSHAREDHV0_MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L 26937 //VMSHAREDHV0_MC_VM_MARC_LEN_LO_3 26938 #define VMSHAREDHV0_MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc 26939 #define VMSHAREDHV0_MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L 26940 //VMSHAREDHV0_MC_VM_MARC_LEN_HI_0 26941 #define VMSHAREDHV0_MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0 26942 #define VMSHAREDHV0_MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL 26943 //VMSHAREDHV0_MC_VM_MARC_LEN_HI_1 26944 #define VMSHAREDHV0_MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0 26945 #define VMSHAREDHV0_MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL 26946 //VMSHAREDHV0_MC_VM_MARC_LEN_HI_2 26947 #define VMSHAREDHV0_MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0 26948 #define VMSHAREDHV0_MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL 26949 //VMSHAREDHV0_MC_VM_MARC_LEN_HI_3 26950 #define VMSHAREDHV0_MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0 26951 #define VMSHAREDHV0_MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL 26952 //VMSHAREDHV0_VM_IOMMU_CONTROL_REGISTER 26953 #define VMSHAREDHV0_VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0 26954 #define VMSHAREDHV0_VM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L 26955 //VMSHAREDHV0_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 26956 #define VMSHAREDHV0_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd 26957 #define VMSHAREDHV0_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L 26958 //VMSHAREDHV0_VM_PCIE_ATS_CNTL 26959 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL__STU__SHIFT 0x10 26960 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f 26961 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L 26962 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L 26963 //VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_0 26964 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f 26965 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L 26966 //VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_1 26967 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f 26968 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L 26969 //VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_2 26970 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f 26971 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L 26972 //VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_3 26973 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f 26974 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L 26975 //VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_4 26976 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f 26977 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L 26978 //VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_5 26979 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f 26980 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L 26981 //VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_6 26982 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f 26983 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L 26984 //VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_7 26985 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f 26986 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L 26987 //VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_8 26988 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f 26989 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L 26990 //VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_9 26991 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f 26992 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L 26993 //VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_10 26994 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f 26995 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L 26996 //VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_11 26997 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f 26998 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L 26999 //VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_12 27000 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f 27001 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L 27002 //VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_13 27003 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f 27004 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L 27005 //VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_14 27006 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f 27007 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L 27008 //VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_15 27009 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f 27010 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L 27011 //VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL 27012 #define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 27013 #define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 27014 #define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT 0xc 27015 #define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf 27016 #define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 27017 #define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 27018 #define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 27019 #define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 27020 #define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK 0x00007000L 27021 #define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L 27022 #define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L 27023 #define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L 27024 //VMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID 27025 #define VMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 27026 #define VMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f 27027 #define VMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 27028 #define VMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L 27029 //VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE 27030 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0__SHIFT 0x0 27031 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1__SHIFT 0x1 27032 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2__SHIFT 0x2 27033 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3__SHIFT 0x3 27034 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4__SHIFT 0x4 27035 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5__SHIFT 0x5 27036 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6__SHIFT 0x6 27037 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7__SHIFT 0x7 27038 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8__SHIFT 0x8 27039 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9__SHIFT 0x9 27040 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10__SHIFT 0xa 27041 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11__SHIFT 0xb 27042 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12__SHIFT 0xc 27043 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13__SHIFT 0xd 27044 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14__SHIFT 0xe 27045 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15__SHIFT 0xf 27046 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF__SHIFT 0x1f 27047 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0_MASK 0x00000001L 27048 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1_MASK 0x00000002L 27049 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2_MASK 0x00000004L 27050 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3_MASK 0x00000008L 27051 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4_MASK 0x00000010L 27052 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5_MASK 0x00000020L 27053 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6_MASK 0x00000040L 27054 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7_MASK 0x00000080L 27055 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8_MASK 0x00000100L 27056 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9_MASK 0x00000200L 27057 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10_MASK 0x00000400L 27058 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11_MASK 0x00000800L 27059 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12_MASK 0x00001000L 27060 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13_MASK 0x00002000L 27061 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14_MASK 0x00004000L 27062 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15_MASK 0x00008000L 27063 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF_MASK 0x80000000L 27064 27065 27066 // addressBlock: mmhub_utcl2_atcl2pfcntrdec 27067 //ATCL2PFCNTR0_ATC_L2_PERFCOUNTER_LO 27068 #define ATCL2PFCNTR0_ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 27069 #define ATCL2PFCNTR0_ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 27070 //ATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI 27071 #define ATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 27072 #define ATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 27073 #define ATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 27074 #define ATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 27075 27076 27077 // addressBlock: mmhub_utcl2_atcl2pfcntldec 27078 //ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG 27079 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 27080 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 27081 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 27082 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 27083 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 27084 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 27085 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 27086 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 27087 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 27088 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 27089 //ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG 27090 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 27091 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 27092 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 27093 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 27094 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 27095 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 27096 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 27097 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 27098 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 27099 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 27100 //ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL 27101 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 27102 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 27103 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 27104 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 27105 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 27106 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 27107 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 27108 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 27109 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 27110 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 27111 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 27112 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 27113 27114 27115 // addressBlock: mmhub_utcl2_vml2pldec 27116 //VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG 27117 #define VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 27118 #define VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 27119 #define VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 27120 #define VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 27121 #define VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 27122 #define VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 27123 #define VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 27124 #define VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 27125 #define VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 27126 #define VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 27127 //VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG 27128 #define VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 27129 #define VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 27130 #define VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 27131 #define VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 27132 #define VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 27133 #define VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 27134 #define VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 27135 #define VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 27136 #define VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 27137 #define VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 27138 //VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG 27139 #define VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 27140 #define VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 27141 #define VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 27142 #define VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 27143 #define VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 27144 #define VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 27145 #define VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 27146 #define VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 27147 #define VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 27148 #define VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 27149 //VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG 27150 #define VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 27151 #define VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 27152 #define VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 27153 #define VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 27154 #define VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 27155 #define VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 27156 #define VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 27157 #define VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 27158 #define VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 27159 #define VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 27160 //VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG 27161 #define VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 27162 #define VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 27163 #define VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 27164 #define VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c 27165 #define VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d 27166 #define VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL 27167 #define VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L 27168 #define VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L 27169 #define VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L 27170 #define VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L 27171 //VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG 27172 #define VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 27173 #define VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 27174 #define VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 27175 #define VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c 27176 #define VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d 27177 #define VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL 27178 #define VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L 27179 #define VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L 27180 #define VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L 27181 #define VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L 27182 //VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG 27183 #define VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 27184 #define VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 27185 #define VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 27186 #define VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c 27187 #define VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d 27188 #define VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL 27189 #define VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L 27190 #define VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L 27191 #define VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L 27192 #define VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L 27193 //VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG 27194 #define VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 27195 #define VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 27196 #define VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 27197 #define VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c 27198 #define VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d 27199 #define VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL 27200 #define VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L 27201 #define VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L 27202 #define VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L 27203 #define VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L 27204 //VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL 27205 #define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 27206 #define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 27207 #define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 27208 #define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 27209 #define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 27210 #define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 27211 #define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 27212 #define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 27213 #define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 27214 #define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 27215 #define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 27216 #define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 27217 27218 27219 // addressBlock: mmhub_utcl2_vml2prdec 27220 //VML2PR0_MC_VM_L2_PERFCOUNTER_LO 27221 #define VML2PR0_MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 27222 #define VML2PR0_MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 27223 //VML2PR0_MC_VM_L2_PERFCOUNTER_HI 27224 #define VML2PR0_MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 27225 #define VML2PR0_MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 27226 #define VML2PR0_MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 27227 #define VML2PR0_MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 27228 27229 27230 // addressBlock: mmhub_dagb_dagbdec5 27231 //DAGB5_RDCLI0 27232 #define DAGB5_RDCLI0__VIRT_CHAN__SHIFT 0x0 27233 #define DAGB5_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 27234 #define DAGB5_RDCLI0__URG_HIGH__SHIFT 0x4 27235 #define DAGB5_RDCLI0__URG_LOW__SHIFT 0x8 27236 #define DAGB5_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 27237 #define DAGB5_RDCLI0__MAX_BW__SHIFT 0xd 27238 #define DAGB5_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 27239 #define DAGB5_RDCLI0__MIN_BW__SHIFT 0x16 27240 #define DAGB5_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 27241 #define DAGB5_RDCLI0__MAX_OSD__SHIFT 0x1a 27242 #define DAGB5_RDCLI0__VIRT_CHAN_MASK 0x00000007L 27243 #define DAGB5_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 27244 #define DAGB5_RDCLI0__URG_HIGH_MASK 0x000000F0L 27245 #define DAGB5_RDCLI0__URG_LOW_MASK 0x00000F00L 27246 #define DAGB5_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L 27247 #define DAGB5_RDCLI0__MAX_BW_MASK 0x001FE000L 27248 #define DAGB5_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L 27249 #define DAGB5_RDCLI0__MIN_BW_MASK 0x01C00000L 27250 #define DAGB5_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 27251 #define DAGB5_RDCLI0__MAX_OSD_MASK 0xFC000000L 27252 //DAGB5_RDCLI1 27253 #define DAGB5_RDCLI1__VIRT_CHAN__SHIFT 0x0 27254 #define DAGB5_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 27255 #define DAGB5_RDCLI1__URG_HIGH__SHIFT 0x4 27256 #define DAGB5_RDCLI1__URG_LOW__SHIFT 0x8 27257 #define DAGB5_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc 27258 #define DAGB5_RDCLI1__MAX_BW__SHIFT 0xd 27259 #define DAGB5_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 27260 #define DAGB5_RDCLI1__MIN_BW__SHIFT 0x16 27261 #define DAGB5_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 27262 #define DAGB5_RDCLI1__MAX_OSD__SHIFT 0x1a 27263 #define DAGB5_RDCLI1__VIRT_CHAN_MASK 0x00000007L 27264 #define DAGB5_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 27265 #define DAGB5_RDCLI1__URG_HIGH_MASK 0x000000F0L 27266 #define DAGB5_RDCLI1__URG_LOW_MASK 0x00000F00L 27267 #define DAGB5_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L 27268 #define DAGB5_RDCLI1__MAX_BW_MASK 0x001FE000L 27269 #define DAGB5_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L 27270 #define DAGB5_RDCLI1__MIN_BW_MASK 0x01C00000L 27271 #define DAGB5_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 27272 #define DAGB5_RDCLI1__MAX_OSD_MASK 0xFC000000L 27273 //DAGB5_RDCLI2 27274 #define DAGB5_RDCLI2__VIRT_CHAN__SHIFT 0x0 27275 #define DAGB5_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 27276 #define DAGB5_RDCLI2__URG_HIGH__SHIFT 0x4 27277 #define DAGB5_RDCLI2__URG_LOW__SHIFT 0x8 27278 #define DAGB5_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc 27279 #define DAGB5_RDCLI2__MAX_BW__SHIFT 0xd 27280 #define DAGB5_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 27281 #define DAGB5_RDCLI2__MIN_BW__SHIFT 0x16 27282 #define DAGB5_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 27283 #define DAGB5_RDCLI2__MAX_OSD__SHIFT 0x1a 27284 #define DAGB5_RDCLI2__VIRT_CHAN_MASK 0x00000007L 27285 #define DAGB5_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 27286 #define DAGB5_RDCLI2__URG_HIGH_MASK 0x000000F0L 27287 #define DAGB5_RDCLI2__URG_LOW_MASK 0x00000F00L 27288 #define DAGB5_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L 27289 #define DAGB5_RDCLI2__MAX_BW_MASK 0x001FE000L 27290 #define DAGB5_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L 27291 #define DAGB5_RDCLI2__MIN_BW_MASK 0x01C00000L 27292 #define DAGB5_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 27293 #define DAGB5_RDCLI2__MAX_OSD_MASK 0xFC000000L 27294 //DAGB5_RDCLI3 27295 #define DAGB5_RDCLI3__VIRT_CHAN__SHIFT 0x0 27296 #define DAGB5_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 27297 #define DAGB5_RDCLI3__URG_HIGH__SHIFT 0x4 27298 #define DAGB5_RDCLI3__URG_LOW__SHIFT 0x8 27299 #define DAGB5_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc 27300 #define DAGB5_RDCLI3__MAX_BW__SHIFT 0xd 27301 #define DAGB5_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 27302 #define DAGB5_RDCLI3__MIN_BW__SHIFT 0x16 27303 #define DAGB5_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 27304 #define DAGB5_RDCLI3__MAX_OSD__SHIFT 0x1a 27305 #define DAGB5_RDCLI3__VIRT_CHAN_MASK 0x00000007L 27306 #define DAGB5_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 27307 #define DAGB5_RDCLI3__URG_HIGH_MASK 0x000000F0L 27308 #define DAGB5_RDCLI3__URG_LOW_MASK 0x00000F00L 27309 #define DAGB5_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L 27310 #define DAGB5_RDCLI3__MAX_BW_MASK 0x001FE000L 27311 #define DAGB5_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L 27312 #define DAGB5_RDCLI3__MIN_BW_MASK 0x01C00000L 27313 #define DAGB5_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 27314 #define DAGB5_RDCLI3__MAX_OSD_MASK 0xFC000000L 27315 //DAGB5_RDCLI4 27316 #define DAGB5_RDCLI4__VIRT_CHAN__SHIFT 0x0 27317 #define DAGB5_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 27318 #define DAGB5_RDCLI4__URG_HIGH__SHIFT 0x4 27319 #define DAGB5_RDCLI4__URG_LOW__SHIFT 0x8 27320 #define DAGB5_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc 27321 #define DAGB5_RDCLI4__MAX_BW__SHIFT 0xd 27322 #define DAGB5_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 27323 #define DAGB5_RDCLI4__MIN_BW__SHIFT 0x16 27324 #define DAGB5_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 27325 #define DAGB5_RDCLI4__MAX_OSD__SHIFT 0x1a 27326 #define DAGB5_RDCLI4__VIRT_CHAN_MASK 0x00000007L 27327 #define DAGB5_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 27328 #define DAGB5_RDCLI4__URG_HIGH_MASK 0x000000F0L 27329 #define DAGB5_RDCLI4__URG_LOW_MASK 0x00000F00L 27330 #define DAGB5_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L 27331 #define DAGB5_RDCLI4__MAX_BW_MASK 0x001FE000L 27332 #define DAGB5_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L 27333 #define DAGB5_RDCLI4__MIN_BW_MASK 0x01C00000L 27334 #define DAGB5_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 27335 #define DAGB5_RDCLI4__MAX_OSD_MASK 0xFC000000L 27336 //DAGB5_RDCLI5 27337 #define DAGB5_RDCLI5__VIRT_CHAN__SHIFT 0x0 27338 #define DAGB5_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 27339 #define DAGB5_RDCLI5__URG_HIGH__SHIFT 0x4 27340 #define DAGB5_RDCLI5__URG_LOW__SHIFT 0x8 27341 #define DAGB5_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc 27342 #define DAGB5_RDCLI5__MAX_BW__SHIFT 0xd 27343 #define DAGB5_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 27344 #define DAGB5_RDCLI5__MIN_BW__SHIFT 0x16 27345 #define DAGB5_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 27346 #define DAGB5_RDCLI5__MAX_OSD__SHIFT 0x1a 27347 #define DAGB5_RDCLI5__VIRT_CHAN_MASK 0x00000007L 27348 #define DAGB5_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 27349 #define DAGB5_RDCLI5__URG_HIGH_MASK 0x000000F0L 27350 #define DAGB5_RDCLI5__URG_LOW_MASK 0x00000F00L 27351 #define DAGB5_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L 27352 #define DAGB5_RDCLI5__MAX_BW_MASK 0x001FE000L 27353 #define DAGB5_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L 27354 #define DAGB5_RDCLI5__MIN_BW_MASK 0x01C00000L 27355 #define DAGB5_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 27356 #define DAGB5_RDCLI5__MAX_OSD_MASK 0xFC000000L 27357 //DAGB5_RDCLI6 27358 #define DAGB5_RDCLI6__VIRT_CHAN__SHIFT 0x0 27359 #define DAGB5_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 27360 #define DAGB5_RDCLI6__URG_HIGH__SHIFT 0x4 27361 #define DAGB5_RDCLI6__URG_LOW__SHIFT 0x8 27362 #define DAGB5_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc 27363 #define DAGB5_RDCLI6__MAX_BW__SHIFT 0xd 27364 #define DAGB5_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 27365 #define DAGB5_RDCLI6__MIN_BW__SHIFT 0x16 27366 #define DAGB5_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 27367 #define DAGB5_RDCLI6__MAX_OSD__SHIFT 0x1a 27368 #define DAGB5_RDCLI6__VIRT_CHAN_MASK 0x00000007L 27369 #define DAGB5_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 27370 #define DAGB5_RDCLI6__URG_HIGH_MASK 0x000000F0L 27371 #define DAGB5_RDCLI6__URG_LOW_MASK 0x00000F00L 27372 #define DAGB5_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L 27373 #define DAGB5_RDCLI6__MAX_BW_MASK 0x001FE000L 27374 #define DAGB5_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L 27375 #define DAGB5_RDCLI6__MIN_BW_MASK 0x01C00000L 27376 #define DAGB5_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 27377 #define DAGB5_RDCLI6__MAX_OSD_MASK 0xFC000000L 27378 //DAGB5_RDCLI7 27379 #define DAGB5_RDCLI7__VIRT_CHAN__SHIFT 0x0 27380 #define DAGB5_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 27381 #define DAGB5_RDCLI7__URG_HIGH__SHIFT 0x4 27382 #define DAGB5_RDCLI7__URG_LOW__SHIFT 0x8 27383 #define DAGB5_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc 27384 #define DAGB5_RDCLI7__MAX_BW__SHIFT 0xd 27385 #define DAGB5_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 27386 #define DAGB5_RDCLI7__MIN_BW__SHIFT 0x16 27387 #define DAGB5_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 27388 #define DAGB5_RDCLI7__MAX_OSD__SHIFT 0x1a 27389 #define DAGB5_RDCLI7__VIRT_CHAN_MASK 0x00000007L 27390 #define DAGB5_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 27391 #define DAGB5_RDCLI7__URG_HIGH_MASK 0x000000F0L 27392 #define DAGB5_RDCLI7__URG_LOW_MASK 0x00000F00L 27393 #define DAGB5_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L 27394 #define DAGB5_RDCLI7__MAX_BW_MASK 0x001FE000L 27395 #define DAGB5_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L 27396 #define DAGB5_RDCLI7__MIN_BW_MASK 0x01C00000L 27397 #define DAGB5_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 27398 #define DAGB5_RDCLI7__MAX_OSD_MASK 0xFC000000L 27399 //DAGB5_RDCLI8 27400 #define DAGB5_RDCLI8__VIRT_CHAN__SHIFT 0x0 27401 #define DAGB5_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 27402 #define DAGB5_RDCLI8__URG_HIGH__SHIFT 0x4 27403 #define DAGB5_RDCLI8__URG_LOW__SHIFT 0x8 27404 #define DAGB5_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc 27405 #define DAGB5_RDCLI8__MAX_BW__SHIFT 0xd 27406 #define DAGB5_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 27407 #define DAGB5_RDCLI8__MIN_BW__SHIFT 0x16 27408 #define DAGB5_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 27409 #define DAGB5_RDCLI8__MAX_OSD__SHIFT 0x1a 27410 #define DAGB5_RDCLI8__VIRT_CHAN_MASK 0x00000007L 27411 #define DAGB5_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 27412 #define DAGB5_RDCLI8__URG_HIGH_MASK 0x000000F0L 27413 #define DAGB5_RDCLI8__URG_LOW_MASK 0x00000F00L 27414 #define DAGB5_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L 27415 #define DAGB5_RDCLI8__MAX_BW_MASK 0x001FE000L 27416 #define DAGB5_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L 27417 #define DAGB5_RDCLI8__MIN_BW_MASK 0x01C00000L 27418 #define DAGB5_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 27419 #define DAGB5_RDCLI8__MAX_OSD_MASK 0xFC000000L 27420 //DAGB5_RDCLI9 27421 #define DAGB5_RDCLI9__VIRT_CHAN__SHIFT 0x0 27422 #define DAGB5_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 27423 #define DAGB5_RDCLI9__URG_HIGH__SHIFT 0x4 27424 #define DAGB5_RDCLI9__URG_LOW__SHIFT 0x8 27425 #define DAGB5_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc 27426 #define DAGB5_RDCLI9__MAX_BW__SHIFT 0xd 27427 #define DAGB5_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 27428 #define DAGB5_RDCLI9__MIN_BW__SHIFT 0x16 27429 #define DAGB5_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 27430 #define DAGB5_RDCLI9__MAX_OSD__SHIFT 0x1a 27431 #define DAGB5_RDCLI9__VIRT_CHAN_MASK 0x00000007L 27432 #define DAGB5_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 27433 #define DAGB5_RDCLI9__URG_HIGH_MASK 0x000000F0L 27434 #define DAGB5_RDCLI9__URG_LOW_MASK 0x00000F00L 27435 #define DAGB5_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L 27436 #define DAGB5_RDCLI9__MAX_BW_MASK 0x001FE000L 27437 #define DAGB5_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L 27438 #define DAGB5_RDCLI9__MIN_BW_MASK 0x01C00000L 27439 #define DAGB5_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 27440 #define DAGB5_RDCLI9__MAX_OSD_MASK 0xFC000000L 27441 //DAGB5_RDCLI10 27442 #define DAGB5_RDCLI10__VIRT_CHAN__SHIFT 0x0 27443 #define DAGB5_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 27444 #define DAGB5_RDCLI10__URG_HIGH__SHIFT 0x4 27445 #define DAGB5_RDCLI10__URG_LOW__SHIFT 0x8 27446 #define DAGB5_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc 27447 #define DAGB5_RDCLI10__MAX_BW__SHIFT 0xd 27448 #define DAGB5_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 27449 #define DAGB5_RDCLI10__MIN_BW__SHIFT 0x16 27450 #define DAGB5_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 27451 #define DAGB5_RDCLI10__MAX_OSD__SHIFT 0x1a 27452 #define DAGB5_RDCLI10__VIRT_CHAN_MASK 0x00000007L 27453 #define DAGB5_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 27454 #define DAGB5_RDCLI10__URG_HIGH_MASK 0x000000F0L 27455 #define DAGB5_RDCLI10__URG_LOW_MASK 0x00000F00L 27456 #define DAGB5_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L 27457 #define DAGB5_RDCLI10__MAX_BW_MASK 0x001FE000L 27458 #define DAGB5_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L 27459 #define DAGB5_RDCLI10__MIN_BW_MASK 0x01C00000L 27460 #define DAGB5_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 27461 #define DAGB5_RDCLI10__MAX_OSD_MASK 0xFC000000L 27462 //DAGB5_RDCLI11 27463 #define DAGB5_RDCLI11__VIRT_CHAN__SHIFT 0x0 27464 #define DAGB5_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 27465 #define DAGB5_RDCLI11__URG_HIGH__SHIFT 0x4 27466 #define DAGB5_RDCLI11__URG_LOW__SHIFT 0x8 27467 #define DAGB5_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc 27468 #define DAGB5_RDCLI11__MAX_BW__SHIFT 0xd 27469 #define DAGB5_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 27470 #define DAGB5_RDCLI11__MIN_BW__SHIFT 0x16 27471 #define DAGB5_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 27472 #define DAGB5_RDCLI11__MAX_OSD__SHIFT 0x1a 27473 #define DAGB5_RDCLI11__VIRT_CHAN_MASK 0x00000007L 27474 #define DAGB5_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 27475 #define DAGB5_RDCLI11__URG_HIGH_MASK 0x000000F0L 27476 #define DAGB5_RDCLI11__URG_LOW_MASK 0x00000F00L 27477 #define DAGB5_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L 27478 #define DAGB5_RDCLI11__MAX_BW_MASK 0x001FE000L 27479 #define DAGB5_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L 27480 #define DAGB5_RDCLI11__MIN_BW_MASK 0x01C00000L 27481 #define DAGB5_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 27482 #define DAGB5_RDCLI11__MAX_OSD_MASK 0xFC000000L 27483 //DAGB5_RDCLI12 27484 #define DAGB5_RDCLI12__VIRT_CHAN__SHIFT 0x0 27485 #define DAGB5_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 27486 #define DAGB5_RDCLI12__URG_HIGH__SHIFT 0x4 27487 #define DAGB5_RDCLI12__URG_LOW__SHIFT 0x8 27488 #define DAGB5_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc 27489 #define DAGB5_RDCLI12__MAX_BW__SHIFT 0xd 27490 #define DAGB5_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 27491 #define DAGB5_RDCLI12__MIN_BW__SHIFT 0x16 27492 #define DAGB5_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 27493 #define DAGB5_RDCLI12__MAX_OSD__SHIFT 0x1a 27494 #define DAGB5_RDCLI12__VIRT_CHAN_MASK 0x00000007L 27495 #define DAGB5_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 27496 #define DAGB5_RDCLI12__URG_HIGH_MASK 0x000000F0L 27497 #define DAGB5_RDCLI12__URG_LOW_MASK 0x00000F00L 27498 #define DAGB5_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L 27499 #define DAGB5_RDCLI12__MAX_BW_MASK 0x001FE000L 27500 #define DAGB5_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L 27501 #define DAGB5_RDCLI12__MIN_BW_MASK 0x01C00000L 27502 #define DAGB5_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 27503 #define DAGB5_RDCLI12__MAX_OSD_MASK 0xFC000000L 27504 //DAGB5_RDCLI13 27505 #define DAGB5_RDCLI13__VIRT_CHAN__SHIFT 0x0 27506 #define DAGB5_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 27507 #define DAGB5_RDCLI13__URG_HIGH__SHIFT 0x4 27508 #define DAGB5_RDCLI13__URG_LOW__SHIFT 0x8 27509 #define DAGB5_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc 27510 #define DAGB5_RDCLI13__MAX_BW__SHIFT 0xd 27511 #define DAGB5_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 27512 #define DAGB5_RDCLI13__MIN_BW__SHIFT 0x16 27513 #define DAGB5_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 27514 #define DAGB5_RDCLI13__MAX_OSD__SHIFT 0x1a 27515 #define DAGB5_RDCLI13__VIRT_CHAN_MASK 0x00000007L 27516 #define DAGB5_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 27517 #define DAGB5_RDCLI13__URG_HIGH_MASK 0x000000F0L 27518 #define DAGB5_RDCLI13__URG_LOW_MASK 0x00000F00L 27519 #define DAGB5_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L 27520 #define DAGB5_RDCLI13__MAX_BW_MASK 0x001FE000L 27521 #define DAGB5_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L 27522 #define DAGB5_RDCLI13__MIN_BW_MASK 0x01C00000L 27523 #define DAGB5_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 27524 #define DAGB5_RDCLI13__MAX_OSD_MASK 0xFC000000L 27525 //DAGB5_RDCLI14 27526 #define DAGB5_RDCLI14__VIRT_CHAN__SHIFT 0x0 27527 #define DAGB5_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 27528 #define DAGB5_RDCLI14__URG_HIGH__SHIFT 0x4 27529 #define DAGB5_RDCLI14__URG_LOW__SHIFT 0x8 27530 #define DAGB5_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc 27531 #define DAGB5_RDCLI14__MAX_BW__SHIFT 0xd 27532 #define DAGB5_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 27533 #define DAGB5_RDCLI14__MIN_BW__SHIFT 0x16 27534 #define DAGB5_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 27535 #define DAGB5_RDCLI14__MAX_OSD__SHIFT 0x1a 27536 #define DAGB5_RDCLI14__VIRT_CHAN_MASK 0x00000007L 27537 #define DAGB5_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 27538 #define DAGB5_RDCLI14__URG_HIGH_MASK 0x000000F0L 27539 #define DAGB5_RDCLI14__URG_LOW_MASK 0x00000F00L 27540 #define DAGB5_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L 27541 #define DAGB5_RDCLI14__MAX_BW_MASK 0x001FE000L 27542 #define DAGB5_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L 27543 #define DAGB5_RDCLI14__MIN_BW_MASK 0x01C00000L 27544 #define DAGB5_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 27545 #define DAGB5_RDCLI14__MAX_OSD_MASK 0xFC000000L 27546 //DAGB5_RDCLI15 27547 #define DAGB5_RDCLI15__VIRT_CHAN__SHIFT 0x0 27548 #define DAGB5_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 27549 #define DAGB5_RDCLI15__URG_HIGH__SHIFT 0x4 27550 #define DAGB5_RDCLI15__URG_LOW__SHIFT 0x8 27551 #define DAGB5_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc 27552 #define DAGB5_RDCLI15__MAX_BW__SHIFT 0xd 27553 #define DAGB5_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 27554 #define DAGB5_RDCLI15__MIN_BW__SHIFT 0x16 27555 #define DAGB5_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 27556 #define DAGB5_RDCLI15__MAX_OSD__SHIFT 0x1a 27557 #define DAGB5_RDCLI15__VIRT_CHAN_MASK 0x00000007L 27558 #define DAGB5_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 27559 #define DAGB5_RDCLI15__URG_HIGH_MASK 0x000000F0L 27560 #define DAGB5_RDCLI15__URG_LOW_MASK 0x00000F00L 27561 #define DAGB5_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L 27562 #define DAGB5_RDCLI15__MAX_BW_MASK 0x001FE000L 27563 #define DAGB5_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L 27564 #define DAGB5_RDCLI15__MIN_BW_MASK 0x01C00000L 27565 #define DAGB5_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 27566 #define DAGB5_RDCLI15__MAX_OSD_MASK 0xFC000000L 27567 //DAGB5_RD_CNTL 27568 #define DAGB5_RD_CNTL__SCLK_FREQ__SHIFT 0x0 27569 #define DAGB5_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 27570 #define DAGB5_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 27571 #define DAGB5_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 27572 #define DAGB5_RD_CNTL__IO_LEVEL__SHIFT 0x11 27573 #define DAGB5_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 27574 #define DAGB5_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 27575 #define DAGB5_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL 27576 #define DAGB5_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 27577 #define DAGB5_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 27578 #define DAGB5_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 27579 #define DAGB5_RD_CNTL__IO_LEVEL_MASK 0x000E0000L 27580 #define DAGB5_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 27581 #define DAGB5_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L 27582 //DAGB5_RD_GMI_CNTL 27583 #define DAGB5_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 27584 #define DAGB5_RD_GMI_CNTL__LEVEL__SHIFT 0x6 27585 #define DAGB5_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 27586 #define DAGB5_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 27587 #define DAGB5_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 27588 #define DAGB5_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L 27589 #define DAGB5_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 27590 #define DAGB5_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 27591 //DAGB5_RD_ADDR_DAGB 27592 #define DAGB5_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 27593 #define DAGB5_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 27594 #define DAGB5_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 27595 #define DAGB5_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 27596 #define DAGB5_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 27597 #define DAGB5_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 27598 #define DAGB5_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 27599 #define DAGB5_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 27600 //DAGB5_RD_OUTPUT_DAGB_MAX_BURST 27601 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 27602 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 27603 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 27604 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 27605 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 27606 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 27607 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 27608 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 27609 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 27610 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 27611 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 27612 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 27613 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 27614 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 27615 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 27616 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 27617 //DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER 27618 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 27619 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 27620 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 27621 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 27622 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 27623 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 27624 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 27625 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 27626 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 27627 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 27628 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 27629 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 27630 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 27631 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 27632 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 27633 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 27634 //DAGB5_RD_CGTT_CLK_CTRL 27635 #define DAGB5_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 27636 #define DAGB5_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 27637 #define DAGB5_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 27638 #define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 27639 #define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 27640 #define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 27641 #define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 27642 #define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 27643 #define DAGB5_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 27644 #define DAGB5_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 27645 #define DAGB5_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 27646 #define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 27647 #define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 27648 #define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 27649 #define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 27650 #define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 27651 //DAGB5_L1TLB_RD_CGTT_CLK_CTRL 27652 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 27653 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 27654 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 27655 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 27656 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 27657 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 27658 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 27659 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 27660 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 27661 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 27662 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 27663 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 27664 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 27665 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 27666 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 27667 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 27668 //DAGB5_ATCVM_RD_CGTT_CLK_CTRL 27669 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 27670 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 27671 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 27672 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 27673 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 27674 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 27675 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 27676 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 27677 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 27678 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 27679 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 27680 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 27681 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 27682 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 27683 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 27684 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 27685 //DAGB5_RD_ADDR_DAGB_MAX_BURST0 27686 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 27687 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 27688 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 27689 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 27690 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 27691 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 27692 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 27693 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 27694 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 27695 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 27696 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 27697 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 27698 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 27699 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 27700 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 27701 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 27702 //DAGB5_RD_ADDR_DAGB_LAZY_TIMER0 27703 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 27704 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 27705 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 27706 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 27707 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 27708 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 27709 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 27710 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 27711 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 27712 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 27713 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 27714 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 27715 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 27716 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 27717 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 27718 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 27719 //DAGB5_RD_ADDR_DAGB_MAX_BURST1 27720 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 27721 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 27722 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 27723 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 27724 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 27725 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 27726 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 27727 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 27728 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 27729 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 27730 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 27731 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 27732 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 27733 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 27734 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 27735 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 27736 //DAGB5_RD_ADDR_DAGB_LAZY_TIMER1 27737 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 27738 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 27739 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 27740 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 27741 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 27742 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 27743 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 27744 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 27745 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 27746 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 27747 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 27748 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 27749 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 27750 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 27751 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 27752 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 27753 //DAGB5_RD_VC0_CNTL 27754 #define DAGB5_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 27755 #define DAGB5_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 27756 #define DAGB5_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 27757 #define DAGB5_RD_VC0_CNTL__MAX_BW__SHIFT 0xc 27758 #define DAGB5_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 27759 #define DAGB5_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 27760 #define DAGB5_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 27761 #define DAGB5_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 27762 #define DAGB5_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 27763 #define DAGB5_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 27764 #define DAGB5_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 27765 #define DAGB5_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L 27766 #define DAGB5_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 27767 #define DAGB5_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L 27768 #define DAGB5_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 27769 #define DAGB5_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 27770 //DAGB5_RD_VC1_CNTL 27771 #define DAGB5_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 27772 #define DAGB5_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 27773 #define DAGB5_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 27774 #define DAGB5_RD_VC1_CNTL__MAX_BW__SHIFT 0xc 27775 #define DAGB5_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 27776 #define DAGB5_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 27777 #define DAGB5_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 27778 #define DAGB5_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 27779 #define DAGB5_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 27780 #define DAGB5_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 27781 #define DAGB5_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 27782 #define DAGB5_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L 27783 #define DAGB5_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 27784 #define DAGB5_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L 27785 #define DAGB5_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 27786 #define DAGB5_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 27787 //DAGB5_RD_VC2_CNTL 27788 #define DAGB5_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 27789 #define DAGB5_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 27790 #define DAGB5_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 27791 #define DAGB5_RD_VC2_CNTL__MAX_BW__SHIFT 0xc 27792 #define DAGB5_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 27793 #define DAGB5_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 27794 #define DAGB5_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 27795 #define DAGB5_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 27796 #define DAGB5_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 27797 #define DAGB5_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 27798 #define DAGB5_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 27799 #define DAGB5_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L 27800 #define DAGB5_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 27801 #define DAGB5_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L 27802 #define DAGB5_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 27803 #define DAGB5_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 27804 //DAGB5_RD_VC3_CNTL 27805 #define DAGB5_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 27806 #define DAGB5_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 27807 #define DAGB5_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 27808 #define DAGB5_RD_VC3_CNTL__MAX_BW__SHIFT 0xc 27809 #define DAGB5_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 27810 #define DAGB5_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 27811 #define DAGB5_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 27812 #define DAGB5_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 27813 #define DAGB5_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 27814 #define DAGB5_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 27815 #define DAGB5_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 27816 #define DAGB5_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L 27817 #define DAGB5_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 27818 #define DAGB5_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L 27819 #define DAGB5_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 27820 #define DAGB5_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 27821 //DAGB5_RD_VC4_CNTL 27822 #define DAGB5_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 27823 #define DAGB5_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 27824 #define DAGB5_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 27825 #define DAGB5_RD_VC4_CNTL__MAX_BW__SHIFT 0xc 27826 #define DAGB5_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 27827 #define DAGB5_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 27828 #define DAGB5_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 27829 #define DAGB5_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 27830 #define DAGB5_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 27831 #define DAGB5_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 27832 #define DAGB5_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 27833 #define DAGB5_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L 27834 #define DAGB5_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 27835 #define DAGB5_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L 27836 #define DAGB5_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 27837 #define DAGB5_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 27838 //DAGB5_RD_VC5_CNTL 27839 #define DAGB5_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 27840 #define DAGB5_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 27841 #define DAGB5_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 27842 #define DAGB5_RD_VC5_CNTL__MAX_BW__SHIFT 0xc 27843 #define DAGB5_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 27844 #define DAGB5_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 27845 #define DAGB5_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 27846 #define DAGB5_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 27847 #define DAGB5_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 27848 #define DAGB5_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 27849 #define DAGB5_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 27850 #define DAGB5_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L 27851 #define DAGB5_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 27852 #define DAGB5_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L 27853 #define DAGB5_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 27854 #define DAGB5_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 27855 //DAGB5_RD_VC6_CNTL 27856 #define DAGB5_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 27857 #define DAGB5_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 27858 #define DAGB5_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 27859 #define DAGB5_RD_VC6_CNTL__MAX_BW__SHIFT 0xc 27860 #define DAGB5_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 27861 #define DAGB5_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 27862 #define DAGB5_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 27863 #define DAGB5_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 27864 #define DAGB5_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 27865 #define DAGB5_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 27866 #define DAGB5_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 27867 #define DAGB5_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L 27868 #define DAGB5_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 27869 #define DAGB5_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L 27870 #define DAGB5_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 27871 #define DAGB5_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 27872 //DAGB5_RD_VC7_CNTL 27873 #define DAGB5_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 27874 #define DAGB5_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 27875 #define DAGB5_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 27876 #define DAGB5_RD_VC7_CNTL__MAX_BW__SHIFT 0xc 27877 #define DAGB5_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 27878 #define DAGB5_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 27879 #define DAGB5_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 27880 #define DAGB5_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 27881 #define DAGB5_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 27882 #define DAGB5_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 27883 #define DAGB5_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 27884 #define DAGB5_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L 27885 #define DAGB5_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 27886 #define DAGB5_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L 27887 #define DAGB5_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 27888 #define DAGB5_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 27889 //DAGB5_RD_CNTL_MISC 27890 #define DAGB5_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 27891 #define DAGB5_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 27892 #define DAGB5_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 27893 #define DAGB5_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 27894 #define DAGB5_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 27895 #define DAGB5_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 27896 #define DAGB5_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a 27897 #define DAGB5_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 27898 #define DAGB5_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 27899 #define DAGB5_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 27900 #define DAGB5_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 27901 #define DAGB5_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 27902 #define DAGB5_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 27903 #define DAGB5_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L 27904 //DAGB5_RD_TLB_CREDIT 27905 #define DAGB5_RD_TLB_CREDIT__TLB0__SHIFT 0x0 27906 #define DAGB5_RD_TLB_CREDIT__TLB1__SHIFT 0x5 27907 #define DAGB5_RD_TLB_CREDIT__TLB2__SHIFT 0xa 27908 #define DAGB5_RD_TLB_CREDIT__TLB3__SHIFT 0xf 27909 #define DAGB5_RD_TLB_CREDIT__TLB4__SHIFT 0x14 27910 #define DAGB5_RD_TLB_CREDIT__TLB5__SHIFT 0x19 27911 #define DAGB5_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL 27912 #define DAGB5_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L 27913 #define DAGB5_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L 27914 #define DAGB5_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L 27915 #define DAGB5_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L 27916 #define DAGB5_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L 27917 //DAGB5_RDCLI_ASK_PENDING 27918 #define DAGB5_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 27919 #define DAGB5_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 27920 //DAGB5_RDCLI_GO_PENDING 27921 #define DAGB5_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 27922 #define DAGB5_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 27923 //DAGB5_RDCLI_GBLSEND_PENDING 27924 #define DAGB5_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 27925 #define DAGB5_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 27926 //DAGB5_RDCLI_TLB_PENDING 27927 #define DAGB5_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 27928 #define DAGB5_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 27929 //DAGB5_RDCLI_OARB_PENDING 27930 #define DAGB5_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 27931 #define DAGB5_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 27932 //DAGB5_RDCLI_OSD_PENDING 27933 #define DAGB5_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 27934 #define DAGB5_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 27935 //DAGB5_WRCLI0 27936 #define DAGB5_WRCLI0__VIRT_CHAN__SHIFT 0x0 27937 #define DAGB5_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 27938 #define DAGB5_WRCLI0__URG_HIGH__SHIFT 0x4 27939 #define DAGB5_WRCLI0__URG_LOW__SHIFT 0x8 27940 #define DAGB5_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc 27941 #define DAGB5_WRCLI0__MAX_BW__SHIFT 0xd 27942 #define DAGB5_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 27943 #define DAGB5_WRCLI0__MIN_BW__SHIFT 0x16 27944 #define DAGB5_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 27945 #define DAGB5_WRCLI0__MAX_OSD__SHIFT 0x1a 27946 #define DAGB5_WRCLI0__VIRT_CHAN_MASK 0x00000007L 27947 #define DAGB5_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 27948 #define DAGB5_WRCLI0__URG_HIGH_MASK 0x000000F0L 27949 #define DAGB5_WRCLI0__URG_LOW_MASK 0x00000F00L 27950 #define DAGB5_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L 27951 #define DAGB5_WRCLI0__MAX_BW_MASK 0x001FE000L 27952 #define DAGB5_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L 27953 #define DAGB5_WRCLI0__MIN_BW_MASK 0x01C00000L 27954 #define DAGB5_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 27955 #define DAGB5_WRCLI0__MAX_OSD_MASK 0xFC000000L 27956 //DAGB5_WRCLI1 27957 #define DAGB5_WRCLI1__VIRT_CHAN__SHIFT 0x0 27958 #define DAGB5_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 27959 #define DAGB5_WRCLI1__URG_HIGH__SHIFT 0x4 27960 #define DAGB5_WRCLI1__URG_LOW__SHIFT 0x8 27961 #define DAGB5_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc 27962 #define DAGB5_WRCLI1__MAX_BW__SHIFT 0xd 27963 #define DAGB5_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 27964 #define DAGB5_WRCLI1__MIN_BW__SHIFT 0x16 27965 #define DAGB5_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 27966 #define DAGB5_WRCLI1__MAX_OSD__SHIFT 0x1a 27967 #define DAGB5_WRCLI1__VIRT_CHAN_MASK 0x00000007L 27968 #define DAGB5_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 27969 #define DAGB5_WRCLI1__URG_HIGH_MASK 0x000000F0L 27970 #define DAGB5_WRCLI1__URG_LOW_MASK 0x00000F00L 27971 #define DAGB5_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L 27972 #define DAGB5_WRCLI1__MAX_BW_MASK 0x001FE000L 27973 #define DAGB5_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L 27974 #define DAGB5_WRCLI1__MIN_BW_MASK 0x01C00000L 27975 #define DAGB5_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 27976 #define DAGB5_WRCLI1__MAX_OSD_MASK 0xFC000000L 27977 //DAGB5_WRCLI2 27978 #define DAGB5_WRCLI2__VIRT_CHAN__SHIFT 0x0 27979 #define DAGB5_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 27980 #define DAGB5_WRCLI2__URG_HIGH__SHIFT 0x4 27981 #define DAGB5_WRCLI2__URG_LOW__SHIFT 0x8 27982 #define DAGB5_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc 27983 #define DAGB5_WRCLI2__MAX_BW__SHIFT 0xd 27984 #define DAGB5_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 27985 #define DAGB5_WRCLI2__MIN_BW__SHIFT 0x16 27986 #define DAGB5_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 27987 #define DAGB5_WRCLI2__MAX_OSD__SHIFT 0x1a 27988 #define DAGB5_WRCLI2__VIRT_CHAN_MASK 0x00000007L 27989 #define DAGB5_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 27990 #define DAGB5_WRCLI2__URG_HIGH_MASK 0x000000F0L 27991 #define DAGB5_WRCLI2__URG_LOW_MASK 0x00000F00L 27992 #define DAGB5_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L 27993 #define DAGB5_WRCLI2__MAX_BW_MASK 0x001FE000L 27994 #define DAGB5_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L 27995 #define DAGB5_WRCLI2__MIN_BW_MASK 0x01C00000L 27996 #define DAGB5_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 27997 #define DAGB5_WRCLI2__MAX_OSD_MASK 0xFC000000L 27998 //DAGB5_WRCLI3 27999 #define DAGB5_WRCLI3__VIRT_CHAN__SHIFT 0x0 28000 #define DAGB5_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 28001 #define DAGB5_WRCLI3__URG_HIGH__SHIFT 0x4 28002 #define DAGB5_WRCLI3__URG_LOW__SHIFT 0x8 28003 #define DAGB5_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc 28004 #define DAGB5_WRCLI3__MAX_BW__SHIFT 0xd 28005 #define DAGB5_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 28006 #define DAGB5_WRCLI3__MIN_BW__SHIFT 0x16 28007 #define DAGB5_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 28008 #define DAGB5_WRCLI3__MAX_OSD__SHIFT 0x1a 28009 #define DAGB5_WRCLI3__VIRT_CHAN_MASK 0x00000007L 28010 #define DAGB5_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 28011 #define DAGB5_WRCLI3__URG_HIGH_MASK 0x000000F0L 28012 #define DAGB5_WRCLI3__URG_LOW_MASK 0x00000F00L 28013 #define DAGB5_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L 28014 #define DAGB5_WRCLI3__MAX_BW_MASK 0x001FE000L 28015 #define DAGB5_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L 28016 #define DAGB5_WRCLI3__MIN_BW_MASK 0x01C00000L 28017 #define DAGB5_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 28018 #define DAGB5_WRCLI3__MAX_OSD_MASK 0xFC000000L 28019 //DAGB5_WRCLI4 28020 #define DAGB5_WRCLI4__VIRT_CHAN__SHIFT 0x0 28021 #define DAGB5_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 28022 #define DAGB5_WRCLI4__URG_HIGH__SHIFT 0x4 28023 #define DAGB5_WRCLI4__URG_LOW__SHIFT 0x8 28024 #define DAGB5_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc 28025 #define DAGB5_WRCLI4__MAX_BW__SHIFT 0xd 28026 #define DAGB5_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 28027 #define DAGB5_WRCLI4__MIN_BW__SHIFT 0x16 28028 #define DAGB5_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 28029 #define DAGB5_WRCLI4__MAX_OSD__SHIFT 0x1a 28030 #define DAGB5_WRCLI4__VIRT_CHAN_MASK 0x00000007L 28031 #define DAGB5_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 28032 #define DAGB5_WRCLI4__URG_HIGH_MASK 0x000000F0L 28033 #define DAGB5_WRCLI4__URG_LOW_MASK 0x00000F00L 28034 #define DAGB5_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L 28035 #define DAGB5_WRCLI4__MAX_BW_MASK 0x001FE000L 28036 #define DAGB5_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L 28037 #define DAGB5_WRCLI4__MIN_BW_MASK 0x01C00000L 28038 #define DAGB5_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 28039 #define DAGB5_WRCLI4__MAX_OSD_MASK 0xFC000000L 28040 //DAGB5_WRCLI5 28041 #define DAGB5_WRCLI5__VIRT_CHAN__SHIFT 0x0 28042 #define DAGB5_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 28043 #define DAGB5_WRCLI5__URG_HIGH__SHIFT 0x4 28044 #define DAGB5_WRCLI5__URG_LOW__SHIFT 0x8 28045 #define DAGB5_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc 28046 #define DAGB5_WRCLI5__MAX_BW__SHIFT 0xd 28047 #define DAGB5_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 28048 #define DAGB5_WRCLI5__MIN_BW__SHIFT 0x16 28049 #define DAGB5_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 28050 #define DAGB5_WRCLI5__MAX_OSD__SHIFT 0x1a 28051 #define DAGB5_WRCLI5__VIRT_CHAN_MASK 0x00000007L 28052 #define DAGB5_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 28053 #define DAGB5_WRCLI5__URG_HIGH_MASK 0x000000F0L 28054 #define DAGB5_WRCLI5__URG_LOW_MASK 0x00000F00L 28055 #define DAGB5_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L 28056 #define DAGB5_WRCLI5__MAX_BW_MASK 0x001FE000L 28057 #define DAGB5_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L 28058 #define DAGB5_WRCLI5__MIN_BW_MASK 0x01C00000L 28059 #define DAGB5_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 28060 #define DAGB5_WRCLI5__MAX_OSD_MASK 0xFC000000L 28061 //DAGB5_WRCLI6 28062 #define DAGB5_WRCLI6__VIRT_CHAN__SHIFT 0x0 28063 #define DAGB5_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 28064 #define DAGB5_WRCLI6__URG_HIGH__SHIFT 0x4 28065 #define DAGB5_WRCLI6__URG_LOW__SHIFT 0x8 28066 #define DAGB5_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc 28067 #define DAGB5_WRCLI6__MAX_BW__SHIFT 0xd 28068 #define DAGB5_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 28069 #define DAGB5_WRCLI6__MIN_BW__SHIFT 0x16 28070 #define DAGB5_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 28071 #define DAGB5_WRCLI6__MAX_OSD__SHIFT 0x1a 28072 #define DAGB5_WRCLI6__VIRT_CHAN_MASK 0x00000007L 28073 #define DAGB5_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 28074 #define DAGB5_WRCLI6__URG_HIGH_MASK 0x000000F0L 28075 #define DAGB5_WRCLI6__URG_LOW_MASK 0x00000F00L 28076 #define DAGB5_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L 28077 #define DAGB5_WRCLI6__MAX_BW_MASK 0x001FE000L 28078 #define DAGB5_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L 28079 #define DAGB5_WRCLI6__MIN_BW_MASK 0x01C00000L 28080 #define DAGB5_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 28081 #define DAGB5_WRCLI6__MAX_OSD_MASK 0xFC000000L 28082 //DAGB5_WRCLI7 28083 #define DAGB5_WRCLI7__VIRT_CHAN__SHIFT 0x0 28084 #define DAGB5_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 28085 #define DAGB5_WRCLI7__URG_HIGH__SHIFT 0x4 28086 #define DAGB5_WRCLI7__URG_LOW__SHIFT 0x8 28087 #define DAGB5_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc 28088 #define DAGB5_WRCLI7__MAX_BW__SHIFT 0xd 28089 #define DAGB5_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 28090 #define DAGB5_WRCLI7__MIN_BW__SHIFT 0x16 28091 #define DAGB5_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 28092 #define DAGB5_WRCLI7__MAX_OSD__SHIFT 0x1a 28093 #define DAGB5_WRCLI7__VIRT_CHAN_MASK 0x00000007L 28094 #define DAGB5_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 28095 #define DAGB5_WRCLI7__URG_HIGH_MASK 0x000000F0L 28096 #define DAGB5_WRCLI7__URG_LOW_MASK 0x00000F00L 28097 #define DAGB5_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L 28098 #define DAGB5_WRCLI7__MAX_BW_MASK 0x001FE000L 28099 #define DAGB5_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L 28100 #define DAGB5_WRCLI7__MIN_BW_MASK 0x01C00000L 28101 #define DAGB5_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 28102 #define DAGB5_WRCLI7__MAX_OSD_MASK 0xFC000000L 28103 //DAGB5_WRCLI8 28104 #define DAGB5_WRCLI8__VIRT_CHAN__SHIFT 0x0 28105 #define DAGB5_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 28106 #define DAGB5_WRCLI8__URG_HIGH__SHIFT 0x4 28107 #define DAGB5_WRCLI8__URG_LOW__SHIFT 0x8 28108 #define DAGB5_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc 28109 #define DAGB5_WRCLI8__MAX_BW__SHIFT 0xd 28110 #define DAGB5_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 28111 #define DAGB5_WRCLI8__MIN_BW__SHIFT 0x16 28112 #define DAGB5_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 28113 #define DAGB5_WRCLI8__MAX_OSD__SHIFT 0x1a 28114 #define DAGB5_WRCLI8__VIRT_CHAN_MASK 0x00000007L 28115 #define DAGB5_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 28116 #define DAGB5_WRCLI8__URG_HIGH_MASK 0x000000F0L 28117 #define DAGB5_WRCLI8__URG_LOW_MASK 0x00000F00L 28118 #define DAGB5_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L 28119 #define DAGB5_WRCLI8__MAX_BW_MASK 0x001FE000L 28120 #define DAGB5_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L 28121 #define DAGB5_WRCLI8__MIN_BW_MASK 0x01C00000L 28122 #define DAGB5_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 28123 #define DAGB5_WRCLI8__MAX_OSD_MASK 0xFC000000L 28124 //DAGB5_WRCLI9 28125 #define DAGB5_WRCLI9__VIRT_CHAN__SHIFT 0x0 28126 #define DAGB5_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 28127 #define DAGB5_WRCLI9__URG_HIGH__SHIFT 0x4 28128 #define DAGB5_WRCLI9__URG_LOW__SHIFT 0x8 28129 #define DAGB5_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc 28130 #define DAGB5_WRCLI9__MAX_BW__SHIFT 0xd 28131 #define DAGB5_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 28132 #define DAGB5_WRCLI9__MIN_BW__SHIFT 0x16 28133 #define DAGB5_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 28134 #define DAGB5_WRCLI9__MAX_OSD__SHIFT 0x1a 28135 #define DAGB5_WRCLI9__VIRT_CHAN_MASK 0x00000007L 28136 #define DAGB5_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 28137 #define DAGB5_WRCLI9__URG_HIGH_MASK 0x000000F0L 28138 #define DAGB5_WRCLI9__URG_LOW_MASK 0x00000F00L 28139 #define DAGB5_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L 28140 #define DAGB5_WRCLI9__MAX_BW_MASK 0x001FE000L 28141 #define DAGB5_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L 28142 #define DAGB5_WRCLI9__MIN_BW_MASK 0x01C00000L 28143 #define DAGB5_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 28144 #define DAGB5_WRCLI9__MAX_OSD_MASK 0xFC000000L 28145 //DAGB5_WRCLI10 28146 #define DAGB5_WRCLI10__VIRT_CHAN__SHIFT 0x0 28147 #define DAGB5_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 28148 #define DAGB5_WRCLI10__URG_HIGH__SHIFT 0x4 28149 #define DAGB5_WRCLI10__URG_LOW__SHIFT 0x8 28150 #define DAGB5_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc 28151 #define DAGB5_WRCLI10__MAX_BW__SHIFT 0xd 28152 #define DAGB5_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 28153 #define DAGB5_WRCLI10__MIN_BW__SHIFT 0x16 28154 #define DAGB5_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 28155 #define DAGB5_WRCLI10__MAX_OSD__SHIFT 0x1a 28156 #define DAGB5_WRCLI10__VIRT_CHAN_MASK 0x00000007L 28157 #define DAGB5_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 28158 #define DAGB5_WRCLI10__URG_HIGH_MASK 0x000000F0L 28159 #define DAGB5_WRCLI10__URG_LOW_MASK 0x00000F00L 28160 #define DAGB5_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L 28161 #define DAGB5_WRCLI10__MAX_BW_MASK 0x001FE000L 28162 #define DAGB5_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L 28163 #define DAGB5_WRCLI10__MIN_BW_MASK 0x01C00000L 28164 #define DAGB5_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 28165 #define DAGB5_WRCLI10__MAX_OSD_MASK 0xFC000000L 28166 //DAGB5_WRCLI11 28167 #define DAGB5_WRCLI11__VIRT_CHAN__SHIFT 0x0 28168 #define DAGB5_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 28169 #define DAGB5_WRCLI11__URG_HIGH__SHIFT 0x4 28170 #define DAGB5_WRCLI11__URG_LOW__SHIFT 0x8 28171 #define DAGB5_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc 28172 #define DAGB5_WRCLI11__MAX_BW__SHIFT 0xd 28173 #define DAGB5_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 28174 #define DAGB5_WRCLI11__MIN_BW__SHIFT 0x16 28175 #define DAGB5_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 28176 #define DAGB5_WRCLI11__MAX_OSD__SHIFT 0x1a 28177 #define DAGB5_WRCLI11__VIRT_CHAN_MASK 0x00000007L 28178 #define DAGB5_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 28179 #define DAGB5_WRCLI11__URG_HIGH_MASK 0x000000F0L 28180 #define DAGB5_WRCLI11__URG_LOW_MASK 0x00000F00L 28181 #define DAGB5_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L 28182 #define DAGB5_WRCLI11__MAX_BW_MASK 0x001FE000L 28183 #define DAGB5_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L 28184 #define DAGB5_WRCLI11__MIN_BW_MASK 0x01C00000L 28185 #define DAGB5_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 28186 #define DAGB5_WRCLI11__MAX_OSD_MASK 0xFC000000L 28187 //DAGB5_WRCLI12 28188 #define DAGB5_WRCLI12__VIRT_CHAN__SHIFT 0x0 28189 #define DAGB5_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 28190 #define DAGB5_WRCLI12__URG_HIGH__SHIFT 0x4 28191 #define DAGB5_WRCLI12__URG_LOW__SHIFT 0x8 28192 #define DAGB5_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc 28193 #define DAGB5_WRCLI12__MAX_BW__SHIFT 0xd 28194 #define DAGB5_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 28195 #define DAGB5_WRCLI12__MIN_BW__SHIFT 0x16 28196 #define DAGB5_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 28197 #define DAGB5_WRCLI12__MAX_OSD__SHIFT 0x1a 28198 #define DAGB5_WRCLI12__VIRT_CHAN_MASK 0x00000007L 28199 #define DAGB5_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 28200 #define DAGB5_WRCLI12__URG_HIGH_MASK 0x000000F0L 28201 #define DAGB5_WRCLI12__URG_LOW_MASK 0x00000F00L 28202 #define DAGB5_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L 28203 #define DAGB5_WRCLI12__MAX_BW_MASK 0x001FE000L 28204 #define DAGB5_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L 28205 #define DAGB5_WRCLI12__MIN_BW_MASK 0x01C00000L 28206 #define DAGB5_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 28207 #define DAGB5_WRCLI12__MAX_OSD_MASK 0xFC000000L 28208 //DAGB5_WRCLI13 28209 #define DAGB5_WRCLI13__VIRT_CHAN__SHIFT 0x0 28210 #define DAGB5_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 28211 #define DAGB5_WRCLI13__URG_HIGH__SHIFT 0x4 28212 #define DAGB5_WRCLI13__URG_LOW__SHIFT 0x8 28213 #define DAGB5_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc 28214 #define DAGB5_WRCLI13__MAX_BW__SHIFT 0xd 28215 #define DAGB5_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 28216 #define DAGB5_WRCLI13__MIN_BW__SHIFT 0x16 28217 #define DAGB5_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 28218 #define DAGB5_WRCLI13__MAX_OSD__SHIFT 0x1a 28219 #define DAGB5_WRCLI13__VIRT_CHAN_MASK 0x00000007L 28220 #define DAGB5_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 28221 #define DAGB5_WRCLI13__URG_HIGH_MASK 0x000000F0L 28222 #define DAGB5_WRCLI13__URG_LOW_MASK 0x00000F00L 28223 #define DAGB5_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L 28224 #define DAGB5_WRCLI13__MAX_BW_MASK 0x001FE000L 28225 #define DAGB5_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L 28226 #define DAGB5_WRCLI13__MIN_BW_MASK 0x01C00000L 28227 #define DAGB5_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 28228 #define DAGB5_WRCLI13__MAX_OSD_MASK 0xFC000000L 28229 //DAGB5_WRCLI14 28230 #define DAGB5_WRCLI14__VIRT_CHAN__SHIFT 0x0 28231 #define DAGB5_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 28232 #define DAGB5_WRCLI14__URG_HIGH__SHIFT 0x4 28233 #define DAGB5_WRCLI14__URG_LOW__SHIFT 0x8 28234 #define DAGB5_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc 28235 #define DAGB5_WRCLI14__MAX_BW__SHIFT 0xd 28236 #define DAGB5_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 28237 #define DAGB5_WRCLI14__MIN_BW__SHIFT 0x16 28238 #define DAGB5_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 28239 #define DAGB5_WRCLI14__MAX_OSD__SHIFT 0x1a 28240 #define DAGB5_WRCLI14__VIRT_CHAN_MASK 0x00000007L 28241 #define DAGB5_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 28242 #define DAGB5_WRCLI14__URG_HIGH_MASK 0x000000F0L 28243 #define DAGB5_WRCLI14__URG_LOW_MASK 0x00000F00L 28244 #define DAGB5_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L 28245 #define DAGB5_WRCLI14__MAX_BW_MASK 0x001FE000L 28246 #define DAGB5_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L 28247 #define DAGB5_WRCLI14__MIN_BW_MASK 0x01C00000L 28248 #define DAGB5_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 28249 #define DAGB5_WRCLI14__MAX_OSD_MASK 0xFC000000L 28250 //DAGB5_WRCLI15 28251 #define DAGB5_WRCLI15__VIRT_CHAN__SHIFT 0x0 28252 #define DAGB5_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 28253 #define DAGB5_WRCLI15__URG_HIGH__SHIFT 0x4 28254 #define DAGB5_WRCLI15__URG_LOW__SHIFT 0x8 28255 #define DAGB5_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc 28256 #define DAGB5_WRCLI15__MAX_BW__SHIFT 0xd 28257 #define DAGB5_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 28258 #define DAGB5_WRCLI15__MIN_BW__SHIFT 0x16 28259 #define DAGB5_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 28260 #define DAGB5_WRCLI15__MAX_OSD__SHIFT 0x1a 28261 #define DAGB5_WRCLI15__VIRT_CHAN_MASK 0x00000007L 28262 #define DAGB5_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 28263 #define DAGB5_WRCLI15__URG_HIGH_MASK 0x000000F0L 28264 #define DAGB5_WRCLI15__URG_LOW_MASK 0x00000F00L 28265 #define DAGB5_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L 28266 #define DAGB5_WRCLI15__MAX_BW_MASK 0x001FE000L 28267 #define DAGB5_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L 28268 #define DAGB5_WRCLI15__MIN_BW_MASK 0x01C00000L 28269 #define DAGB5_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 28270 #define DAGB5_WRCLI15__MAX_OSD_MASK 0xFC000000L 28271 //DAGB5_WR_CNTL 28272 #define DAGB5_WR_CNTL__SCLK_FREQ__SHIFT 0x0 28273 #define DAGB5_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 28274 #define DAGB5_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 28275 #define DAGB5_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 28276 #define DAGB5_WR_CNTL__IO_LEVEL__SHIFT 0x11 28277 #define DAGB5_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 28278 #define DAGB5_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 28279 #define DAGB5_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL 28280 #define DAGB5_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 28281 #define DAGB5_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 28282 #define DAGB5_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 28283 #define DAGB5_WR_CNTL__IO_LEVEL_MASK 0x000E0000L 28284 #define DAGB5_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 28285 #define DAGB5_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L 28286 //DAGB5_WR_GMI_CNTL 28287 #define DAGB5_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 28288 #define DAGB5_WR_GMI_CNTL__LEVEL__SHIFT 0x6 28289 #define DAGB5_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 28290 #define DAGB5_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 28291 #define DAGB5_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 28292 #define DAGB5_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L 28293 #define DAGB5_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 28294 #define DAGB5_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 28295 //DAGB5_WR_ADDR_DAGB 28296 #define DAGB5_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 28297 #define DAGB5_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 28298 #define DAGB5_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 28299 #define DAGB5_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 28300 #define DAGB5_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 28301 #define DAGB5_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 28302 #define DAGB5_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 28303 #define DAGB5_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 28304 //DAGB5_WR_OUTPUT_DAGB_MAX_BURST 28305 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 28306 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 28307 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 28308 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 28309 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 28310 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 28311 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 28312 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 28313 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 28314 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 28315 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 28316 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 28317 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 28318 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 28319 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 28320 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 28321 //DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER 28322 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 28323 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 28324 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 28325 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 28326 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 28327 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 28328 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 28329 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 28330 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 28331 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 28332 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 28333 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 28334 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 28335 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 28336 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 28337 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 28338 //DAGB5_WR_CGTT_CLK_CTRL 28339 #define DAGB5_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 28340 #define DAGB5_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 28341 #define DAGB5_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 28342 #define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 28343 #define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 28344 #define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 28345 #define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 28346 #define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 28347 #define DAGB5_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 28348 #define DAGB5_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 28349 #define DAGB5_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 28350 #define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 28351 #define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 28352 #define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 28353 #define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 28354 #define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 28355 //DAGB5_L1TLB_WR_CGTT_CLK_CTRL 28356 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 28357 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 28358 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 28359 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 28360 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 28361 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 28362 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 28363 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 28364 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 28365 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 28366 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 28367 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 28368 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 28369 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 28370 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 28371 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 28372 //DAGB5_ATCVM_WR_CGTT_CLK_CTRL 28373 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 28374 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 28375 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 28376 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 28377 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 28378 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 28379 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 28380 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 28381 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 28382 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 28383 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 28384 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 28385 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 28386 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 28387 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 28388 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 28389 //DAGB5_WR_ADDR_DAGB_MAX_BURST0 28390 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 28391 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 28392 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 28393 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 28394 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 28395 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 28396 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 28397 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 28398 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 28399 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 28400 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 28401 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 28402 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 28403 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 28404 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 28405 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 28406 //DAGB5_WR_ADDR_DAGB_LAZY_TIMER0 28407 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 28408 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 28409 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 28410 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 28411 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 28412 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 28413 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 28414 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 28415 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 28416 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 28417 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 28418 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 28419 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 28420 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 28421 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 28422 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 28423 //DAGB5_WR_ADDR_DAGB_MAX_BURST1 28424 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 28425 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 28426 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 28427 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 28428 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 28429 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 28430 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 28431 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 28432 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 28433 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 28434 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 28435 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 28436 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 28437 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 28438 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 28439 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 28440 //DAGB5_WR_ADDR_DAGB_LAZY_TIMER1 28441 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 28442 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 28443 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 28444 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 28445 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 28446 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 28447 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 28448 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 28449 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 28450 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 28451 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 28452 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 28453 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 28454 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 28455 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 28456 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 28457 //DAGB5_WR_DATA_DAGB 28458 #define DAGB5_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 28459 #define DAGB5_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 28460 #define DAGB5_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 28461 #define DAGB5_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 28462 #define DAGB5_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L 28463 #define DAGB5_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 28464 #define DAGB5_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 28465 #define DAGB5_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L 28466 //DAGB5_WR_DATA_DAGB_MAX_BURST0 28467 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 28468 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 28469 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 28470 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 28471 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 28472 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 28473 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 28474 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 28475 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 28476 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 28477 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 28478 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 28479 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 28480 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 28481 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 28482 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 28483 //DAGB5_WR_DATA_DAGB_LAZY_TIMER0 28484 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 28485 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 28486 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 28487 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 28488 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 28489 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 28490 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 28491 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 28492 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 28493 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 28494 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 28495 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 28496 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 28497 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 28498 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 28499 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 28500 //DAGB5_WR_DATA_DAGB_MAX_BURST1 28501 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 28502 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 28503 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 28504 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 28505 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 28506 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 28507 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 28508 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 28509 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 28510 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 28511 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 28512 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 28513 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 28514 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 28515 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 28516 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 28517 //DAGB5_WR_DATA_DAGB_LAZY_TIMER1 28518 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 28519 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 28520 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 28521 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 28522 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 28523 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 28524 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 28525 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 28526 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 28527 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 28528 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 28529 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 28530 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 28531 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 28532 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 28533 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 28534 //DAGB5_WR_VC0_CNTL 28535 #define DAGB5_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 28536 #define DAGB5_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 28537 #define DAGB5_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 28538 #define DAGB5_WR_VC0_CNTL__MAX_BW__SHIFT 0xc 28539 #define DAGB5_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 28540 #define DAGB5_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 28541 #define DAGB5_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 28542 #define DAGB5_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 28543 #define DAGB5_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 28544 #define DAGB5_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 28545 #define DAGB5_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 28546 #define DAGB5_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L 28547 #define DAGB5_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 28548 #define DAGB5_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L 28549 #define DAGB5_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 28550 #define DAGB5_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 28551 //DAGB5_WR_VC1_CNTL 28552 #define DAGB5_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 28553 #define DAGB5_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 28554 #define DAGB5_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 28555 #define DAGB5_WR_VC1_CNTL__MAX_BW__SHIFT 0xc 28556 #define DAGB5_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 28557 #define DAGB5_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 28558 #define DAGB5_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 28559 #define DAGB5_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 28560 #define DAGB5_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 28561 #define DAGB5_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 28562 #define DAGB5_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 28563 #define DAGB5_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L 28564 #define DAGB5_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 28565 #define DAGB5_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L 28566 #define DAGB5_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 28567 #define DAGB5_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 28568 //DAGB5_WR_VC2_CNTL 28569 #define DAGB5_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 28570 #define DAGB5_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 28571 #define DAGB5_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 28572 #define DAGB5_WR_VC2_CNTL__MAX_BW__SHIFT 0xc 28573 #define DAGB5_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 28574 #define DAGB5_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 28575 #define DAGB5_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 28576 #define DAGB5_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 28577 #define DAGB5_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 28578 #define DAGB5_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 28579 #define DAGB5_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 28580 #define DAGB5_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L 28581 #define DAGB5_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 28582 #define DAGB5_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L 28583 #define DAGB5_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 28584 #define DAGB5_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 28585 //DAGB5_WR_VC3_CNTL 28586 #define DAGB5_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 28587 #define DAGB5_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 28588 #define DAGB5_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 28589 #define DAGB5_WR_VC3_CNTL__MAX_BW__SHIFT 0xc 28590 #define DAGB5_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 28591 #define DAGB5_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 28592 #define DAGB5_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 28593 #define DAGB5_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 28594 #define DAGB5_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 28595 #define DAGB5_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 28596 #define DAGB5_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 28597 #define DAGB5_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L 28598 #define DAGB5_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 28599 #define DAGB5_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L 28600 #define DAGB5_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 28601 #define DAGB5_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 28602 //DAGB5_WR_VC4_CNTL 28603 #define DAGB5_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 28604 #define DAGB5_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 28605 #define DAGB5_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 28606 #define DAGB5_WR_VC4_CNTL__MAX_BW__SHIFT 0xc 28607 #define DAGB5_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 28608 #define DAGB5_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 28609 #define DAGB5_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 28610 #define DAGB5_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 28611 #define DAGB5_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 28612 #define DAGB5_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 28613 #define DAGB5_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 28614 #define DAGB5_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L 28615 #define DAGB5_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 28616 #define DAGB5_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L 28617 #define DAGB5_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 28618 #define DAGB5_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 28619 //DAGB5_WR_VC5_CNTL 28620 #define DAGB5_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 28621 #define DAGB5_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 28622 #define DAGB5_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 28623 #define DAGB5_WR_VC5_CNTL__MAX_BW__SHIFT 0xc 28624 #define DAGB5_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 28625 #define DAGB5_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 28626 #define DAGB5_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 28627 #define DAGB5_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 28628 #define DAGB5_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 28629 #define DAGB5_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 28630 #define DAGB5_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 28631 #define DAGB5_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L 28632 #define DAGB5_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 28633 #define DAGB5_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L 28634 #define DAGB5_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 28635 #define DAGB5_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 28636 //DAGB5_WR_VC6_CNTL 28637 #define DAGB5_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 28638 #define DAGB5_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 28639 #define DAGB5_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 28640 #define DAGB5_WR_VC6_CNTL__MAX_BW__SHIFT 0xc 28641 #define DAGB5_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 28642 #define DAGB5_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 28643 #define DAGB5_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 28644 #define DAGB5_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 28645 #define DAGB5_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 28646 #define DAGB5_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 28647 #define DAGB5_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 28648 #define DAGB5_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L 28649 #define DAGB5_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 28650 #define DAGB5_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L 28651 #define DAGB5_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 28652 #define DAGB5_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 28653 //DAGB5_WR_VC7_CNTL 28654 #define DAGB5_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 28655 #define DAGB5_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 28656 #define DAGB5_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 28657 #define DAGB5_WR_VC7_CNTL__MAX_BW__SHIFT 0xc 28658 #define DAGB5_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 28659 #define DAGB5_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 28660 #define DAGB5_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 28661 #define DAGB5_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 28662 #define DAGB5_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 28663 #define DAGB5_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 28664 #define DAGB5_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 28665 #define DAGB5_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L 28666 #define DAGB5_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 28667 #define DAGB5_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L 28668 #define DAGB5_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 28669 #define DAGB5_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 28670 //DAGB5_WR_CNTL_MISC 28671 #define DAGB5_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 28672 #define DAGB5_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 28673 #define DAGB5_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 28674 #define DAGB5_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 28675 #define DAGB5_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 28676 #define DAGB5_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 28677 #define DAGB5_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a 28678 #define DAGB5_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 28679 #define DAGB5_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 28680 #define DAGB5_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 28681 #define DAGB5_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 28682 #define DAGB5_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 28683 #define DAGB5_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 28684 #define DAGB5_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L 28685 //DAGB5_WR_TLB_CREDIT 28686 #define DAGB5_WR_TLB_CREDIT__TLB0__SHIFT 0x0 28687 #define DAGB5_WR_TLB_CREDIT__TLB1__SHIFT 0x5 28688 #define DAGB5_WR_TLB_CREDIT__TLB2__SHIFT 0xa 28689 #define DAGB5_WR_TLB_CREDIT__TLB3__SHIFT 0xf 28690 #define DAGB5_WR_TLB_CREDIT__TLB4__SHIFT 0x14 28691 #define DAGB5_WR_TLB_CREDIT__TLB5__SHIFT 0x19 28692 #define DAGB5_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL 28693 #define DAGB5_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L 28694 #define DAGB5_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L 28695 #define DAGB5_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L 28696 #define DAGB5_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L 28697 #define DAGB5_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L 28698 //DAGB5_WR_DATA_CREDIT 28699 #define DAGB5_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 28700 #define DAGB5_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 28701 #define DAGB5_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 28702 #define DAGB5_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 28703 #define DAGB5_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL 28704 #define DAGB5_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L 28705 #define DAGB5_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L 28706 #define DAGB5_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L 28707 //DAGB5_WR_MISC_CREDIT 28708 #define DAGB5_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 28709 #define DAGB5_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 28710 #define DAGB5_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 28711 #define DAGB5_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 28712 #define DAGB5_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL 28713 #define DAGB5_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L 28714 #define DAGB5_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L 28715 #define DAGB5_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L 28716 //DAGB5_WRCLI_ASK_PENDING 28717 #define DAGB5_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 28718 #define DAGB5_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 28719 //DAGB5_WRCLI_GO_PENDING 28720 #define DAGB5_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 28721 #define DAGB5_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 28722 //DAGB5_WRCLI_GBLSEND_PENDING 28723 #define DAGB5_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 28724 #define DAGB5_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 28725 //DAGB5_WRCLI_TLB_PENDING 28726 #define DAGB5_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 28727 #define DAGB5_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 28728 //DAGB5_WRCLI_OARB_PENDING 28729 #define DAGB5_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 28730 #define DAGB5_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 28731 //DAGB5_WRCLI_OSD_PENDING 28732 #define DAGB5_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 28733 #define DAGB5_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 28734 //DAGB5_WRCLI_DBUS_ASK_PENDING 28735 #define DAGB5_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 28736 #define DAGB5_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 28737 //DAGB5_WRCLI_DBUS_GO_PENDING 28738 #define DAGB5_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 28739 #define DAGB5_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 28740 //DAGB5_DAGB_DLY 28741 #define DAGB5_DAGB_DLY__DLY__SHIFT 0x0 28742 #define DAGB5_DAGB_DLY__CLI__SHIFT 0x8 28743 #define DAGB5_DAGB_DLY__POS__SHIFT 0x10 28744 #define DAGB5_DAGB_DLY__DLY_MASK 0x000000FFL 28745 #define DAGB5_DAGB_DLY__CLI_MASK 0x0000FF00L 28746 #define DAGB5_DAGB_DLY__POS_MASK 0x000F0000L 28747 //DAGB5_CNTL_MISC 28748 #define DAGB5_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 28749 #define DAGB5_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 28750 #define DAGB5_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 28751 #define DAGB5_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 28752 #define DAGB5_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc 28753 #define DAGB5_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf 28754 #define DAGB5_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 28755 #define DAGB5_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 28756 #define DAGB5_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 28757 #define DAGB5_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e 28758 #define DAGB5_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L 28759 #define DAGB5_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L 28760 #define DAGB5_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L 28761 #define DAGB5_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L 28762 #define DAGB5_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L 28763 #define DAGB5_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L 28764 #define DAGB5_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L 28765 #define DAGB5_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L 28766 #define DAGB5_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L 28767 #define DAGB5_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L 28768 //DAGB5_CNTL_MISC2 28769 #define DAGB5_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 28770 #define DAGB5_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 28771 #define DAGB5_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 28772 #define DAGB5_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 28773 #define DAGB5_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 28774 #define DAGB5_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 28775 #define DAGB5_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 28776 #define DAGB5_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 28777 #define DAGB5_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 28778 #define DAGB5_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 28779 #define DAGB5_CNTL_MISC2__SWAP_CTL__SHIFT 0xa 28780 #define DAGB5_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xb 28781 #define DAGB5_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x11 28782 #define DAGB5_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L 28783 #define DAGB5_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L 28784 #define DAGB5_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L 28785 #define DAGB5_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L 28786 #define DAGB5_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L 28787 #define DAGB5_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L 28788 #define DAGB5_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L 28789 #define DAGB5_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L 28790 #define DAGB5_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L 28791 #define DAGB5_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L 28792 #define DAGB5_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L 28793 #define DAGB5_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000800L 28794 #define DAGB5_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x007E0000L 28795 //DAGB5_FIFO_EMPTY 28796 #define DAGB5_FIFO_EMPTY__EMPTY__SHIFT 0x0 28797 #define DAGB5_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL 28798 //DAGB5_FIFO_FULL 28799 #define DAGB5_FIFO_FULL__FULL__SHIFT 0x0 28800 #define DAGB5_FIFO_FULL__FULL_MASK 0x007FFFFFL 28801 //DAGB5_WR_CREDITS_FULL 28802 #define DAGB5_WR_CREDITS_FULL__FULL__SHIFT 0x0 28803 #define DAGB5_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL 28804 //DAGB5_RD_CREDITS_FULL 28805 #define DAGB5_RD_CREDITS_FULL__FULL__SHIFT 0x0 28806 #define DAGB5_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL 28807 //DAGB5_PERFCOUNTER_LO 28808 #define DAGB5_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 28809 #define DAGB5_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 28810 //DAGB5_PERFCOUNTER_HI 28811 #define DAGB5_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 28812 #define DAGB5_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 28813 #define DAGB5_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 28814 #define DAGB5_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 28815 //DAGB5_PERFCOUNTER0_CFG 28816 #define DAGB5_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 28817 #define DAGB5_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 28818 #define DAGB5_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 28819 #define DAGB5_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 28820 #define DAGB5_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 28821 #define DAGB5_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 28822 #define DAGB5_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 28823 #define DAGB5_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 28824 #define DAGB5_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 28825 #define DAGB5_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 28826 //DAGB5_PERFCOUNTER1_CFG 28827 #define DAGB5_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 28828 #define DAGB5_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 28829 #define DAGB5_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 28830 #define DAGB5_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 28831 #define DAGB5_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 28832 #define DAGB5_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 28833 #define DAGB5_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 28834 #define DAGB5_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 28835 #define DAGB5_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 28836 #define DAGB5_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 28837 //DAGB5_PERFCOUNTER2_CFG 28838 #define DAGB5_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 28839 #define DAGB5_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 28840 #define DAGB5_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 28841 #define DAGB5_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 28842 #define DAGB5_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 28843 #define DAGB5_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 28844 #define DAGB5_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 28845 #define DAGB5_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 28846 #define DAGB5_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 28847 #define DAGB5_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 28848 //DAGB5_PERFCOUNTER_RSLT_CNTL 28849 #define DAGB5_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 28850 #define DAGB5_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 28851 #define DAGB5_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 28852 #define DAGB5_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 28853 #define DAGB5_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 28854 #define DAGB5_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 28855 #define DAGB5_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 28856 #define DAGB5_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 28857 #define DAGB5_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 28858 #define DAGB5_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 28859 #define DAGB5_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 28860 #define DAGB5_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 28861 //DAGB5_RESERVE0 28862 #define DAGB5_RESERVE0__RESERVE__SHIFT 0x0 28863 #define DAGB5_RESERVE0__RESERVE_MASK 0xFFFFFFFFL 28864 //DAGB5_RESERVE1 28865 #define DAGB5_RESERVE1__RESERVE__SHIFT 0x0 28866 #define DAGB5_RESERVE1__RESERVE_MASK 0xFFFFFFFFL 28867 //DAGB5_RESERVE2 28868 #define DAGB5_RESERVE2__RESERVE__SHIFT 0x0 28869 #define DAGB5_RESERVE2__RESERVE_MASK 0xFFFFFFFFL 28870 //DAGB5_RESERVE3 28871 #define DAGB5_RESERVE3__RESERVE__SHIFT 0x0 28872 #define DAGB5_RESERVE3__RESERVE_MASK 0xFFFFFFFFL 28873 //DAGB5_RESERVE4 28874 #define DAGB5_RESERVE4__RESERVE__SHIFT 0x0 28875 #define DAGB5_RESERVE4__RESERVE_MASK 0xFFFFFFFFL 28876 //DAGB5_RESERVE5 28877 #define DAGB5_RESERVE5__RESERVE__SHIFT 0x0 28878 #define DAGB5_RESERVE5__RESERVE_MASK 0xFFFFFFFFL 28879 //DAGB5_RESERVE6 28880 #define DAGB5_RESERVE6__RESERVE__SHIFT 0x0 28881 #define DAGB5_RESERVE6__RESERVE_MASK 0xFFFFFFFFL 28882 //DAGB5_RESERVE7 28883 #define DAGB5_RESERVE7__RESERVE__SHIFT 0x0 28884 #define DAGB5_RESERVE7__RESERVE_MASK 0xFFFFFFFFL 28885 //DAGB5_RESERVE8 28886 #define DAGB5_RESERVE8__RESERVE__SHIFT 0x0 28887 #define DAGB5_RESERVE8__RESERVE_MASK 0xFFFFFFFFL 28888 //DAGB5_RESERVE9 28889 #define DAGB5_RESERVE9__RESERVE__SHIFT 0x0 28890 #define DAGB5_RESERVE9__RESERVE_MASK 0xFFFFFFFFL 28891 //DAGB5_RESERVE10 28892 #define DAGB5_RESERVE10__RESERVE__SHIFT 0x0 28893 #define DAGB5_RESERVE10__RESERVE_MASK 0xFFFFFFFFL 28894 //DAGB5_RESERVE11 28895 #define DAGB5_RESERVE11__RESERVE__SHIFT 0x0 28896 #define DAGB5_RESERVE11__RESERVE_MASK 0xFFFFFFFFL 28897 //DAGB5_RESERVE12 28898 #define DAGB5_RESERVE12__RESERVE__SHIFT 0x0 28899 #define DAGB5_RESERVE12__RESERVE_MASK 0xFFFFFFFFL 28900 //DAGB5_RESERVE13 28901 #define DAGB5_RESERVE13__RESERVE__SHIFT 0x0 28902 #define DAGB5_RESERVE13__RESERVE_MASK 0xFFFFFFFFL 28903 28904 28905 // addressBlock: mmhub_dagb_dagbdec6 28906 //DAGB6_RDCLI0 28907 #define DAGB6_RDCLI0__VIRT_CHAN__SHIFT 0x0 28908 #define DAGB6_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 28909 #define DAGB6_RDCLI0__URG_HIGH__SHIFT 0x4 28910 #define DAGB6_RDCLI0__URG_LOW__SHIFT 0x8 28911 #define DAGB6_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 28912 #define DAGB6_RDCLI0__MAX_BW__SHIFT 0xd 28913 #define DAGB6_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 28914 #define DAGB6_RDCLI0__MIN_BW__SHIFT 0x16 28915 #define DAGB6_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 28916 #define DAGB6_RDCLI0__MAX_OSD__SHIFT 0x1a 28917 #define DAGB6_RDCLI0__VIRT_CHAN_MASK 0x00000007L 28918 #define DAGB6_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 28919 #define DAGB6_RDCLI0__URG_HIGH_MASK 0x000000F0L 28920 #define DAGB6_RDCLI0__URG_LOW_MASK 0x00000F00L 28921 #define DAGB6_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L 28922 #define DAGB6_RDCLI0__MAX_BW_MASK 0x001FE000L 28923 #define DAGB6_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L 28924 #define DAGB6_RDCLI0__MIN_BW_MASK 0x01C00000L 28925 #define DAGB6_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 28926 #define DAGB6_RDCLI0__MAX_OSD_MASK 0xFC000000L 28927 //DAGB6_RDCLI1 28928 #define DAGB6_RDCLI1__VIRT_CHAN__SHIFT 0x0 28929 #define DAGB6_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 28930 #define DAGB6_RDCLI1__URG_HIGH__SHIFT 0x4 28931 #define DAGB6_RDCLI1__URG_LOW__SHIFT 0x8 28932 #define DAGB6_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc 28933 #define DAGB6_RDCLI1__MAX_BW__SHIFT 0xd 28934 #define DAGB6_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 28935 #define DAGB6_RDCLI1__MIN_BW__SHIFT 0x16 28936 #define DAGB6_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 28937 #define DAGB6_RDCLI1__MAX_OSD__SHIFT 0x1a 28938 #define DAGB6_RDCLI1__VIRT_CHAN_MASK 0x00000007L 28939 #define DAGB6_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 28940 #define DAGB6_RDCLI1__URG_HIGH_MASK 0x000000F0L 28941 #define DAGB6_RDCLI1__URG_LOW_MASK 0x00000F00L 28942 #define DAGB6_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L 28943 #define DAGB6_RDCLI1__MAX_BW_MASK 0x001FE000L 28944 #define DAGB6_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L 28945 #define DAGB6_RDCLI1__MIN_BW_MASK 0x01C00000L 28946 #define DAGB6_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 28947 #define DAGB6_RDCLI1__MAX_OSD_MASK 0xFC000000L 28948 //DAGB6_RDCLI2 28949 #define DAGB6_RDCLI2__VIRT_CHAN__SHIFT 0x0 28950 #define DAGB6_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 28951 #define DAGB6_RDCLI2__URG_HIGH__SHIFT 0x4 28952 #define DAGB6_RDCLI2__URG_LOW__SHIFT 0x8 28953 #define DAGB6_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc 28954 #define DAGB6_RDCLI2__MAX_BW__SHIFT 0xd 28955 #define DAGB6_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 28956 #define DAGB6_RDCLI2__MIN_BW__SHIFT 0x16 28957 #define DAGB6_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 28958 #define DAGB6_RDCLI2__MAX_OSD__SHIFT 0x1a 28959 #define DAGB6_RDCLI2__VIRT_CHAN_MASK 0x00000007L 28960 #define DAGB6_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 28961 #define DAGB6_RDCLI2__URG_HIGH_MASK 0x000000F0L 28962 #define DAGB6_RDCLI2__URG_LOW_MASK 0x00000F00L 28963 #define DAGB6_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L 28964 #define DAGB6_RDCLI2__MAX_BW_MASK 0x001FE000L 28965 #define DAGB6_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L 28966 #define DAGB6_RDCLI2__MIN_BW_MASK 0x01C00000L 28967 #define DAGB6_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 28968 #define DAGB6_RDCLI2__MAX_OSD_MASK 0xFC000000L 28969 //DAGB6_RDCLI3 28970 #define DAGB6_RDCLI3__VIRT_CHAN__SHIFT 0x0 28971 #define DAGB6_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 28972 #define DAGB6_RDCLI3__URG_HIGH__SHIFT 0x4 28973 #define DAGB6_RDCLI3__URG_LOW__SHIFT 0x8 28974 #define DAGB6_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc 28975 #define DAGB6_RDCLI3__MAX_BW__SHIFT 0xd 28976 #define DAGB6_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 28977 #define DAGB6_RDCLI3__MIN_BW__SHIFT 0x16 28978 #define DAGB6_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 28979 #define DAGB6_RDCLI3__MAX_OSD__SHIFT 0x1a 28980 #define DAGB6_RDCLI3__VIRT_CHAN_MASK 0x00000007L 28981 #define DAGB6_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 28982 #define DAGB6_RDCLI3__URG_HIGH_MASK 0x000000F0L 28983 #define DAGB6_RDCLI3__URG_LOW_MASK 0x00000F00L 28984 #define DAGB6_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L 28985 #define DAGB6_RDCLI3__MAX_BW_MASK 0x001FE000L 28986 #define DAGB6_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L 28987 #define DAGB6_RDCLI3__MIN_BW_MASK 0x01C00000L 28988 #define DAGB6_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 28989 #define DAGB6_RDCLI3__MAX_OSD_MASK 0xFC000000L 28990 //DAGB6_RDCLI4 28991 #define DAGB6_RDCLI4__VIRT_CHAN__SHIFT 0x0 28992 #define DAGB6_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 28993 #define DAGB6_RDCLI4__URG_HIGH__SHIFT 0x4 28994 #define DAGB6_RDCLI4__URG_LOW__SHIFT 0x8 28995 #define DAGB6_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc 28996 #define DAGB6_RDCLI4__MAX_BW__SHIFT 0xd 28997 #define DAGB6_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 28998 #define DAGB6_RDCLI4__MIN_BW__SHIFT 0x16 28999 #define DAGB6_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 29000 #define DAGB6_RDCLI4__MAX_OSD__SHIFT 0x1a 29001 #define DAGB6_RDCLI4__VIRT_CHAN_MASK 0x00000007L 29002 #define DAGB6_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 29003 #define DAGB6_RDCLI4__URG_HIGH_MASK 0x000000F0L 29004 #define DAGB6_RDCLI4__URG_LOW_MASK 0x00000F00L 29005 #define DAGB6_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L 29006 #define DAGB6_RDCLI4__MAX_BW_MASK 0x001FE000L 29007 #define DAGB6_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L 29008 #define DAGB6_RDCLI4__MIN_BW_MASK 0x01C00000L 29009 #define DAGB6_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 29010 #define DAGB6_RDCLI4__MAX_OSD_MASK 0xFC000000L 29011 //DAGB6_RDCLI5 29012 #define DAGB6_RDCLI5__VIRT_CHAN__SHIFT 0x0 29013 #define DAGB6_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 29014 #define DAGB6_RDCLI5__URG_HIGH__SHIFT 0x4 29015 #define DAGB6_RDCLI5__URG_LOW__SHIFT 0x8 29016 #define DAGB6_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc 29017 #define DAGB6_RDCLI5__MAX_BW__SHIFT 0xd 29018 #define DAGB6_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 29019 #define DAGB6_RDCLI5__MIN_BW__SHIFT 0x16 29020 #define DAGB6_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 29021 #define DAGB6_RDCLI5__MAX_OSD__SHIFT 0x1a 29022 #define DAGB6_RDCLI5__VIRT_CHAN_MASK 0x00000007L 29023 #define DAGB6_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 29024 #define DAGB6_RDCLI5__URG_HIGH_MASK 0x000000F0L 29025 #define DAGB6_RDCLI5__URG_LOW_MASK 0x00000F00L 29026 #define DAGB6_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L 29027 #define DAGB6_RDCLI5__MAX_BW_MASK 0x001FE000L 29028 #define DAGB6_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L 29029 #define DAGB6_RDCLI5__MIN_BW_MASK 0x01C00000L 29030 #define DAGB6_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 29031 #define DAGB6_RDCLI5__MAX_OSD_MASK 0xFC000000L 29032 //DAGB6_RDCLI6 29033 #define DAGB6_RDCLI6__VIRT_CHAN__SHIFT 0x0 29034 #define DAGB6_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 29035 #define DAGB6_RDCLI6__URG_HIGH__SHIFT 0x4 29036 #define DAGB6_RDCLI6__URG_LOW__SHIFT 0x8 29037 #define DAGB6_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc 29038 #define DAGB6_RDCLI6__MAX_BW__SHIFT 0xd 29039 #define DAGB6_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 29040 #define DAGB6_RDCLI6__MIN_BW__SHIFT 0x16 29041 #define DAGB6_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 29042 #define DAGB6_RDCLI6__MAX_OSD__SHIFT 0x1a 29043 #define DAGB6_RDCLI6__VIRT_CHAN_MASK 0x00000007L 29044 #define DAGB6_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 29045 #define DAGB6_RDCLI6__URG_HIGH_MASK 0x000000F0L 29046 #define DAGB6_RDCLI6__URG_LOW_MASK 0x00000F00L 29047 #define DAGB6_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L 29048 #define DAGB6_RDCLI6__MAX_BW_MASK 0x001FE000L 29049 #define DAGB6_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L 29050 #define DAGB6_RDCLI6__MIN_BW_MASK 0x01C00000L 29051 #define DAGB6_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 29052 #define DAGB6_RDCLI6__MAX_OSD_MASK 0xFC000000L 29053 //DAGB6_RDCLI7 29054 #define DAGB6_RDCLI7__VIRT_CHAN__SHIFT 0x0 29055 #define DAGB6_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 29056 #define DAGB6_RDCLI7__URG_HIGH__SHIFT 0x4 29057 #define DAGB6_RDCLI7__URG_LOW__SHIFT 0x8 29058 #define DAGB6_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc 29059 #define DAGB6_RDCLI7__MAX_BW__SHIFT 0xd 29060 #define DAGB6_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 29061 #define DAGB6_RDCLI7__MIN_BW__SHIFT 0x16 29062 #define DAGB6_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 29063 #define DAGB6_RDCLI7__MAX_OSD__SHIFT 0x1a 29064 #define DAGB6_RDCLI7__VIRT_CHAN_MASK 0x00000007L 29065 #define DAGB6_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 29066 #define DAGB6_RDCLI7__URG_HIGH_MASK 0x000000F0L 29067 #define DAGB6_RDCLI7__URG_LOW_MASK 0x00000F00L 29068 #define DAGB6_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L 29069 #define DAGB6_RDCLI7__MAX_BW_MASK 0x001FE000L 29070 #define DAGB6_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L 29071 #define DAGB6_RDCLI7__MIN_BW_MASK 0x01C00000L 29072 #define DAGB6_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 29073 #define DAGB6_RDCLI7__MAX_OSD_MASK 0xFC000000L 29074 //DAGB6_RDCLI8 29075 #define DAGB6_RDCLI8__VIRT_CHAN__SHIFT 0x0 29076 #define DAGB6_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 29077 #define DAGB6_RDCLI8__URG_HIGH__SHIFT 0x4 29078 #define DAGB6_RDCLI8__URG_LOW__SHIFT 0x8 29079 #define DAGB6_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc 29080 #define DAGB6_RDCLI8__MAX_BW__SHIFT 0xd 29081 #define DAGB6_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 29082 #define DAGB6_RDCLI8__MIN_BW__SHIFT 0x16 29083 #define DAGB6_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 29084 #define DAGB6_RDCLI8__MAX_OSD__SHIFT 0x1a 29085 #define DAGB6_RDCLI8__VIRT_CHAN_MASK 0x00000007L 29086 #define DAGB6_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 29087 #define DAGB6_RDCLI8__URG_HIGH_MASK 0x000000F0L 29088 #define DAGB6_RDCLI8__URG_LOW_MASK 0x00000F00L 29089 #define DAGB6_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L 29090 #define DAGB6_RDCLI8__MAX_BW_MASK 0x001FE000L 29091 #define DAGB6_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L 29092 #define DAGB6_RDCLI8__MIN_BW_MASK 0x01C00000L 29093 #define DAGB6_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 29094 #define DAGB6_RDCLI8__MAX_OSD_MASK 0xFC000000L 29095 //DAGB6_RDCLI9 29096 #define DAGB6_RDCLI9__VIRT_CHAN__SHIFT 0x0 29097 #define DAGB6_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 29098 #define DAGB6_RDCLI9__URG_HIGH__SHIFT 0x4 29099 #define DAGB6_RDCLI9__URG_LOW__SHIFT 0x8 29100 #define DAGB6_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc 29101 #define DAGB6_RDCLI9__MAX_BW__SHIFT 0xd 29102 #define DAGB6_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 29103 #define DAGB6_RDCLI9__MIN_BW__SHIFT 0x16 29104 #define DAGB6_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 29105 #define DAGB6_RDCLI9__MAX_OSD__SHIFT 0x1a 29106 #define DAGB6_RDCLI9__VIRT_CHAN_MASK 0x00000007L 29107 #define DAGB6_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 29108 #define DAGB6_RDCLI9__URG_HIGH_MASK 0x000000F0L 29109 #define DAGB6_RDCLI9__URG_LOW_MASK 0x00000F00L 29110 #define DAGB6_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L 29111 #define DAGB6_RDCLI9__MAX_BW_MASK 0x001FE000L 29112 #define DAGB6_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L 29113 #define DAGB6_RDCLI9__MIN_BW_MASK 0x01C00000L 29114 #define DAGB6_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 29115 #define DAGB6_RDCLI9__MAX_OSD_MASK 0xFC000000L 29116 //DAGB6_RDCLI10 29117 #define DAGB6_RDCLI10__VIRT_CHAN__SHIFT 0x0 29118 #define DAGB6_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 29119 #define DAGB6_RDCLI10__URG_HIGH__SHIFT 0x4 29120 #define DAGB6_RDCLI10__URG_LOW__SHIFT 0x8 29121 #define DAGB6_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc 29122 #define DAGB6_RDCLI10__MAX_BW__SHIFT 0xd 29123 #define DAGB6_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 29124 #define DAGB6_RDCLI10__MIN_BW__SHIFT 0x16 29125 #define DAGB6_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 29126 #define DAGB6_RDCLI10__MAX_OSD__SHIFT 0x1a 29127 #define DAGB6_RDCLI10__VIRT_CHAN_MASK 0x00000007L 29128 #define DAGB6_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 29129 #define DAGB6_RDCLI10__URG_HIGH_MASK 0x000000F0L 29130 #define DAGB6_RDCLI10__URG_LOW_MASK 0x00000F00L 29131 #define DAGB6_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L 29132 #define DAGB6_RDCLI10__MAX_BW_MASK 0x001FE000L 29133 #define DAGB6_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L 29134 #define DAGB6_RDCLI10__MIN_BW_MASK 0x01C00000L 29135 #define DAGB6_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 29136 #define DAGB6_RDCLI10__MAX_OSD_MASK 0xFC000000L 29137 //DAGB6_RDCLI11 29138 #define DAGB6_RDCLI11__VIRT_CHAN__SHIFT 0x0 29139 #define DAGB6_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 29140 #define DAGB6_RDCLI11__URG_HIGH__SHIFT 0x4 29141 #define DAGB6_RDCLI11__URG_LOW__SHIFT 0x8 29142 #define DAGB6_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc 29143 #define DAGB6_RDCLI11__MAX_BW__SHIFT 0xd 29144 #define DAGB6_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 29145 #define DAGB6_RDCLI11__MIN_BW__SHIFT 0x16 29146 #define DAGB6_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 29147 #define DAGB6_RDCLI11__MAX_OSD__SHIFT 0x1a 29148 #define DAGB6_RDCLI11__VIRT_CHAN_MASK 0x00000007L 29149 #define DAGB6_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 29150 #define DAGB6_RDCLI11__URG_HIGH_MASK 0x000000F0L 29151 #define DAGB6_RDCLI11__URG_LOW_MASK 0x00000F00L 29152 #define DAGB6_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L 29153 #define DAGB6_RDCLI11__MAX_BW_MASK 0x001FE000L 29154 #define DAGB6_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L 29155 #define DAGB6_RDCLI11__MIN_BW_MASK 0x01C00000L 29156 #define DAGB6_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 29157 #define DAGB6_RDCLI11__MAX_OSD_MASK 0xFC000000L 29158 //DAGB6_RDCLI12 29159 #define DAGB6_RDCLI12__VIRT_CHAN__SHIFT 0x0 29160 #define DAGB6_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 29161 #define DAGB6_RDCLI12__URG_HIGH__SHIFT 0x4 29162 #define DAGB6_RDCLI12__URG_LOW__SHIFT 0x8 29163 #define DAGB6_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc 29164 #define DAGB6_RDCLI12__MAX_BW__SHIFT 0xd 29165 #define DAGB6_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 29166 #define DAGB6_RDCLI12__MIN_BW__SHIFT 0x16 29167 #define DAGB6_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 29168 #define DAGB6_RDCLI12__MAX_OSD__SHIFT 0x1a 29169 #define DAGB6_RDCLI12__VIRT_CHAN_MASK 0x00000007L 29170 #define DAGB6_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 29171 #define DAGB6_RDCLI12__URG_HIGH_MASK 0x000000F0L 29172 #define DAGB6_RDCLI12__URG_LOW_MASK 0x00000F00L 29173 #define DAGB6_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L 29174 #define DAGB6_RDCLI12__MAX_BW_MASK 0x001FE000L 29175 #define DAGB6_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L 29176 #define DAGB6_RDCLI12__MIN_BW_MASK 0x01C00000L 29177 #define DAGB6_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 29178 #define DAGB6_RDCLI12__MAX_OSD_MASK 0xFC000000L 29179 //DAGB6_RDCLI13 29180 #define DAGB6_RDCLI13__VIRT_CHAN__SHIFT 0x0 29181 #define DAGB6_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 29182 #define DAGB6_RDCLI13__URG_HIGH__SHIFT 0x4 29183 #define DAGB6_RDCLI13__URG_LOW__SHIFT 0x8 29184 #define DAGB6_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc 29185 #define DAGB6_RDCLI13__MAX_BW__SHIFT 0xd 29186 #define DAGB6_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 29187 #define DAGB6_RDCLI13__MIN_BW__SHIFT 0x16 29188 #define DAGB6_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 29189 #define DAGB6_RDCLI13__MAX_OSD__SHIFT 0x1a 29190 #define DAGB6_RDCLI13__VIRT_CHAN_MASK 0x00000007L 29191 #define DAGB6_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 29192 #define DAGB6_RDCLI13__URG_HIGH_MASK 0x000000F0L 29193 #define DAGB6_RDCLI13__URG_LOW_MASK 0x00000F00L 29194 #define DAGB6_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L 29195 #define DAGB6_RDCLI13__MAX_BW_MASK 0x001FE000L 29196 #define DAGB6_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L 29197 #define DAGB6_RDCLI13__MIN_BW_MASK 0x01C00000L 29198 #define DAGB6_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 29199 #define DAGB6_RDCLI13__MAX_OSD_MASK 0xFC000000L 29200 //DAGB6_RDCLI14 29201 #define DAGB6_RDCLI14__VIRT_CHAN__SHIFT 0x0 29202 #define DAGB6_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 29203 #define DAGB6_RDCLI14__URG_HIGH__SHIFT 0x4 29204 #define DAGB6_RDCLI14__URG_LOW__SHIFT 0x8 29205 #define DAGB6_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc 29206 #define DAGB6_RDCLI14__MAX_BW__SHIFT 0xd 29207 #define DAGB6_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 29208 #define DAGB6_RDCLI14__MIN_BW__SHIFT 0x16 29209 #define DAGB6_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 29210 #define DAGB6_RDCLI14__MAX_OSD__SHIFT 0x1a 29211 #define DAGB6_RDCLI14__VIRT_CHAN_MASK 0x00000007L 29212 #define DAGB6_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 29213 #define DAGB6_RDCLI14__URG_HIGH_MASK 0x000000F0L 29214 #define DAGB6_RDCLI14__URG_LOW_MASK 0x00000F00L 29215 #define DAGB6_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L 29216 #define DAGB6_RDCLI14__MAX_BW_MASK 0x001FE000L 29217 #define DAGB6_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L 29218 #define DAGB6_RDCLI14__MIN_BW_MASK 0x01C00000L 29219 #define DAGB6_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 29220 #define DAGB6_RDCLI14__MAX_OSD_MASK 0xFC000000L 29221 //DAGB6_RDCLI15 29222 #define DAGB6_RDCLI15__VIRT_CHAN__SHIFT 0x0 29223 #define DAGB6_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 29224 #define DAGB6_RDCLI15__URG_HIGH__SHIFT 0x4 29225 #define DAGB6_RDCLI15__URG_LOW__SHIFT 0x8 29226 #define DAGB6_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc 29227 #define DAGB6_RDCLI15__MAX_BW__SHIFT 0xd 29228 #define DAGB6_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 29229 #define DAGB6_RDCLI15__MIN_BW__SHIFT 0x16 29230 #define DAGB6_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 29231 #define DAGB6_RDCLI15__MAX_OSD__SHIFT 0x1a 29232 #define DAGB6_RDCLI15__VIRT_CHAN_MASK 0x00000007L 29233 #define DAGB6_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 29234 #define DAGB6_RDCLI15__URG_HIGH_MASK 0x000000F0L 29235 #define DAGB6_RDCLI15__URG_LOW_MASK 0x00000F00L 29236 #define DAGB6_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L 29237 #define DAGB6_RDCLI15__MAX_BW_MASK 0x001FE000L 29238 #define DAGB6_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L 29239 #define DAGB6_RDCLI15__MIN_BW_MASK 0x01C00000L 29240 #define DAGB6_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 29241 #define DAGB6_RDCLI15__MAX_OSD_MASK 0xFC000000L 29242 //DAGB6_RD_CNTL 29243 #define DAGB6_RD_CNTL__SCLK_FREQ__SHIFT 0x0 29244 #define DAGB6_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 29245 #define DAGB6_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 29246 #define DAGB6_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 29247 #define DAGB6_RD_CNTL__IO_LEVEL__SHIFT 0x11 29248 #define DAGB6_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 29249 #define DAGB6_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 29250 #define DAGB6_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL 29251 #define DAGB6_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 29252 #define DAGB6_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 29253 #define DAGB6_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 29254 #define DAGB6_RD_CNTL__IO_LEVEL_MASK 0x000E0000L 29255 #define DAGB6_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 29256 #define DAGB6_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L 29257 //DAGB6_RD_GMI_CNTL 29258 #define DAGB6_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 29259 #define DAGB6_RD_GMI_CNTL__LEVEL__SHIFT 0x6 29260 #define DAGB6_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 29261 #define DAGB6_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 29262 #define DAGB6_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 29263 #define DAGB6_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L 29264 #define DAGB6_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 29265 #define DAGB6_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 29266 //DAGB6_RD_ADDR_DAGB 29267 #define DAGB6_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 29268 #define DAGB6_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 29269 #define DAGB6_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 29270 #define DAGB6_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 29271 #define DAGB6_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 29272 #define DAGB6_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 29273 #define DAGB6_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 29274 #define DAGB6_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 29275 //DAGB6_RD_OUTPUT_DAGB_MAX_BURST 29276 #define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 29277 #define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 29278 #define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 29279 #define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 29280 #define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 29281 #define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 29282 #define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 29283 #define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 29284 #define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 29285 #define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 29286 #define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 29287 #define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 29288 #define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 29289 #define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 29290 #define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 29291 #define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 29292 //DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER 29293 #define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 29294 #define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 29295 #define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 29296 #define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 29297 #define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 29298 #define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 29299 #define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 29300 #define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 29301 #define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 29302 #define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 29303 #define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 29304 #define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 29305 #define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 29306 #define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 29307 #define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 29308 #define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 29309 //DAGB6_RD_CGTT_CLK_CTRL 29310 #define DAGB6_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 29311 #define DAGB6_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 29312 #define DAGB6_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 29313 #define DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 29314 #define DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 29315 #define DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 29316 #define DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 29317 #define DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 29318 #define DAGB6_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 29319 #define DAGB6_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 29320 #define DAGB6_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 29321 #define DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 29322 #define DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 29323 #define DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 29324 #define DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 29325 #define DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 29326 //DAGB6_L1TLB_RD_CGTT_CLK_CTRL 29327 #define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 29328 #define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 29329 #define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 29330 #define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 29331 #define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 29332 #define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 29333 #define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 29334 #define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 29335 #define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 29336 #define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 29337 #define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 29338 #define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 29339 #define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 29340 #define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 29341 #define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 29342 #define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 29343 //DAGB6_ATCVM_RD_CGTT_CLK_CTRL 29344 #define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 29345 #define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 29346 #define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 29347 #define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 29348 #define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 29349 #define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 29350 #define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 29351 #define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 29352 #define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 29353 #define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 29354 #define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 29355 #define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 29356 #define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 29357 #define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 29358 #define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 29359 #define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 29360 //DAGB6_RD_ADDR_DAGB_MAX_BURST0 29361 #define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 29362 #define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 29363 #define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 29364 #define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 29365 #define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 29366 #define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 29367 #define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 29368 #define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 29369 #define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 29370 #define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 29371 #define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 29372 #define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 29373 #define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 29374 #define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 29375 #define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 29376 #define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 29377 //DAGB6_RD_ADDR_DAGB_LAZY_TIMER0 29378 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 29379 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 29380 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 29381 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 29382 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 29383 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 29384 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 29385 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 29386 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 29387 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 29388 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 29389 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 29390 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 29391 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 29392 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 29393 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 29394 //DAGB6_RD_ADDR_DAGB_MAX_BURST1 29395 #define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 29396 #define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 29397 #define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 29398 #define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 29399 #define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 29400 #define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 29401 #define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 29402 #define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 29403 #define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 29404 #define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 29405 #define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 29406 #define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 29407 #define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 29408 #define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 29409 #define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 29410 #define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 29411 //DAGB6_RD_ADDR_DAGB_LAZY_TIMER1 29412 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 29413 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 29414 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 29415 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 29416 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 29417 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 29418 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 29419 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 29420 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 29421 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 29422 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 29423 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 29424 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 29425 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 29426 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 29427 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 29428 //DAGB6_RD_VC0_CNTL 29429 #define DAGB6_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 29430 #define DAGB6_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 29431 #define DAGB6_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 29432 #define DAGB6_RD_VC0_CNTL__MAX_BW__SHIFT 0xc 29433 #define DAGB6_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 29434 #define DAGB6_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 29435 #define DAGB6_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 29436 #define DAGB6_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 29437 #define DAGB6_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 29438 #define DAGB6_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 29439 #define DAGB6_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 29440 #define DAGB6_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L 29441 #define DAGB6_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 29442 #define DAGB6_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L 29443 #define DAGB6_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 29444 #define DAGB6_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 29445 //DAGB6_RD_VC1_CNTL 29446 #define DAGB6_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 29447 #define DAGB6_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 29448 #define DAGB6_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 29449 #define DAGB6_RD_VC1_CNTL__MAX_BW__SHIFT 0xc 29450 #define DAGB6_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 29451 #define DAGB6_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 29452 #define DAGB6_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 29453 #define DAGB6_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 29454 #define DAGB6_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 29455 #define DAGB6_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 29456 #define DAGB6_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 29457 #define DAGB6_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L 29458 #define DAGB6_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 29459 #define DAGB6_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L 29460 #define DAGB6_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 29461 #define DAGB6_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 29462 //DAGB6_RD_VC2_CNTL 29463 #define DAGB6_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 29464 #define DAGB6_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 29465 #define DAGB6_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 29466 #define DAGB6_RD_VC2_CNTL__MAX_BW__SHIFT 0xc 29467 #define DAGB6_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 29468 #define DAGB6_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 29469 #define DAGB6_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 29470 #define DAGB6_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 29471 #define DAGB6_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 29472 #define DAGB6_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 29473 #define DAGB6_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 29474 #define DAGB6_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L 29475 #define DAGB6_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 29476 #define DAGB6_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L 29477 #define DAGB6_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 29478 #define DAGB6_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 29479 //DAGB6_RD_VC3_CNTL 29480 #define DAGB6_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 29481 #define DAGB6_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 29482 #define DAGB6_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 29483 #define DAGB6_RD_VC3_CNTL__MAX_BW__SHIFT 0xc 29484 #define DAGB6_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 29485 #define DAGB6_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 29486 #define DAGB6_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 29487 #define DAGB6_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 29488 #define DAGB6_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 29489 #define DAGB6_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 29490 #define DAGB6_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 29491 #define DAGB6_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L 29492 #define DAGB6_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 29493 #define DAGB6_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L 29494 #define DAGB6_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 29495 #define DAGB6_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 29496 //DAGB6_RD_VC4_CNTL 29497 #define DAGB6_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 29498 #define DAGB6_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 29499 #define DAGB6_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 29500 #define DAGB6_RD_VC4_CNTL__MAX_BW__SHIFT 0xc 29501 #define DAGB6_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 29502 #define DAGB6_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 29503 #define DAGB6_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 29504 #define DAGB6_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 29505 #define DAGB6_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 29506 #define DAGB6_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 29507 #define DAGB6_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 29508 #define DAGB6_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L 29509 #define DAGB6_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 29510 #define DAGB6_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L 29511 #define DAGB6_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 29512 #define DAGB6_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 29513 //DAGB6_RD_VC5_CNTL 29514 #define DAGB6_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 29515 #define DAGB6_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 29516 #define DAGB6_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 29517 #define DAGB6_RD_VC5_CNTL__MAX_BW__SHIFT 0xc 29518 #define DAGB6_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 29519 #define DAGB6_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 29520 #define DAGB6_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 29521 #define DAGB6_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 29522 #define DAGB6_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 29523 #define DAGB6_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 29524 #define DAGB6_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 29525 #define DAGB6_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L 29526 #define DAGB6_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 29527 #define DAGB6_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L 29528 #define DAGB6_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 29529 #define DAGB6_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 29530 //DAGB6_RD_VC6_CNTL 29531 #define DAGB6_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 29532 #define DAGB6_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 29533 #define DAGB6_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 29534 #define DAGB6_RD_VC6_CNTL__MAX_BW__SHIFT 0xc 29535 #define DAGB6_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 29536 #define DAGB6_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 29537 #define DAGB6_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 29538 #define DAGB6_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 29539 #define DAGB6_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 29540 #define DAGB6_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 29541 #define DAGB6_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 29542 #define DAGB6_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L 29543 #define DAGB6_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 29544 #define DAGB6_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L 29545 #define DAGB6_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 29546 #define DAGB6_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 29547 //DAGB6_RD_VC7_CNTL 29548 #define DAGB6_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 29549 #define DAGB6_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 29550 #define DAGB6_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 29551 #define DAGB6_RD_VC7_CNTL__MAX_BW__SHIFT 0xc 29552 #define DAGB6_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 29553 #define DAGB6_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 29554 #define DAGB6_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 29555 #define DAGB6_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 29556 #define DAGB6_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 29557 #define DAGB6_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 29558 #define DAGB6_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 29559 #define DAGB6_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L 29560 #define DAGB6_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 29561 #define DAGB6_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L 29562 #define DAGB6_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 29563 #define DAGB6_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 29564 //DAGB6_RD_CNTL_MISC 29565 #define DAGB6_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 29566 #define DAGB6_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 29567 #define DAGB6_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 29568 #define DAGB6_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 29569 #define DAGB6_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 29570 #define DAGB6_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 29571 #define DAGB6_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a 29572 #define DAGB6_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 29573 #define DAGB6_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 29574 #define DAGB6_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 29575 #define DAGB6_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 29576 #define DAGB6_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 29577 #define DAGB6_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 29578 #define DAGB6_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L 29579 //DAGB6_RD_TLB_CREDIT 29580 #define DAGB6_RD_TLB_CREDIT__TLB0__SHIFT 0x0 29581 #define DAGB6_RD_TLB_CREDIT__TLB1__SHIFT 0x5 29582 #define DAGB6_RD_TLB_CREDIT__TLB2__SHIFT 0xa 29583 #define DAGB6_RD_TLB_CREDIT__TLB3__SHIFT 0xf 29584 #define DAGB6_RD_TLB_CREDIT__TLB4__SHIFT 0x14 29585 #define DAGB6_RD_TLB_CREDIT__TLB5__SHIFT 0x19 29586 #define DAGB6_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL 29587 #define DAGB6_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L 29588 #define DAGB6_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L 29589 #define DAGB6_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L 29590 #define DAGB6_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L 29591 #define DAGB6_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L 29592 //DAGB6_RDCLI_ASK_PENDING 29593 #define DAGB6_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 29594 #define DAGB6_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 29595 //DAGB6_RDCLI_GO_PENDING 29596 #define DAGB6_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 29597 #define DAGB6_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 29598 //DAGB6_RDCLI_GBLSEND_PENDING 29599 #define DAGB6_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 29600 #define DAGB6_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 29601 //DAGB6_RDCLI_TLB_PENDING 29602 #define DAGB6_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 29603 #define DAGB6_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 29604 //DAGB6_RDCLI_OARB_PENDING 29605 #define DAGB6_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 29606 #define DAGB6_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 29607 //DAGB6_RDCLI_OSD_PENDING 29608 #define DAGB6_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 29609 #define DAGB6_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 29610 //DAGB6_WRCLI0 29611 #define DAGB6_WRCLI0__VIRT_CHAN__SHIFT 0x0 29612 #define DAGB6_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 29613 #define DAGB6_WRCLI0__URG_HIGH__SHIFT 0x4 29614 #define DAGB6_WRCLI0__URG_LOW__SHIFT 0x8 29615 #define DAGB6_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc 29616 #define DAGB6_WRCLI0__MAX_BW__SHIFT 0xd 29617 #define DAGB6_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 29618 #define DAGB6_WRCLI0__MIN_BW__SHIFT 0x16 29619 #define DAGB6_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 29620 #define DAGB6_WRCLI0__MAX_OSD__SHIFT 0x1a 29621 #define DAGB6_WRCLI0__VIRT_CHAN_MASK 0x00000007L 29622 #define DAGB6_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 29623 #define DAGB6_WRCLI0__URG_HIGH_MASK 0x000000F0L 29624 #define DAGB6_WRCLI0__URG_LOW_MASK 0x00000F00L 29625 #define DAGB6_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L 29626 #define DAGB6_WRCLI0__MAX_BW_MASK 0x001FE000L 29627 #define DAGB6_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L 29628 #define DAGB6_WRCLI0__MIN_BW_MASK 0x01C00000L 29629 #define DAGB6_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 29630 #define DAGB6_WRCLI0__MAX_OSD_MASK 0xFC000000L 29631 //DAGB6_WRCLI1 29632 #define DAGB6_WRCLI1__VIRT_CHAN__SHIFT 0x0 29633 #define DAGB6_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 29634 #define DAGB6_WRCLI1__URG_HIGH__SHIFT 0x4 29635 #define DAGB6_WRCLI1__URG_LOW__SHIFT 0x8 29636 #define DAGB6_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc 29637 #define DAGB6_WRCLI1__MAX_BW__SHIFT 0xd 29638 #define DAGB6_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 29639 #define DAGB6_WRCLI1__MIN_BW__SHIFT 0x16 29640 #define DAGB6_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 29641 #define DAGB6_WRCLI1__MAX_OSD__SHIFT 0x1a 29642 #define DAGB6_WRCLI1__VIRT_CHAN_MASK 0x00000007L 29643 #define DAGB6_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 29644 #define DAGB6_WRCLI1__URG_HIGH_MASK 0x000000F0L 29645 #define DAGB6_WRCLI1__URG_LOW_MASK 0x00000F00L 29646 #define DAGB6_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L 29647 #define DAGB6_WRCLI1__MAX_BW_MASK 0x001FE000L 29648 #define DAGB6_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L 29649 #define DAGB6_WRCLI1__MIN_BW_MASK 0x01C00000L 29650 #define DAGB6_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 29651 #define DAGB6_WRCLI1__MAX_OSD_MASK 0xFC000000L 29652 //DAGB6_WRCLI2 29653 #define DAGB6_WRCLI2__VIRT_CHAN__SHIFT 0x0 29654 #define DAGB6_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 29655 #define DAGB6_WRCLI2__URG_HIGH__SHIFT 0x4 29656 #define DAGB6_WRCLI2__URG_LOW__SHIFT 0x8 29657 #define DAGB6_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc 29658 #define DAGB6_WRCLI2__MAX_BW__SHIFT 0xd 29659 #define DAGB6_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 29660 #define DAGB6_WRCLI2__MIN_BW__SHIFT 0x16 29661 #define DAGB6_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 29662 #define DAGB6_WRCLI2__MAX_OSD__SHIFT 0x1a 29663 #define DAGB6_WRCLI2__VIRT_CHAN_MASK 0x00000007L 29664 #define DAGB6_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 29665 #define DAGB6_WRCLI2__URG_HIGH_MASK 0x000000F0L 29666 #define DAGB6_WRCLI2__URG_LOW_MASK 0x00000F00L 29667 #define DAGB6_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L 29668 #define DAGB6_WRCLI2__MAX_BW_MASK 0x001FE000L 29669 #define DAGB6_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L 29670 #define DAGB6_WRCLI2__MIN_BW_MASK 0x01C00000L 29671 #define DAGB6_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 29672 #define DAGB6_WRCLI2__MAX_OSD_MASK 0xFC000000L 29673 //DAGB6_WRCLI3 29674 #define DAGB6_WRCLI3__VIRT_CHAN__SHIFT 0x0 29675 #define DAGB6_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 29676 #define DAGB6_WRCLI3__URG_HIGH__SHIFT 0x4 29677 #define DAGB6_WRCLI3__URG_LOW__SHIFT 0x8 29678 #define DAGB6_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc 29679 #define DAGB6_WRCLI3__MAX_BW__SHIFT 0xd 29680 #define DAGB6_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 29681 #define DAGB6_WRCLI3__MIN_BW__SHIFT 0x16 29682 #define DAGB6_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 29683 #define DAGB6_WRCLI3__MAX_OSD__SHIFT 0x1a 29684 #define DAGB6_WRCLI3__VIRT_CHAN_MASK 0x00000007L 29685 #define DAGB6_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 29686 #define DAGB6_WRCLI3__URG_HIGH_MASK 0x000000F0L 29687 #define DAGB6_WRCLI3__URG_LOW_MASK 0x00000F00L 29688 #define DAGB6_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L 29689 #define DAGB6_WRCLI3__MAX_BW_MASK 0x001FE000L 29690 #define DAGB6_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L 29691 #define DAGB6_WRCLI3__MIN_BW_MASK 0x01C00000L 29692 #define DAGB6_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 29693 #define DAGB6_WRCLI3__MAX_OSD_MASK 0xFC000000L 29694 //DAGB6_WRCLI4 29695 #define DAGB6_WRCLI4__VIRT_CHAN__SHIFT 0x0 29696 #define DAGB6_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 29697 #define DAGB6_WRCLI4__URG_HIGH__SHIFT 0x4 29698 #define DAGB6_WRCLI4__URG_LOW__SHIFT 0x8 29699 #define DAGB6_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc 29700 #define DAGB6_WRCLI4__MAX_BW__SHIFT 0xd 29701 #define DAGB6_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 29702 #define DAGB6_WRCLI4__MIN_BW__SHIFT 0x16 29703 #define DAGB6_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 29704 #define DAGB6_WRCLI4__MAX_OSD__SHIFT 0x1a 29705 #define DAGB6_WRCLI4__VIRT_CHAN_MASK 0x00000007L 29706 #define DAGB6_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 29707 #define DAGB6_WRCLI4__URG_HIGH_MASK 0x000000F0L 29708 #define DAGB6_WRCLI4__URG_LOW_MASK 0x00000F00L 29709 #define DAGB6_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L 29710 #define DAGB6_WRCLI4__MAX_BW_MASK 0x001FE000L 29711 #define DAGB6_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L 29712 #define DAGB6_WRCLI4__MIN_BW_MASK 0x01C00000L 29713 #define DAGB6_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 29714 #define DAGB6_WRCLI4__MAX_OSD_MASK 0xFC000000L 29715 //DAGB6_WRCLI5 29716 #define DAGB6_WRCLI5__VIRT_CHAN__SHIFT 0x0 29717 #define DAGB6_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 29718 #define DAGB6_WRCLI5__URG_HIGH__SHIFT 0x4 29719 #define DAGB6_WRCLI5__URG_LOW__SHIFT 0x8 29720 #define DAGB6_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc 29721 #define DAGB6_WRCLI5__MAX_BW__SHIFT 0xd 29722 #define DAGB6_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 29723 #define DAGB6_WRCLI5__MIN_BW__SHIFT 0x16 29724 #define DAGB6_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 29725 #define DAGB6_WRCLI5__MAX_OSD__SHIFT 0x1a 29726 #define DAGB6_WRCLI5__VIRT_CHAN_MASK 0x00000007L 29727 #define DAGB6_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 29728 #define DAGB6_WRCLI5__URG_HIGH_MASK 0x000000F0L 29729 #define DAGB6_WRCLI5__URG_LOW_MASK 0x00000F00L 29730 #define DAGB6_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L 29731 #define DAGB6_WRCLI5__MAX_BW_MASK 0x001FE000L 29732 #define DAGB6_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L 29733 #define DAGB6_WRCLI5__MIN_BW_MASK 0x01C00000L 29734 #define DAGB6_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 29735 #define DAGB6_WRCLI5__MAX_OSD_MASK 0xFC000000L 29736 //DAGB6_WRCLI6 29737 #define DAGB6_WRCLI6__VIRT_CHAN__SHIFT 0x0 29738 #define DAGB6_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 29739 #define DAGB6_WRCLI6__URG_HIGH__SHIFT 0x4 29740 #define DAGB6_WRCLI6__URG_LOW__SHIFT 0x8 29741 #define DAGB6_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc 29742 #define DAGB6_WRCLI6__MAX_BW__SHIFT 0xd 29743 #define DAGB6_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 29744 #define DAGB6_WRCLI6__MIN_BW__SHIFT 0x16 29745 #define DAGB6_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 29746 #define DAGB6_WRCLI6__MAX_OSD__SHIFT 0x1a 29747 #define DAGB6_WRCLI6__VIRT_CHAN_MASK 0x00000007L 29748 #define DAGB6_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 29749 #define DAGB6_WRCLI6__URG_HIGH_MASK 0x000000F0L 29750 #define DAGB6_WRCLI6__URG_LOW_MASK 0x00000F00L 29751 #define DAGB6_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L 29752 #define DAGB6_WRCLI6__MAX_BW_MASK 0x001FE000L 29753 #define DAGB6_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L 29754 #define DAGB6_WRCLI6__MIN_BW_MASK 0x01C00000L 29755 #define DAGB6_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 29756 #define DAGB6_WRCLI6__MAX_OSD_MASK 0xFC000000L 29757 //DAGB6_WRCLI7 29758 #define DAGB6_WRCLI7__VIRT_CHAN__SHIFT 0x0 29759 #define DAGB6_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 29760 #define DAGB6_WRCLI7__URG_HIGH__SHIFT 0x4 29761 #define DAGB6_WRCLI7__URG_LOW__SHIFT 0x8 29762 #define DAGB6_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc 29763 #define DAGB6_WRCLI7__MAX_BW__SHIFT 0xd 29764 #define DAGB6_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 29765 #define DAGB6_WRCLI7__MIN_BW__SHIFT 0x16 29766 #define DAGB6_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 29767 #define DAGB6_WRCLI7__MAX_OSD__SHIFT 0x1a 29768 #define DAGB6_WRCLI7__VIRT_CHAN_MASK 0x00000007L 29769 #define DAGB6_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 29770 #define DAGB6_WRCLI7__URG_HIGH_MASK 0x000000F0L 29771 #define DAGB6_WRCLI7__URG_LOW_MASK 0x00000F00L 29772 #define DAGB6_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L 29773 #define DAGB6_WRCLI7__MAX_BW_MASK 0x001FE000L 29774 #define DAGB6_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L 29775 #define DAGB6_WRCLI7__MIN_BW_MASK 0x01C00000L 29776 #define DAGB6_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 29777 #define DAGB6_WRCLI7__MAX_OSD_MASK 0xFC000000L 29778 //DAGB6_WRCLI8 29779 #define DAGB6_WRCLI8__VIRT_CHAN__SHIFT 0x0 29780 #define DAGB6_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 29781 #define DAGB6_WRCLI8__URG_HIGH__SHIFT 0x4 29782 #define DAGB6_WRCLI8__URG_LOW__SHIFT 0x8 29783 #define DAGB6_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc 29784 #define DAGB6_WRCLI8__MAX_BW__SHIFT 0xd 29785 #define DAGB6_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 29786 #define DAGB6_WRCLI8__MIN_BW__SHIFT 0x16 29787 #define DAGB6_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 29788 #define DAGB6_WRCLI8__MAX_OSD__SHIFT 0x1a 29789 #define DAGB6_WRCLI8__VIRT_CHAN_MASK 0x00000007L 29790 #define DAGB6_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 29791 #define DAGB6_WRCLI8__URG_HIGH_MASK 0x000000F0L 29792 #define DAGB6_WRCLI8__URG_LOW_MASK 0x00000F00L 29793 #define DAGB6_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L 29794 #define DAGB6_WRCLI8__MAX_BW_MASK 0x001FE000L 29795 #define DAGB6_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L 29796 #define DAGB6_WRCLI8__MIN_BW_MASK 0x01C00000L 29797 #define DAGB6_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 29798 #define DAGB6_WRCLI8__MAX_OSD_MASK 0xFC000000L 29799 //DAGB6_WRCLI9 29800 #define DAGB6_WRCLI9__VIRT_CHAN__SHIFT 0x0 29801 #define DAGB6_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 29802 #define DAGB6_WRCLI9__URG_HIGH__SHIFT 0x4 29803 #define DAGB6_WRCLI9__URG_LOW__SHIFT 0x8 29804 #define DAGB6_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc 29805 #define DAGB6_WRCLI9__MAX_BW__SHIFT 0xd 29806 #define DAGB6_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 29807 #define DAGB6_WRCLI9__MIN_BW__SHIFT 0x16 29808 #define DAGB6_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 29809 #define DAGB6_WRCLI9__MAX_OSD__SHIFT 0x1a 29810 #define DAGB6_WRCLI9__VIRT_CHAN_MASK 0x00000007L 29811 #define DAGB6_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 29812 #define DAGB6_WRCLI9__URG_HIGH_MASK 0x000000F0L 29813 #define DAGB6_WRCLI9__URG_LOW_MASK 0x00000F00L 29814 #define DAGB6_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L 29815 #define DAGB6_WRCLI9__MAX_BW_MASK 0x001FE000L 29816 #define DAGB6_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L 29817 #define DAGB6_WRCLI9__MIN_BW_MASK 0x01C00000L 29818 #define DAGB6_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 29819 #define DAGB6_WRCLI9__MAX_OSD_MASK 0xFC000000L 29820 //DAGB6_WRCLI10 29821 #define DAGB6_WRCLI10__VIRT_CHAN__SHIFT 0x0 29822 #define DAGB6_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 29823 #define DAGB6_WRCLI10__URG_HIGH__SHIFT 0x4 29824 #define DAGB6_WRCLI10__URG_LOW__SHIFT 0x8 29825 #define DAGB6_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc 29826 #define DAGB6_WRCLI10__MAX_BW__SHIFT 0xd 29827 #define DAGB6_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 29828 #define DAGB6_WRCLI10__MIN_BW__SHIFT 0x16 29829 #define DAGB6_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 29830 #define DAGB6_WRCLI10__MAX_OSD__SHIFT 0x1a 29831 #define DAGB6_WRCLI10__VIRT_CHAN_MASK 0x00000007L 29832 #define DAGB6_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 29833 #define DAGB6_WRCLI10__URG_HIGH_MASK 0x000000F0L 29834 #define DAGB6_WRCLI10__URG_LOW_MASK 0x00000F00L 29835 #define DAGB6_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L 29836 #define DAGB6_WRCLI10__MAX_BW_MASK 0x001FE000L 29837 #define DAGB6_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L 29838 #define DAGB6_WRCLI10__MIN_BW_MASK 0x01C00000L 29839 #define DAGB6_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 29840 #define DAGB6_WRCLI10__MAX_OSD_MASK 0xFC000000L 29841 //DAGB6_WRCLI11 29842 #define DAGB6_WRCLI11__VIRT_CHAN__SHIFT 0x0 29843 #define DAGB6_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 29844 #define DAGB6_WRCLI11__URG_HIGH__SHIFT 0x4 29845 #define DAGB6_WRCLI11__URG_LOW__SHIFT 0x8 29846 #define DAGB6_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc 29847 #define DAGB6_WRCLI11__MAX_BW__SHIFT 0xd 29848 #define DAGB6_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 29849 #define DAGB6_WRCLI11__MIN_BW__SHIFT 0x16 29850 #define DAGB6_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 29851 #define DAGB6_WRCLI11__MAX_OSD__SHIFT 0x1a 29852 #define DAGB6_WRCLI11__VIRT_CHAN_MASK 0x00000007L 29853 #define DAGB6_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 29854 #define DAGB6_WRCLI11__URG_HIGH_MASK 0x000000F0L 29855 #define DAGB6_WRCLI11__URG_LOW_MASK 0x00000F00L 29856 #define DAGB6_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L 29857 #define DAGB6_WRCLI11__MAX_BW_MASK 0x001FE000L 29858 #define DAGB6_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L 29859 #define DAGB6_WRCLI11__MIN_BW_MASK 0x01C00000L 29860 #define DAGB6_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 29861 #define DAGB6_WRCLI11__MAX_OSD_MASK 0xFC000000L 29862 //DAGB6_WRCLI12 29863 #define DAGB6_WRCLI12__VIRT_CHAN__SHIFT 0x0 29864 #define DAGB6_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 29865 #define DAGB6_WRCLI12__URG_HIGH__SHIFT 0x4 29866 #define DAGB6_WRCLI12__URG_LOW__SHIFT 0x8 29867 #define DAGB6_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc 29868 #define DAGB6_WRCLI12__MAX_BW__SHIFT 0xd 29869 #define DAGB6_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 29870 #define DAGB6_WRCLI12__MIN_BW__SHIFT 0x16 29871 #define DAGB6_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 29872 #define DAGB6_WRCLI12__MAX_OSD__SHIFT 0x1a 29873 #define DAGB6_WRCLI12__VIRT_CHAN_MASK 0x00000007L 29874 #define DAGB6_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 29875 #define DAGB6_WRCLI12__URG_HIGH_MASK 0x000000F0L 29876 #define DAGB6_WRCLI12__URG_LOW_MASK 0x00000F00L 29877 #define DAGB6_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L 29878 #define DAGB6_WRCLI12__MAX_BW_MASK 0x001FE000L 29879 #define DAGB6_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L 29880 #define DAGB6_WRCLI12__MIN_BW_MASK 0x01C00000L 29881 #define DAGB6_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 29882 #define DAGB6_WRCLI12__MAX_OSD_MASK 0xFC000000L 29883 //DAGB6_WRCLI13 29884 #define DAGB6_WRCLI13__VIRT_CHAN__SHIFT 0x0 29885 #define DAGB6_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 29886 #define DAGB6_WRCLI13__URG_HIGH__SHIFT 0x4 29887 #define DAGB6_WRCLI13__URG_LOW__SHIFT 0x8 29888 #define DAGB6_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc 29889 #define DAGB6_WRCLI13__MAX_BW__SHIFT 0xd 29890 #define DAGB6_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 29891 #define DAGB6_WRCLI13__MIN_BW__SHIFT 0x16 29892 #define DAGB6_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 29893 #define DAGB6_WRCLI13__MAX_OSD__SHIFT 0x1a 29894 #define DAGB6_WRCLI13__VIRT_CHAN_MASK 0x00000007L 29895 #define DAGB6_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 29896 #define DAGB6_WRCLI13__URG_HIGH_MASK 0x000000F0L 29897 #define DAGB6_WRCLI13__URG_LOW_MASK 0x00000F00L 29898 #define DAGB6_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L 29899 #define DAGB6_WRCLI13__MAX_BW_MASK 0x001FE000L 29900 #define DAGB6_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L 29901 #define DAGB6_WRCLI13__MIN_BW_MASK 0x01C00000L 29902 #define DAGB6_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 29903 #define DAGB6_WRCLI13__MAX_OSD_MASK 0xFC000000L 29904 //DAGB6_WRCLI14 29905 #define DAGB6_WRCLI14__VIRT_CHAN__SHIFT 0x0 29906 #define DAGB6_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 29907 #define DAGB6_WRCLI14__URG_HIGH__SHIFT 0x4 29908 #define DAGB6_WRCLI14__URG_LOW__SHIFT 0x8 29909 #define DAGB6_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc 29910 #define DAGB6_WRCLI14__MAX_BW__SHIFT 0xd 29911 #define DAGB6_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 29912 #define DAGB6_WRCLI14__MIN_BW__SHIFT 0x16 29913 #define DAGB6_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 29914 #define DAGB6_WRCLI14__MAX_OSD__SHIFT 0x1a 29915 #define DAGB6_WRCLI14__VIRT_CHAN_MASK 0x00000007L 29916 #define DAGB6_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 29917 #define DAGB6_WRCLI14__URG_HIGH_MASK 0x000000F0L 29918 #define DAGB6_WRCLI14__URG_LOW_MASK 0x00000F00L 29919 #define DAGB6_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L 29920 #define DAGB6_WRCLI14__MAX_BW_MASK 0x001FE000L 29921 #define DAGB6_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L 29922 #define DAGB6_WRCLI14__MIN_BW_MASK 0x01C00000L 29923 #define DAGB6_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 29924 #define DAGB6_WRCLI14__MAX_OSD_MASK 0xFC000000L 29925 //DAGB6_WRCLI15 29926 #define DAGB6_WRCLI15__VIRT_CHAN__SHIFT 0x0 29927 #define DAGB6_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 29928 #define DAGB6_WRCLI15__URG_HIGH__SHIFT 0x4 29929 #define DAGB6_WRCLI15__URG_LOW__SHIFT 0x8 29930 #define DAGB6_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc 29931 #define DAGB6_WRCLI15__MAX_BW__SHIFT 0xd 29932 #define DAGB6_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 29933 #define DAGB6_WRCLI15__MIN_BW__SHIFT 0x16 29934 #define DAGB6_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 29935 #define DAGB6_WRCLI15__MAX_OSD__SHIFT 0x1a 29936 #define DAGB6_WRCLI15__VIRT_CHAN_MASK 0x00000007L 29937 #define DAGB6_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 29938 #define DAGB6_WRCLI15__URG_HIGH_MASK 0x000000F0L 29939 #define DAGB6_WRCLI15__URG_LOW_MASK 0x00000F00L 29940 #define DAGB6_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L 29941 #define DAGB6_WRCLI15__MAX_BW_MASK 0x001FE000L 29942 #define DAGB6_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L 29943 #define DAGB6_WRCLI15__MIN_BW_MASK 0x01C00000L 29944 #define DAGB6_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 29945 #define DAGB6_WRCLI15__MAX_OSD_MASK 0xFC000000L 29946 //DAGB6_WR_CNTL 29947 #define DAGB6_WR_CNTL__SCLK_FREQ__SHIFT 0x0 29948 #define DAGB6_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 29949 #define DAGB6_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 29950 #define DAGB6_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 29951 #define DAGB6_WR_CNTL__IO_LEVEL__SHIFT 0x11 29952 #define DAGB6_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 29953 #define DAGB6_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 29954 #define DAGB6_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL 29955 #define DAGB6_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 29956 #define DAGB6_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 29957 #define DAGB6_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 29958 #define DAGB6_WR_CNTL__IO_LEVEL_MASK 0x000E0000L 29959 #define DAGB6_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 29960 #define DAGB6_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L 29961 //DAGB6_WR_GMI_CNTL 29962 #define DAGB6_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 29963 #define DAGB6_WR_GMI_CNTL__LEVEL__SHIFT 0x6 29964 #define DAGB6_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 29965 #define DAGB6_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 29966 #define DAGB6_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 29967 #define DAGB6_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L 29968 #define DAGB6_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 29969 #define DAGB6_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 29970 //DAGB6_WR_ADDR_DAGB 29971 #define DAGB6_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 29972 #define DAGB6_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 29973 #define DAGB6_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 29974 #define DAGB6_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 29975 #define DAGB6_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 29976 #define DAGB6_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 29977 #define DAGB6_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 29978 #define DAGB6_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 29979 //DAGB6_WR_OUTPUT_DAGB_MAX_BURST 29980 #define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 29981 #define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 29982 #define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 29983 #define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 29984 #define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 29985 #define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 29986 #define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 29987 #define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 29988 #define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 29989 #define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 29990 #define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 29991 #define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 29992 #define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 29993 #define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 29994 #define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 29995 #define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 29996 //DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER 29997 #define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 29998 #define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 29999 #define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 30000 #define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 30001 #define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 30002 #define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 30003 #define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 30004 #define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 30005 #define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 30006 #define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 30007 #define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 30008 #define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 30009 #define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 30010 #define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 30011 #define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 30012 #define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 30013 //DAGB6_WR_CGTT_CLK_CTRL 30014 #define DAGB6_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 30015 #define DAGB6_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 30016 #define DAGB6_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 30017 #define DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 30018 #define DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 30019 #define DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 30020 #define DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 30021 #define DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 30022 #define DAGB6_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 30023 #define DAGB6_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 30024 #define DAGB6_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 30025 #define DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 30026 #define DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 30027 #define DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 30028 #define DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 30029 #define DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 30030 //DAGB6_L1TLB_WR_CGTT_CLK_CTRL 30031 #define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 30032 #define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 30033 #define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 30034 #define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 30035 #define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 30036 #define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 30037 #define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 30038 #define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 30039 #define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 30040 #define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 30041 #define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 30042 #define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 30043 #define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 30044 #define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 30045 #define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 30046 #define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 30047 //DAGB6_ATCVM_WR_CGTT_CLK_CTRL 30048 #define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 30049 #define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 30050 #define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 30051 #define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 30052 #define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 30053 #define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 30054 #define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 30055 #define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 30056 #define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 30057 #define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 30058 #define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 30059 #define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 30060 #define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 30061 #define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 30062 #define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 30063 #define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 30064 //DAGB6_WR_ADDR_DAGB_MAX_BURST0 30065 #define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 30066 #define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 30067 #define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 30068 #define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 30069 #define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 30070 #define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 30071 #define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 30072 #define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 30073 #define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 30074 #define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 30075 #define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 30076 #define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 30077 #define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 30078 #define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 30079 #define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 30080 #define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 30081 //DAGB6_WR_ADDR_DAGB_LAZY_TIMER0 30082 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 30083 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 30084 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 30085 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 30086 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 30087 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 30088 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 30089 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 30090 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 30091 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 30092 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 30093 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 30094 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 30095 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 30096 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 30097 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 30098 //DAGB6_WR_ADDR_DAGB_MAX_BURST1 30099 #define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 30100 #define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 30101 #define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 30102 #define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 30103 #define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 30104 #define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 30105 #define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 30106 #define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 30107 #define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 30108 #define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 30109 #define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 30110 #define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 30111 #define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 30112 #define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 30113 #define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 30114 #define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 30115 //DAGB6_WR_ADDR_DAGB_LAZY_TIMER1 30116 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 30117 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 30118 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 30119 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 30120 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 30121 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 30122 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 30123 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 30124 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 30125 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 30126 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 30127 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 30128 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 30129 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 30130 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 30131 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 30132 //DAGB6_WR_DATA_DAGB 30133 #define DAGB6_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 30134 #define DAGB6_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 30135 #define DAGB6_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 30136 #define DAGB6_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 30137 #define DAGB6_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L 30138 #define DAGB6_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 30139 #define DAGB6_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 30140 #define DAGB6_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L 30141 //DAGB6_WR_DATA_DAGB_MAX_BURST0 30142 #define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 30143 #define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 30144 #define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 30145 #define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 30146 #define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 30147 #define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 30148 #define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 30149 #define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 30150 #define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 30151 #define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 30152 #define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 30153 #define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 30154 #define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 30155 #define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 30156 #define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 30157 #define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 30158 //DAGB6_WR_DATA_DAGB_LAZY_TIMER0 30159 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 30160 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 30161 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 30162 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 30163 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 30164 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 30165 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 30166 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 30167 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 30168 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 30169 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 30170 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 30171 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 30172 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 30173 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 30174 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 30175 //DAGB6_WR_DATA_DAGB_MAX_BURST1 30176 #define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 30177 #define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 30178 #define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 30179 #define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 30180 #define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 30181 #define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 30182 #define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 30183 #define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 30184 #define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 30185 #define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 30186 #define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 30187 #define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 30188 #define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 30189 #define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 30190 #define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 30191 #define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 30192 //DAGB6_WR_DATA_DAGB_LAZY_TIMER1 30193 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 30194 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 30195 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 30196 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 30197 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 30198 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 30199 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 30200 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 30201 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 30202 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 30203 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 30204 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 30205 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 30206 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 30207 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 30208 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 30209 //DAGB6_WR_VC0_CNTL 30210 #define DAGB6_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 30211 #define DAGB6_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 30212 #define DAGB6_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 30213 #define DAGB6_WR_VC0_CNTL__MAX_BW__SHIFT 0xc 30214 #define DAGB6_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 30215 #define DAGB6_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 30216 #define DAGB6_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 30217 #define DAGB6_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 30218 #define DAGB6_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 30219 #define DAGB6_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 30220 #define DAGB6_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 30221 #define DAGB6_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L 30222 #define DAGB6_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 30223 #define DAGB6_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L 30224 #define DAGB6_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 30225 #define DAGB6_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 30226 //DAGB6_WR_VC1_CNTL 30227 #define DAGB6_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 30228 #define DAGB6_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 30229 #define DAGB6_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 30230 #define DAGB6_WR_VC1_CNTL__MAX_BW__SHIFT 0xc 30231 #define DAGB6_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 30232 #define DAGB6_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 30233 #define DAGB6_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 30234 #define DAGB6_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 30235 #define DAGB6_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 30236 #define DAGB6_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 30237 #define DAGB6_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 30238 #define DAGB6_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L 30239 #define DAGB6_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 30240 #define DAGB6_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L 30241 #define DAGB6_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 30242 #define DAGB6_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 30243 //DAGB6_WR_VC2_CNTL 30244 #define DAGB6_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 30245 #define DAGB6_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 30246 #define DAGB6_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 30247 #define DAGB6_WR_VC2_CNTL__MAX_BW__SHIFT 0xc 30248 #define DAGB6_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 30249 #define DAGB6_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 30250 #define DAGB6_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 30251 #define DAGB6_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 30252 #define DAGB6_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 30253 #define DAGB6_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 30254 #define DAGB6_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 30255 #define DAGB6_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L 30256 #define DAGB6_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 30257 #define DAGB6_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L 30258 #define DAGB6_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 30259 #define DAGB6_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 30260 //DAGB6_WR_VC3_CNTL 30261 #define DAGB6_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 30262 #define DAGB6_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 30263 #define DAGB6_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 30264 #define DAGB6_WR_VC3_CNTL__MAX_BW__SHIFT 0xc 30265 #define DAGB6_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 30266 #define DAGB6_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 30267 #define DAGB6_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 30268 #define DAGB6_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 30269 #define DAGB6_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 30270 #define DAGB6_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 30271 #define DAGB6_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 30272 #define DAGB6_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L 30273 #define DAGB6_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 30274 #define DAGB6_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L 30275 #define DAGB6_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 30276 #define DAGB6_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 30277 //DAGB6_WR_VC4_CNTL 30278 #define DAGB6_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 30279 #define DAGB6_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 30280 #define DAGB6_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 30281 #define DAGB6_WR_VC4_CNTL__MAX_BW__SHIFT 0xc 30282 #define DAGB6_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 30283 #define DAGB6_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 30284 #define DAGB6_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 30285 #define DAGB6_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 30286 #define DAGB6_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 30287 #define DAGB6_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 30288 #define DAGB6_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 30289 #define DAGB6_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L 30290 #define DAGB6_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 30291 #define DAGB6_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L 30292 #define DAGB6_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 30293 #define DAGB6_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 30294 //DAGB6_WR_VC5_CNTL 30295 #define DAGB6_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 30296 #define DAGB6_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 30297 #define DAGB6_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 30298 #define DAGB6_WR_VC5_CNTL__MAX_BW__SHIFT 0xc 30299 #define DAGB6_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 30300 #define DAGB6_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 30301 #define DAGB6_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 30302 #define DAGB6_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 30303 #define DAGB6_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 30304 #define DAGB6_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 30305 #define DAGB6_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 30306 #define DAGB6_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L 30307 #define DAGB6_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 30308 #define DAGB6_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L 30309 #define DAGB6_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 30310 #define DAGB6_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 30311 //DAGB6_WR_VC6_CNTL 30312 #define DAGB6_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 30313 #define DAGB6_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 30314 #define DAGB6_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 30315 #define DAGB6_WR_VC6_CNTL__MAX_BW__SHIFT 0xc 30316 #define DAGB6_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 30317 #define DAGB6_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 30318 #define DAGB6_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 30319 #define DAGB6_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 30320 #define DAGB6_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 30321 #define DAGB6_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 30322 #define DAGB6_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 30323 #define DAGB6_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L 30324 #define DAGB6_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 30325 #define DAGB6_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L 30326 #define DAGB6_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 30327 #define DAGB6_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 30328 //DAGB6_WR_VC7_CNTL 30329 #define DAGB6_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 30330 #define DAGB6_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 30331 #define DAGB6_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 30332 #define DAGB6_WR_VC7_CNTL__MAX_BW__SHIFT 0xc 30333 #define DAGB6_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 30334 #define DAGB6_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 30335 #define DAGB6_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 30336 #define DAGB6_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 30337 #define DAGB6_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 30338 #define DAGB6_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 30339 #define DAGB6_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 30340 #define DAGB6_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L 30341 #define DAGB6_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 30342 #define DAGB6_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L 30343 #define DAGB6_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 30344 #define DAGB6_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 30345 //DAGB6_WR_CNTL_MISC 30346 #define DAGB6_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 30347 #define DAGB6_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 30348 #define DAGB6_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 30349 #define DAGB6_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 30350 #define DAGB6_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 30351 #define DAGB6_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 30352 #define DAGB6_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a 30353 #define DAGB6_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 30354 #define DAGB6_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 30355 #define DAGB6_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 30356 #define DAGB6_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 30357 #define DAGB6_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 30358 #define DAGB6_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 30359 #define DAGB6_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L 30360 //DAGB6_WR_TLB_CREDIT 30361 #define DAGB6_WR_TLB_CREDIT__TLB0__SHIFT 0x0 30362 #define DAGB6_WR_TLB_CREDIT__TLB1__SHIFT 0x5 30363 #define DAGB6_WR_TLB_CREDIT__TLB2__SHIFT 0xa 30364 #define DAGB6_WR_TLB_CREDIT__TLB3__SHIFT 0xf 30365 #define DAGB6_WR_TLB_CREDIT__TLB4__SHIFT 0x14 30366 #define DAGB6_WR_TLB_CREDIT__TLB5__SHIFT 0x19 30367 #define DAGB6_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL 30368 #define DAGB6_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L 30369 #define DAGB6_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L 30370 #define DAGB6_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L 30371 #define DAGB6_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L 30372 #define DAGB6_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L 30373 //DAGB6_WR_DATA_CREDIT 30374 #define DAGB6_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 30375 #define DAGB6_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 30376 #define DAGB6_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 30377 #define DAGB6_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 30378 #define DAGB6_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL 30379 #define DAGB6_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L 30380 #define DAGB6_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L 30381 #define DAGB6_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L 30382 //DAGB6_WR_MISC_CREDIT 30383 #define DAGB6_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 30384 #define DAGB6_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 30385 #define DAGB6_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 30386 #define DAGB6_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 30387 #define DAGB6_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL 30388 #define DAGB6_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L 30389 #define DAGB6_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L 30390 #define DAGB6_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L 30391 //DAGB6_WRCLI_ASK_PENDING 30392 #define DAGB6_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 30393 #define DAGB6_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 30394 //DAGB6_WRCLI_GO_PENDING 30395 #define DAGB6_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 30396 #define DAGB6_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 30397 //DAGB6_WRCLI_GBLSEND_PENDING 30398 #define DAGB6_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 30399 #define DAGB6_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 30400 //DAGB6_WRCLI_TLB_PENDING 30401 #define DAGB6_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 30402 #define DAGB6_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 30403 //DAGB6_WRCLI_OARB_PENDING 30404 #define DAGB6_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 30405 #define DAGB6_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 30406 //DAGB6_WRCLI_OSD_PENDING 30407 #define DAGB6_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 30408 #define DAGB6_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 30409 //DAGB6_WRCLI_DBUS_ASK_PENDING 30410 #define DAGB6_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 30411 #define DAGB6_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 30412 //DAGB6_WRCLI_DBUS_GO_PENDING 30413 #define DAGB6_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 30414 #define DAGB6_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 30415 //DAGB6_DAGB_DLY 30416 #define DAGB6_DAGB_DLY__DLY__SHIFT 0x0 30417 #define DAGB6_DAGB_DLY__CLI__SHIFT 0x8 30418 #define DAGB6_DAGB_DLY__POS__SHIFT 0x10 30419 #define DAGB6_DAGB_DLY__DLY_MASK 0x000000FFL 30420 #define DAGB6_DAGB_DLY__CLI_MASK 0x0000FF00L 30421 #define DAGB6_DAGB_DLY__POS_MASK 0x000F0000L 30422 //DAGB6_CNTL_MISC 30423 #define DAGB6_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 30424 #define DAGB6_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 30425 #define DAGB6_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 30426 #define DAGB6_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 30427 #define DAGB6_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc 30428 #define DAGB6_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf 30429 #define DAGB6_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 30430 #define DAGB6_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 30431 #define DAGB6_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 30432 #define DAGB6_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e 30433 #define DAGB6_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L 30434 #define DAGB6_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L 30435 #define DAGB6_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L 30436 #define DAGB6_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L 30437 #define DAGB6_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L 30438 #define DAGB6_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L 30439 #define DAGB6_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L 30440 #define DAGB6_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L 30441 #define DAGB6_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L 30442 #define DAGB6_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L 30443 //DAGB6_CNTL_MISC2 30444 #define DAGB6_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 30445 #define DAGB6_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 30446 #define DAGB6_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 30447 #define DAGB6_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 30448 #define DAGB6_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 30449 #define DAGB6_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 30450 #define DAGB6_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 30451 #define DAGB6_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 30452 #define DAGB6_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 30453 #define DAGB6_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 30454 #define DAGB6_CNTL_MISC2__SWAP_CTL__SHIFT 0xa 30455 #define DAGB6_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xb 30456 #define DAGB6_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x11 30457 #define DAGB6_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L 30458 #define DAGB6_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L 30459 #define DAGB6_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L 30460 #define DAGB6_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L 30461 #define DAGB6_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L 30462 #define DAGB6_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L 30463 #define DAGB6_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L 30464 #define DAGB6_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L 30465 #define DAGB6_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L 30466 #define DAGB6_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L 30467 #define DAGB6_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L 30468 #define DAGB6_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000800L 30469 #define DAGB6_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x007E0000L 30470 //DAGB6_FIFO_EMPTY 30471 #define DAGB6_FIFO_EMPTY__EMPTY__SHIFT 0x0 30472 #define DAGB6_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL 30473 //DAGB6_FIFO_FULL 30474 #define DAGB6_FIFO_FULL__FULL__SHIFT 0x0 30475 #define DAGB6_FIFO_FULL__FULL_MASK 0x007FFFFFL 30476 //DAGB6_WR_CREDITS_FULL 30477 #define DAGB6_WR_CREDITS_FULL__FULL__SHIFT 0x0 30478 #define DAGB6_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL 30479 //DAGB6_RD_CREDITS_FULL 30480 #define DAGB6_RD_CREDITS_FULL__FULL__SHIFT 0x0 30481 #define DAGB6_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL 30482 //DAGB6_PERFCOUNTER_LO 30483 #define DAGB6_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 30484 #define DAGB6_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 30485 //DAGB6_PERFCOUNTER_HI 30486 #define DAGB6_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 30487 #define DAGB6_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 30488 #define DAGB6_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 30489 #define DAGB6_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 30490 //DAGB6_PERFCOUNTER0_CFG 30491 #define DAGB6_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 30492 #define DAGB6_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 30493 #define DAGB6_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 30494 #define DAGB6_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 30495 #define DAGB6_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 30496 #define DAGB6_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 30497 #define DAGB6_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 30498 #define DAGB6_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 30499 #define DAGB6_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 30500 #define DAGB6_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 30501 //DAGB6_PERFCOUNTER1_CFG 30502 #define DAGB6_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 30503 #define DAGB6_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 30504 #define DAGB6_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 30505 #define DAGB6_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 30506 #define DAGB6_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 30507 #define DAGB6_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 30508 #define DAGB6_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 30509 #define DAGB6_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 30510 #define DAGB6_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 30511 #define DAGB6_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 30512 //DAGB6_PERFCOUNTER2_CFG 30513 #define DAGB6_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 30514 #define DAGB6_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 30515 #define DAGB6_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 30516 #define DAGB6_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 30517 #define DAGB6_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 30518 #define DAGB6_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 30519 #define DAGB6_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 30520 #define DAGB6_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 30521 #define DAGB6_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 30522 #define DAGB6_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 30523 //DAGB6_PERFCOUNTER_RSLT_CNTL 30524 #define DAGB6_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 30525 #define DAGB6_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 30526 #define DAGB6_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 30527 #define DAGB6_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 30528 #define DAGB6_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 30529 #define DAGB6_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 30530 #define DAGB6_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 30531 #define DAGB6_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 30532 #define DAGB6_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 30533 #define DAGB6_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 30534 #define DAGB6_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 30535 #define DAGB6_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 30536 //DAGB6_RESERVE0 30537 #define DAGB6_RESERVE0__RESERVE__SHIFT 0x0 30538 #define DAGB6_RESERVE0__RESERVE_MASK 0xFFFFFFFFL 30539 //DAGB6_RESERVE1 30540 #define DAGB6_RESERVE1__RESERVE__SHIFT 0x0 30541 #define DAGB6_RESERVE1__RESERVE_MASK 0xFFFFFFFFL 30542 //DAGB6_RESERVE2 30543 #define DAGB6_RESERVE2__RESERVE__SHIFT 0x0 30544 #define DAGB6_RESERVE2__RESERVE_MASK 0xFFFFFFFFL 30545 //DAGB6_RESERVE3 30546 #define DAGB6_RESERVE3__RESERVE__SHIFT 0x0 30547 #define DAGB6_RESERVE3__RESERVE_MASK 0xFFFFFFFFL 30548 //DAGB6_RESERVE4 30549 #define DAGB6_RESERVE4__RESERVE__SHIFT 0x0 30550 #define DAGB6_RESERVE4__RESERVE_MASK 0xFFFFFFFFL 30551 //DAGB6_RESERVE5 30552 #define DAGB6_RESERVE5__RESERVE__SHIFT 0x0 30553 #define DAGB6_RESERVE5__RESERVE_MASK 0xFFFFFFFFL 30554 //DAGB6_RESERVE6 30555 #define DAGB6_RESERVE6__RESERVE__SHIFT 0x0 30556 #define DAGB6_RESERVE6__RESERVE_MASK 0xFFFFFFFFL 30557 //DAGB6_RESERVE7 30558 #define DAGB6_RESERVE7__RESERVE__SHIFT 0x0 30559 #define DAGB6_RESERVE7__RESERVE_MASK 0xFFFFFFFFL 30560 //DAGB6_RESERVE8 30561 #define DAGB6_RESERVE8__RESERVE__SHIFT 0x0 30562 #define DAGB6_RESERVE8__RESERVE_MASK 0xFFFFFFFFL 30563 //DAGB6_RESERVE9 30564 #define DAGB6_RESERVE9__RESERVE__SHIFT 0x0 30565 #define DAGB6_RESERVE9__RESERVE_MASK 0xFFFFFFFFL 30566 //DAGB6_RESERVE10 30567 #define DAGB6_RESERVE10__RESERVE__SHIFT 0x0 30568 #define DAGB6_RESERVE10__RESERVE_MASK 0xFFFFFFFFL 30569 //DAGB6_RESERVE11 30570 #define DAGB6_RESERVE11__RESERVE__SHIFT 0x0 30571 #define DAGB6_RESERVE11__RESERVE_MASK 0xFFFFFFFFL 30572 //DAGB6_RESERVE12 30573 #define DAGB6_RESERVE12__RESERVE__SHIFT 0x0 30574 #define DAGB6_RESERVE12__RESERVE_MASK 0xFFFFFFFFL 30575 //DAGB6_RESERVE13 30576 #define DAGB6_RESERVE13__RESERVE__SHIFT 0x0 30577 #define DAGB6_RESERVE13__RESERVE_MASK 0xFFFFFFFFL 30578 30579 30580 // addressBlock: mmhub_dagb_dagbdec7 30581 //DAGB7_RDCLI0 30582 #define DAGB7_RDCLI0__VIRT_CHAN__SHIFT 0x0 30583 #define DAGB7_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 30584 #define DAGB7_RDCLI0__URG_HIGH__SHIFT 0x4 30585 #define DAGB7_RDCLI0__URG_LOW__SHIFT 0x8 30586 #define DAGB7_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 30587 #define DAGB7_RDCLI0__MAX_BW__SHIFT 0xd 30588 #define DAGB7_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 30589 #define DAGB7_RDCLI0__MIN_BW__SHIFT 0x16 30590 #define DAGB7_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 30591 #define DAGB7_RDCLI0__MAX_OSD__SHIFT 0x1a 30592 #define DAGB7_RDCLI0__VIRT_CHAN_MASK 0x00000007L 30593 #define DAGB7_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 30594 #define DAGB7_RDCLI0__URG_HIGH_MASK 0x000000F0L 30595 #define DAGB7_RDCLI0__URG_LOW_MASK 0x00000F00L 30596 #define DAGB7_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L 30597 #define DAGB7_RDCLI0__MAX_BW_MASK 0x001FE000L 30598 #define DAGB7_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L 30599 #define DAGB7_RDCLI0__MIN_BW_MASK 0x01C00000L 30600 #define DAGB7_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 30601 #define DAGB7_RDCLI0__MAX_OSD_MASK 0xFC000000L 30602 //DAGB7_RDCLI1 30603 #define DAGB7_RDCLI1__VIRT_CHAN__SHIFT 0x0 30604 #define DAGB7_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 30605 #define DAGB7_RDCLI1__URG_HIGH__SHIFT 0x4 30606 #define DAGB7_RDCLI1__URG_LOW__SHIFT 0x8 30607 #define DAGB7_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc 30608 #define DAGB7_RDCLI1__MAX_BW__SHIFT 0xd 30609 #define DAGB7_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 30610 #define DAGB7_RDCLI1__MIN_BW__SHIFT 0x16 30611 #define DAGB7_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 30612 #define DAGB7_RDCLI1__MAX_OSD__SHIFT 0x1a 30613 #define DAGB7_RDCLI1__VIRT_CHAN_MASK 0x00000007L 30614 #define DAGB7_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 30615 #define DAGB7_RDCLI1__URG_HIGH_MASK 0x000000F0L 30616 #define DAGB7_RDCLI1__URG_LOW_MASK 0x00000F00L 30617 #define DAGB7_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L 30618 #define DAGB7_RDCLI1__MAX_BW_MASK 0x001FE000L 30619 #define DAGB7_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L 30620 #define DAGB7_RDCLI1__MIN_BW_MASK 0x01C00000L 30621 #define DAGB7_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 30622 #define DAGB7_RDCLI1__MAX_OSD_MASK 0xFC000000L 30623 //DAGB7_RDCLI2 30624 #define DAGB7_RDCLI2__VIRT_CHAN__SHIFT 0x0 30625 #define DAGB7_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 30626 #define DAGB7_RDCLI2__URG_HIGH__SHIFT 0x4 30627 #define DAGB7_RDCLI2__URG_LOW__SHIFT 0x8 30628 #define DAGB7_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc 30629 #define DAGB7_RDCLI2__MAX_BW__SHIFT 0xd 30630 #define DAGB7_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 30631 #define DAGB7_RDCLI2__MIN_BW__SHIFT 0x16 30632 #define DAGB7_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 30633 #define DAGB7_RDCLI2__MAX_OSD__SHIFT 0x1a 30634 #define DAGB7_RDCLI2__VIRT_CHAN_MASK 0x00000007L 30635 #define DAGB7_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 30636 #define DAGB7_RDCLI2__URG_HIGH_MASK 0x000000F0L 30637 #define DAGB7_RDCLI2__URG_LOW_MASK 0x00000F00L 30638 #define DAGB7_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L 30639 #define DAGB7_RDCLI2__MAX_BW_MASK 0x001FE000L 30640 #define DAGB7_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L 30641 #define DAGB7_RDCLI2__MIN_BW_MASK 0x01C00000L 30642 #define DAGB7_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 30643 #define DAGB7_RDCLI2__MAX_OSD_MASK 0xFC000000L 30644 //DAGB7_RDCLI3 30645 #define DAGB7_RDCLI3__VIRT_CHAN__SHIFT 0x0 30646 #define DAGB7_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 30647 #define DAGB7_RDCLI3__URG_HIGH__SHIFT 0x4 30648 #define DAGB7_RDCLI3__URG_LOW__SHIFT 0x8 30649 #define DAGB7_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc 30650 #define DAGB7_RDCLI3__MAX_BW__SHIFT 0xd 30651 #define DAGB7_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 30652 #define DAGB7_RDCLI3__MIN_BW__SHIFT 0x16 30653 #define DAGB7_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 30654 #define DAGB7_RDCLI3__MAX_OSD__SHIFT 0x1a 30655 #define DAGB7_RDCLI3__VIRT_CHAN_MASK 0x00000007L 30656 #define DAGB7_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 30657 #define DAGB7_RDCLI3__URG_HIGH_MASK 0x000000F0L 30658 #define DAGB7_RDCLI3__URG_LOW_MASK 0x00000F00L 30659 #define DAGB7_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L 30660 #define DAGB7_RDCLI3__MAX_BW_MASK 0x001FE000L 30661 #define DAGB7_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L 30662 #define DAGB7_RDCLI3__MIN_BW_MASK 0x01C00000L 30663 #define DAGB7_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 30664 #define DAGB7_RDCLI3__MAX_OSD_MASK 0xFC000000L 30665 //DAGB7_RDCLI4 30666 #define DAGB7_RDCLI4__VIRT_CHAN__SHIFT 0x0 30667 #define DAGB7_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 30668 #define DAGB7_RDCLI4__URG_HIGH__SHIFT 0x4 30669 #define DAGB7_RDCLI4__URG_LOW__SHIFT 0x8 30670 #define DAGB7_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc 30671 #define DAGB7_RDCLI4__MAX_BW__SHIFT 0xd 30672 #define DAGB7_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 30673 #define DAGB7_RDCLI4__MIN_BW__SHIFT 0x16 30674 #define DAGB7_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 30675 #define DAGB7_RDCLI4__MAX_OSD__SHIFT 0x1a 30676 #define DAGB7_RDCLI4__VIRT_CHAN_MASK 0x00000007L 30677 #define DAGB7_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 30678 #define DAGB7_RDCLI4__URG_HIGH_MASK 0x000000F0L 30679 #define DAGB7_RDCLI4__URG_LOW_MASK 0x00000F00L 30680 #define DAGB7_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L 30681 #define DAGB7_RDCLI4__MAX_BW_MASK 0x001FE000L 30682 #define DAGB7_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L 30683 #define DAGB7_RDCLI4__MIN_BW_MASK 0x01C00000L 30684 #define DAGB7_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 30685 #define DAGB7_RDCLI4__MAX_OSD_MASK 0xFC000000L 30686 //DAGB7_RDCLI5 30687 #define DAGB7_RDCLI5__VIRT_CHAN__SHIFT 0x0 30688 #define DAGB7_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 30689 #define DAGB7_RDCLI5__URG_HIGH__SHIFT 0x4 30690 #define DAGB7_RDCLI5__URG_LOW__SHIFT 0x8 30691 #define DAGB7_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc 30692 #define DAGB7_RDCLI5__MAX_BW__SHIFT 0xd 30693 #define DAGB7_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 30694 #define DAGB7_RDCLI5__MIN_BW__SHIFT 0x16 30695 #define DAGB7_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 30696 #define DAGB7_RDCLI5__MAX_OSD__SHIFT 0x1a 30697 #define DAGB7_RDCLI5__VIRT_CHAN_MASK 0x00000007L 30698 #define DAGB7_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 30699 #define DAGB7_RDCLI5__URG_HIGH_MASK 0x000000F0L 30700 #define DAGB7_RDCLI5__URG_LOW_MASK 0x00000F00L 30701 #define DAGB7_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L 30702 #define DAGB7_RDCLI5__MAX_BW_MASK 0x001FE000L 30703 #define DAGB7_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L 30704 #define DAGB7_RDCLI5__MIN_BW_MASK 0x01C00000L 30705 #define DAGB7_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 30706 #define DAGB7_RDCLI5__MAX_OSD_MASK 0xFC000000L 30707 //DAGB7_RDCLI6 30708 #define DAGB7_RDCLI6__VIRT_CHAN__SHIFT 0x0 30709 #define DAGB7_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 30710 #define DAGB7_RDCLI6__URG_HIGH__SHIFT 0x4 30711 #define DAGB7_RDCLI6__URG_LOW__SHIFT 0x8 30712 #define DAGB7_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc 30713 #define DAGB7_RDCLI6__MAX_BW__SHIFT 0xd 30714 #define DAGB7_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 30715 #define DAGB7_RDCLI6__MIN_BW__SHIFT 0x16 30716 #define DAGB7_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 30717 #define DAGB7_RDCLI6__MAX_OSD__SHIFT 0x1a 30718 #define DAGB7_RDCLI6__VIRT_CHAN_MASK 0x00000007L 30719 #define DAGB7_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 30720 #define DAGB7_RDCLI6__URG_HIGH_MASK 0x000000F0L 30721 #define DAGB7_RDCLI6__URG_LOW_MASK 0x00000F00L 30722 #define DAGB7_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L 30723 #define DAGB7_RDCLI6__MAX_BW_MASK 0x001FE000L 30724 #define DAGB7_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L 30725 #define DAGB7_RDCLI6__MIN_BW_MASK 0x01C00000L 30726 #define DAGB7_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 30727 #define DAGB7_RDCLI6__MAX_OSD_MASK 0xFC000000L 30728 //DAGB7_RDCLI7 30729 #define DAGB7_RDCLI7__VIRT_CHAN__SHIFT 0x0 30730 #define DAGB7_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 30731 #define DAGB7_RDCLI7__URG_HIGH__SHIFT 0x4 30732 #define DAGB7_RDCLI7__URG_LOW__SHIFT 0x8 30733 #define DAGB7_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc 30734 #define DAGB7_RDCLI7__MAX_BW__SHIFT 0xd 30735 #define DAGB7_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 30736 #define DAGB7_RDCLI7__MIN_BW__SHIFT 0x16 30737 #define DAGB7_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 30738 #define DAGB7_RDCLI7__MAX_OSD__SHIFT 0x1a 30739 #define DAGB7_RDCLI7__VIRT_CHAN_MASK 0x00000007L 30740 #define DAGB7_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 30741 #define DAGB7_RDCLI7__URG_HIGH_MASK 0x000000F0L 30742 #define DAGB7_RDCLI7__URG_LOW_MASK 0x00000F00L 30743 #define DAGB7_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L 30744 #define DAGB7_RDCLI7__MAX_BW_MASK 0x001FE000L 30745 #define DAGB7_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L 30746 #define DAGB7_RDCLI7__MIN_BW_MASK 0x01C00000L 30747 #define DAGB7_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 30748 #define DAGB7_RDCLI7__MAX_OSD_MASK 0xFC000000L 30749 //DAGB7_RDCLI8 30750 #define DAGB7_RDCLI8__VIRT_CHAN__SHIFT 0x0 30751 #define DAGB7_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 30752 #define DAGB7_RDCLI8__URG_HIGH__SHIFT 0x4 30753 #define DAGB7_RDCLI8__URG_LOW__SHIFT 0x8 30754 #define DAGB7_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc 30755 #define DAGB7_RDCLI8__MAX_BW__SHIFT 0xd 30756 #define DAGB7_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 30757 #define DAGB7_RDCLI8__MIN_BW__SHIFT 0x16 30758 #define DAGB7_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 30759 #define DAGB7_RDCLI8__MAX_OSD__SHIFT 0x1a 30760 #define DAGB7_RDCLI8__VIRT_CHAN_MASK 0x00000007L 30761 #define DAGB7_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 30762 #define DAGB7_RDCLI8__URG_HIGH_MASK 0x000000F0L 30763 #define DAGB7_RDCLI8__URG_LOW_MASK 0x00000F00L 30764 #define DAGB7_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L 30765 #define DAGB7_RDCLI8__MAX_BW_MASK 0x001FE000L 30766 #define DAGB7_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L 30767 #define DAGB7_RDCLI8__MIN_BW_MASK 0x01C00000L 30768 #define DAGB7_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 30769 #define DAGB7_RDCLI8__MAX_OSD_MASK 0xFC000000L 30770 //DAGB7_RDCLI9 30771 #define DAGB7_RDCLI9__VIRT_CHAN__SHIFT 0x0 30772 #define DAGB7_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 30773 #define DAGB7_RDCLI9__URG_HIGH__SHIFT 0x4 30774 #define DAGB7_RDCLI9__URG_LOW__SHIFT 0x8 30775 #define DAGB7_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc 30776 #define DAGB7_RDCLI9__MAX_BW__SHIFT 0xd 30777 #define DAGB7_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 30778 #define DAGB7_RDCLI9__MIN_BW__SHIFT 0x16 30779 #define DAGB7_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 30780 #define DAGB7_RDCLI9__MAX_OSD__SHIFT 0x1a 30781 #define DAGB7_RDCLI9__VIRT_CHAN_MASK 0x00000007L 30782 #define DAGB7_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 30783 #define DAGB7_RDCLI9__URG_HIGH_MASK 0x000000F0L 30784 #define DAGB7_RDCLI9__URG_LOW_MASK 0x00000F00L 30785 #define DAGB7_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L 30786 #define DAGB7_RDCLI9__MAX_BW_MASK 0x001FE000L 30787 #define DAGB7_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L 30788 #define DAGB7_RDCLI9__MIN_BW_MASK 0x01C00000L 30789 #define DAGB7_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 30790 #define DAGB7_RDCLI9__MAX_OSD_MASK 0xFC000000L 30791 //DAGB7_RDCLI10 30792 #define DAGB7_RDCLI10__VIRT_CHAN__SHIFT 0x0 30793 #define DAGB7_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 30794 #define DAGB7_RDCLI10__URG_HIGH__SHIFT 0x4 30795 #define DAGB7_RDCLI10__URG_LOW__SHIFT 0x8 30796 #define DAGB7_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc 30797 #define DAGB7_RDCLI10__MAX_BW__SHIFT 0xd 30798 #define DAGB7_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 30799 #define DAGB7_RDCLI10__MIN_BW__SHIFT 0x16 30800 #define DAGB7_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 30801 #define DAGB7_RDCLI10__MAX_OSD__SHIFT 0x1a 30802 #define DAGB7_RDCLI10__VIRT_CHAN_MASK 0x00000007L 30803 #define DAGB7_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 30804 #define DAGB7_RDCLI10__URG_HIGH_MASK 0x000000F0L 30805 #define DAGB7_RDCLI10__URG_LOW_MASK 0x00000F00L 30806 #define DAGB7_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L 30807 #define DAGB7_RDCLI10__MAX_BW_MASK 0x001FE000L 30808 #define DAGB7_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L 30809 #define DAGB7_RDCLI10__MIN_BW_MASK 0x01C00000L 30810 #define DAGB7_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 30811 #define DAGB7_RDCLI10__MAX_OSD_MASK 0xFC000000L 30812 //DAGB7_RDCLI11 30813 #define DAGB7_RDCLI11__VIRT_CHAN__SHIFT 0x0 30814 #define DAGB7_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 30815 #define DAGB7_RDCLI11__URG_HIGH__SHIFT 0x4 30816 #define DAGB7_RDCLI11__URG_LOW__SHIFT 0x8 30817 #define DAGB7_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc 30818 #define DAGB7_RDCLI11__MAX_BW__SHIFT 0xd 30819 #define DAGB7_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 30820 #define DAGB7_RDCLI11__MIN_BW__SHIFT 0x16 30821 #define DAGB7_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 30822 #define DAGB7_RDCLI11__MAX_OSD__SHIFT 0x1a 30823 #define DAGB7_RDCLI11__VIRT_CHAN_MASK 0x00000007L 30824 #define DAGB7_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 30825 #define DAGB7_RDCLI11__URG_HIGH_MASK 0x000000F0L 30826 #define DAGB7_RDCLI11__URG_LOW_MASK 0x00000F00L 30827 #define DAGB7_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L 30828 #define DAGB7_RDCLI11__MAX_BW_MASK 0x001FE000L 30829 #define DAGB7_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L 30830 #define DAGB7_RDCLI11__MIN_BW_MASK 0x01C00000L 30831 #define DAGB7_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 30832 #define DAGB7_RDCLI11__MAX_OSD_MASK 0xFC000000L 30833 //DAGB7_RDCLI12 30834 #define DAGB7_RDCLI12__VIRT_CHAN__SHIFT 0x0 30835 #define DAGB7_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 30836 #define DAGB7_RDCLI12__URG_HIGH__SHIFT 0x4 30837 #define DAGB7_RDCLI12__URG_LOW__SHIFT 0x8 30838 #define DAGB7_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc 30839 #define DAGB7_RDCLI12__MAX_BW__SHIFT 0xd 30840 #define DAGB7_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 30841 #define DAGB7_RDCLI12__MIN_BW__SHIFT 0x16 30842 #define DAGB7_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 30843 #define DAGB7_RDCLI12__MAX_OSD__SHIFT 0x1a 30844 #define DAGB7_RDCLI12__VIRT_CHAN_MASK 0x00000007L 30845 #define DAGB7_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 30846 #define DAGB7_RDCLI12__URG_HIGH_MASK 0x000000F0L 30847 #define DAGB7_RDCLI12__URG_LOW_MASK 0x00000F00L 30848 #define DAGB7_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L 30849 #define DAGB7_RDCLI12__MAX_BW_MASK 0x001FE000L 30850 #define DAGB7_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L 30851 #define DAGB7_RDCLI12__MIN_BW_MASK 0x01C00000L 30852 #define DAGB7_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 30853 #define DAGB7_RDCLI12__MAX_OSD_MASK 0xFC000000L 30854 //DAGB7_RDCLI13 30855 #define DAGB7_RDCLI13__VIRT_CHAN__SHIFT 0x0 30856 #define DAGB7_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 30857 #define DAGB7_RDCLI13__URG_HIGH__SHIFT 0x4 30858 #define DAGB7_RDCLI13__URG_LOW__SHIFT 0x8 30859 #define DAGB7_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc 30860 #define DAGB7_RDCLI13__MAX_BW__SHIFT 0xd 30861 #define DAGB7_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 30862 #define DAGB7_RDCLI13__MIN_BW__SHIFT 0x16 30863 #define DAGB7_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 30864 #define DAGB7_RDCLI13__MAX_OSD__SHIFT 0x1a 30865 #define DAGB7_RDCLI13__VIRT_CHAN_MASK 0x00000007L 30866 #define DAGB7_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 30867 #define DAGB7_RDCLI13__URG_HIGH_MASK 0x000000F0L 30868 #define DAGB7_RDCLI13__URG_LOW_MASK 0x00000F00L 30869 #define DAGB7_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L 30870 #define DAGB7_RDCLI13__MAX_BW_MASK 0x001FE000L 30871 #define DAGB7_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L 30872 #define DAGB7_RDCLI13__MIN_BW_MASK 0x01C00000L 30873 #define DAGB7_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 30874 #define DAGB7_RDCLI13__MAX_OSD_MASK 0xFC000000L 30875 //DAGB7_RDCLI14 30876 #define DAGB7_RDCLI14__VIRT_CHAN__SHIFT 0x0 30877 #define DAGB7_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 30878 #define DAGB7_RDCLI14__URG_HIGH__SHIFT 0x4 30879 #define DAGB7_RDCLI14__URG_LOW__SHIFT 0x8 30880 #define DAGB7_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc 30881 #define DAGB7_RDCLI14__MAX_BW__SHIFT 0xd 30882 #define DAGB7_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 30883 #define DAGB7_RDCLI14__MIN_BW__SHIFT 0x16 30884 #define DAGB7_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 30885 #define DAGB7_RDCLI14__MAX_OSD__SHIFT 0x1a 30886 #define DAGB7_RDCLI14__VIRT_CHAN_MASK 0x00000007L 30887 #define DAGB7_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 30888 #define DAGB7_RDCLI14__URG_HIGH_MASK 0x000000F0L 30889 #define DAGB7_RDCLI14__URG_LOW_MASK 0x00000F00L 30890 #define DAGB7_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L 30891 #define DAGB7_RDCLI14__MAX_BW_MASK 0x001FE000L 30892 #define DAGB7_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L 30893 #define DAGB7_RDCLI14__MIN_BW_MASK 0x01C00000L 30894 #define DAGB7_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 30895 #define DAGB7_RDCLI14__MAX_OSD_MASK 0xFC000000L 30896 //DAGB7_RDCLI15 30897 #define DAGB7_RDCLI15__VIRT_CHAN__SHIFT 0x0 30898 #define DAGB7_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 30899 #define DAGB7_RDCLI15__URG_HIGH__SHIFT 0x4 30900 #define DAGB7_RDCLI15__URG_LOW__SHIFT 0x8 30901 #define DAGB7_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc 30902 #define DAGB7_RDCLI15__MAX_BW__SHIFT 0xd 30903 #define DAGB7_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 30904 #define DAGB7_RDCLI15__MIN_BW__SHIFT 0x16 30905 #define DAGB7_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 30906 #define DAGB7_RDCLI15__MAX_OSD__SHIFT 0x1a 30907 #define DAGB7_RDCLI15__VIRT_CHAN_MASK 0x00000007L 30908 #define DAGB7_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 30909 #define DAGB7_RDCLI15__URG_HIGH_MASK 0x000000F0L 30910 #define DAGB7_RDCLI15__URG_LOW_MASK 0x00000F00L 30911 #define DAGB7_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L 30912 #define DAGB7_RDCLI15__MAX_BW_MASK 0x001FE000L 30913 #define DAGB7_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L 30914 #define DAGB7_RDCLI15__MIN_BW_MASK 0x01C00000L 30915 #define DAGB7_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 30916 #define DAGB7_RDCLI15__MAX_OSD_MASK 0xFC000000L 30917 //DAGB7_RD_CNTL 30918 #define DAGB7_RD_CNTL__SCLK_FREQ__SHIFT 0x0 30919 #define DAGB7_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 30920 #define DAGB7_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 30921 #define DAGB7_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 30922 #define DAGB7_RD_CNTL__IO_LEVEL__SHIFT 0x11 30923 #define DAGB7_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 30924 #define DAGB7_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 30925 #define DAGB7_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL 30926 #define DAGB7_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 30927 #define DAGB7_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 30928 #define DAGB7_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 30929 #define DAGB7_RD_CNTL__IO_LEVEL_MASK 0x000E0000L 30930 #define DAGB7_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 30931 #define DAGB7_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L 30932 //DAGB7_RD_GMI_CNTL 30933 #define DAGB7_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 30934 #define DAGB7_RD_GMI_CNTL__LEVEL__SHIFT 0x6 30935 #define DAGB7_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 30936 #define DAGB7_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 30937 #define DAGB7_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 30938 #define DAGB7_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L 30939 #define DAGB7_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 30940 #define DAGB7_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 30941 //DAGB7_RD_ADDR_DAGB 30942 #define DAGB7_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 30943 #define DAGB7_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 30944 #define DAGB7_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 30945 #define DAGB7_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 30946 #define DAGB7_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 30947 #define DAGB7_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 30948 #define DAGB7_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 30949 #define DAGB7_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 30950 //DAGB7_RD_OUTPUT_DAGB_MAX_BURST 30951 #define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 30952 #define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 30953 #define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 30954 #define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 30955 #define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 30956 #define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 30957 #define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 30958 #define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 30959 #define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 30960 #define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 30961 #define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 30962 #define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 30963 #define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 30964 #define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 30965 #define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 30966 #define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 30967 //DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER 30968 #define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 30969 #define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 30970 #define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 30971 #define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 30972 #define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 30973 #define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 30974 #define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 30975 #define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 30976 #define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 30977 #define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 30978 #define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 30979 #define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 30980 #define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 30981 #define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 30982 #define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 30983 #define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 30984 //DAGB7_RD_CGTT_CLK_CTRL 30985 #define DAGB7_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 30986 #define DAGB7_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 30987 #define DAGB7_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 30988 #define DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 30989 #define DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 30990 #define DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 30991 #define DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 30992 #define DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 30993 #define DAGB7_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 30994 #define DAGB7_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 30995 #define DAGB7_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 30996 #define DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 30997 #define DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 30998 #define DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 30999 #define DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 31000 #define DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 31001 //DAGB7_L1TLB_RD_CGTT_CLK_CTRL 31002 #define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 31003 #define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 31004 #define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 31005 #define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 31006 #define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 31007 #define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 31008 #define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 31009 #define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 31010 #define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 31011 #define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 31012 #define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 31013 #define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 31014 #define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 31015 #define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 31016 #define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 31017 #define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 31018 //DAGB7_ATCVM_RD_CGTT_CLK_CTRL 31019 #define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 31020 #define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 31021 #define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 31022 #define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 31023 #define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 31024 #define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 31025 #define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 31026 #define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 31027 #define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 31028 #define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 31029 #define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 31030 #define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 31031 #define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 31032 #define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 31033 #define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 31034 #define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 31035 //DAGB7_RD_ADDR_DAGB_MAX_BURST0 31036 #define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 31037 #define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 31038 #define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 31039 #define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 31040 #define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 31041 #define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 31042 #define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 31043 #define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 31044 #define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 31045 #define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 31046 #define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 31047 #define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 31048 #define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 31049 #define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 31050 #define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 31051 #define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 31052 //DAGB7_RD_ADDR_DAGB_LAZY_TIMER0 31053 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 31054 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 31055 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 31056 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 31057 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 31058 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 31059 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 31060 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 31061 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 31062 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 31063 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 31064 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 31065 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 31066 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 31067 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 31068 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 31069 //DAGB7_RD_ADDR_DAGB_MAX_BURST1 31070 #define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 31071 #define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 31072 #define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 31073 #define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 31074 #define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 31075 #define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 31076 #define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 31077 #define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 31078 #define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 31079 #define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 31080 #define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 31081 #define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 31082 #define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 31083 #define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 31084 #define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 31085 #define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 31086 //DAGB7_RD_ADDR_DAGB_LAZY_TIMER1 31087 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 31088 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 31089 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 31090 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 31091 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 31092 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 31093 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 31094 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 31095 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 31096 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 31097 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 31098 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 31099 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 31100 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 31101 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 31102 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 31103 //DAGB7_RD_VC0_CNTL 31104 #define DAGB7_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 31105 #define DAGB7_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 31106 #define DAGB7_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 31107 #define DAGB7_RD_VC0_CNTL__MAX_BW__SHIFT 0xc 31108 #define DAGB7_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 31109 #define DAGB7_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 31110 #define DAGB7_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 31111 #define DAGB7_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 31112 #define DAGB7_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 31113 #define DAGB7_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 31114 #define DAGB7_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 31115 #define DAGB7_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L 31116 #define DAGB7_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 31117 #define DAGB7_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L 31118 #define DAGB7_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 31119 #define DAGB7_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 31120 //DAGB7_RD_VC1_CNTL 31121 #define DAGB7_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 31122 #define DAGB7_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 31123 #define DAGB7_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 31124 #define DAGB7_RD_VC1_CNTL__MAX_BW__SHIFT 0xc 31125 #define DAGB7_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 31126 #define DAGB7_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 31127 #define DAGB7_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 31128 #define DAGB7_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 31129 #define DAGB7_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 31130 #define DAGB7_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 31131 #define DAGB7_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 31132 #define DAGB7_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L 31133 #define DAGB7_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 31134 #define DAGB7_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L 31135 #define DAGB7_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 31136 #define DAGB7_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 31137 //DAGB7_RD_VC2_CNTL 31138 #define DAGB7_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 31139 #define DAGB7_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 31140 #define DAGB7_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 31141 #define DAGB7_RD_VC2_CNTL__MAX_BW__SHIFT 0xc 31142 #define DAGB7_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 31143 #define DAGB7_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 31144 #define DAGB7_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 31145 #define DAGB7_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 31146 #define DAGB7_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 31147 #define DAGB7_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 31148 #define DAGB7_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 31149 #define DAGB7_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L 31150 #define DAGB7_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 31151 #define DAGB7_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L 31152 #define DAGB7_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 31153 #define DAGB7_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 31154 //DAGB7_RD_VC3_CNTL 31155 #define DAGB7_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 31156 #define DAGB7_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 31157 #define DAGB7_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 31158 #define DAGB7_RD_VC3_CNTL__MAX_BW__SHIFT 0xc 31159 #define DAGB7_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 31160 #define DAGB7_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 31161 #define DAGB7_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 31162 #define DAGB7_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 31163 #define DAGB7_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 31164 #define DAGB7_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 31165 #define DAGB7_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 31166 #define DAGB7_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L 31167 #define DAGB7_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 31168 #define DAGB7_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L 31169 #define DAGB7_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 31170 #define DAGB7_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 31171 //DAGB7_RD_VC4_CNTL 31172 #define DAGB7_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 31173 #define DAGB7_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 31174 #define DAGB7_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 31175 #define DAGB7_RD_VC4_CNTL__MAX_BW__SHIFT 0xc 31176 #define DAGB7_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 31177 #define DAGB7_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 31178 #define DAGB7_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 31179 #define DAGB7_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 31180 #define DAGB7_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 31181 #define DAGB7_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 31182 #define DAGB7_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 31183 #define DAGB7_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L 31184 #define DAGB7_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 31185 #define DAGB7_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L 31186 #define DAGB7_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 31187 #define DAGB7_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 31188 //DAGB7_RD_VC5_CNTL 31189 #define DAGB7_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 31190 #define DAGB7_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 31191 #define DAGB7_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 31192 #define DAGB7_RD_VC5_CNTL__MAX_BW__SHIFT 0xc 31193 #define DAGB7_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 31194 #define DAGB7_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 31195 #define DAGB7_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 31196 #define DAGB7_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 31197 #define DAGB7_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 31198 #define DAGB7_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 31199 #define DAGB7_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 31200 #define DAGB7_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L 31201 #define DAGB7_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 31202 #define DAGB7_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L 31203 #define DAGB7_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 31204 #define DAGB7_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 31205 //DAGB7_RD_VC6_CNTL 31206 #define DAGB7_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 31207 #define DAGB7_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 31208 #define DAGB7_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 31209 #define DAGB7_RD_VC6_CNTL__MAX_BW__SHIFT 0xc 31210 #define DAGB7_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 31211 #define DAGB7_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 31212 #define DAGB7_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 31213 #define DAGB7_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 31214 #define DAGB7_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 31215 #define DAGB7_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 31216 #define DAGB7_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 31217 #define DAGB7_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L 31218 #define DAGB7_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 31219 #define DAGB7_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L 31220 #define DAGB7_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 31221 #define DAGB7_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 31222 //DAGB7_RD_VC7_CNTL 31223 #define DAGB7_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 31224 #define DAGB7_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 31225 #define DAGB7_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 31226 #define DAGB7_RD_VC7_CNTL__MAX_BW__SHIFT 0xc 31227 #define DAGB7_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 31228 #define DAGB7_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 31229 #define DAGB7_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 31230 #define DAGB7_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 31231 #define DAGB7_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 31232 #define DAGB7_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 31233 #define DAGB7_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 31234 #define DAGB7_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L 31235 #define DAGB7_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 31236 #define DAGB7_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L 31237 #define DAGB7_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 31238 #define DAGB7_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 31239 //DAGB7_RD_CNTL_MISC 31240 #define DAGB7_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 31241 #define DAGB7_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 31242 #define DAGB7_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 31243 #define DAGB7_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 31244 #define DAGB7_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 31245 #define DAGB7_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 31246 #define DAGB7_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a 31247 #define DAGB7_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 31248 #define DAGB7_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 31249 #define DAGB7_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 31250 #define DAGB7_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 31251 #define DAGB7_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 31252 #define DAGB7_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 31253 #define DAGB7_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L 31254 //DAGB7_RD_TLB_CREDIT 31255 #define DAGB7_RD_TLB_CREDIT__TLB0__SHIFT 0x0 31256 #define DAGB7_RD_TLB_CREDIT__TLB1__SHIFT 0x5 31257 #define DAGB7_RD_TLB_CREDIT__TLB2__SHIFT 0xa 31258 #define DAGB7_RD_TLB_CREDIT__TLB3__SHIFT 0xf 31259 #define DAGB7_RD_TLB_CREDIT__TLB4__SHIFT 0x14 31260 #define DAGB7_RD_TLB_CREDIT__TLB5__SHIFT 0x19 31261 #define DAGB7_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL 31262 #define DAGB7_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L 31263 #define DAGB7_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L 31264 #define DAGB7_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L 31265 #define DAGB7_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L 31266 #define DAGB7_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L 31267 //DAGB7_RDCLI_ASK_PENDING 31268 #define DAGB7_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 31269 #define DAGB7_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 31270 //DAGB7_RDCLI_GO_PENDING 31271 #define DAGB7_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 31272 #define DAGB7_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 31273 //DAGB7_RDCLI_GBLSEND_PENDING 31274 #define DAGB7_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 31275 #define DAGB7_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 31276 //DAGB7_RDCLI_TLB_PENDING 31277 #define DAGB7_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 31278 #define DAGB7_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 31279 //DAGB7_RDCLI_OARB_PENDING 31280 #define DAGB7_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 31281 #define DAGB7_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 31282 //DAGB7_RDCLI_OSD_PENDING 31283 #define DAGB7_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 31284 #define DAGB7_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 31285 //DAGB7_WRCLI0 31286 #define DAGB7_WRCLI0__VIRT_CHAN__SHIFT 0x0 31287 #define DAGB7_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 31288 #define DAGB7_WRCLI0__URG_HIGH__SHIFT 0x4 31289 #define DAGB7_WRCLI0__URG_LOW__SHIFT 0x8 31290 #define DAGB7_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc 31291 #define DAGB7_WRCLI0__MAX_BW__SHIFT 0xd 31292 #define DAGB7_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 31293 #define DAGB7_WRCLI0__MIN_BW__SHIFT 0x16 31294 #define DAGB7_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 31295 #define DAGB7_WRCLI0__MAX_OSD__SHIFT 0x1a 31296 #define DAGB7_WRCLI0__VIRT_CHAN_MASK 0x00000007L 31297 #define DAGB7_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 31298 #define DAGB7_WRCLI0__URG_HIGH_MASK 0x000000F0L 31299 #define DAGB7_WRCLI0__URG_LOW_MASK 0x00000F00L 31300 #define DAGB7_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L 31301 #define DAGB7_WRCLI0__MAX_BW_MASK 0x001FE000L 31302 #define DAGB7_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L 31303 #define DAGB7_WRCLI0__MIN_BW_MASK 0x01C00000L 31304 #define DAGB7_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 31305 #define DAGB7_WRCLI0__MAX_OSD_MASK 0xFC000000L 31306 //DAGB7_WRCLI1 31307 #define DAGB7_WRCLI1__VIRT_CHAN__SHIFT 0x0 31308 #define DAGB7_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 31309 #define DAGB7_WRCLI1__URG_HIGH__SHIFT 0x4 31310 #define DAGB7_WRCLI1__URG_LOW__SHIFT 0x8 31311 #define DAGB7_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc 31312 #define DAGB7_WRCLI1__MAX_BW__SHIFT 0xd 31313 #define DAGB7_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 31314 #define DAGB7_WRCLI1__MIN_BW__SHIFT 0x16 31315 #define DAGB7_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 31316 #define DAGB7_WRCLI1__MAX_OSD__SHIFT 0x1a 31317 #define DAGB7_WRCLI1__VIRT_CHAN_MASK 0x00000007L 31318 #define DAGB7_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 31319 #define DAGB7_WRCLI1__URG_HIGH_MASK 0x000000F0L 31320 #define DAGB7_WRCLI1__URG_LOW_MASK 0x00000F00L 31321 #define DAGB7_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L 31322 #define DAGB7_WRCLI1__MAX_BW_MASK 0x001FE000L 31323 #define DAGB7_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L 31324 #define DAGB7_WRCLI1__MIN_BW_MASK 0x01C00000L 31325 #define DAGB7_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 31326 #define DAGB7_WRCLI1__MAX_OSD_MASK 0xFC000000L 31327 //DAGB7_WRCLI2 31328 #define DAGB7_WRCLI2__VIRT_CHAN__SHIFT 0x0 31329 #define DAGB7_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 31330 #define DAGB7_WRCLI2__URG_HIGH__SHIFT 0x4 31331 #define DAGB7_WRCLI2__URG_LOW__SHIFT 0x8 31332 #define DAGB7_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc 31333 #define DAGB7_WRCLI2__MAX_BW__SHIFT 0xd 31334 #define DAGB7_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 31335 #define DAGB7_WRCLI2__MIN_BW__SHIFT 0x16 31336 #define DAGB7_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 31337 #define DAGB7_WRCLI2__MAX_OSD__SHIFT 0x1a 31338 #define DAGB7_WRCLI2__VIRT_CHAN_MASK 0x00000007L 31339 #define DAGB7_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 31340 #define DAGB7_WRCLI2__URG_HIGH_MASK 0x000000F0L 31341 #define DAGB7_WRCLI2__URG_LOW_MASK 0x00000F00L 31342 #define DAGB7_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L 31343 #define DAGB7_WRCLI2__MAX_BW_MASK 0x001FE000L 31344 #define DAGB7_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L 31345 #define DAGB7_WRCLI2__MIN_BW_MASK 0x01C00000L 31346 #define DAGB7_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 31347 #define DAGB7_WRCLI2__MAX_OSD_MASK 0xFC000000L 31348 //DAGB7_WRCLI3 31349 #define DAGB7_WRCLI3__VIRT_CHAN__SHIFT 0x0 31350 #define DAGB7_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 31351 #define DAGB7_WRCLI3__URG_HIGH__SHIFT 0x4 31352 #define DAGB7_WRCLI3__URG_LOW__SHIFT 0x8 31353 #define DAGB7_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc 31354 #define DAGB7_WRCLI3__MAX_BW__SHIFT 0xd 31355 #define DAGB7_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 31356 #define DAGB7_WRCLI3__MIN_BW__SHIFT 0x16 31357 #define DAGB7_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 31358 #define DAGB7_WRCLI3__MAX_OSD__SHIFT 0x1a 31359 #define DAGB7_WRCLI3__VIRT_CHAN_MASK 0x00000007L 31360 #define DAGB7_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 31361 #define DAGB7_WRCLI3__URG_HIGH_MASK 0x000000F0L 31362 #define DAGB7_WRCLI3__URG_LOW_MASK 0x00000F00L 31363 #define DAGB7_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L 31364 #define DAGB7_WRCLI3__MAX_BW_MASK 0x001FE000L 31365 #define DAGB7_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L 31366 #define DAGB7_WRCLI3__MIN_BW_MASK 0x01C00000L 31367 #define DAGB7_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 31368 #define DAGB7_WRCLI3__MAX_OSD_MASK 0xFC000000L 31369 //DAGB7_WRCLI4 31370 #define DAGB7_WRCLI4__VIRT_CHAN__SHIFT 0x0 31371 #define DAGB7_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 31372 #define DAGB7_WRCLI4__URG_HIGH__SHIFT 0x4 31373 #define DAGB7_WRCLI4__URG_LOW__SHIFT 0x8 31374 #define DAGB7_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc 31375 #define DAGB7_WRCLI4__MAX_BW__SHIFT 0xd 31376 #define DAGB7_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 31377 #define DAGB7_WRCLI4__MIN_BW__SHIFT 0x16 31378 #define DAGB7_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 31379 #define DAGB7_WRCLI4__MAX_OSD__SHIFT 0x1a 31380 #define DAGB7_WRCLI4__VIRT_CHAN_MASK 0x00000007L 31381 #define DAGB7_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 31382 #define DAGB7_WRCLI4__URG_HIGH_MASK 0x000000F0L 31383 #define DAGB7_WRCLI4__URG_LOW_MASK 0x00000F00L 31384 #define DAGB7_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L 31385 #define DAGB7_WRCLI4__MAX_BW_MASK 0x001FE000L 31386 #define DAGB7_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L 31387 #define DAGB7_WRCLI4__MIN_BW_MASK 0x01C00000L 31388 #define DAGB7_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 31389 #define DAGB7_WRCLI4__MAX_OSD_MASK 0xFC000000L 31390 //DAGB7_WRCLI5 31391 #define DAGB7_WRCLI5__VIRT_CHAN__SHIFT 0x0 31392 #define DAGB7_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 31393 #define DAGB7_WRCLI5__URG_HIGH__SHIFT 0x4 31394 #define DAGB7_WRCLI5__URG_LOW__SHIFT 0x8 31395 #define DAGB7_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc 31396 #define DAGB7_WRCLI5__MAX_BW__SHIFT 0xd 31397 #define DAGB7_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 31398 #define DAGB7_WRCLI5__MIN_BW__SHIFT 0x16 31399 #define DAGB7_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 31400 #define DAGB7_WRCLI5__MAX_OSD__SHIFT 0x1a 31401 #define DAGB7_WRCLI5__VIRT_CHAN_MASK 0x00000007L 31402 #define DAGB7_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 31403 #define DAGB7_WRCLI5__URG_HIGH_MASK 0x000000F0L 31404 #define DAGB7_WRCLI5__URG_LOW_MASK 0x00000F00L 31405 #define DAGB7_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L 31406 #define DAGB7_WRCLI5__MAX_BW_MASK 0x001FE000L 31407 #define DAGB7_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L 31408 #define DAGB7_WRCLI5__MIN_BW_MASK 0x01C00000L 31409 #define DAGB7_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 31410 #define DAGB7_WRCLI5__MAX_OSD_MASK 0xFC000000L 31411 //DAGB7_WRCLI6 31412 #define DAGB7_WRCLI6__VIRT_CHAN__SHIFT 0x0 31413 #define DAGB7_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 31414 #define DAGB7_WRCLI6__URG_HIGH__SHIFT 0x4 31415 #define DAGB7_WRCLI6__URG_LOW__SHIFT 0x8 31416 #define DAGB7_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc 31417 #define DAGB7_WRCLI6__MAX_BW__SHIFT 0xd 31418 #define DAGB7_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 31419 #define DAGB7_WRCLI6__MIN_BW__SHIFT 0x16 31420 #define DAGB7_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 31421 #define DAGB7_WRCLI6__MAX_OSD__SHIFT 0x1a 31422 #define DAGB7_WRCLI6__VIRT_CHAN_MASK 0x00000007L 31423 #define DAGB7_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 31424 #define DAGB7_WRCLI6__URG_HIGH_MASK 0x000000F0L 31425 #define DAGB7_WRCLI6__URG_LOW_MASK 0x00000F00L 31426 #define DAGB7_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L 31427 #define DAGB7_WRCLI6__MAX_BW_MASK 0x001FE000L 31428 #define DAGB7_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L 31429 #define DAGB7_WRCLI6__MIN_BW_MASK 0x01C00000L 31430 #define DAGB7_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 31431 #define DAGB7_WRCLI6__MAX_OSD_MASK 0xFC000000L 31432 //DAGB7_WRCLI7 31433 #define DAGB7_WRCLI7__VIRT_CHAN__SHIFT 0x0 31434 #define DAGB7_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 31435 #define DAGB7_WRCLI7__URG_HIGH__SHIFT 0x4 31436 #define DAGB7_WRCLI7__URG_LOW__SHIFT 0x8 31437 #define DAGB7_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc 31438 #define DAGB7_WRCLI7__MAX_BW__SHIFT 0xd 31439 #define DAGB7_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 31440 #define DAGB7_WRCLI7__MIN_BW__SHIFT 0x16 31441 #define DAGB7_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 31442 #define DAGB7_WRCLI7__MAX_OSD__SHIFT 0x1a 31443 #define DAGB7_WRCLI7__VIRT_CHAN_MASK 0x00000007L 31444 #define DAGB7_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 31445 #define DAGB7_WRCLI7__URG_HIGH_MASK 0x000000F0L 31446 #define DAGB7_WRCLI7__URG_LOW_MASK 0x00000F00L 31447 #define DAGB7_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L 31448 #define DAGB7_WRCLI7__MAX_BW_MASK 0x001FE000L 31449 #define DAGB7_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L 31450 #define DAGB7_WRCLI7__MIN_BW_MASK 0x01C00000L 31451 #define DAGB7_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 31452 #define DAGB7_WRCLI7__MAX_OSD_MASK 0xFC000000L 31453 //DAGB7_WRCLI8 31454 #define DAGB7_WRCLI8__VIRT_CHAN__SHIFT 0x0 31455 #define DAGB7_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 31456 #define DAGB7_WRCLI8__URG_HIGH__SHIFT 0x4 31457 #define DAGB7_WRCLI8__URG_LOW__SHIFT 0x8 31458 #define DAGB7_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc 31459 #define DAGB7_WRCLI8__MAX_BW__SHIFT 0xd 31460 #define DAGB7_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 31461 #define DAGB7_WRCLI8__MIN_BW__SHIFT 0x16 31462 #define DAGB7_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 31463 #define DAGB7_WRCLI8__MAX_OSD__SHIFT 0x1a 31464 #define DAGB7_WRCLI8__VIRT_CHAN_MASK 0x00000007L 31465 #define DAGB7_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 31466 #define DAGB7_WRCLI8__URG_HIGH_MASK 0x000000F0L 31467 #define DAGB7_WRCLI8__URG_LOW_MASK 0x00000F00L 31468 #define DAGB7_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L 31469 #define DAGB7_WRCLI8__MAX_BW_MASK 0x001FE000L 31470 #define DAGB7_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L 31471 #define DAGB7_WRCLI8__MIN_BW_MASK 0x01C00000L 31472 #define DAGB7_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 31473 #define DAGB7_WRCLI8__MAX_OSD_MASK 0xFC000000L 31474 //DAGB7_WRCLI9 31475 #define DAGB7_WRCLI9__VIRT_CHAN__SHIFT 0x0 31476 #define DAGB7_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 31477 #define DAGB7_WRCLI9__URG_HIGH__SHIFT 0x4 31478 #define DAGB7_WRCLI9__URG_LOW__SHIFT 0x8 31479 #define DAGB7_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc 31480 #define DAGB7_WRCLI9__MAX_BW__SHIFT 0xd 31481 #define DAGB7_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 31482 #define DAGB7_WRCLI9__MIN_BW__SHIFT 0x16 31483 #define DAGB7_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 31484 #define DAGB7_WRCLI9__MAX_OSD__SHIFT 0x1a 31485 #define DAGB7_WRCLI9__VIRT_CHAN_MASK 0x00000007L 31486 #define DAGB7_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 31487 #define DAGB7_WRCLI9__URG_HIGH_MASK 0x000000F0L 31488 #define DAGB7_WRCLI9__URG_LOW_MASK 0x00000F00L 31489 #define DAGB7_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L 31490 #define DAGB7_WRCLI9__MAX_BW_MASK 0x001FE000L 31491 #define DAGB7_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L 31492 #define DAGB7_WRCLI9__MIN_BW_MASK 0x01C00000L 31493 #define DAGB7_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 31494 #define DAGB7_WRCLI9__MAX_OSD_MASK 0xFC000000L 31495 //DAGB7_WRCLI10 31496 #define DAGB7_WRCLI10__VIRT_CHAN__SHIFT 0x0 31497 #define DAGB7_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 31498 #define DAGB7_WRCLI10__URG_HIGH__SHIFT 0x4 31499 #define DAGB7_WRCLI10__URG_LOW__SHIFT 0x8 31500 #define DAGB7_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc 31501 #define DAGB7_WRCLI10__MAX_BW__SHIFT 0xd 31502 #define DAGB7_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 31503 #define DAGB7_WRCLI10__MIN_BW__SHIFT 0x16 31504 #define DAGB7_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 31505 #define DAGB7_WRCLI10__MAX_OSD__SHIFT 0x1a 31506 #define DAGB7_WRCLI10__VIRT_CHAN_MASK 0x00000007L 31507 #define DAGB7_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 31508 #define DAGB7_WRCLI10__URG_HIGH_MASK 0x000000F0L 31509 #define DAGB7_WRCLI10__URG_LOW_MASK 0x00000F00L 31510 #define DAGB7_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L 31511 #define DAGB7_WRCLI10__MAX_BW_MASK 0x001FE000L 31512 #define DAGB7_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L 31513 #define DAGB7_WRCLI10__MIN_BW_MASK 0x01C00000L 31514 #define DAGB7_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 31515 #define DAGB7_WRCLI10__MAX_OSD_MASK 0xFC000000L 31516 //DAGB7_WRCLI11 31517 #define DAGB7_WRCLI11__VIRT_CHAN__SHIFT 0x0 31518 #define DAGB7_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 31519 #define DAGB7_WRCLI11__URG_HIGH__SHIFT 0x4 31520 #define DAGB7_WRCLI11__URG_LOW__SHIFT 0x8 31521 #define DAGB7_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc 31522 #define DAGB7_WRCLI11__MAX_BW__SHIFT 0xd 31523 #define DAGB7_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 31524 #define DAGB7_WRCLI11__MIN_BW__SHIFT 0x16 31525 #define DAGB7_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 31526 #define DAGB7_WRCLI11__MAX_OSD__SHIFT 0x1a 31527 #define DAGB7_WRCLI11__VIRT_CHAN_MASK 0x00000007L 31528 #define DAGB7_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 31529 #define DAGB7_WRCLI11__URG_HIGH_MASK 0x000000F0L 31530 #define DAGB7_WRCLI11__URG_LOW_MASK 0x00000F00L 31531 #define DAGB7_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L 31532 #define DAGB7_WRCLI11__MAX_BW_MASK 0x001FE000L 31533 #define DAGB7_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L 31534 #define DAGB7_WRCLI11__MIN_BW_MASK 0x01C00000L 31535 #define DAGB7_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 31536 #define DAGB7_WRCLI11__MAX_OSD_MASK 0xFC000000L 31537 //DAGB7_WRCLI12 31538 #define DAGB7_WRCLI12__VIRT_CHAN__SHIFT 0x0 31539 #define DAGB7_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 31540 #define DAGB7_WRCLI12__URG_HIGH__SHIFT 0x4 31541 #define DAGB7_WRCLI12__URG_LOW__SHIFT 0x8 31542 #define DAGB7_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc 31543 #define DAGB7_WRCLI12__MAX_BW__SHIFT 0xd 31544 #define DAGB7_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 31545 #define DAGB7_WRCLI12__MIN_BW__SHIFT 0x16 31546 #define DAGB7_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 31547 #define DAGB7_WRCLI12__MAX_OSD__SHIFT 0x1a 31548 #define DAGB7_WRCLI12__VIRT_CHAN_MASK 0x00000007L 31549 #define DAGB7_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 31550 #define DAGB7_WRCLI12__URG_HIGH_MASK 0x000000F0L 31551 #define DAGB7_WRCLI12__URG_LOW_MASK 0x00000F00L 31552 #define DAGB7_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L 31553 #define DAGB7_WRCLI12__MAX_BW_MASK 0x001FE000L 31554 #define DAGB7_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L 31555 #define DAGB7_WRCLI12__MIN_BW_MASK 0x01C00000L 31556 #define DAGB7_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 31557 #define DAGB7_WRCLI12__MAX_OSD_MASK 0xFC000000L 31558 //DAGB7_WRCLI13 31559 #define DAGB7_WRCLI13__VIRT_CHAN__SHIFT 0x0 31560 #define DAGB7_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 31561 #define DAGB7_WRCLI13__URG_HIGH__SHIFT 0x4 31562 #define DAGB7_WRCLI13__URG_LOW__SHIFT 0x8 31563 #define DAGB7_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc 31564 #define DAGB7_WRCLI13__MAX_BW__SHIFT 0xd 31565 #define DAGB7_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 31566 #define DAGB7_WRCLI13__MIN_BW__SHIFT 0x16 31567 #define DAGB7_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 31568 #define DAGB7_WRCLI13__MAX_OSD__SHIFT 0x1a 31569 #define DAGB7_WRCLI13__VIRT_CHAN_MASK 0x00000007L 31570 #define DAGB7_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 31571 #define DAGB7_WRCLI13__URG_HIGH_MASK 0x000000F0L 31572 #define DAGB7_WRCLI13__URG_LOW_MASK 0x00000F00L 31573 #define DAGB7_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L 31574 #define DAGB7_WRCLI13__MAX_BW_MASK 0x001FE000L 31575 #define DAGB7_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L 31576 #define DAGB7_WRCLI13__MIN_BW_MASK 0x01C00000L 31577 #define DAGB7_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 31578 #define DAGB7_WRCLI13__MAX_OSD_MASK 0xFC000000L 31579 //DAGB7_WRCLI14 31580 #define DAGB7_WRCLI14__VIRT_CHAN__SHIFT 0x0 31581 #define DAGB7_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 31582 #define DAGB7_WRCLI14__URG_HIGH__SHIFT 0x4 31583 #define DAGB7_WRCLI14__URG_LOW__SHIFT 0x8 31584 #define DAGB7_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc 31585 #define DAGB7_WRCLI14__MAX_BW__SHIFT 0xd 31586 #define DAGB7_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 31587 #define DAGB7_WRCLI14__MIN_BW__SHIFT 0x16 31588 #define DAGB7_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 31589 #define DAGB7_WRCLI14__MAX_OSD__SHIFT 0x1a 31590 #define DAGB7_WRCLI14__VIRT_CHAN_MASK 0x00000007L 31591 #define DAGB7_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 31592 #define DAGB7_WRCLI14__URG_HIGH_MASK 0x000000F0L 31593 #define DAGB7_WRCLI14__URG_LOW_MASK 0x00000F00L 31594 #define DAGB7_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L 31595 #define DAGB7_WRCLI14__MAX_BW_MASK 0x001FE000L 31596 #define DAGB7_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L 31597 #define DAGB7_WRCLI14__MIN_BW_MASK 0x01C00000L 31598 #define DAGB7_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 31599 #define DAGB7_WRCLI14__MAX_OSD_MASK 0xFC000000L 31600 //DAGB7_WRCLI15 31601 #define DAGB7_WRCLI15__VIRT_CHAN__SHIFT 0x0 31602 #define DAGB7_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 31603 #define DAGB7_WRCLI15__URG_HIGH__SHIFT 0x4 31604 #define DAGB7_WRCLI15__URG_LOW__SHIFT 0x8 31605 #define DAGB7_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc 31606 #define DAGB7_WRCLI15__MAX_BW__SHIFT 0xd 31607 #define DAGB7_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 31608 #define DAGB7_WRCLI15__MIN_BW__SHIFT 0x16 31609 #define DAGB7_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 31610 #define DAGB7_WRCLI15__MAX_OSD__SHIFT 0x1a 31611 #define DAGB7_WRCLI15__VIRT_CHAN_MASK 0x00000007L 31612 #define DAGB7_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 31613 #define DAGB7_WRCLI15__URG_HIGH_MASK 0x000000F0L 31614 #define DAGB7_WRCLI15__URG_LOW_MASK 0x00000F00L 31615 #define DAGB7_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L 31616 #define DAGB7_WRCLI15__MAX_BW_MASK 0x001FE000L 31617 #define DAGB7_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L 31618 #define DAGB7_WRCLI15__MIN_BW_MASK 0x01C00000L 31619 #define DAGB7_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 31620 #define DAGB7_WRCLI15__MAX_OSD_MASK 0xFC000000L 31621 //DAGB7_WR_CNTL 31622 #define DAGB7_WR_CNTL__SCLK_FREQ__SHIFT 0x0 31623 #define DAGB7_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 31624 #define DAGB7_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 31625 #define DAGB7_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 31626 #define DAGB7_WR_CNTL__IO_LEVEL__SHIFT 0x11 31627 #define DAGB7_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 31628 #define DAGB7_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 31629 #define DAGB7_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL 31630 #define DAGB7_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 31631 #define DAGB7_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 31632 #define DAGB7_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 31633 #define DAGB7_WR_CNTL__IO_LEVEL_MASK 0x000E0000L 31634 #define DAGB7_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 31635 #define DAGB7_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L 31636 //DAGB7_WR_GMI_CNTL 31637 #define DAGB7_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 31638 #define DAGB7_WR_GMI_CNTL__LEVEL__SHIFT 0x6 31639 #define DAGB7_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 31640 #define DAGB7_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 31641 #define DAGB7_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 31642 #define DAGB7_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L 31643 #define DAGB7_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 31644 #define DAGB7_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 31645 //DAGB7_WR_ADDR_DAGB 31646 #define DAGB7_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 31647 #define DAGB7_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 31648 #define DAGB7_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 31649 #define DAGB7_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 31650 #define DAGB7_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 31651 #define DAGB7_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 31652 #define DAGB7_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 31653 #define DAGB7_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 31654 //DAGB7_WR_OUTPUT_DAGB_MAX_BURST 31655 #define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 31656 #define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 31657 #define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 31658 #define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 31659 #define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 31660 #define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 31661 #define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 31662 #define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 31663 #define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 31664 #define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 31665 #define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 31666 #define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 31667 #define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 31668 #define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 31669 #define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 31670 #define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 31671 //DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER 31672 #define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 31673 #define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 31674 #define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 31675 #define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 31676 #define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 31677 #define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 31678 #define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 31679 #define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 31680 #define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 31681 #define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 31682 #define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 31683 #define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 31684 #define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 31685 #define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 31686 #define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 31687 #define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 31688 //DAGB7_WR_CGTT_CLK_CTRL 31689 #define DAGB7_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 31690 #define DAGB7_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 31691 #define DAGB7_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 31692 #define DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 31693 #define DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 31694 #define DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 31695 #define DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 31696 #define DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 31697 #define DAGB7_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 31698 #define DAGB7_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 31699 #define DAGB7_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 31700 #define DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 31701 #define DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 31702 #define DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 31703 #define DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 31704 #define DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 31705 //DAGB7_L1TLB_WR_CGTT_CLK_CTRL 31706 #define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 31707 #define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 31708 #define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 31709 #define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 31710 #define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 31711 #define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 31712 #define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 31713 #define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 31714 #define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 31715 #define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 31716 #define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 31717 #define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 31718 #define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 31719 #define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 31720 #define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 31721 #define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 31722 //DAGB7_ATCVM_WR_CGTT_CLK_CTRL 31723 #define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 31724 #define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 31725 #define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 31726 #define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 31727 #define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 31728 #define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 31729 #define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 31730 #define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 31731 #define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 31732 #define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 31733 #define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 31734 #define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 31735 #define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 31736 #define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 31737 #define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 31738 #define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 31739 //DAGB7_WR_ADDR_DAGB_MAX_BURST0 31740 #define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 31741 #define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 31742 #define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 31743 #define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 31744 #define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 31745 #define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 31746 #define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 31747 #define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 31748 #define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 31749 #define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 31750 #define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 31751 #define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 31752 #define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 31753 #define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 31754 #define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 31755 #define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 31756 //DAGB7_WR_ADDR_DAGB_LAZY_TIMER0 31757 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 31758 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 31759 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 31760 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 31761 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 31762 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 31763 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 31764 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 31765 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 31766 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 31767 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 31768 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 31769 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 31770 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 31771 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 31772 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 31773 //DAGB7_WR_ADDR_DAGB_MAX_BURST1 31774 #define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 31775 #define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 31776 #define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 31777 #define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 31778 #define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 31779 #define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 31780 #define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 31781 #define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 31782 #define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 31783 #define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 31784 #define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 31785 #define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 31786 #define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 31787 #define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 31788 #define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 31789 #define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 31790 //DAGB7_WR_ADDR_DAGB_LAZY_TIMER1 31791 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 31792 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 31793 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 31794 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 31795 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 31796 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 31797 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 31798 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 31799 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 31800 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 31801 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 31802 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 31803 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 31804 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 31805 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 31806 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 31807 //DAGB7_WR_DATA_DAGB 31808 #define DAGB7_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 31809 #define DAGB7_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 31810 #define DAGB7_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 31811 #define DAGB7_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 31812 #define DAGB7_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L 31813 #define DAGB7_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 31814 #define DAGB7_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 31815 #define DAGB7_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L 31816 //DAGB7_WR_DATA_DAGB_MAX_BURST0 31817 #define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 31818 #define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 31819 #define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 31820 #define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 31821 #define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 31822 #define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 31823 #define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 31824 #define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 31825 #define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 31826 #define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 31827 #define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 31828 #define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 31829 #define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 31830 #define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 31831 #define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 31832 #define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 31833 //DAGB7_WR_DATA_DAGB_LAZY_TIMER0 31834 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 31835 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 31836 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 31837 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 31838 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 31839 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 31840 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 31841 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 31842 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 31843 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 31844 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 31845 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 31846 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 31847 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 31848 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 31849 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 31850 //DAGB7_WR_DATA_DAGB_MAX_BURST1 31851 #define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 31852 #define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 31853 #define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 31854 #define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 31855 #define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 31856 #define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 31857 #define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 31858 #define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 31859 #define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 31860 #define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 31861 #define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 31862 #define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 31863 #define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 31864 #define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 31865 #define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 31866 #define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 31867 //DAGB7_WR_DATA_DAGB_LAZY_TIMER1 31868 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 31869 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 31870 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 31871 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 31872 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 31873 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 31874 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 31875 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 31876 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 31877 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 31878 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 31879 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 31880 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 31881 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 31882 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 31883 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 31884 //DAGB7_WR_VC0_CNTL 31885 #define DAGB7_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 31886 #define DAGB7_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 31887 #define DAGB7_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 31888 #define DAGB7_WR_VC0_CNTL__MAX_BW__SHIFT 0xc 31889 #define DAGB7_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 31890 #define DAGB7_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 31891 #define DAGB7_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 31892 #define DAGB7_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 31893 #define DAGB7_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 31894 #define DAGB7_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 31895 #define DAGB7_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 31896 #define DAGB7_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L 31897 #define DAGB7_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 31898 #define DAGB7_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L 31899 #define DAGB7_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 31900 #define DAGB7_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 31901 //DAGB7_WR_VC1_CNTL 31902 #define DAGB7_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 31903 #define DAGB7_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 31904 #define DAGB7_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 31905 #define DAGB7_WR_VC1_CNTL__MAX_BW__SHIFT 0xc 31906 #define DAGB7_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 31907 #define DAGB7_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 31908 #define DAGB7_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 31909 #define DAGB7_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 31910 #define DAGB7_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 31911 #define DAGB7_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 31912 #define DAGB7_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 31913 #define DAGB7_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L 31914 #define DAGB7_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 31915 #define DAGB7_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L 31916 #define DAGB7_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 31917 #define DAGB7_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 31918 //DAGB7_WR_VC2_CNTL 31919 #define DAGB7_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 31920 #define DAGB7_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 31921 #define DAGB7_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 31922 #define DAGB7_WR_VC2_CNTL__MAX_BW__SHIFT 0xc 31923 #define DAGB7_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 31924 #define DAGB7_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 31925 #define DAGB7_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 31926 #define DAGB7_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 31927 #define DAGB7_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 31928 #define DAGB7_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 31929 #define DAGB7_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 31930 #define DAGB7_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L 31931 #define DAGB7_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 31932 #define DAGB7_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L 31933 #define DAGB7_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 31934 #define DAGB7_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 31935 //DAGB7_WR_VC3_CNTL 31936 #define DAGB7_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 31937 #define DAGB7_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 31938 #define DAGB7_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 31939 #define DAGB7_WR_VC3_CNTL__MAX_BW__SHIFT 0xc 31940 #define DAGB7_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 31941 #define DAGB7_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 31942 #define DAGB7_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 31943 #define DAGB7_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 31944 #define DAGB7_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 31945 #define DAGB7_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 31946 #define DAGB7_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 31947 #define DAGB7_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L 31948 #define DAGB7_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 31949 #define DAGB7_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L 31950 #define DAGB7_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 31951 #define DAGB7_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 31952 //DAGB7_WR_VC4_CNTL 31953 #define DAGB7_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 31954 #define DAGB7_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 31955 #define DAGB7_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 31956 #define DAGB7_WR_VC4_CNTL__MAX_BW__SHIFT 0xc 31957 #define DAGB7_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 31958 #define DAGB7_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 31959 #define DAGB7_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 31960 #define DAGB7_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 31961 #define DAGB7_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 31962 #define DAGB7_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 31963 #define DAGB7_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 31964 #define DAGB7_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L 31965 #define DAGB7_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 31966 #define DAGB7_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L 31967 #define DAGB7_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 31968 #define DAGB7_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 31969 //DAGB7_WR_VC5_CNTL 31970 #define DAGB7_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 31971 #define DAGB7_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 31972 #define DAGB7_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 31973 #define DAGB7_WR_VC5_CNTL__MAX_BW__SHIFT 0xc 31974 #define DAGB7_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 31975 #define DAGB7_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 31976 #define DAGB7_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 31977 #define DAGB7_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 31978 #define DAGB7_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 31979 #define DAGB7_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 31980 #define DAGB7_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 31981 #define DAGB7_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L 31982 #define DAGB7_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 31983 #define DAGB7_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L 31984 #define DAGB7_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 31985 #define DAGB7_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 31986 //DAGB7_WR_VC6_CNTL 31987 #define DAGB7_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 31988 #define DAGB7_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 31989 #define DAGB7_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 31990 #define DAGB7_WR_VC6_CNTL__MAX_BW__SHIFT 0xc 31991 #define DAGB7_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 31992 #define DAGB7_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 31993 #define DAGB7_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 31994 #define DAGB7_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 31995 #define DAGB7_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 31996 #define DAGB7_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 31997 #define DAGB7_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 31998 #define DAGB7_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L 31999 #define DAGB7_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 32000 #define DAGB7_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L 32001 #define DAGB7_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 32002 #define DAGB7_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 32003 //DAGB7_WR_VC7_CNTL 32004 #define DAGB7_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 32005 #define DAGB7_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 32006 #define DAGB7_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 32007 #define DAGB7_WR_VC7_CNTL__MAX_BW__SHIFT 0xc 32008 #define DAGB7_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 32009 #define DAGB7_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 32010 #define DAGB7_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 32011 #define DAGB7_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 32012 #define DAGB7_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 32013 #define DAGB7_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 32014 #define DAGB7_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 32015 #define DAGB7_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L 32016 #define DAGB7_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 32017 #define DAGB7_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L 32018 #define DAGB7_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 32019 #define DAGB7_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 32020 //DAGB7_WR_CNTL_MISC 32021 #define DAGB7_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 32022 #define DAGB7_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 32023 #define DAGB7_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 32024 #define DAGB7_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 32025 #define DAGB7_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 32026 #define DAGB7_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 32027 #define DAGB7_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a 32028 #define DAGB7_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 32029 #define DAGB7_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 32030 #define DAGB7_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 32031 #define DAGB7_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 32032 #define DAGB7_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 32033 #define DAGB7_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 32034 #define DAGB7_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L 32035 //DAGB7_WR_TLB_CREDIT 32036 #define DAGB7_WR_TLB_CREDIT__TLB0__SHIFT 0x0 32037 #define DAGB7_WR_TLB_CREDIT__TLB1__SHIFT 0x5 32038 #define DAGB7_WR_TLB_CREDIT__TLB2__SHIFT 0xa 32039 #define DAGB7_WR_TLB_CREDIT__TLB3__SHIFT 0xf 32040 #define DAGB7_WR_TLB_CREDIT__TLB4__SHIFT 0x14 32041 #define DAGB7_WR_TLB_CREDIT__TLB5__SHIFT 0x19 32042 #define DAGB7_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL 32043 #define DAGB7_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L 32044 #define DAGB7_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L 32045 #define DAGB7_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L 32046 #define DAGB7_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L 32047 #define DAGB7_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L 32048 //DAGB7_WR_DATA_CREDIT 32049 #define DAGB7_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 32050 #define DAGB7_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 32051 #define DAGB7_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 32052 #define DAGB7_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 32053 #define DAGB7_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL 32054 #define DAGB7_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L 32055 #define DAGB7_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L 32056 #define DAGB7_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L 32057 //DAGB7_WR_MISC_CREDIT 32058 #define DAGB7_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 32059 #define DAGB7_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 32060 #define DAGB7_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 32061 #define DAGB7_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 32062 #define DAGB7_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL 32063 #define DAGB7_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L 32064 #define DAGB7_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L 32065 #define DAGB7_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L 32066 //DAGB7_WRCLI_ASK_PENDING 32067 #define DAGB7_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 32068 #define DAGB7_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 32069 //DAGB7_WRCLI_GO_PENDING 32070 #define DAGB7_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 32071 #define DAGB7_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 32072 //DAGB7_WRCLI_GBLSEND_PENDING 32073 #define DAGB7_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 32074 #define DAGB7_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 32075 //DAGB7_WRCLI_TLB_PENDING 32076 #define DAGB7_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 32077 #define DAGB7_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 32078 //DAGB7_WRCLI_OARB_PENDING 32079 #define DAGB7_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 32080 #define DAGB7_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 32081 //DAGB7_WRCLI_OSD_PENDING 32082 #define DAGB7_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 32083 #define DAGB7_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 32084 //DAGB7_WRCLI_DBUS_ASK_PENDING 32085 #define DAGB7_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 32086 #define DAGB7_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 32087 //DAGB7_WRCLI_DBUS_GO_PENDING 32088 #define DAGB7_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 32089 #define DAGB7_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 32090 //DAGB7_DAGB_DLY 32091 #define DAGB7_DAGB_DLY__DLY__SHIFT 0x0 32092 #define DAGB7_DAGB_DLY__CLI__SHIFT 0x8 32093 #define DAGB7_DAGB_DLY__POS__SHIFT 0x10 32094 #define DAGB7_DAGB_DLY__DLY_MASK 0x000000FFL 32095 #define DAGB7_DAGB_DLY__CLI_MASK 0x0000FF00L 32096 #define DAGB7_DAGB_DLY__POS_MASK 0x000F0000L 32097 //DAGB7_CNTL_MISC 32098 #define DAGB7_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 32099 #define DAGB7_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 32100 #define DAGB7_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 32101 #define DAGB7_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 32102 #define DAGB7_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc 32103 #define DAGB7_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf 32104 #define DAGB7_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 32105 #define DAGB7_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 32106 #define DAGB7_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 32107 #define DAGB7_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e 32108 #define DAGB7_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L 32109 #define DAGB7_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L 32110 #define DAGB7_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L 32111 #define DAGB7_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L 32112 #define DAGB7_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L 32113 #define DAGB7_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L 32114 #define DAGB7_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L 32115 #define DAGB7_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L 32116 #define DAGB7_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L 32117 #define DAGB7_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L 32118 //DAGB7_CNTL_MISC2 32119 #define DAGB7_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 32120 #define DAGB7_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 32121 #define DAGB7_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 32122 #define DAGB7_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 32123 #define DAGB7_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 32124 #define DAGB7_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 32125 #define DAGB7_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 32126 #define DAGB7_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 32127 #define DAGB7_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 32128 #define DAGB7_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 32129 #define DAGB7_CNTL_MISC2__SWAP_CTL__SHIFT 0xa 32130 #define DAGB7_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xb 32131 #define DAGB7_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x11 32132 #define DAGB7_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L 32133 #define DAGB7_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L 32134 #define DAGB7_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L 32135 #define DAGB7_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L 32136 #define DAGB7_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L 32137 #define DAGB7_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L 32138 #define DAGB7_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L 32139 #define DAGB7_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L 32140 #define DAGB7_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L 32141 #define DAGB7_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L 32142 #define DAGB7_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L 32143 #define DAGB7_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000800L 32144 #define DAGB7_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x007E0000L 32145 //DAGB7_FIFO_EMPTY 32146 #define DAGB7_FIFO_EMPTY__EMPTY__SHIFT 0x0 32147 #define DAGB7_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL 32148 //DAGB7_FIFO_FULL 32149 #define DAGB7_FIFO_FULL__FULL__SHIFT 0x0 32150 #define DAGB7_FIFO_FULL__FULL_MASK 0x007FFFFFL 32151 //DAGB7_WR_CREDITS_FULL 32152 #define DAGB7_WR_CREDITS_FULL__FULL__SHIFT 0x0 32153 #define DAGB7_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL 32154 //DAGB7_RD_CREDITS_FULL 32155 #define DAGB7_RD_CREDITS_FULL__FULL__SHIFT 0x0 32156 #define DAGB7_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL 32157 //DAGB7_PERFCOUNTER_LO 32158 #define DAGB7_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 32159 #define DAGB7_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 32160 //DAGB7_PERFCOUNTER_HI 32161 #define DAGB7_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 32162 #define DAGB7_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 32163 #define DAGB7_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 32164 #define DAGB7_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 32165 //DAGB7_PERFCOUNTER0_CFG 32166 #define DAGB7_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 32167 #define DAGB7_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 32168 #define DAGB7_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 32169 #define DAGB7_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 32170 #define DAGB7_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 32171 #define DAGB7_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 32172 #define DAGB7_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 32173 #define DAGB7_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 32174 #define DAGB7_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 32175 #define DAGB7_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 32176 //DAGB7_PERFCOUNTER1_CFG 32177 #define DAGB7_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 32178 #define DAGB7_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 32179 #define DAGB7_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 32180 #define DAGB7_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 32181 #define DAGB7_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 32182 #define DAGB7_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 32183 #define DAGB7_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 32184 #define DAGB7_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 32185 #define DAGB7_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 32186 #define DAGB7_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 32187 //DAGB7_PERFCOUNTER2_CFG 32188 #define DAGB7_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 32189 #define DAGB7_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 32190 #define DAGB7_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 32191 #define DAGB7_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 32192 #define DAGB7_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 32193 #define DAGB7_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 32194 #define DAGB7_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 32195 #define DAGB7_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 32196 #define DAGB7_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 32197 #define DAGB7_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 32198 //DAGB7_PERFCOUNTER_RSLT_CNTL 32199 #define DAGB7_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 32200 #define DAGB7_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 32201 #define DAGB7_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 32202 #define DAGB7_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 32203 #define DAGB7_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 32204 #define DAGB7_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 32205 #define DAGB7_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 32206 #define DAGB7_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 32207 #define DAGB7_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 32208 #define DAGB7_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 32209 #define DAGB7_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 32210 #define DAGB7_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 32211 //DAGB7_RESERVE0 32212 #define DAGB7_RESERVE0__RESERVE__SHIFT 0x0 32213 #define DAGB7_RESERVE0__RESERVE_MASK 0xFFFFFFFFL 32214 //DAGB7_RESERVE1 32215 #define DAGB7_RESERVE1__RESERVE__SHIFT 0x0 32216 #define DAGB7_RESERVE1__RESERVE_MASK 0xFFFFFFFFL 32217 //DAGB7_RESERVE2 32218 #define DAGB7_RESERVE2__RESERVE__SHIFT 0x0 32219 #define DAGB7_RESERVE2__RESERVE_MASK 0xFFFFFFFFL 32220 //DAGB7_RESERVE3 32221 #define DAGB7_RESERVE3__RESERVE__SHIFT 0x0 32222 #define DAGB7_RESERVE3__RESERVE_MASK 0xFFFFFFFFL 32223 //DAGB7_RESERVE4 32224 #define DAGB7_RESERVE4__RESERVE__SHIFT 0x0 32225 #define DAGB7_RESERVE4__RESERVE_MASK 0xFFFFFFFFL 32226 //DAGB7_RESERVE5 32227 #define DAGB7_RESERVE5__RESERVE__SHIFT 0x0 32228 #define DAGB7_RESERVE5__RESERVE_MASK 0xFFFFFFFFL 32229 //DAGB7_RESERVE6 32230 #define DAGB7_RESERVE6__RESERVE__SHIFT 0x0 32231 #define DAGB7_RESERVE6__RESERVE_MASK 0xFFFFFFFFL 32232 //DAGB7_RESERVE7 32233 #define DAGB7_RESERVE7__RESERVE__SHIFT 0x0 32234 #define DAGB7_RESERVE7__RESERVE_MASK 0xFFFFFFFFL 32235 //DAGB7_RESERVE8 32236 #define DAGB7_RESERVE8__RESERVE__SHIFT 0x0 32237 #define DAGB7_RESERVE8__RESERVE_MASK 0xFFFFFFFFL 32238 //DAGB7_RESERVE9 32239 #define DAGB7_RESERVE9__RESERVE__SHIFT 0x0 32240 #define DAGB7_RESERVE9__RESERVE_MASK 0xFFFFFFFFL 32241 //DAGB7_RESERVE10 32242 #define DAGB7_RESERVE10__RESERVE__SHIFT 0x0 32243 #define DAGB7_RESERVE10__RESERVE_MASK 0xFFFFFFFFL 32244 //DAGB7_RESERVE11 32245 #define DAGB7_RESERVE11__RESERVE__SHIFT 0x0 32246 #define DAGB7_RESERVE11__RESERVE_MASK 0xFFFFFFFFL 32247 //DAGB7_RESERVE12 32248 #define DAGB7_RESERVE12__RESERVE__SHIFT 0x0 32249 #define DAGB7_RESERVE12__RESERVE_MASK 0xFFFFFFFFL 32250 //DAGB7_RESERVE13 32251 #define DAGB7_RESERVE13__RESERVE__SHIFT 0x0 32252 #define DAGB7_RESERVE13__RESERVE_MASK 0xFFFFFFFFL 32253 32254 32255 // addressBlock: mmhub_ea_mmeadec5 32256 //MMEA5_DRAM_RD_CLI2GRP_MAP0 32257 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 32258 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 32259 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 32260 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 32261 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 32262 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 32263 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 32264 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 32265 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 32266 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 32267 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 32268 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 32269 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 32270 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 32271 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 32272 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 32273 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 32274 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 32275 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 32276 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 32277 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 32278 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 32279 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 32280 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 32281 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 32282 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 32283 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 32284 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 32285 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 32286 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 32287 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 32288 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 32289 //MMEA5_DRAM_RD_CLI2GRP_MAP1 32290 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 32291 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 32292 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 32293 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 32294 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 32295 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 32296 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 32297 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 32298 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 32299 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 32300 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 32301 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 32302 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 32303 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 32304 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 32305 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 32306 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 32307 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 32308 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 32309 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 32310 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 32311 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 32312 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 32313 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 32314 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 32315 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 32316 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 32317 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 32318 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 32319 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 32320 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 32321 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 32322 //MMEA5_DRAM_WR_CLI2GRP_MAP0 32323 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 32324 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 32325 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 32326 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 32327 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 32328 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 32329 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 32330 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 32331 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 32332 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 32333 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 32334 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 32335 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 32336 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 32337 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 32338 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 32339 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 32340 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 32341 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 32342 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 32343 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 32344 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 32345 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 32346 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 32347 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 32348 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 32349 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 32350 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 32351 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 32352 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 32353 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 32354 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 32355 //MMEA5_DRAM_WR_CLI2GRP_MAP1 32356 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 32357 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 32358 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 32359 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 32360 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 32361 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 32362 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 32363 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 32364 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 32365 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 32366 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 32367 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 32368 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 32369 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 32370 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 32371 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 32372 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 32373 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 32374 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 32375 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 32376 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 32377 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 32378 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 32379 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 32380 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 32381 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 32382 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 32383 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 32384 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 32385 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 32386 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 32387 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 32388 //MMEA5_DRAM_RD_GRP2VC_MAP 32389 #define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 32390 #define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 32391 #define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 32392 #define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 32393 #define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 32394 #define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 32395 #define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 32396 #define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 32397 //MMEA5_DRAM_WR_GRP2VC_MAP 32398 #define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 32399 #define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 32400 #define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 32401 #define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 32402 #define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 32403 #define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 32404 #define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 32405 #define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 32406 //MMEA5_DRAM_RD_LAZY 32407 #define MMEA5_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 32408 #define MMEA5_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 32409 #define MMEA5_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 32410 #define MMEA5_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 32411 #define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 32412 #define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 32413 #define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 32414 #define MMEA5_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L 32415 #define MMEA5_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L 32416 #define MMEA5_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L 32417 #define MMEA5_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L 32418 #define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 32419 #define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 32420 #define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 32421 //MMEA5_DRAM_WR_LAZY 32422 #define MMEA5_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 32423 #define MMEA5_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 32424 #define MMEA5_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 32425 #define MMEA5_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 32426 #define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 32427 #define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 32428 #define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 32429 #define MMEA5_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L 32430 #define MMEA5_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L 32431 #define MMEA5_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L 32432 #define MMEA5_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L 32433 #define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 32434 #define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 32435 #define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 32436 //MMEA5_DRAM_RD_CAM_CNTL 32437 #define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 32438 #define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 32439 #define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 32440 #define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 32441 #define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 32442 #define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 32443 #define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 32444 #define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 32445 #define MMEA5_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 32446 #define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 32447 #define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 32448 #define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 32449 #define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 32450 #define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 32451 #define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 32452 #define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 32453 #define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 32454 #define MMEA5_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 32455 //MMEA5_DRAM_WR_CAM_CNTL 32456 #define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 32457 #define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 32458 #define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 32459 #define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 32460 #define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 32461 #define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 32462 #define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 32463 #define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 32464 #define MMEA5_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 32465 #define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 32466 #define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 32467 #define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 32468 #define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 32469 #define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 32470 #define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 32471 #define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 32472 #define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 32473 #define MMEA5_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 32474 //MMEA5_DRAM_PAGE_BURST 32475 #define MMEA5_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 32476 #define MMEA5_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 32477 #define MMEA5_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 32478 #define MMEA5_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 32479 #define MMEA5_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL 32480 #define MMEA5_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 32481 #define MMEA5_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 32482 #define MMEA5_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L 32483 //MMEA5_DRAM_RD_PRI_AGE 32484 #define MMEA5_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 32485 #define MMEA5_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 32486 #define MMEA5_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 32487 #define MMEA5_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 32488 #define MMEA5_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 32489 #define MMEA5_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 32490 #define MMEA5_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 32491 #define MMEA5_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 32492 #define MMEA5_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 32493 #define MMEA5_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 32494 #define MMEA5_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 32495 #define MMEA5_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 32496 #define MMEA5_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 32497 #define MMEA5_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 32498 #define MMEA5_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 32499 #define MMEA5_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 32500 //MMEA5_DRAM_WR_PRI_AGE 32501 #define MMEA5_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 32502 #define MMEA5_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 32503 #define MMEA5_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 32504 #define MMEA5_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 32505 #define MMEA5_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 32506 #define MMEA5_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 32507 #define MMEA5_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 32508 #define MMEA5_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 32509 #define MMEA5_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 32510 #define MMEA5_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 32511 #define MMEA5_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 32512 #define MMEA5_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 32513 #define MMEA5_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 32514 #define MMEA5_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 32515 #define MMEA5_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 32516 #define MMEA5_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 32517 //MMEA5_DRAM_RD_PRI_QUEUING 32518 #define MMEA5_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 32519 #define MMEA5_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 32520 #define MMEA5_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 32521 #define MMEA5_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 32522 #define MMEA5_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 32523 #define MMEA5_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 32524 #define MMEA5_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 32525 #define MMEA5_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 32526 //MMEA5_DRAM_WR_PRI_QUEUING 32527 #define MMEA5_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 32528 #define MMEA5_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 32529 #define MMEA5_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 32530 #define MMEA5_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 32531 #define MMEA5_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 32532 #define MMEA5_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 32533 #define MMEA5_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 32534 #define MMEA5_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 32535 //MMEA5_DRAM_RD_PRI_FIXED 32536 #define MMEA5_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 32537 #define MMEA5_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 32538 #define MMEA5_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 32539 #define MMEA5_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 32540 #define MMEA5_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 32541 #define MMEA5_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 32542 #define MMEA5_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 32543 #define MMEA5_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 32544 //MMEA5_DRAM_WR_PRI_FIXED 32545 #define MMEA5_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 32546 #define MMEA5_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 32547 #define MMEA5_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 32548 #define MMEA5_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 32549 #define MMEA5_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 32550 #define MMEA5_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 32551 #define MMEA5_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 32552 #define MMEA5_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 32553 //MMEA5_DRAM_RD_PRI_URGENCY 32554 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 32555 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 32556 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 32557 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 32558 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 32559 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 32560 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 32561 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 32562 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 32563 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 32564 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 32565 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 32566 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 32567 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 32568 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 32569 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 32570 //MMEA5_DRAM_WR_PRI_URGENCY 32571 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 32572 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 32573 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 32574 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 32575 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 32576 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 32577 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 32578 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 32579 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 32580 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 32581 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 32582 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 32583 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 32584 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 32585 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 32586 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 32587 //MMEA5_DRAM_RD_PRI_QUANT_PRI1 32588 #define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 32589 #define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 32590 #define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 32591 #define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 32592 #define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 32593 #define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 32594 #define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 32595 #define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 32596 //MMEA5_DRAM_RD_PRI_QUANT_PRI2 32597 #define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 32598 #define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 32599 #define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 32600 #define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 32601 #define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 32602 #define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 32603 #define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 32604 #define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 32605 //MMEA5_DRAM_RD_PRI_QUANT_PRI3 32606 #define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 32607 #define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 32608 #define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 32609 #define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 32610 #define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 32611 #define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 32612 #define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 32613 #define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 32614 //MMEA5_DRAM_WR_PRI_QUANT_PRI1 32615 #define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 32616 #define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 32617 #define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 32618 #define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 32619 #define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 32620 #define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 32621 #define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 32622 #define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 32623 //MMEA5_DRAM_WR_PRI_QUANT_PRI2 32624 #define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 32625 #define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 32626 #define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 32627 #define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 32628 #define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 32629 #define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 32630 #define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 32631 #define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 32632 //MMEA5_DRAM_WR_PRI_QUANT_PRI3 32633 #define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 32634 #define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 32635 #define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 32636 #define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 32637 #define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 32638 #define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 32639 #define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 32640 #define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 32641 //MMEA5_GMI_RD_CLI2GRP_MAP0 32642 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 32643 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 32644 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 32645 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 32646 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 32647 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 32648 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 32649 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 32650 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 32651 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 32652 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 32653 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 32654 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 32655 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 32656 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 32657 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 32658 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 32659 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 32660 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 32661 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 32662 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 32663 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 32664 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 32665 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 32666 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 32667 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 32668 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 32669 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 32670 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 32671 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 32672 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 32673 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 32674 //MMEA5_GMI_RD_CLI2GRP_MAP1 32675 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 32676 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 32677 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 32678 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 32679 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 32680 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 32681 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 32682 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 32683 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 32684 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 32685 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 32686 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 32687 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 32688 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 32689 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 32690 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 32691 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 32692 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 32693 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 32694 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 32695 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 32696 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 32697 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 32698 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 32699 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 32700 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 32701 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 32702 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 32703 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 32704 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 32705 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 32706 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 32707 //MMEA5_GMI_WR_CLI2GRP_MAP0 32708 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 32709 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 32710 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 32711 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 32712 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 32713 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 32714 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 32715 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 32716 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 32717 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 32718 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 32719 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 32720 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 32721 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 32722 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 32723 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 32724 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 32725 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 32726 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 32727 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 32728 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 32729 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 32730 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 32731 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 32732 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 32733 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 32734 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 32735 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 32736 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 32737 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 32738 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 32739 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 32740 //MMEA5_GMI_WR_CLI2GRP_MAP1 32741 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 32742 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 32743 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 32744 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 32745 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 32746 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 32747 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 32748 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 32749 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 32750 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 32751 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 32752 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 32753 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 32754 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 32755 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 32756 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 32757 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 32758 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 32759 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 32760 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 32761 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 32762 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 32763 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 32764 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 32765 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 32766 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 32767 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 32768 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 32769 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 32770 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 32771 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 32772 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 32773 //MMEA5_GMI_RD_GRP2VC_MAP 32774 #define MMEA5_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 32775 #define MMEA5_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 32776 #define MMEA5_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 32777 #define MMEA5_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 32778 #define MMEA5_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 32779 #define MMEA5_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 32780 #define MMEA5_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 32781 #define MMEA5_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 32782 //MMEA5_GMI_WR_GRP2VC_MAP 32783 #define MMEA5_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 32784 #define MMEA5_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 32785 #define MMEA5_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 32786 #define MMEA5_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 32787 #define MMEA5_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 32788 #define MMEA5_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 32789 #define MMEA5_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 32790 #define MMEA5_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 32791 //MMEA5_GMI_RD_LAZY 32792 #define MMEA5_GMI_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 32793 #define MMEA5_GMI_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 32794 #define MMEA5_GMI_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 32795 #define MMEA5_GMI_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 32796 #define MMEA5_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 32797 #define MMEA5_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 32798 #define MMEA5_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 32799 #define MMEA5_GMI_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L 32800 #define MMEA5_GMI_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L 32801 #define MMEA5_GMI_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L 32802 #define MMEA5_GMI_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L 32803 #define MMEA5_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 32804 #define MMEA5_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 32805 #define MMEA5_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 32806 //MMEA5_GMI_WR_LAZY 32807 #define MMEA5_GMI_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 32808 #define MMEA5_GMI_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 32809 #define MMEA5_GMI_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 32810 #define MMEA5_GMI_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 32811 #define MMEA5_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 32812 #define MMEA5_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 32813 #define MMEA5_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 32814 #define MMEA5_GMI_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L 32815 #define MMEA5_GMI_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L 32816 #define MMEA5_GMI_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L 32817 #define MMEA5_GMI_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L 32818 #define MMEA5_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 32819 #define MMEA5_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 32820 #define MMEA5_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 32821 //MMEA5_GMI_RD_CAM_CNTL 32822 #define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 32823 #define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 32824 #define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 32825 #define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 32826 #define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 32827 #define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 32828 #define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 32829 #define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 32830 #define MMEA5_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 32831 #define MMEA5_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d 32832 #define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 32833 #define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 32834 #define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 32835 #define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 32836 #define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 32837 #define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 32838 #define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 32839 #define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 32840 #define MMEA5_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 32841 #define MMEA5_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L 32842 //MMEA5_GMI_WR_CAM_CNTL 32843 #define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 32844 #define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 32845 #define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 32846 #define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 32847 #define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 32848 #define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 32849 #define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 32850 #define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 32851 #define MMEA5_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 32852 #define MMEA5_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d 32853 #define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 32854 #define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 32855 #define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 32856 #define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 32857 #define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 32858 #define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 32859 #define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 32860 #define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 32861 #define MMEA5_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 32862 #define MMEA5_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L 32863 //MMEA5_GMI_PAGE_BURST 32864 #define MMEA5_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 32865 #define MMEA5_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 32866 #define MMEA5_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 32867 #define MMEA5_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 32868 #define MMEA5_GMI_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL 32869 #define MMEA5_GMI_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 32870 #define MMEA5_GMI_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 32871 #define MMEA5_GMI_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L 32872 //MMEA5_GMI_RD_PRI_AGE 32873 #define MMEA5_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 32874 #define MMEA5_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 32875 #define MMEA5_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 32876 #define MMEA5_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 32877 #define MMEA5_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 32878 #define MMEA5_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 32879 #define MMEA5_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 32880 #define MMEA5_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 32881 #define MMEA5_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 32882 #define MMEA5_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 32883 #define MMEA5_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 32884 #define MMEA5_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 32885 #define MMEA5_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 32886 #define MMEA5_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 32887 #define MMEA5_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 32888 #define MMEA5_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 32889 //MMEA5_GMI_WR_PRI_AGE 32890 #define MMEA5_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 32891 #define MMEA5_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 32892 #define MMEA5_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 32893 #define MMEA5_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 32894 #define MMEA5_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 32895 #define MMEA5_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 32896 #define MMEA5_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 32897 #define MMEA5_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 32898 #define MMEA5_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 32899 #define MMEA5_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 32900 #define MMEA5_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 32901 #define MMEA5_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 32902 #define MMEA5_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 32903 #define MMEA5_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 32904 #define MMEA5_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 32905 #define MMEA5_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 32906 //MMEA5_GMI_RD_PRI_QUEUING 32907 #define MMEA5_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 32908 #define MMEA5_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 32909 #define MMEA5_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 32910 #define MMEA5_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 32911 #define MMEA5_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 32912 #define MMEA5_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 32913 #define MMEA5_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 32914 #define MMEA5_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 32915 //MMEA5_GMI_WR_PRI_QUEUING 32916 #define MMEA5_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 32917 #define MMEA5_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 32918 #define MMEA5_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 32919 #define MMEA5_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 32920 #define MMEA5_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 32921 #define MMEA5_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 32922 #define MMEA5_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 32923 #define MMEA5_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 32924 //MMEA5_GMI_RD_PRI_FIXED 32925 #define MMEA5_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 32926 #define MMEA5_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 32927 #define MMEA5_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 32928 #define MMEA5_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 32929 #define MMEA5_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 32930 #define MMEA5_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 32931 #define MMEA5_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 32932 #define MMEA5_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 32933 //MMEA5_GMI_WR_PRI_FIXED 32934 #define MMEA5_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 32935 #define MMEA5_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 32936 #define MMEA5_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 32937 #define MMEA5_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 32938 #define MMEA5_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 32939 #define MMEA5_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 32940 #define MMEA5_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 32941 #define MMEA5_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 32942 //MMEA5_GMI_RD_PRI_URGENCY 32943 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 32944 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 32945 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 32946 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 32947 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 32948 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 32949 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 32950 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 32951 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 32952 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 32953 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 32954 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 32955 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 32956 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 32957 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 32958 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 32959 //MMEA5_GMI_WR_PRI_URGENCY 32960 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 32961 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 32962 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 32963 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 32964 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 32965 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 32966 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 32967 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 32968 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 32969 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 32970 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 32971 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 32972 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 32973 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 32974 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 32975 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 32976 //MMEA5_GMI_RD_PRI_URGENCY_MASKING 32977 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 32978 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 32979 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 32980 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 32981 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 32982 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 32983 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 32984 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 32985 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 32986 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 32987 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 32988 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 32989 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 32990 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 32991 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 32992 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 32993 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 32994 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 32995 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 32996 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 32997 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 32998 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 32999 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 33000 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 33001 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 33002 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 33003 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 33004 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 33005 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 33006 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 33007 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 33008 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 33009 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 33010 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 33011 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 33012 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 33013 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 33014 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 33015 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 33016 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 33017 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 33018 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 33019 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 33020 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 33021 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 33022 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 33023 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 33024 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 33025 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 33026 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 33027 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 33028 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 33029 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 33030 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 33031 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 33032 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 33033 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 33034 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 33035 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 33036 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 33037 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 33038 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 33039 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 33040 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 33041 //MMEA5_GMI_WR_PRI_URGENCY_MASKING 33042 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 33043 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 33044 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 33045 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 33046 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 33047 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 33048 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 33049 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 33050 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 33051 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 33052 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 33053 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 33054 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 33055 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 33056 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 33057 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 33058 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 33059 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 33060 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 33061 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 33062 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 33063 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 33064 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 33065 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 33066 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 33067 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 33068 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 33069 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 33070 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 33071 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 33072 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 33073 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 33074 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 33075 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 33076 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 33077 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 33078 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 33079 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 33080 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 33081 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 33082 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 33083 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 33084 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 33085 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 33086 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 33087 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 33088 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 33089 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 33090 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 33091 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 33092 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 33093 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 33094 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 33095 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 33096 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 33097 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 33098 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 33099 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 33100 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 33101 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 33102 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 33103 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 33104 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 33105 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 33106 //MMEA5_GMI_RD_PRI_QUANT_PRI1 33107 #define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 33108 #define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 33109 #define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 33110 #define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 33111 #define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 33112 #define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 33113 #define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 33114 #define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 33115 //MMEA5_GMI_RD_PRI_QUANT_PRI2 33116 #define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 33117 #define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 33118 #define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 33119 #define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 33120 #define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 33121 #define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 33122 #define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 33123 #define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 33124 //MMEA5_GMI_RD_PRI_QUANT_PRI3 33125 #define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 33126 #define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 33127 #define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 33128 #define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 33129 #define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 33130 #define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 33131 #define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 33132 #define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 33133 //MMEA5_GMI_WR_PRI_QUANT_PRI1 33134 #define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 33135 #define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 33136 #define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 33137 #define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 33138 #define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 33139 #define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 33140 #define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 33141 #define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 33142 //MMEA5_GMI_WR_PRI_QUANT_PRI2 33143 #define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 33144 #define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 33145 #define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 33146 #define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 33147 #define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 33148 #define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 33149 #define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 33150 #define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 33151 //MMEA5_GMI_WR_PRI_QUANT_PRI3 33152 #define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 33153 #define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 33154 #define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 33155 #define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 33156 #define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 33157 #define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 33158 #define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 33159 #define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 33160 //MMEA5_ADDRNORM_BASE_ADDR0 33161 #define MMEA5_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 33162 #define MMEA5_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 33163 #define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 33164 #define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x6 33165 #define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 33166 #define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 33167 #define MMEA5_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc 33168 #define MMEA5_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L 33169 #define MMEA5_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 33170 #define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000003CL 33171 #define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x000000C0L 33172 #define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L 33173 #define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L 33174 #define MMEA5_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L 33175 //MMEA5_ADDRNORM_LIMIT_ADDR0 33176 #define MMEA5_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 33177 #define MMEA5_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc 33178 #define MMEA5_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL 33179 #define MMEA5_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L 33180 //MMEA5_ADDRNORM_BASE_ADDR1 33181 #define MMEA5_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 33182 #define MMEA5_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 33183 #define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 33184 #define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x6 33185 #define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 33186 #define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 33187 #define MMEA5_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc 33188 #define MMEA5_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L 33189 #define MMEA5_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 33190 #define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000003CL 33191 #define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x000000C0L 33192 #define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L 33193 #define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L 33194 #define MMEA5_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L 33195 //MMEA5_ADDRNORM_LIMIT_ADDR1 33196 #define MMEA5_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 33197 #define MMEA5_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc 33198 #define MMEA5_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL 33199 #define MMEA5_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L 33200 //MMEA5_ADDRNORM_OFFSET_ADDR1 33201 #define MMEA5_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 33202 #define MMEA5_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 33203 #define MMEA5_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L 33204 #define MMEA5_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L 33205 //MMEA5_ADDRNORM_BASE_ADDR2 33206 #define MMEA5_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT 0x0 33207 #define MMEA5_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT 0x1 33208 #define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT 0x2 33209 #define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT 0x6 33210 #define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT 0x8 33211 #define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT 0x9 33212 #define MMEA5_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT 0xc 33213 #define MMEA5_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK 0x00000001L 33214 #define MMEA5_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 33215 #define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK 0x0000003CL 33216 #define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK 0x000000C0L 33217 #define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK 0x00000100L 33218 #define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK 0x00000E00L 33219 #define MMEA5_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK 0xFFFFF000L 33220 //MMEA5_ADDRNORM_LIMIT_ADDR2 33221 #define MMEA5_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT 0x0 33222 #define MMEA5_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT 0xc 33223 #define MMEA5_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK 0x0000001FL 33224 #define MMEA5_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK 0xFFFFF000L 33225 //MMEA5_ADDRNORM_BASE_ADDR3 33226 #define MMEA5_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT 0x0 33227 #define MMEA5_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT 0x1 33228 #define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT 0x2 33229 #define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT 0x6 33230 #define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT 0x8 33231 #define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT 0x9 33232 #define MMEA5_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT 0xc 33233 #define MMEA5_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK 0x00000001L 33234 #define MMEA5_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 33235 #define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK 0x0000003CL 33236 #define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK 0x000000C0L 33237 #define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK 0x00000100L 33238 #define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK 0x00000E00L 33239 #define MMEA5_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK 0xFFFFF000L 33240 //MMEA5_ADDRNORM_LIMIT_ADDR3 33241 #define MMEA5_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT 0x0 33242 #define MMEA5_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT 0xc 33243 #define MMEA5_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK 0x0000001FL 33244 #define MMEA5_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK 0xFFFFF000L 33245 //MMEA5_ADDRNORM_OFFSET_ADDR3 33246 #define MMEA5_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT 0x0 33247 #define MMEA5_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT 0x14 33248 #define MMEA5_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK 0x00000001L 33249 #define MMEA5_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK 0xFFF00000L 33250 //MMEA5_ADDRNORM_BASE_ADDR4 33251 #define MMEA5_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL__SHIFT 0x0 33252 #define MMEA5_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN__SHIFT 0x1 33253 #define MMEA5_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN__SHIFT 0x2 33254 #define MMEA5_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES__SHIFT 0x6 33255 #define MMEA5_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS__SHIFT 0x8 33256 #define MMEA5_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL__SHIFT 0x9 33257 #define MMEA5_ADDRNORM_BASE_ADDR4__BASE_ADDR__SHIFT 0xc 33258 #define MMEA5_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL_MASK 0x00000001L 33259 #define MMEA5_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 33260 #define MMEA5_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN_MASK 0x0000003CL 33261 #define MMEA5_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES_MASK 0x000000C0L 33262 #define MMEA5_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS_MASK 0x00000100L 33263 #define MMEA5_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL_MASK 0x00000E00L 33264 #define MMEA5_ADDRNORM_BASE_ADDR4__BASE_ADDR_MASK 0xFFFFF000L 33265 //MMEA5_ADDRNORM_LIMIT_ADDR4 33266 #define MMEA5_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID__SHIFT 0x0 33267 #define MMEA5_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR__SHIFT 0xc 33268 #define MMEA5_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID_MASK 0x0000001FL 33269 #define MMEA5_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR_MASK 0xFFFFF000L 33270 //MMEA5_ADDRNORM_BASE_ADDR5 33271 #define MMEA5_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL__SHIFT 0x0 33272 #define MMEA5_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN__SHIFT 0x1 33273 #define MMEA5_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN__SHIFT 0x2 33274 #define MMEA5_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES__SHIFT 0x6 33275 #define MMEA5_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS__SHIFT 0x8 33276 #define MMEA5_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL__SHIFT 0x9 33277 #define MMEA5_ADDRNORM_BASE_ADDR5__BASE_ADDR__SHIFT 0xc 33278 #define MMEA5_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL_MASK 0x00000001L 33279 #define MMEA5_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 33280 #define MMEA5_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN_MASK 0x0000003CL 33281 #define MMEA5_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES_MASK 0x000000C0L 33282 #define MMEA5_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS_MASK 0x00000100L 33283 #define MMEA5_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL_MASK 0x00000E00L 33284 #define MMEA5_ADDRNORM_BASE_ADDR5__BASE_ADDR_MASK 0xFFFFF000L 33285 //MMEA5_ADDRNORM_LIMIT_ADDR5 33286 #define MMEA5_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID__SHIFT 0x0 33287 #define MMEA5_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR__SHIFT 0xc 33288 #define MMEA5_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID_MASK 0x0000001FL 33289 #define MMEA5_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR_MASK 0xFFFFF000L 33290 //MMEA5_ADDRNORM_OFFSET_ADDR5 33291 #define MMEA5_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN__SHIFT 0x0 33292 #define MMEA5_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET__SHIFT 0x14 33293 #define MMEA5_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN_MASK 0x00000001L 33294 #define MMEA5_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_MASK 0xFFF00000L 33295 //MMEA5_ADDRNORMDRAM_HOLE_CNTL 33296 #define MMEA5_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 33297 #define MMEA5_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 33298 #define MMEA5_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L 33299 #define MMEA5_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L 33300 //MMEA5_ADDRNORMGMI_HOLE_CNTL 33301 #define MMEA5_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 33302 #define MMEA5_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 33303 #define MMEA5_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L 33304 #define MMEA5_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L 33305 //MMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG 33306 #define MMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0 33307 #define MMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6 33308 #define MMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL 33309 #define MMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L 33310 //MMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG 33311 #define MMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT 0x0 33312 #define MMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT 0x6 33313 #define MMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK 0x0000003FL 33314 #define MMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK 0x00000FC0L 33315 //MMEA5_ADDRDEC_BANK_CFG 33316 #define MMEA5_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 33317 #define MMEA5_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x6 33318 #define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xc 33319 #define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xf 33320 #define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x12 33321 #define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x13 33322 #define MMEA5_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000003FL 33323 #define MMEA5_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x00000FC0L 33324 #define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00007000L 33325 #define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x00038000L 33326 #define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00040000L 33327 #define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00080000L 33328 //MMEA5_ADDRDEC_MISC_CFG 33329 #define MMEA5_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 33330 #define MMEA5_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 33331 #define MMEA5_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 33332 #define MMEA5_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 33333 #define MMEA5_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 33334 #define MMEA5_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc 33335 #define MMEA5_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11 33336 #define MMEA5_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16 33337 #define MMEA5_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18 33338 #define MMEA5_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a 33339 #define MMEA5_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d 33340 #define MMEA5_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L 33341 #define MMEA5_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L 33342 #define MMEA5_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L 33343 #define MMEA5_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L 33344 #define MMEA5_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L 33345 #define MMEA5_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L 33346 #define MMEA5_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L 33347 #define MMEA5_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L 33348 #define MMEA5_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L 33349 #define MMEA5_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L 33350 #define MMEA5_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L 33351 //MMEA5_ADDRDECDRAM_ADDR_HASH_BANK0 33352 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 33353 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 33354 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe 33355 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L 33356 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL 33357 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L 33358 //MMEA5_ADDRDECDRAM_ADDR_HASH_BANK1 33359 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 33360 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 33361 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe 33362 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L 33363 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL 33364 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L 33365 //MMEA5_ADDRDECDRAM_ADDR_HASH_BANK2 33366 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 33367 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 33368 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe 33369 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L 33370 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL 33371 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L 33372 //MMEA5_ADDRDECDRAM_ADDR_HASH_BANK3 33373 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 33374 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 33375 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe 33376 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L 33377 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL 33378 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L 33379 //MMEA5_ADDRDECDRAM_ADDR_HASH_BANK4 33380 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 33381 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 33382 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe 33383 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L 33384 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL 33385 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L 33386 //MMEA5_ADDRDECDRAM_ADDR_HASH_BANK5 33387 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT 0x0 33388 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR__SHIFT 0x1 33389 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR__SHIFT 0xe 33390 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE_MASK 0x00000001L 33391 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR_MASK 0x00003FFEL 33392 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR_MASK 0xFFFFC000L 33393 //MMEA5_ADDRDECDRAM_ADDR_HASH_PC 33394 #define MMEA5_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 33395 #define MMEA5_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 33396 #define MMEA5_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe 33397 #define MMEA5_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L 33398 #define MMEA5_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL 33399 #define MMEA5_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L 33400 //MMEA5_ADDRDECDRAM_ADDR_HASH_PC2 33401 #define MMEA5_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 33402 #define MMEA5_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000003FL 33403 //MMEA5_ADDRDECDRAM_ADDR_HASH_CS0 33404 #define MMEA5_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 33405 #define MMEA5_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 33406 #define MMEA5_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L 33407 #define MMEA5_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL 33408 //MMEA5_ADDRDECDRAM_ADDR_HASH_CS1 33409 #define MMEA5_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 33410 #define MMEA5_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 33411 #define MMEA5_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L 33412 #define MMEA5_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL 33413 //MMEA5_ADDRDECDRAM_HARVEST_ENABLE 33414 #define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 33415 #define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 33416 #define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 33417 #define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 33418 #define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 33419 #define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 33420 #define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L 33421 #define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L 33422 #define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L 33423 #define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L 33424 #define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L 33425 #define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L 33426 //MMEA5_ADDRDECGMI_ADDR_HASH_BANK0 33427 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 33428 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 33429 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe 33430 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L 33431 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL 33432 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L 33433 //MMEA5_ADDRDECGMI_ADDR_HASH_BANK1 33434 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 33435 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 33436 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe 33437 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L 33438 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL 33439 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L 33440 //MMEA5_ADDRDECGMI_ADDR_HASH_BANK2 33441 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 33442 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 33443 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe 33444 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L 33445 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL 33446 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L 33447 //MMEA5_ADDRDECGMI_ADDR_HASH_BANK3 33448 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 33449 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 33450 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe 33451 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L 33452 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL 33453 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L 33454 //MMEA5_ADDRDECGMI_ADDR_HASH_BANK4 33455 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 33456 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 33457 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe 33458 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L 33459 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL 33460 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L 33461 //MMEA5_ADDRDECGMI_ADDR_HASH_BANK5 33462 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT 0x0 33463 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR__SHIFT 0x1 33464 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR__SHIFT 0xe 33465 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE_MASK 0x00000001L 33466 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR_MASK 0x00003FFEL 33467 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR_MASK 0xFFFFC000L 33468 //MMEA5_ADDRDECGMI_ADDR_HASH_PC 33469 #define MMEA5_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 33470 #define MMEA5_ADDRDECGMI_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 33471 #define MMEA5_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe 33472 #define MMEA5_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L 33473 #define MMEA5_ADDRDECGMI_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL 33474 #define MMEA5_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L 33475 //MMEA5_ADDRDECGMI_ADDR_HASH_PC2 33476 #define MMEA5_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 33477 #define MMEA5_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000003FL 33478 //MMEA5_ADDRDECGMI_ADDR_HASH_CS0 33479 #define MMEA5_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 33480 #define MMEA5_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 33481 #define MMEA5_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L 33482 #define MMEA5_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL 33483 //MMEA5_ADDRDECGMI_ADDR_HASH_CS1 33484 #define MMEA5_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 33485 #define MMEA5_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 33486 #define MMEA5_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L 33487 #define MMEA5_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL 33488 //MMEA5_ADDRDECGMI_HARVEST_ENABLE 33489 #define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 33490 #define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 33491 #define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 33492 #define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 33493 #define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 33494 #define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 33495 #define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L 33496 #define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L 33497 #define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L 33498 #define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L 33499 #define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L 33500 #define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L 33501 //MMEA5_ADDRDEC0_BASE_ADDR_CS0 33502 #define MMEA5_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 33503 #define MMEA5_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 33504 #define MMEA5_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 33505 #define MMEA5_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 33506 //MMEA5_ADDRDEC0_BASE_ADDR_CS1 33507 #define MMEA5_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 33508 #define MMEA5_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 33509 #define MMEA5_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 33510 #define MMEA5_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 33511 //MMEA5_ADDRDEC0_BASE_ADDR_CS2 33512 #define MMEA5_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 33513 #define MMEA5_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 33514 #define MMEA5_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 33515 #define MMEA5_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 33516 //MMEA5_ADDRDEC0_BASE_ADDR_CS3 33517 #define MMEA5_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 33518 #define MMEA5_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 33519 #define MMEA5_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 33520 #define MMEA5_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 33521 //MMEA5_ADDRDEC0_BASE_ADDR_SECCS0 33522 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 33523 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 33524 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 33525 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 33526 //MMEA5_ADDRDEC0_BASE_ADDR_SECCS1 33527 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 33528 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 33529 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 33530 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 33531 //MMEA5_ADDRDEC0_BASE_ADDR_SECCS2 33532 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 33533 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 33534 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 33535 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 33536 //MMEA5_ADDRDEC0_BASE_ADDR_SECCS3 33537 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 33538 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 33539 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 33540 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 33541 //MMEA5_ADDRDEC0_ADDR_MASK_CS01 33542 #define MMEA5_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 33543 #define MMEA5_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 33544 //MMEA5_ADDRDEC0_ADDR_MASK_CS23 33545 #define MMEA5_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 33546 #define MMEA5_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 33547 //MMEA5_ADDRDEC0_ADDR_MASK_SECCS01 33548 #define MMEA5_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 33549 #define MMEA5_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 33550 //MMEA5_ADDRDEC0_ADDR_MASK_SECCS23 33551 #define MMEA5_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 33552 #define MMEA5_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 33553 //MMEA5_ADDRDEC0_ADDR_CFG_CS01 33554 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 33555 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 33556 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 33557 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 33558 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 33559 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 33560 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 33561 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 33562 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 33563 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 33564 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 33565 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 33566 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 33567 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 33568 //MMEA5_ADDRDEC0_ADDR_CFG_CS23 33569 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 33570 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 33571 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 33572 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 33573 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 33574 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 33575 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 33576 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 33577 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 33578 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 33579 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 33580 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 33581 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 33582 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 33583 //MMEA5_ADDRDEC0_ADDR_SEL_CS01 33584 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 33585 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 33586 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 33587 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc 33588 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 33589 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 33590 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 33591 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 33592 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 33593 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 33594 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 33595 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 33596 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 33597 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 33598 //MMEA5_ADDRDEC0_ADDR_SEL_CS23 33599 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 33600 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 33601 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 33602 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc 33603 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 33604 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 33605 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 33606 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 33607 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 33608 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 33609 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 33610 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 33611 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 33612 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 33613 //MMEA5_ADDRDEC0_ADDR_SEL2_CS01 33614 #define MMEA5_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 33615 #define MMEA5_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 33616 //MMEA5_ADDRDEC0_ADDR_SEL2_CS23 33617 #define MMEA5_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 33618 #define MMEA5_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 33619 //MMEA5_ADDRDEC0_COL_SEL_LO_CS01 33620 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 33621 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 33622 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 33623 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc 33624 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 33625 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 33626 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 33627 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 33628 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 33629 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 33630 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 33631 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 33632 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 33633 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 33634 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 33635 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 33636 //MMEA5_ADDRDEC0_COL_SEL_LO_CS23 33637 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 33638 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 33639 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 33640 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc 33641 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 33642 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 33643 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 33644 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 33645 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 33646 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 33647 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 33648 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 33649 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 33650 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 33651 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 33652 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 33653 //MMEA5_ADDRDEC0_COL_SEL_HI_CS01 33654 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 33655 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 33656 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 33657 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc 33658 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 33659 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 33660 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 33661 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 33662 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 33663 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 33664 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 33665 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 33666 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 33667 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 33668 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 33669 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 33670 //MMEA5_ADDRDEC0_COL_SEL_HI_CS23 33671 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 33672 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 33673 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 33674 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc 33675 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 33676 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 33677 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 33678 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 33679 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 33680 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 33681 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 33682 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 33683 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 33684 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 33685 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 33686 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 33687 //MMEA5_ADDRDEC0_RM_SEL_CS01 33688 #define MMEA5_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 33689 #define MMEA5_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 33690 #define MMEA5_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 33691 #define MMEA5_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 33692 #define MMEA5_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 33693 #define MMEA5_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 33694 #define MMEA5_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL 33695 #define MMEA5_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L 33696 #define MMEA5_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L 33697 #define MMEA5_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 33698 #define MMEA5_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 33699 #define MMEA5_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 33700 //MMEA5_ADDRDEC0_RM_SEL_CS23 33701 #define MMEA5_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 33702 #define MMEA5_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 33703 #define MMEA5_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 33704 #define MMEA5_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 33705 #define MMEA5_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 33706 #define MMEA5_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 33707 #define MMEA5_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL 33708 #define MMEA5_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L 33709 #define MMEA5_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L 33710 #define MMEA5_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 33711 #define MMEA5_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 33712 #define MMEA5_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 33713 //MMEA5_ADDRDEC0_RM_SEL_SECCS01 33714 #define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 33715 #define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 33716 #define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 33717 #define MMEA5_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 33718 #define MMEA5_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 33719 #define MMEA5_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 33720 #define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 33721 #define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 33722 #define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 33723 #define MMEA5_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 33724 #define MMEA5_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 33725 #define MMEA5_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 33726 //MMEA5_ADDRDEC0_RM_SEL_SECCS23 33727 #define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 33728 #define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 33729 #define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 33730 #define MMEA5_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 33731 #define MMEA5_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 33732 #define MMEA5_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 33733 #define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 33734 #define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 33735 #define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 33736 #define MMEA5_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 33737 #define MMEA5_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 33738 #define MMEA5_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 33739 //MMEA5_ADDRDEC1_BASE_ADDR_CS0 33740 #define MMEA5_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 33741 #define MMEA5_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 33742 #define MMEA5_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 33743 #define MMEA5_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 33744 //MMEA5_ADDRDEC1_BASE_ADDR_CS1 33745 #define MMEA5_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 33746 #define MMEA5_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 33747 #define MMEA5_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 33748 #define MMEA5_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 33749 //MMEA5_ADDRDEC1_BASE_ADDR_CS2 33750 #define MMEA5_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 33751 #define MMEA5_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 33752 #define MMEA5_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 33753 #define MMEA5_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 33754 //MMEA5_ADDRDEC1_BASE_ADDR_CS3 33755 #define MMEA5_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 33756 #define MMEA5_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 33757 #define MMEA5_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 33758 #define MMEA5_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 33759 //MMEA5_ADDRDEC1_BASE_ADDR_SECCS0 33760 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 33761 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 33762 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 33763 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 33764 //MMEA5_ADDRDEC1_BASE_ADDR_SECCS1 33765 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 33766 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 33767 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 33768 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 33769 //MMEA5_ADDRDEC1_BASE_ADDR_SECCS2 33770 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 33771 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 33772 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 33773 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 33774 //MMEA5_ADDRDEC1_BASE_ADDR_SECCS3 33775 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 33776 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 33777 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 33778 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 33779 //MMEA5_ADDRDEC1_ADDR_MASK_CS01 33780 #define MMEA5_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 33781 #define MMEA5_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 33782 //MMEA5_ADDRDEC1_ADDR_MASK_CS23 33783 #define MMEA5_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 33784 #define MMEA5_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 33785 //MMEA5_ADDRDEC1_ADDR_MASK_SECCS01 33786 #define MMEA5_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 33787 #define MMEA5_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 33788 //MMEA5_ADDRDEC1_ADDR_MASK_SECCS23 33789 #define MMEA5_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 33790 #define MMEA5_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 33791 //MMEA5_ADDRDEC1_ADDR_CFG_CS01 33792 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 33793 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 33794 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 33795 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 33796 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 33797 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 33798 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 33799 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 33800 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 33801 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 33802 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 33803 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 33804 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 33805 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 33806 //MMEA5_ADDRDEC1_ADDR_CFG_CS23 33807 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 33808 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 33809 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 33810 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 33811 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 33812 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 33813 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 33814 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 33815 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 33816 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 33817 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 33818 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 33819 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 33820 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 33821 //MMEA5_ADDRDEC1_ADDR_SEL_CS01 33822 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 33823 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 33824 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 33825 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc 33826 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 33827 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 33828 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 33829 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 33830 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 33831 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 33832 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 33833 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 33834 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 33835 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 33836 //MMEA5_ADDRDEC1_ADDR_SEL_CS23 33837 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 33838 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 33839 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 33840 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc 33841 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 33842 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 33843 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 33844 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 33845 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 33846 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 33847 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 33848 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 33849 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 33850 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 33851 //MMEA5_ADDRDEC1_ADDR_SEL2_CS01 33852 #define MMEA5_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 33853 #define MMEA5_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 33854 //MMEA5_ADDRDEC1_ADDR_SEL2_CS23 33855 #define MMEA5_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 33856 #define MMEA5_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 33857 //MMEA5_ADDRDEC1_COL_SEL_LO_CS01 33858 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 33859 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 33860 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 33861 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc 33862 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 33863 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 33864 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 33865 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 33866 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 33867 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 33868 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 33869 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 33870 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 33871 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 33872 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 33873 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 33874 //MMEA5_ADDRDEC1_COL_SEL_LO_CS23 33875 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 33876 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 33877 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 33878 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc 33879 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 33880 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 33881 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 33882 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 33883 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 33884 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 33885 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 33886 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 33887 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 33888 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 33889 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 33890 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 33891 //MMEA5_ADDRDEC1_COL_SEL_HI_CS01 33892 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 33893 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 33894 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 33895 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc 33896 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 33897 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 33898 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 33899 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 33900 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 33901 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 33902 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 33903 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 33904 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 33905 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 33906 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 33907 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 33908 //MMEA5_ADDRDEC1_COL_SEL_HI_CS23 33909 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 33910 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 33911 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 33912 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc 33913 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 33914 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 33915 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 33916 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 33917 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 33918 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 33919 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 33920 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 33921 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 33922 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 33923 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 33924 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 33925 //MMEA5_ADDRDEC1_RM_SEL_CS01 33926 #define MMEA5_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 33927 #define MMEA5_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 33928 #define MMEA5_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 33929 #define MMEA5_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 33930 #define MMEA5_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 33931 #define MMEA5_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 33932 #define MMEA5_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL 33933 #define MMEA5_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L 33934 #define MMEA5_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L 33935 #define MMEA5_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 33936 #define MMEA5_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 33937 #define MMEA5_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 33938 //MMEA5_ADDRDEC1_RM_SEL_CS23 33939 #define MMEA5_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 33940 #define MMEA5_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 33941 #define MMEA5_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 33942 #define MMEA5_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 33943 #define MMEA5_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 33944 #define MMEA5_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 33945 #define MMEA5_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL 33946 #define MMEA5_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L 33947 #define MMEA5_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L 33948 #define MMEA5_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 33949 #define MMEA5_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 33950 #define MMEA5_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 33951 //MMEA5_ADDRDEC1_RM_SEL_SECCS01 33952 #define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 33953 #define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 33954 #define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 33955 #define MMEA5_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 33956 #define MMEA5_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 33957 #define MMEA5_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 33958 #define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 33959 #define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 33960 #define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 33961 #define MMEA5_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 33962 #define MMEA5_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 33963 #define MMEA5_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 33964 //MMEA5_ADDRDEC1_RM_SEL_SECCS23 33965 #define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 33966 #define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 33967 #define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 33968 #define MMEA5_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 33969 #define MMEA5_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 33970 #define MMEA5_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 33971 #define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 33972 #define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 33973 #define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 33974 #define MMEA5_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 33975 #define MMEA5_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 33976 #define MMEA5_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 33977 //MMEA5_ADDRDEC2_BASE_ADDR_CS0 33978 #define MMEA5_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 33979 #define MMEA5_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 33980 #define MMEA5_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 33981 #define MMEA5_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 33982 //MMEA5_ADDRDEC2_BASE_ADDR_CS1 33983 #define MMEA5_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 33984 #define MMEA5_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 33985 #define MMEA5_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 33986 #define MMEA5_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 33987 //MMEA5_ADDRDEC2_BASE_ADDR_CS2 33988 #define MMEA5_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 33989 #define MMEA5_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 33990 #define MMEA5_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 33991 #define MMEA5_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 33992 //MMEA5_ADDRDEC2_BASE_ADDR_CS3 33993 #define MMEA5_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 33994 #define MMEA5_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 33995 #define MMEA5_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 33996 #define MMEA5_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 33997 //MMEA5_ADDRDEC2_BASE_ADDR_SECCS0 33998 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 33999 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 34000 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 34001 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 34002 //MMEA5_ADDRDEC2_BASE_ADDR_SECCS1 34003 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 34004 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 34005 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 34006 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 34007 //MMEA5_ADDRDEC2_BASE_ADDR_SECCS2 34008 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 34009 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 34010 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 34011 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 34012 //MMEA5_ADDRDEC2_BASE_ADDR_SECCS3 34013 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 34014 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 34015 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 34016 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 34017 //MMEA5_ADDRDEC2_ADDR_MASK_CS01 34018 #define MMEA5_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 34019 #define MMEA5_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 34020 //MMEA5_ADDRDEC2_ADDR_MASK_CS23 34021 #define MMEA5_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 34022 #define MMEA5_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 34023 //MMEA5_ADDRDEC2_ADDR_MASK_SECCS01 34024 #define MMEA5_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 34025 #define MMEA5_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 34026 //MMEA5_ADDRDEC2_ADDR_MASK_SECCS23 34027 #define MMEA5_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 34028 #define MMEA5_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 34029 //MMEA5_ADDRDEC2_ADDR_CFG_CS01 34030 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 34031 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 34032 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 34033 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 34034 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 34035 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 34036 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 34037 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 34038 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 34039 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 34040 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 34041 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 34042 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 34043 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 34044 //MMEA5_ADDRDEC2_ADDR_CFG_CS23 34045 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 34046 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 34047 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 34048 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 34049 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 34050 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 34051 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 34052 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 34053 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 34054 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 34055 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 34056 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 34057 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 34058 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 34059 //MMEA5_ADDRDEC2_ADDR_SEL_CS01 34060 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT 0x0 34061 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT 0x4 34062 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT 0x8 34063 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT 0xc 34064 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT 0x10 34065 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 34066 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 34067 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 34068 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 34069 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 34070 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 34071 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 34072 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 34073 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 34074 //MMEA5_ADDRDEC2_ADDR_SEL_CS23 34075 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT 0x0 34076 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT 0x4 34077 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT 0x8 34078 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT 0xc 34079 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT 0x10 34080 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 34081 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 34082 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 34083 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 34084 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 34085 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 34086 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 34087 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 34088 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 34089 //MMEA5_ADDRDEC2_ADDR_SEL2_CS01 34090 #define MMEA5_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 34091 #define MMEA5_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 34092 //MMEA5_ADDRDEC2_ADDR_SEL2_CS23 34093 #define MMEA5_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 34094 #define MMEA5_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 34095 //MMEA5_ADDRDEC2_COL_SEL_LO_CS01 34096 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT 0x0 34097 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT 0x4 34098 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT 0x8 34099 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT 0xc 34100 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT 0x10 34101 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT 0x14 34102 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT 0x18 34103 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 34104 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 34105 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 34106 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 34107 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 34108 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 34109 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 34110 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 34111 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 34112 //MMEA5_ADDRDEC2_COL_SEL_LO_CS23 34113 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT 0x0 34114 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT 0x4 34115 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT 0x8 34116 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT 0xc 34117 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT 0x10 34118 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT 0x14 34119 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT 0x18 34120 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 34121 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 34122 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 34123 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 34124 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 34125 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 34126 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 34127 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 34128 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 34129 //MMEA5_ADDRDEC2_COL_SEL_HI_CS01 34130 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT 0x0 34131 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT 0x4 34132 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT 0x8 34133 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT 0xc 34134 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT 0x10 34135 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT 0x14 34136 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT 0x18 34137 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 34138 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 34139 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 34140 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 34141 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 34142 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 34143 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 34144 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 34145 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 34146 //MMEA5_ADDRDEC2_COL_SEL_HI_CS23 34147 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT 0x0 34148 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT 0x4 34149 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT 0x8 34150 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT 0xc 34151 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT 0x10 34152 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT 0x14 34153 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT 0x18 34154 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 34155 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 34156 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 34157 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 34158 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 34159 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 34160 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 34161 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 34162 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 34163 //MMEA5_ADDRDEC2_RM_SEL_CS01 34164 #define MMEA5_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT 0x0 34165 #define MMEA5_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT 0x4 34166 #define MMEA5_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT 0x8 34167 #define MMEA5_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 34168 #define MMEA5_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 34169 #define MMEA5_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 34170 #define MMEA5_ADDRDEC2_RM_SEL_CS01__RM0_MASK 0x0000000FL 34171 #define MMEA5_ADDRDEC2_RM_SEL_CS01__RM1_MASK 0x000000F0L 34172 #define MMEA5_ADDRDEC2_RM_SEL_CS01__RM2_MASK 0x00000F00L 34173 #define MMEA5_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 34174 #define MMEA5_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 34175 #define MMEA5_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 34176 //MMEA5_ADDRDEC2_RM_SEL_CS23 34177 #define MMEA5_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT 0x0 34178 #define MMEA5_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT 0x4 34179 #define MMEA5_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT 0x8 34180 #define MMEA5_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 34181 #define MMEA5_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 34182 #define MMEA5_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 34183 #define MMEA5_ADDRDEC2_RM_SEL_CS23__RM0_MASK 0x0000000FL 34184 #define MMEA5_ADDRDEC2_RM_SEL_CS23__RM1_MASK 0x000000F0L 34185 #define MMEA5_ADDRDEC2_RM_SEL_CS23__RM2_MASK 0x00000F00L 34186 #define MMEA5_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 34187 #define MMEA5_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 34188 #define MMEA5_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 34189 //MMEA5_ADDRDEC2_RM_SEL_SECCS01 34190 #define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT 0x0 34191 #define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT 0x4 34192 #define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT 0x8 34193 #define MMEA5_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 34194 #define MMEA5_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 34195 #define MMEA5_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 34196 #define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 34197 #define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 34198 #define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 34199 #define MMEA5_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 34200 #define MMEA5_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 34201 #define MMEA5_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 34202 //MMEA5_ADDRDEC2_RM_SEL_SECCS23 34203 #define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT 0x0 34204 #define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT 0x4 34205 #define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT 0x8 34206 #define MMEA5_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 34207 #define MMEA5_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 34208 #define MMEA5_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 34209 #define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 34210 #define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 34211 #define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 34212 #define MMEA5_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 34213 #define MMEA5_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 34214 #define MMEA5_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 34215 //MMEA5_ADDRNORMDRAM_GLOBAL_CNTL 34216 #define MMEA5_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT 0x14 34217 #define MMEA5_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT 0x15 34218 #define MMEA5_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT 0x16 34219 #define MMEA5_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK 0x00100000L 34220 #define MMEA5_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK 0x00200000L 34221 #define MMEA5_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK 0x00400000L 34222 //MMEA5_ADDRNORMGMI_GLOBAL_CNTL 34223 #define MMEA5_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT 0x14 34224 #define MMEA5_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT 0x15 34225 #define MMEA5_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT 0x16 34226 #define MMEA5_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK 0x00100000L 34227 #define MMEA5_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK 0x00200000L 34228 #define MMEA5_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK 0x00400000L 34229 //MMEA5_IO_RD_CLI2GRP_MAP0 34230 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 34231 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 34232 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 34233 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 34234 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 34235 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 34236 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 34237 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 34238 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 34239 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 34240 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 34241 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 34242 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 34243 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 34244 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 34245 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 34246 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 34247 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 34248 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 34249 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 34250 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 34251 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 34252 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 34253 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 34254 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 34255 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 34256 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 34257 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 34258 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 34259 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 34260 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 34261 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 34262 //MMEA5_IO_RD_CLI2GRP_MAP1 34263 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 34264 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 34265 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 34266 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 34267 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 34268 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 34269 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 34270 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 34271 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 34272 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 34273 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 34274 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 34275 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 34276 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 34277 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 34278 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 34279 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 34280 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 34281 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 34282 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 34283 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 34284 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 34285 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 34286 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 34287 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 34288 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 34289 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 34290 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 34291 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 34292 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 34293 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 34294 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 34295 //MMEA5_IO_WR_CLI2GRP_MAP0 34296 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 34297 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 34298 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 34299 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 34300 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 34301 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 34302 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 34303 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 34304 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 34305 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 34306 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 34307 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 34308 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 34309 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 34310 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 34311 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 34312 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 34313 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 34314 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 34315 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 34316 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 34317 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 34318 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 34319 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 34320 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 34321 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 34322 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 34323 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 34324 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 34325 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 34326 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 34327 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 34328 //MMEA5_IO_WR_CLI2GRP_MAP1 34329 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 34330 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 34331 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 34332 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 34333 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 34334 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 34335 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 34336 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 34337 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 34338 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 34339 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 34340 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 34341 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 34342 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 34343 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 34344 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 34345 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 34346 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 34347 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 34348 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 34349 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 34350 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 34351 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 34352 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 34353 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 34354 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 34355 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 34356 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 34357 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 34358 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 34359 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 34360 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 34361 //MMEA5_IO_RD_COMBINE_FLUSH 34362 #define MMEA5_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 34363 #define MMEA5_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 34364 #define MMEA5_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 34365 #define MMEA5_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 34366 #define MMEA5_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT 0x10 34367 #define MMEA5_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 34368 #define MMEA5_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 34369 #define MMEA5_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 34370 #define MMEA5_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 34371 #define MMEA5_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK 0x00010000L 34372 //MMEA5_IO_WR_COMBINE_FLUSH 34373 #define MMEA5_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 34374 #define MMEA5_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 34375 #define MMEA5_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 34376 #define MMEA5_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 34377 #define MMEA5_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT 0x10 34378 #define MMEA5_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 34379 #define MMEA5_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 34380 #define MMEA5_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 34381 #define MMEA5_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 34382 #define MMEA5_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK 0x00010000L 34383 //MMEA5_IO_GROUP_BURST 34384 #define MMEA5_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 34385 #define MMEA5_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 34386 #define MMEA5_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 34387 #define MMEA5_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 34388 #define MMEA5_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL 34389 #define MMEA5_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 34390 #define MMEA5_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 34391 #define MMEA5_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L 34392 //MMEA5_IO_RD_PRI_AGE 34393 #define MMEA5_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 34394 #define MMEA5_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 34395 #define MMEA5_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 34396 #define MMEA5_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 34397 #define MMEA5_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 34398 #define MMEA5_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 34399 #define MMEA5_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 34400 #define MMEA5_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 34401 #define MMEA5_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 34402 #define MMEA5_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 34403 #define MMEA5_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 34404 #define MMEA5_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 34405 #define MMEA5_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 34406 #define MMEA5_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 34407 #define MMEA5_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 34408 #define MMEA5_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 34409 //MMEA5_IO_WR_PRI_AGE 34410 #define MMEA5_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 34411 #define MMEA5_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 34412 #define MMEA5_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 34413 #define MMEA5_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 34414 #define MMEA5_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 34415 #define MMEA5_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 34416 #define MMEA5_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 34417 #define MMEA5_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 34418 #define MMEA5_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 34419 #define MMEA5_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 34420 #define MMEA5_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 34421 #define MMEA5_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 34422 #define MMEA5_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 34423 #define MMEA5_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 34424 #define MMEA5_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 34425 #define MMEA5_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 34426 //MMEA5_IO_RD_PRI_QUEUING 34427 #define MMEA5_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 34428 #define MMEA5_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 34429 #define MMEA5_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 34430 #define MMEA5_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 34431 #define MMEA5_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 34432 #define MMEA5_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 34433 #define MMEA5_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 34434 #define MMEA5_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 34435 //MMEA5_IO_WR_PRI_QUEUING 34436 #define MMEA5_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 34437 #define MMEA5_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 34438 #define MMEA5_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 34439 #define MMEA5_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 34440 #define MMEA5_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 34441 #define MMEA5_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 34442 #define MMEA5_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 34443 #define MMEA5_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 34444 //MMEA5_IO_RD_PRI_FIXED 34445 #define MMEA5_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 34446 #define MMEA5_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 34447 #define MMEA5_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 34448 #define MMEA5_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 34449 #define MMEA5_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 34450 #define MMEA5_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 34451 #define MMEA5_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 34452 #define MMEA5_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 34453 //MMEA5_IO_WR_PRI_FIXED 34454 #define MMEA5_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 34455 #define MMEA5_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 34456 #define MMEA5_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 34457 #define MMEA5_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 34458 #define MMEA5_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 34459 #define MMEA5_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 34460 #define MMEA5_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 34461 #define MMEA5_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 34462 //MMEA5_IO_RD_PRI_URGENCY 34463 #define MMEA5_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 34464 #define MMEA5_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 34465 #define MMEA5_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 34466 #define MMEA5_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 34467 #define MMEA5_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 34468 #define MMEA5_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 34469 #define MMEA5_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 34470 #define MMEA5_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 34471 #define MMEA5_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 34472 #define MMEA5_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 34473 #define MMEA5_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 34474 #define MMEA5_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 34475 #define MMEA5_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 34476 #define MMEA5_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 34477 #define MMEA5_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 34478 #define MMEA5_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 34479 //MMEA5_IO_WR_PRI_URGENCY 34480 #define MMEA5_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 34481 #define MMEA5_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 34482 #define MMEA5_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 34483 #define MMEA5_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 34484 #define MMEA5_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 34485 #define MMEA5_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 34486 #define MMEA5_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 34487 #define MMEA5_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 34488 #define MMEA5_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 34489 #define MMEA5_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 34490 #define MMEA5_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 34491 #define MMEA5_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 34492 #define MMEA5_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 34493 #define MMEA5_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 34494 #define MMEA5_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 34495 #define MMEA5_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 34496 //MMEA5_IO_RD_PRI_URGENCY_MASKING 34497 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 34498 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 34499 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 34500 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 34501 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 34502 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 34503 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 34504 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 34505 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 34506 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 34507 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 34508 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 34509 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 34510 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 34511 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 34512 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 34513 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 34514 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 34515 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 34516 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 34517 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 34518 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 34519 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 34520 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 34521 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 34522 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 34523 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 34524 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 34525 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 34526 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 34527 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 34528 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 34529 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 34530 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 34531 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 34532 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 34533 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 34534 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 34535 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 34536 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 34537 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 34538 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 34539 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 34540 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 34541 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 34542 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 34543 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 34544 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 34545 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 34546 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 34547 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 34548 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 34549 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 34550 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 34551 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 34552 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 34553 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 34554 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 34555 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 34556 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 34557 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 34558 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 34559 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 34560 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 34561 //MMEA5_IO_WR_PRI_URGENCY_MASKING 34562 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 34563 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 34564 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 34565 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 34566 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 34567 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 34568 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 34569 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 34570 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 34571 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 34572 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 34573 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 34574 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 34575 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 34576 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 34577 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 34578 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 34579 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 34580 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 34581 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 34582 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 34583 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 34584 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 34585 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 34586 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 34587 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 34588 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 34589 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 34590 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 34591 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 34592 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 34593 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 34594 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 34595 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 34596 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 34597 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 34598 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 34599 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 34600 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 34601 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 34602 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 34603 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 34604 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 34605 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 34606 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 34607 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 34608 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 34609 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 34610 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 34611 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 34612 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 34613 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 34614 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 34615 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 34616 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 34617 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 34618 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 34619 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 34620 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 34621 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 34622 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 34623 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 34624 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 34625 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 34626 //MMEA5_IO_RD_PRI_QUANT_PRI1 34627 #define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 34628 #define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 34629 #define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 34630 #define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 34631 #define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 34632 #define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 34633 #define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 34634 #define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 34635 //MMEA5_IO_RD_PRI_QUANT_PRI2 34636 #define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 34637 #define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 34638 #define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 34639 #define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 34640 #define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 34641 #define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 34642 #define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 34643 #define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 34644 //MMEA5_IO_RD_PRI_QUANT_PRI3 34645 #define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 34646 #define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 34647 #define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 34648 #define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 34649 #define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 34650 #define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 34651 #define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 34652 #define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 34653 //MMEA5_IO_WR_PRI_QUANT_PRI1 34654 #define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 34655 #define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 34656 #define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 34657 #define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 34658 #define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 34659 #define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 34660 #define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 34661 #define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 34662 //MMEA5_IO_WR_PRI_QUANT_PRI2 34663 #define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 34664 #define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 34665 #define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 34666 #define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 34667 #define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 34668 #define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 34669 #define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 34670 #define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 34671 //MMEA5_IO_WR_PRI_QUANT_PRI3 34672 #define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 34673 #define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 34674 #define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 34675 #define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 34676 #define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 34677 #define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 34678 #define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 34679 #define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 34680 //MMEA5_SDP_ARB_DRAM 34681 #define MMEA5_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 34682 #define MMEA5_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 34683 #define MMEA5_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 34684 #define MMEA5_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 34685 #define MMEA5_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 34686 #define MMEA5_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 34687 #define MMEA5_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 34688 #define MMEA5_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 34689 #define MMEA5_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL 34690 #define MMEA5_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L 34691 #define MMEA5_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L 34692 #define MMEA5_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L 34693 #define MMEA5_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L 34694 #define MMEA5_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L 34695 #define MMEA5_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L 34696 #define MMEA5_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L 34697 //MMEA5_SDP_ARB_GMI 34698 #define MMEA5_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 34699 #define MMEA5_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 34700 #define MMEA5_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT 0x10 34701 #define MMEA5_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT 0x11 34702 #define MMEA5_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT 0x12 34703 #define MMEA5_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT 0x13 34704 #define MMEA5_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT 0x14 34705 #define MMEA5_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 34706 #define MMEA5_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT 0x16 34707 #define MMEA5_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL 34708 #define MMEA5_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L 34709 #define MMEA5_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK 0x00010000L 34710 #define MMEA5_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK 0x00020000L 34711 #define MMEA5_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK 0x00040000L 34712 #define MMEA5_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK 0x00080000L 34713 #define MMEA5_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK 0x00100000L 34714 #define MMEA5_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L 34715 #define MMEA5_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK 0x00400000L 34716 //MMEA5_SDP_ARB_FINAL 34717 #define MMEA5_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 34718 #define MMEA5_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 34719 #define MMEA5_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa 34720 #define MMEA5_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf 34721 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 34722 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 34723 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 34724 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 34725 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 34726 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 34727 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 34728 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 34729 #define MMEA5_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 34730 #define MMEA5_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a 34731 #define MMEA5_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1b 34732 #define MMEA5_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL 34733 #define MMEA5_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L 34734 #define MMEA5_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L 34735 #define MMEA5_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L 34736 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L 34737 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L 34738 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L 34739 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L 34740 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L 34741 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L 34742 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L 34743 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L 34744 #define MMEA5_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L 34745 #define MMEA5_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L 34746 #define MMEA5_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x08000000L 34747 //MMEA5_SDP_DRAM_PRIORITY 34748 #define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 34749 #define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 34750 #define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 34751 #define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 34752 #define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 34753 #define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 34754 #define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 34755 #define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 34756 #define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 34757 #define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 34758 #define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 34759 #define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 34760 #define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 34761 #define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 34762 #define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 34763 #define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 34764 //MMEA5_SDP_GMI_PRIORITY 34765 #define MMEA5_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 34766 #define MMEA5_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 34767 #define MMEA5_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 34768 #define MMEA5_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 34769 #define MMEA5_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 34770 #define MMEA5_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 34771 #define MMEA5_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 34772 #define MMEA5_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 34773 #define MMEA5_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 34774 #define MMEA5_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 34775 #define MMEA5_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 34776 #define MMEA5_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 34777 #define MMEA5_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 34778 #define MMEA5_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 34779 #define MMEA5_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 34780 #define MMEA5_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 34781 //MMEA5_SDP_IO_PRIORITY 34782 #define MMEA5_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 34783 #define MMEA5_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 34784 #define MMEA5_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 34785 #define MMEA5_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 34786 #define MMEA5_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 34787 #define MMEA5_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 34788 #define MMEA5_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 34789 #define MMEA5_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 34790 #define MMEA5_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 34791 #define MMEA5_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 34792 #define MMEA5_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 34793 #define MMEA5_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 34794 #define MMEA5_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 34795 #define MMEA5_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 34796 #define MMEA5_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 34797 #define MMEA5_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 34798 //MMEA5_SDP_CREDITS 34799 #define MMEA5_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 34800 #define MMEA5_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 34801 #define MMEA5_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 34802 #define MMEA5_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL 34803 #define MMEA5_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L 34804 #define MMEA5_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L 34805 //MMEA5_SDP_TAG_RESERVE0 34806 #define MMEA5_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 34807 #define MMEA5_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 34808 #define MMEA5_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 34809 #define MMEA5_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 34810 #define MMEA5_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL 34811 #define MMEA5_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L 34812 #define MMEA5_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L 34813 #define MMEA5_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L 34814 //MMEA5_SDP_TAG_RESERVE1 34815 #define MMEA5_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 34816 #define MMEA5_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 34817 #define MMEA5_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 34818 #define MMEA5_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 34819 #define MMEA5_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL 34820 #define MMEA5_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L 34821 #define MMEA5_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L 34822 #define MMEA5_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L 34823 //MMEA5_SDP_VCC_RESERVE0 34824 #define MMEA5_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 34825 #define MMEA5_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 34826 #define MMEA5_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc 34827 #define MMEA5_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 34828 #define MMEA5_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 34829 #define MMEA5_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 34830 #define MMEA5_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 34831 #define MMEA5_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 34832 #define MMEA5_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 34833 #define MMEA5_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 34834 //MMEA5_SDP_VCC_RESERVE1 34835 #define MMEA5_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 34836 #define MMEA5_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 34837 #define MMEA5_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc 34838 #define MMEA5_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 34839 #define MMEA5_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 34840 #define MMEA5_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 34841 #define MMEA5_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 34842 #define MMEA5_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 34843 //MMEA5_SDP_VCD_RESERVE0 34844 #define MMEA5_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 34845 #define MMEA5_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 34846 #define MMEA5_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc 34847 #define MMEA5_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 34848 #define MMEA5_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 34849 #define MMEA5_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 34850 #define MMEA5_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 34851 #define MMEA5_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 34852 #define MMEA5_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 34853 #define MMEA5_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 34854 //MMEA5_SDP_VCD_RESERVE1 34855 #define MMEA5_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 34856 #define MMEA5_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 34857 #define MMEA5_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc 34858 #define MMEA5_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 34859 #define MMEA5_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 34860 #define MMEA5_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 34861 #define MMEA5_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 34862 #define MMEA5_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 34863 //MMEA5_SDP_REQ_CNTL 34864 #define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 34865 #define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 34866 #define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 34867 #define MMEA5_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 34868 #define MMEA5_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 34869 #define MMEA5_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 34870 #define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L 34871 #define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L 34872 #define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L 34873 #define MMEA5_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L 34874 #define MMEA5_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L 34875 #define MMEA5_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L 34876 //MMEA5_MISC 34877 #define MMEA5_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 34878 #define MMEA5_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 34879 #define MMEA5_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 34880 #define MMEA5_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 34881 #define MMEA5_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 34882 #define MMEA5_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 34883 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 34884 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 34885 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 34886 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 34887 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa 34888 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb 34889 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc 34890 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd 34891 #define MMEA5_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe 34892 #define MMEA5_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf 34893 #define MMEA5_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 34894 #define MMEA5_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 34895 #define MMEA5_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 34896 #define MMEA5_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a 34897 #define MMEA5_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b 34898 #define MMEA5_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c 34899 #define MMEA5_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d 34900 #define MMEA5_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e 34901 #define MMEA5_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f 34902 #define MMEA5_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L 34903 #define MMEA5_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L 34904 #define MMEA5_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L 34905 #define MMEA5_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L 34906 #define MMEA5_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L 34907 #define MMEA5_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L 34908 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L 34909 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L 34910 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L 34911 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L 34912 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L 34913 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L 34914 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L 34915 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L 34916 #define MMEA5_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L 34917 #define MMEA5_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L 34918 #define MMEA5_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L 34919 #define MMEA5_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L 34920 #define MMEA5_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L 34921 #define MMEA5_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L 34922 #define MMEA5_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L 34923 #define MMEA5_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L 34924 #define MMEA5_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L 34925 #define MMEA5_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L 34926 #define MMEA5_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L 34927 //MMEA5_LATENCY_SAMPLING 34928 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 34929 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 34930 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 34931 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 34932 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 34933 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 34934 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 34935 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 34936 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 34937 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 34938 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa 34939 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb 34940 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc 34941 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd 34942 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe 34943 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 34944 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L 34945 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L 34946 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L 34947 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L 34948 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L 34949 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L 34950 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L 34951 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L 34952 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L 34953 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L 34954 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L 34955 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L 34956 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L 34957 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L 34958 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L 34959 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L 34960 //MMEA5_PERFCOUNTER_LO 34961 #define MMEA5_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 34962 #define MMEA5_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 34963 //MMEA5_PERFCOUNTER_HI 34964 #define MMEA5_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 34965 #define MMEA5_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 34966 #define MMEA5_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 34967 #define MMEA5_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 34968 //MMEA5_PERFCOUNTER0_CFG 34969 #define MMEA5_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 34970 #define MMEA5_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 34971 #define MMEA5_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 34972 #define MMEA5_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 34973 #define MMEA5_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 34974 #define MMEA5_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 34975 #define MMEA5_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 34976 #define MMEA5_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 34977 #define MMEA5_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 34978 #define MMEA5_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 34979 //MMEA5_PERFCOUNTER1_CFG 34980 #define MMEA5_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 34981 #define MMEA5_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 34982 #define MMEA5_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 34983 #define MMEA5_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 34984 #define MMEA5_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 34985 #define MMEA5_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 34986 #define MMEA5_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 34987 #define MMEA5_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 34988 #define MMEA5_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 34989 #define MMEA5_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 34990 //MMEA5_PERFCOUNTER_RSLT_CNTL 34991 #define MMEA5_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 34992 #define MMEA5_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 34993 #define MMEA5_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 34994 #define MMEA5_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 34995 #define MMEA5_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 34996 #define MMEA5_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 34997 #define MMEA5_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 34998 #define MMEA5_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 34999 #define MMEA5_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 35000 #define MMEA5_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 35001 #define MMEA5_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 35002 #define MMEA5_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 35003 //MMEA5_EDC_CNT 35004 #define MMEA5_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 35005 #define MMEA5_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 35006 #define MMEA5_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 35007 #define MMEA5_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 35008 #define MMEA5_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 35009 #define MMEA5_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa 35010 #define MMEA5_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc 35011 #define MMEA5_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe 35012 #define MMEA5_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 35013 #define MMEA5_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 35014 #define MMEA5_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 35015 #define MMEA5_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 35016 #define MMEA5_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 35017 #define MMEA5_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a 35018 #define MMEA5_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c 35019 #define MMEA5_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 35020 #define MMEA5_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 35021 #define MMEA5_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 35022 #define MMEA5_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 35023 #define MMEA5_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 35024 #define MMEA5_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 35025 #define MMEA5_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L 35026 #define MMEA5_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L 35027 #define MMEA5_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L 35028 #define MMEA5_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L 35029 #define MMEA5_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L 35030 #define MMEA5_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L 35031 #define MMEA5_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L 35032 #define MMEA5_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L 35033 #define MMEA5_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L 35034 //MMEA5_EDC_CNT2 35035 #define MMEA5_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 35036 #define MMEA5_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 35037 #define MMEA5_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 35038 #define MMEA5_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 35039 #define MMEA5_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 35040 #define MMEA5_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa 35041 #define MMEA5_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc 35042 #define MMEA5_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe 35043 #define MMEA5_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10 35044 #define MMEA5_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12 35045 #define MMEA5_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14 35046 #define MMEA5_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16 35047 #define MMEA5_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT 0x18 35048 #define MMEA5_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT 0x1a 35049 #define MMEA5_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT 0x1c 35050 #define MMEA5_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT 0x1e 35051 #define MMEA5_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 35052 #define MMEA5_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 35053 #define MMEA5_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 35054 #define MMEA5_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 35055 #define MMEA5_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 35056 #define MMEA5_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 35057 #define MMEA5_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L 35058 #define MMEA5_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L 35059 #define MMEA5_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L 35060 #define MMEA5_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L 35061 #define MMEA5_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L 35062 #define MMEA5_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L 35063 #define MMEA5_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK 0x03000000L 35064 #define MMEA5_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK 0x0C000000L 35065 #define MMEA5_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK 0x30000000L 35066 #define MMEA5_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK 0xC0000000L 35067 //MMEA5_DSM_CNTL 35068 #define MMEA5_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 35069 #define MMEA5_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 35070 #define MMEA5_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 35071 #define MMEA5_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 35072 #define MMEA5_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 35073 #define MMEA5_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 35074 #define MMEA5_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 35075 #define MMEA5_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 35076 #define MMEA5_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 35077 #define MMEA5_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 35078 #define MMEA5_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 35079 #define MMEA5_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 35080 #define MMEA5_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 35081 #define MMEA5_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 35082 #define MMEA5_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 35083 #define MMEA5_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 35084 #define MMEA5_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 35085 #define MMEA5_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 35086 #define MMEA5_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 35087 #define MMEA5_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 35088 #define MMEA5_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 35089 #define MMEA5_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 35090 #define MMEA5_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 35091 #define MMEA5_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 35092 #define MMEA5_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 35093 #define MMEA5_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 35094 #define MMEA5_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 35095 #define MMEA5_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 35096 #define MMEA5_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 35097 #define MMEA5_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 35098 #define MMEA5_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L 35099 #define MMEA5_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L 35100 //MMEA5_DSM_CNTLA 35101 #define MMEA5_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 35102 #define MMEA5_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 35103 #define MMEA5_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 35104 #define MMEA5_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 35105 #define MMEA5_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 35106 #define MMEA5_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 35107 #define MMEA5_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 35108 #define MMEA5_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 35109 #define MMEA5_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 35110 #define MMEA5_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 35111 #define MMEA5_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 35112 #define MMEA5_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 35113 #define MMEA5_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 35114 #define MMEA5_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 35115 #define MMEA5_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 35116 #define MMEA5_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 35117 #define MMEA5_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 35118 #define MMEA5_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 35119 #define MMEA5_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 35120 #define MMEA5_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 35121 #define MMEA5_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 35122 #define MMEA5_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 35123 #define MMEA5_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 35124 #define MMEA5_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 35125 #define MMEA5_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 35126 #define MMEA5_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 35127 #define MMEA5_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 35128 #define MMEA5_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 35129 //MMEA5_DSM_CNTL2 35130 #define MMEA5_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 35131 #define MMEA5_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 35132 #define MMEA5_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 35133 #define MMEA5_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 35134 #define MMEA5_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 35135 #define MMEA5_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 35136 #define MMEA5_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 35137 #define MMEA5_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb 35138 #define MMEA5_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 35139 #define MMEA5_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe 35140 #define MMEA5_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 35141 #define MMEA5_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 35142 #define MMEA5_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 35143 #define MMEA5_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 35144 #define MMEA5_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 35145 #define MMEA5_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 35146 #define MMEA5_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a 35147 #define MMEA5_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 35148 #define MMEA5_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 35149 #define MMEA5_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 35150 #define MMEA5_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 35151 #define MMEA5_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 35152 #define MMEA5_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 35153 #define MMEA5_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 35154 #define MMEA5_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 35155 #define MMEA5_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 35156 #define MMEA5_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 35157 #define MMEA5_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 35158 #define MMEA5_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 35159 #define MMEA5_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 35160 #define MMEA5_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 35161 #define MMEA5_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L 35162 #define MMEA5_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L 35163 #define MMEA5_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L 35164 //MMEA5_DSM_CNTL2A 35165 #define MMEA5_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 35166 #define MMEA5_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 35167 #define MMEA5_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 35168 #define MMEA5_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 35169 #define MMEA5_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 35170 #define MMEA5_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 35171 #define MMEA5_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 35172 #define MMEA5_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb 35173 #define MMEA5_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 35174 #define MMEA5_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe 35175 #define MMEA5_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 35176 #define MMEA5_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 35177 #define MMEA5_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 35178 #define MMEA5_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 35179 #define MMEA5_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 35180 #define MMEA5_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 35181 #define MMEA5_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 35182 #define MMEA5_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 35183 #define MMEA5_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 35184 #define MMEA5_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 35185 #define MMEA5_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 35186 #define MMEA5_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 35187 #define MMEA5_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 35188 #define MMEA5_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 35189 #define MMEA5_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 35190 #define MMEA5_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 35191 #define MMEA5_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 35192 #define MMEA5_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 35193 //MMEA5_CGTT_CLK_CTRL 35194 #define MMEA5_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 35195 #define MMEA5_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 35196 #define MMEA5_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc 35197 #define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 35198 #define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 35199 #define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 35200 #define MMEA5_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 35201 #define MMEA5_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 35202 #define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c 35203 #define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d 35204 #define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e 35205 #define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f 35206 #define MMEA5_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 35207 #define MMEA5_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 35208 #define MMEA5_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L 35209 #define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L 35210 #define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L 35211 #define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L 35212 #define MMEA5_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L 35213 #define MMEA5_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 35214 #define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L 35215 #define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L 35216 #define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L 35217 #define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L 35218 //MMEA5_EDC_MODE 35219 #define MMEA5_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 35220 #define MMEA5_EDC_MODE__GATE_FUE__SHIFT 0x11 35221 #define MMEA5_EDC_MODE__DED_MODE__SHIFT 0x14 35222 #define MMEA5_EDC_MODE__PROP_FED__SHIFT 0x1d 35223 #define MMEA5_EDC_MODE__BYPASS__SHIFT 0x1f 35224 #define MMEA5_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L 35225 #define MMEA5_EDC_MODE__GATE_FUE_MASK 0x00020000L 35226 #define MMEA5_EDC_MODE__DED_MODE_MASK 0x00300000L 35227 #define MMEA5_EDC_MODE__PROP_FED_MASK 0x20000000L 35228 #define MMEA5_EDC_MODE__BYPASS_MASK 0x80000000L 35229 //MMEA5_ERR_STATUS 35230 #define MMEA5_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 35231 #define MMEA5_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 35232 #define MMEA5_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 35233 #define MMEA5_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa 35234 #define MMEA5_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb 35235 #define MMEA5_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc 35236 #define MMEA5_ERR_STATUS__FUE_FLAG__SHIFT 0xd 35237 #define MMEA5_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL 35238 #define MMEA5_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L 35239 #define MMEA5_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L 35240 #define MMEA5_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L 35241 #define MMEA5_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L 35242 #define MMEA5_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L 35243 #define MMEA5_ERR_STATUS__FUE_FLAG_MASK 0x00002000L 35244 //MMEA5_MISC2 35245 #define MMEA5_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 35246 #define MMEA5_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 35247 #define MMEA5_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 35248 #define MMEA5_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 35249 #define MMEA5_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc 35250 #define MMEA5_MISC2__RRET_SWAP_MODE__SHIFT 0xd 35251 #define MMEA5_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L 35252 #define MMEA5_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L 35253 #define MMEA5_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL 35254 #define MMEA5_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L 35255 #define MMEA5_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L 35256 #define MMEA5_MISC2__RRET_SWAP_MODE_MASK 0x00002000L 35257 //MMEA5_ADDRDEC_SELECT 35258 #define MMEA5_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0 35259 #define MMEA5_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5 35260 #define MMEA5_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa 35261 #define MMEA5_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf 35262 #define MMEA5_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL 35263 #define MMEA5_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L 35264 #define MMEA5_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L 35265 #define MMEA5_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L 35266 //MMEA5_EDC_CNT3 35267 #define MMEA5_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0 35268 #define MMEA5_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2 35269 #define MMEA5_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4 35270 #define MMEA5_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6 35271 #define MMEA5_EDC_CNT3__IOWR_DATAMEM_DED_COUNT__SHIFT 0x8 35272 #define MMEA5_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0xa 35273 #define MMEA5_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xc 35274 #define MMEA5_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L 35275 #define MMEA5_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL 35276 #define MMEA5_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L 35277 #define MMEA5_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 35278 #define MMEA5_EDC_CNT3__IOWR_DATAMEM_DED_COUNT_MASK 0x00000300L 35279 #define MMEA5_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000C00L 35280 #define MMEA5_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00003000L 35281 35282 35283 // addressBlock: mmhub_ea_mmeadec6 35284 //MMEA6_DRAM_RD_CLI2GRP_MAP0 35285 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 35286 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 35287 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 35288 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 35289 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 35290 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 35291 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 35292 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 35293 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 35294 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 35295 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 35296 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 35297 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 35298 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 35299 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 35300 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 35301 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 35302 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 35303 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 35304 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 35305 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 35306 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 35307 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 35308 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 35309 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 35310 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 35311 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 35312 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 35313 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 35314 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 35315 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 35316 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 35317 //MMEA6_DRAM_RD_CLI2GRP_MAP1 35318 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 35319 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 35320 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 35321 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 35322 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 35323 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 35324 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 35325 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 35326 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 35327 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 35328 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 35329 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 35330 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 35331 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 35332 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 35333 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 35334 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 35335 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 35336 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 35337 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 35338 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 35339 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 35340 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 35341 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 35342 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 35343 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 35344 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 35345 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 35346 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 35347 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 35348 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 35349 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 35350 //MMEA6_DRAM_WR_CLI2GRP_MAP0 35351 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 35352 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 35353 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 35354 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 35355 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 35356 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 35357 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 35358 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 35359 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 35360 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 35361 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 35362 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 35363 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 35364 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 35365 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 35366 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 35367 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 35368 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 35369 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 35370 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 35371 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 35372 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 35373 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 35374 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 35375 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 35376 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 35377 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 35378 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 35379 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 35380 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 35381 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 35382 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 35383 //MMEA6_DRAM_WR_CLI2GRP_MAP1 35384 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 35385 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 35386 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 35387 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 35388 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 35389 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 35390 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 35391 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 35392 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 35393 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 35394 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 35395 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 35396 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 35397 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 35398 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 35399 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 35400 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 35401 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 35402 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 35403 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 35404 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 35405 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 35406 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 35407 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 35408 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 35409 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 35410 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 35411 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 35412 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 35413 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 35414 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 35415 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 35416 //MMEA6_DRAM_RD_GRP2VC_MAP 35417 #define MMEA6_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 35418 #define MMEA6_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 35419 #define MMEA6_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 35420 #define MMEA6_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 35421 #define MMEA6_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 35422 #define MMEA6_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 35423 #define MMEA6_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 35424 #define MMEA6_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 35425 //MMEA6_DRAM_WR_GRP2VC_MAP 35426 #define MMEA6_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 35427 #define MMEA6_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 35428 #define MMEA6_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 35429 #define MMEA6_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 35430 #define MMEA6_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 35431 #define MMEA6_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 35432 #define MMEA6_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 35433 #define MMEA6_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 35434 //MMEA6_DRAM_RD_LAZY 35435 #define MMEA6_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 35436 #define MMEA6_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 35437 #define MMEA6_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 35438 #define MMEA6_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 35439 #define MMEA6_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 35440 #define MMEA6_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 35441 #define MMEA6_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 35442 #define MMEA6_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L 35443 #define MMEA6_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L 35444 #define MMEA6_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L 35445 #define MMEA6_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L 35446 #define MMEA6_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 35447 #define MMEA6_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 35448 #define MMEA6_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 35449 //MMEA6_DRAM_WR_LAZY 35450 #define MMEA6_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 35451 #define MMEA6_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 35452 #define MMEA6_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 35453 #define MMEA6_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 35454 #define MMEA6_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 35455 #define MMEA6_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 35456 #define MMEA6_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 35457 #define MMEA6_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L 35458 #define MMEA6_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L 35459 #define MMEA6_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L 35460 #define MMEA6_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L 35461 #define MMEA6_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 35462 #define MMEA6_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 35463 #define MMEA6_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 35464 //MMEA6_DRAM_RD_CAM_CNTL 35465 #define MMEA6_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 35466 #define MMEA6_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 35467 #define MMEA6_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 35468 #define MMEA6_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 35469 #define MMEA6_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 35470 #define MMEA6_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 35471 #define MMEA6_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 35472 #define MMEA6_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 35473 #define MMEA6_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 35474 #define MMEA6_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 35475 #define MMEA6_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 35476 #define MMEA6_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 35477 #define MMEA6_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 35478 #define MMEA6_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 35479 #define MMEA6_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 35480 #define MMEA6_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 35481 #define MMEA6_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 35482 #define MMEA6_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 35483 //MMEA6_DRAM_WR_CAM_CNTL 35484 #define MMEA6_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 35485 #define MMEA6_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 35486 #define MMEA6_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 35487 #define MMEA6_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 35488 #define MMEA6_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 35489 #define MMEA6_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 35490 #define MMEA6_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 35491 #define MMEA6_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 35492 #define MMEA6_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 35493 #define MMEA6_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 35494 #define MMEA6_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 35495 #define MMEA6_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 35496 #define MMEA6_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 35497 #define MMEA6_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 35498 #define MMEA6_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 35499 #define MMEA6_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 35500 #define MMEA6_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 35501 #define MMEA6_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 35502 //MMEA6_DRAM_PAGE_BURST 35503 #define MMEA6_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 35504 #define MMEA6_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 35505 #define MMEA6_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 35506 #define MMEA6_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 35507 #define MMEA6_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL 35508 #define MMEA6_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 35509 #define MMEA6_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 35510 #define MMEA6_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L 35511 //MMEA6_DRAM_RD_PRI_AGE 35512 #define MMEA6_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 35513 #define MMEA6_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 35514 #define MMEA6_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 35515 #define MMEA6_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 35516 #define MMEA6_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 35517 #define MMEA6_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 35518 #define MMEA6_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 35519 #define MMEA6_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 35520 #define MMEA6_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 35521 #define MMEA6_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 35522 #define MMEA6_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 35523 #define MMEA6_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 35524 #define MMEA6_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 35525 #define MMEA6_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 35526 #define MMEA6_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 35527 #define MMEA6_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 35528 //MMEA6_DRAM_WR_PRI_AGE 35529 #define MMEA6_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 35530 #define MMEA6_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 35531 #define MMEA6_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 35532 #define MMEA6_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 35533 #define MMEA6_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 35534 #define MMEA6_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 35535 #define MMEA6_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 35536 #define MMEA6_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 35537 #define MMEA6_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 35538 #define MMEA6_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 35539 #define MMEA6_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 35540 #define MMEA6_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 35541 #define MMEA6_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 35542 #define MMEA6_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 35543 #define MMEA6_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 35544 #define MMEA6_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 35545 //MMEA6_DRAM_RD_PRI_QUEUING 35546 #define MMEA6_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 35547 #define MMEA6_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 35548 #define MMEA6_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 35549 #define MMEA6_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 35550 #define MMEA6_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 35551 #define MMEA6_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 35552 #define MMEA6_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 35553 #define MMEA6_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 35554 //MMEA6_DRAM_WR_PRI_QUEUING 35555 #define MMEA6_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 35556 #define MMEA6_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 35557 #define MMEA6_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 35558 #define MMEA6_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 35559 #define MMEA6_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 35560 #define MMEA6_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 35561 #define MMEA6_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 35562 #define MMEA6_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 35563 //MMEA6_DRAM_RD_PRI_FIXED 35564 #define MMEA6_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 35565 #define MMEA6_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 35566 #define MMEA6_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 35567 #define MMEA6_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 35568 #define MMEA6_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 35569 #define MMEA6_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 35570 #define MMEA6_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 35571 #define MMEA6_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 35572 //MMEA6_DRAM_WR_PRI_FIXED 35573 #define MMEA6_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 35574 #define MMEA6_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 35575 #define MMEA6_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 35576 #define MMEA6_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 35577 #define MMEA6_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 35578 #define MMEA6_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 35579 #define MMEA6_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 35580 #define MMEA6_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 35581 //MMEA6_DRAM_RD_PRI_URGENCY 35582 #define MMEA6_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 35583 #define MMEA6_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 35584 #define MMEA6_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 35585 #define MMEA6_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 35586 #define MMEA6_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 35587 #define MMEA6_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 35588 #define MMEA6_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 35589 #define MMEA6_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 35590 #define MMEA6_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 35591 #define MMEA6_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 35592 #define MMEA6_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 35593 #define MMEA6_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 35594 #define MMEA6_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 35595 #define MMEA6_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 35596 #define MMEA6_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 35597 #define MMEA6_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 35598 //MMEA6_DRAM_WR_PRI_URGENCY 35599 #define MMEA6_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 35600 #define MMEA6_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 35601 #define MMEA6_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 35602 #define MMEA6_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 35603 #define MMEA6_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 35604 #define MMEA6_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 35605 #define MMEA6_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 35606 #define MMEA6_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 35607 #define MMEA6_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 35608 #define MMEA6_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 35609 #define MMEA6_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 35610 #define MMEA6_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 35611 #define MMEA6_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 35612 #define MMEA6_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 35613 #define MMEA6_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 35614 #define MMEA6_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 35615 //MMEA6_DRAM_RD_PRI_QUANT_PRI1 35616 #define MMEA6_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 35617 #define MMEA6_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 35618 #define MMEA6_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 35619 #define MMEA6_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 35620 #define MMEA6_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 35621 #define MMEA6_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 35622 #define MMEA6_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 35623 #define MMEA6_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 35624 //MMEA6_DRAM_RD_PRI_QUANT_PRI2 35625 #define MMEA6_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 35626 #define MMEA6_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 35627 #define MMEA6_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 35628 #define MMEA6_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 35629 #define MMEA6_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 35630 #define MMEA6_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 35631 #define MMEA6_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 35632 #define MMEA6_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 35633 //MMEA6_DRAM_RD_PRI_QUANT_PRI3 35634 #define MMEA6_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 35635 #define MMEA6_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 35636 #define MMEA6_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 35637 #define MMEA6_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 35638 #define MMEA6_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 35639 #define MMEA6_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 35640 #define MMEA6_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 35641 #define MMEA6_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 35642 //MMEA6_DRAM_WR_PRI_QUANT_PRI1 35643 #define MMEA6_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 35644 #define MMEA6_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 35645 #define MMEA6_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 35646 #define MMEA6_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 35647 #define MMEA6_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 35648 #define MMEA6_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 35649 #define MMEA6_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 35650 #define MMEA6_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 35651 //MMEA6_DRAM_WR_PRI_QUANT_PRI2 35652 #define MMEA6_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 35653 #define MMEA6_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 35654 #define MMEA6_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 35655 #define MMEA6_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 35656 #define MMEA6_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 35657 #define MMEA6_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 35658 #define MMEA6_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 35659 #define MMEA6_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 35660 //MMEA6_DRAM_WR_PRI_QUANT_PRI3 35661 #define MMEA6_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 35662 #define MMEA6_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 35663 #define MMEA6_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 35664 #define MMEA6_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 35665 #define MMEA6_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 35666 #define MMEA6_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 35667 #define MMEA6_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 35668 #define MMEA6_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 35669 //MMEA6_GMI_RD_CLI2GRP_MAP0 35670 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 35671 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 35672 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 35673 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 35674 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 35675 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 35676 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 35677 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 35678 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 35679 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 35680 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 35681 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 35682 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 35683 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 35684 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 35685 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 35686 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 35687 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 35688 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 35689 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 35690 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 35691 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 35692 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 35693 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 35694 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 35695 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 35696 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 35697 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 35698 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 35699 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 35700 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 35701 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 35702 //MMEA6_GMI_RD_CLI2GRP_MAP1 35703 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 35704 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 35705 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 35706 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 35707 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 35708 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 35709 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 35710 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 35711 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 35712 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 35713 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 35714 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 35715 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 35716 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 35717 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 35718 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 35719 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 35720 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 35721 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 35722 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 35723 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 35724 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 35725 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 35726 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 35727 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 35728 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 35729 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 35730 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 35731 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 35732 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 35733 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 35734 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 35735 //MMEA6_GMI_WR_CLI2GRP_MAP0 35736 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 35737 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 35738 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 35739 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 35740 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 35741 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 35742 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 35743 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 35744 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 35745 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 35746 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 35747 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 35748 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 35749 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 35750 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 35751 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 35752 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 35753 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 35754 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 35755 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 35756 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 35757 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 35758 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 35759 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 35760 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 35761 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 35762 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 35763 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 35764 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 35765 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 35766 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 35767 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 35768 //MMEA6_GMI_WR_CLI2GRP_MAP1 35769 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 35770 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 35771 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 35772 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 35773 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 35774 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 35775 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 35776 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 35777 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 35778 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 35779 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 35780 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 35781 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 35782 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 35783 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 35784 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 35785 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 35786 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 35787 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 35788 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 35789 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 35790 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 35791 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 35792 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 35793 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 35794 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 35795 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 35796 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 35797 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 35798 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 35799 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 35800 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 35801 //MMEA6_GMI_RD_GRP2VC_MAP 35802 #define MMEA6_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 35803 #define MMEA6_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 35804 #define MMEA6_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 35805 #define MMEA6_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 35806 #define MMEA6_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 35807 #define MMEA6_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 35808 #define MMEA6_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 35809 #define MMEA6_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 35810 //MMEA6_GMI_WR_GRP2VC_MAP 35811 #define MMEA6_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 35812 #define MMEA6_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 35813 #define MMEA6_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 35814 #define MMEA6_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 35815 #define MMEA6_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 35816 #define MMEA6_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 35817 #define MMEA6_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 35818 #define MMEA6_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 35819 //MMEA6_GMI_RD_LAZY 35820 #define MMEA6_GMI_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 35821 #define MMEA6_GMI_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 35822 #define MMEA6_GMI_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 35823 #define MMEA6_GMI_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 35824 #define MMEA6_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 35825 #define MMEA6_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 35826 #define MMEA6_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 35827 #define MMEA6_GMI_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L 35828 #define MMEA6_GMI_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L 35829 #define MMEA6_GMI_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L 35830 #define MMEA6_GMI_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L 35831 #define MMEA6_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 35832 #define MMEA6_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 35833 #define MMEA6_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 35834 //MMEA6_GMI_WR_LAZY 35835 #define MMEA6_GMI_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 35836 #define MMEA6_GMI_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 35837 #define MMEA6_GMI_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 35838 #define MMEA6_GMI_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 35839 #define MMEA6_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 35840 #define MMEA6_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 35841 #define MMEA6_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 35842 #define MMEA6_GMI_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L 35843 #define MMEA6_GMI_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L 35844 #define MMEA6_GMI_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L 35845 #define MMEA6_GMI_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L 35846 #define MMEA6_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 35847 #define MMEA6_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 35848 #define MMEA6_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 35849 //MMEA6_GMI_RD_CAM_CNTL 35850 #define MMEA6_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 35851 #define MMEA6_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 35852 #define MMEA6_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 35853 #define MMEA6_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 35854 #define MMEA6_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 35855 #define MMEA6_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 35856 #define MMEA6_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 35857 #define MMEA6_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 35858 #define MMEA6_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 35859 #define MMEA6_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d 35860 #define MMEA6_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 35861 #define MMEA6_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 35862 #define MMEA6_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 35863 #define MMEA6_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 35864 #define MMEA6_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 35865 #define MMEA6_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 35866 #define MMEA6_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 35867 #define MMEA6_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 35868 #define MMEA6_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 35869 #define MMEA6_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L 35870 //MMEA6_GMI_WR_CAM_CNTL 35871 #define MMEA6_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 35872 #define MMEA6_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 35873 #define MMEA6_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 35874 #define MMEA6_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 35875 #define MMEA6_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 35876 #define MMEA6_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 35877 #define MMEA6_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 35878 #define MMEA6_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 35879 #define MMEA6_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 35880 #define MMEA6_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d 35881 #define MMEA6_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 35882 #define MMEA6_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 35883 #define MMEA6_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 35884 #define MMEA6_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 35885 #define MMEA6_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 35886 #define MMEA6_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 35887 #define MMEA6_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 35888 #define MMEA6_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 35889 #define MMEA6_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 35890 #define MMEA6_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L 35891 //MMEA6_GMI_PAGE_BURST 35892 #define MMEA6_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 35893 #define MMEA6_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 35894 #define MMEA6_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 35895 #define MMEA6_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 35896 #define MMEA6_GMI_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL 35897 #define MMEA6_GMI_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 35898 #define MMEA6_GMI_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 35899 #define MMEA6_GMI_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L 35900 //MMEA6_GMI_RD_PRI_AGE 35901 #define MMEA6_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 35902 #define MMEA6_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 35903 #define MMEA6_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 35904 #define MMEA6_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 35905 #define MMEA6_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 35906 #define MMEA6_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 35907 #define MMEA6_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 35908 #define MMEA6_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 35909 #define MMEA6_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 35910 #define MMEA6_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 35911 #define MMEA6_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 35912 #define MMEA6_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 35913 #define MMEA6_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 35914 #define MMEA6_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 35915 #define MMEA6_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 35916 #define MMEA6_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 35917 //MMEA6_GMI_WR_PRI_AGE 35918 #define MMEA6_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 35919 #define MMEA6_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 35920 #define MMEA6_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 35921 #define MMEA6_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 35922 #define MMEA6_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 35923 #define MMEA6_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 35924 #define MMEA6_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 35925 #define MMEA6_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 35926 #define MMEA6_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 35927 #define MMEA6_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 35928 #define MMEA6_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 35929 #define MMEA6_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 35930 #define MMEA6_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 35931 #define MMEA6_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 35932 #define MMEA6_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 35933 #define MMEA6_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 35934 //MMEA6_GMI_RD_PRI_QUEUING 35935 #define MMEA6_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 35936 #define MMEA6_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 35937 #define MMEA6_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 35938 #define MMEA6_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 35939 #define MMEA6_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 35940 #define MMEA6_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 35941 #define MMEA6_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 35942 #define MMEA6_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 35943 //MMEA6_GMI_WR_PRI_QUEUING 35944 #define MMEA6_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 35945 #define MMEA6_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 35946 #define MMEA6_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 35947 #define MMEA6_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 35948 #define MMEA6_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 35949 #define MMEA6_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 35950 #define MMEA6_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 35951 #define MMEA6_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 35952 //MMEA6_GMI_RD_PRI_FIXED 35953 #define MMEA6_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 35954 #define MMEA6_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 35955 #define MMEA6_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 35956 #define MMEA6_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 35957 #define MMEA6_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 35958 #define MMEA6_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 35959 #define MMEA6_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 35960 #define MMEA6_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 35961 //MMEA6_GMI_WR_PRI_FIXED 35962 #define MMEA6_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 35963 #define MMEA6_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 35964 #define MMEA6_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 35965 #define MMEA6_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 35966 #define MMEA6_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 35967 #define MMEA6_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 35968 #define MMEA6_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 35969 #define MMEA6_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 35970 //MMEA6_GMI_RD_PRI_URGENCY 35971 #define MMEA6_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 35972 #define MMEA6_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 35973 #define MMEA6_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 35974 #define MMEA6_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 35975 #define MMEA6_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 35976 #define MMEA6_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 35977 #define MMEA6_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 35978 #define MMEA6_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 35979 #define MMEA6_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 35980 #define MMEA6_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 35981 #define MMEA6_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 35982 #define MMEA6_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 35983 #define MMEA6_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 35984 #define MMEA6_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 35985 #define MMEA6_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 35986 #define MMEA6_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 35987 //MMEA6_GMI_WR_PRI_URGENCY 35988 #define MMEA6_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 35989 #define MMEA6_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 35990 #define MMEA6_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 35991 #define MMEA6_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 35992 #define MMEA6_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 35993 #define MMEA6_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 35994 #define MMEA6_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 35995 #define MMEA6_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 35996 #define MMEA6_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 35997 #define MMEA6_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 35998 #define MMEA6_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 35999 #define MMEA6_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 36000 #define MMEA6_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 36001 #define MMEA6_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 36002 #define MMEA6_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 36003 #define MMEA6_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 36004 //MMEA6_GMI_RD_PRI_URGENCY_MASKING 36005 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 36006 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 36007 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 36008 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 36009 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 36010 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 36011 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 36012 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 36013 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 36014 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 36015 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 36016 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 36017 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 36018 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 36019 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 36020 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 36021 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 36022 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 36023 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 36024 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 36025 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 36026 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 36027 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 36028 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 36029 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 36030 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 36031 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 36032 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 36033 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 36034 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 36035 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 36036 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 36037 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 36038 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 36039 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 36040 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 36041 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 36042 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 36043 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 36044 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 36045 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 36046 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 36047 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 36048 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 36049 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 36050 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 36051 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 36052 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 36053 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 36054 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 36055 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 36056 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 36057 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 36058 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 36059 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 36060 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 36061 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 36062 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 36063 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 36064 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 36065 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 36066 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 36067 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 36068 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 36069 //MMEA6_GMI_WR_PRI_URGENCY_MASKING 36070 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 36071 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 36072 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 36073 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 36074 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 36075 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 36076 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 36077 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 36078 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 36079 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 36080 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 36081 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 36082 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 36083 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 36084 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 36085 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 36086 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 36087 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 36088 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 36089 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 36090 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 36091 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 36092 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 36093 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 36094 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 36095 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 36096 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 36097 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 36098 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 36099 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 36100 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 36101 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 36102 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 36103 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 36104 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 36105 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 36106 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 36107 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 36108 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 36109 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 36110 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 36111 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 36112 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 36113 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 36114 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 36115 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 36116 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 36117 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 36118 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 36119 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 36120 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 36121 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 36122 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 36123 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 36124 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 36125 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 36126 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 36127 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 36128 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 36129 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 36130 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 36131 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 36132 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 36133 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 36134 //MMEA6_GMI_RD_PRI_QUANT_PRI1 36135 #define MMEA6_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 36136 #define MMEA6_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 36137 #define MMEA6_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 36138 #define MMEA6_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 36139 #define MMEA6_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 36140 #define MMEA6_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 36141 #define MMEA6_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 36142 #define MMEA6_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 36143 //MMEA6_GMI_RD_PRI_QUANT_PRI2 36144 #define MMEA6_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 36145 #define MMEA6_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 36146 #define MMEA6_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 36147 #define MMEA6_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 36148 #define MMEA6_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 36149 #define MMEA6_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 36150 #define MMEA6_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 36151 #define MMEA6_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 36152 //MMEA6_GMI_RD_PRI_QUANT_PRI3 36153 #define MMEA6_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 36154 #define MMEA6_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 36155 #define MMEA6_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 36156 #define MMEA6_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 36157 #define MMEA6_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 36158 #define MMEA6_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 36159 #define MMEA6_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 36160 #define MMEA6_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 36161 //MMEA6_GMI_WR_PRI_QUANT_PRI1 36162 #define MMEA6_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 36163 #define MMEA6_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 36164 #define MMEA6_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 36165 #define MMEA6_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 36166 #define MMEA6_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 36167 #define MMEA6_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 36168 #define MMEA6_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 36169 #define MMEA6_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 36170 //MMEA6_GMI_WR_PRI_QUANT_PRI2 36171 #define MMEA6_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 36172 #define MMEA6_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 36173 #define MMEA6_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 36174 #define MMEA6_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 36175 #define MMEA6_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 36176 #define MMEA6_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 36177 #define MMEA6_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 36178 #define MMEA6_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 36179 //MMEA6_GMI_WR_PRI_QUANT_PRI3 36180 #define MMEA6_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 36181 #define MMEA6_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 36182 #define MMEA6_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 36183 #define MMEA6_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 36184 #define MMEA6_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 36185 #define MMEA6_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 36186 #define MMEA6_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 36187 #define MMEA6_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 36188 //MMEA6_ADDRNORM_BASE_ADDR0 36189 #define MMEA6_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 36190 #define MMEA6_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 36191 #define MMEA6_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 36192 #define MMEA6_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x6 36193 #define MMEA6_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 36194 #define MMEA6_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 36195 #define MMEA6_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc 36196 #define MMEA6_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L 36197 #define MMEA6_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 36198 #define MMEA6_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000003CL 36199 #define MMEA6_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x000000C0L 36200 #define MMEA6_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L 36201 #define MMEA6_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L 36202 #define MMEA6_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L 36203 //MMEA6_ADDRNORM_LIMIT_ADDR0 36204 #define MMEA6_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 36205 #define MMEA6_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc 36206 #define MMEA6_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL 36207 #define MMEA6_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L 36208 //MMEA6_ADDRNORM_BASE_ADDR1 36209 #define MMEA6_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 36210 #define MMEA6_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 36211 #define MMEA6_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 36212 #define MMEA6_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x6 36213 #define MMEA6_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 36214 #define MMEA6_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 36215 #define MMEA6_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc 36216 #define MMEA6_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L 36217 #define MMEA6_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 36218 #define MMEA6_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000003CL 36219 #define MMEA6_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x000000C0L 36220 #define MMEA6_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L 36221 #define MMEA6_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L 36222 #define MMEA6_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L 36223 //MMEA6_ADDRNORM_LIMIT_ADDR1 36224 #define MMEA6_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 36225 #define MMEA6_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc 36226 #define MMEA6_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL 36227 #define MMEA6_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L 36228 //MMEA6_ADDRNORM_OFFSET_ADDR1 36229 #define MMEA6_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 36230 #define MMEA6_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 36231 #define MMEA6_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L 36232 #define MMEA6_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L 36233 //MMEA6_ADDRNORM_BASE_ADDR2 36234 #define MMEA6_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT 0x0 36235 #define MMEA6_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT 0x1 36236 #define MMEA6_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT 0x2 36237 #define MMEA6_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT 0x6 36238 #define MMEA6_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT 0x8 36239 #define MMEA6_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT 0x9 36240 #define MMEA6_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT 0xc 36241 #define MMEA6_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK 0x00000001L 36242 #define MMEA6_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 36243 #define MMEA6_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK 0x0000003CL 36244 #define MMEA6_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK 0x000000C0L 36245 #define MMEA6_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK 0x00000100L 36246 #define MMEA6_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK 0x00000E00L 36247 #define MMEA6_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK 0xFFFFF000L 36248 //MMEA6_ADDRNORM_LIMIT_ADDR2 36249 #define MMEA6_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT 0x0 36250 #define MMEA6_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT 0xc 36251 #define MMEA6_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK 0x0000001FL 36252 #define MMEA6_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK 0xFFFFF000L 36253 //MMEA6_ADDRNORM_BASE_ADDR3 36254 #define MMEA6_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT 0x0 36255 #define MMEA6_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT 0x1 36256 #define MMEA6_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT 0x2 36257 #define MMEA6_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT 0x6 36258 #define MMEA6_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT 0x8 36259 #define MMEA6_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT 0x9 36260 #define MMEA6_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT 0xc 36261 #define MMEA6_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK 0x00000001L 36262 #define MMEA6_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 36263 #define MMEA6_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK 0x0000003CL 36264 #define MMEA6_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK 0x000000C0L 36265 #define MMEA6_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK 0x00000100L 36266 #define MMEA6_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK 0x00000E00L 36267 #define MMEA6_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK 0xFFFFF000L 36268 //MMEA6_ADDRNORM_LIMIT_ADDR3 36269 #define MMEA6_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT 0x0 36270 #define MMEA6_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT 0xc 36271 #define MMEA6_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK 0x0000001FL 36272 #define MMEA6_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK 0xFFFFF000L 36273 //MMEA6_ADDRNORM_OFFSET_ADDR3 36274 #define MMEA6_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT 0x0 36275 #define MMEA6_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT 0x14 36276 #define MMEA6_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK 0x00000001L 36277 #define MMEA6_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK 0xFFF00000L 36278 //MMEA6_ADDRNORM_BASE_ADDR4 36279 #define MMEA6_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL__SHIFT 0x0 36280 #define MMEA6_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN__SHIFT 0x1 36281 #define MMEA6_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN__SHIFT 0x2 36282 #define MMEA6_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES__SHIFT 0x6 36283 #define MMEA6_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS__SHIFT 0x8 36284 #define MMEA6_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL__SHIFT 0x9 36285 #define MMEA6_ADDRNORM_BASE_ADDR4__BASE_ADDR__SHIFT 0xc 36286 #define MMEA6_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL_MASK 0x00000001L 36287 #define MMEA6_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 36288 #define MMEA6_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN_MASK 0x0000003CL 36289 #define MMEA6_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES_MASK 0x000000C0L 36290 #define MMEA6_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS_MASK 0x00000100L 36291 #define MMEA6_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL_MASK 0x00000E00L 36292 #define MMEA6_ADDRNORM_BASE_ADDR4__BASE_ADDR_MASK 0xFFFFF000L 36293 //MMEA6_ADDRNORM_LIMIT_ADDR4 36294 #define MMEA6_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID__SHIFT 0x0 36295 #define MMEA6_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR__SHIFT 0xc 36296 #define MMEA6_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID_MASK 0x0000001FL 36297 #define MMEA6_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR_MASK 0xFFFFF000L 36298 //MMEA6_ADDRNORM_BASE_ADDR5 36299 #define MMEA6_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL__SHIFT 0x0 36300 #define MMEA6_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN__SHIFT 0x1 36301 #define MMEA6_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN__SHIFT 0x2 36302 #define MMEA6_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES__SHIFT 0x6 36303 #define MMEA6_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS__SHIFT 0x8 36304 #define MMEA6_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL__SHIFT 0x9 36305 #define MMEA6_ADDRNORM_BASE_ADDR5__BASE_ADDR__SHIFT 0xc 36306 #define MMEA6_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL_MASK 0x00000001L 36307 #define MMEA6_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 36308 #define MMEA6_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN_MASK 0x0000003CL 36309 #define MMEA6_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES_MASK 0x000000C0L 36310 #define MMEA6_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS_MASK 0x00000100L 36311 #define MMEA6_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL_MASK 0x00000E00L 36312 #define MMEA6_ADDRNORM_BASE_ADDR5__BASE_ADDR_MASK 0xFFFFF000L 36313 //MMEA6_ADDRNORM_LIMIT_ADDR5 36314 #define MMEA6_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID__SHIFT 0x0 36315 #define MMEA6_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR__SHIFT 0xc 36316 #define MMEA6_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID_MASK 0x0000001FL 36317 #define MMEA6_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR_MASK 0xFFFFF000L 36318 //MMEA6_ADDRNORM_OFFSET_ADDR5 36319 #define MMEA6_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN__SHIFT 0x0 36320 #define MMEA6_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET__SHIFT 0x14 36321 #define MMEA6_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN_MASK 0x00000001L 36322 #define MMEA6_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_MASK 0xFFF00000L 36323 //MMEA6_ADDRNORMDRAM_HOLE_CNTL 36324 #define MMEA6_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 36325 #define MMEA6_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 36326 #define MMEA6_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L 36327 #define MMEA6_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L 36328 //MMEA6_ADDRNORMGMI_HOLE_CNTL 36329 #define MMEA6_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 36330 #define MMEA6_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 36331 #define MMEA6_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L 36332 #define MMEA6_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L 36333 //MMEA6_ADDRNORMDRAM_NP2_CHANNEL_CFG 36334 #define MMEA6_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0 36335 #define MMEA6_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6 36336 #define MMEA6_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL 36337 #define MMEA6_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L 36338 //MMEA6_ADDRNORMGMI_NP2_CHANNEL_CFG 36339 #define MMEA6_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT 0x0 36340 #define MMEA6_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT 0x6 36341 #define MMEA6_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK 0x0000003FL 36342 #define MMEA6_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK 0x00000FC0L 36343 //MMEA6_ADDRDEC_BANK_CFG 36344 #define MMEA6_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 36345 #define MMEA6_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x6 36346 #define MMEA6_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xc 36347 #define MMEA6_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xf 36348 #define MMEA6_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x12 36349 #define MMEA6_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x13 36350 #define MMEA6_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000003FL 36351 #define MMEA6_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x00000FC0L 36352 #define MMEA6_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00007000L 36353 #define MMEA6_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x00038000L 36354 #define MMEA6_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00040000L 36355 #define MMEA6_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00080000L 36356 //MMEA6_ADDRDEC_MISC_CFG 36357 #define MMEA6_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 36358 #define MMEA6_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 36359 #define MMEA6_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 36360 #define MMEA6_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 36361 #define MMEA6_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 36362 #define MMEA6_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc 36363 #define MMEA6_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11 36364 #define MMEA6_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16 36365 #define MMEA6_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18 36366 #define MMEA6_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a 36367 #define MMEA6_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d 36368 #define MMEA6_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L 36369 #define MMEA6_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L 36370 #define MMEA6_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L 36371 #define MMEA6_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L 36372 #define MMEA6_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L 36373 #define MMEA6_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L 36374 #define MMEA6_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L 36375 #define MMEA6_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L 36376 #define MMEA6_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L 36377 #define MMEA6_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L 36378 #define MMEA6_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L 36379 //MMEA6_ADDRDECDRAM_ADDR_HASH_BANK0 36380 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 36381 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 36382 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe 36383 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L 36384 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL 36385 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L 36386 //MMEA6_ADDRDECDRAM_ADDR_HASH_BANK1 36387 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 36388 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 36389 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe 36390 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L 36391 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL 36392 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L 36393 //MMEA6_ADDRDECDRAM_ADDR_HASH_BANK2 36394 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 36395 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 36396 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe 36397 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L 36398 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL 36399 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L 36400 //MMEA6_ADDRDECDRAM_ADDR_HASH_BANK3 36401 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 36402 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 36403 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe 36404 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L 36405 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL 36406 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L 36407 //MMEA6_ADDRDECDRAM_ADDR_HASH_BANK4 36408 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 36409 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 36410 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe 36411 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L 36412 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL 36413 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L 36414 //MMEA6_ADDRDECDRAM_ADDR_HASH_BANK5 36415 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT 0x0 36416 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR__SHIFT 0x1 36417 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR__SHIFT 0xe 36418 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE_MASK 0x00000001L 36419 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR_MASK 0x00003FFEL 36420 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR_MASK 0xFFFFC000L 36421 //MMEA6_ADDRDECDRAM_ADDR_HASH_PC 36422 #define MMEA6_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 36423 #define MMEA6_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 36424 #define MMEA6_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe 36425 #define MMEA6_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L 36426 #define MMEA6_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL 36427 #define MMEA6_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L 36428 //MMEA6_ADDRDECDRAM_ADDR_HASH_PC2 36429 #define MMEA6_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 36430 #define MMEA6_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000003FL 36431 //MMEA6_ADDRDECDRAM_ADDR_HASH_CS0 36432 #define MMEA6_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 36433 #define MMEA6_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 36434 #define MMEA6_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L 36435 #define MMEA6_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL 36436 //MMEA6_ADDRDECDRAM_ADDR_HASH_CS1 36437 #define MMEA6_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 36438 #define MMEA6_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 36439 #define MMEA6_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L 36440 #define MMEA6_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL 36441 //MMEA6_ADDRDECDRAM_HARVEST_ENABLE 36442 #define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 36443 #define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 36444 #define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 36445 #define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 36446 #define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 36447 #define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 36448 #define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L 36449 #define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L 36450 #define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L 36451 #define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L 36452 #define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L 36453 #define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L 36454 //MMEA6_ADDRDECGMI_ADDR_HASH_BANK0 36455 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 36456 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 36457 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe 36458 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L 36459 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL 36460 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L 36461 //MMEA6_ADDRDECGMI_ADDR_HASH_BANK1 36462 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 36463 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 36464 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe 36465 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L 36466 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL 36467 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L 36468 //MMEA6_ADDRDECGMI_ADDR_HASH_BANK2 36469 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 36470 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 36471 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe 36472 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L 36473 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL 36474 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L 36475 //MMEA6_ADDRDECGMI_ADDR_HASH_BANK3 36476 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 36477 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 36478 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe 36479 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L 36480 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL 36481 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L 36482 //MMEA6_ADDRDECGMI_ADDR_HASH_BANK4 36483 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 36484 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 36485 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe 36486 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L 36487 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL 36488 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L 36489 //MMEA6_ADDRDECGMI_ADDR_HASH_BANK5 36490 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT 0x0 36491 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR__SHIFT 0x1 36492 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR__SHIFT 0xe 36493 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE_MASK 0x00000001L 36494 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR_MASK 0x00003FFEL 36495 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR_MASK 0xFFFFC000L 36496 //MMEA6_ADDRDECGMI_ADDR_HASH_PC 36497 #define MMEA6_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 36498 #define MMEA6_ADDRDECGMI_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 36499 #define MMEA6_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe 36500 #define MMEA6_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L 36501 #define MMEA6_ADDRDECGMI_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL 36502 #define MMEA6_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L 36503 //MMEA6_ADDRDECGMI_ADDR_HASH_PC2 36504 #define MMEA6_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 36505 #define MMEA6_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000003FL 36506 //MMEA6_ADDRDECGMI_ADDR_HASH_CS0 36507 #define MMEA6_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 36508 #define MMEA6_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 36509 #define MMEA6_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L 36510 #define MMEA6_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL 36511 //MMEA6_ADDRDECGMI_ADDR_HASH_CS1 36512 #define MMEA6_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 36513 #define MMEA6_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 36514 #define MMEA6_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L 36515 #define MMEA6_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL 36516 //MMEA6_ADDRDECGMI_HARVEST_ENABLE 36517 #define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 36518 #define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 36519 #define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 36520 #define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 36521 #define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 36522 #define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 36523 #define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L 36524 #define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L 36525 #define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L 36526 #define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L 36527 #define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L 36528 #define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L 36529 //MMEA6_ADDRDEC0_BASE_ADDR_CS0 36530 #define MMEA6_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 36531 #define MMEA6_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 36532 #define MMEA6_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 36533 #define MMEA6_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 36534 //MMEA6_ADDRDEC0_BASE_ADDR_CS1 36535 #define MMEA6_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 36536 #define MMEA6_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 36537 #define MMEA6_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 36538 #define MMEA6_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 36539 //MMEA6_ADDRDEC0_BASE_ADDR_CS2 36540 #define MMEA6_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 36541 #define MMEA6_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 36542 #define MMEA6_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 36543 #define MMEA6_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 36544 //MMEA6_ADDRDEC0_BASE_ADDR_CS3 36545 #define MMEA6_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 36546 #define MMEA6_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 36547 #define MMEA6_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 36548 #define MMEA6_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 36549 //MMEA6_ADDRDEC0_BASE_ADDR_SECCS0 36550 #define MMEA6_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 36551 #define MMEA6_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 36552 #define MMEA6_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 36553 #define MMEA6_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 36554 //MMEA6_ADDRDEC0_BASE_ADDR_SECCS1 36555 #define MMEA6_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 36556 #define MMEA6_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 36557 #define MMEA6_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 36558 #define MMEA6_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 36559 //MMEA6_ADDRDEC0_BASE_ADDR_SECCS2 36560 #define MMEA6_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 36561 #define MMEA6_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 36562 #define MMEA6_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 36563 #define MMEA6_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 36564 //MMEA6_ADDRDEC0_BASE_ADDR_SECCS3 36565 #define MMEA6_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 36566 #define MMEA6_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 36567 #define MMEA6_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 36568 #define MMEA6_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 36569 //MMEA6_ADDRDEC0_ADDR_MASK_CS01 36570 #define MMEA6_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 36571 #define MMEA6_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 36572 //MMEA6_ADDRDEC0_ADDR_MASK_CS23 36573 #define MMEA6_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 36574 #define MMEA6_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 36575 //MMEA6_ADDRDEC0_ADDR_MASK_SECCS01 36576 #define MMEA6_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 36577 #define MMEA6_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 36578 //MMEA6_ADDRDEC0_ADDR_MASK_SECCS23 36579 #define MMEA6_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 36580 #define MMEA6_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 36581 //MMEA6_ADDRDEC0_ADDR_CFG_CS01 36582 #define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 36583 #define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 36584 #define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 36585 #define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 36586 #define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 36587 #define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 36588 #define MMEA6_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 36589 #define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 36590 #define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 36591 #define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 36592 #define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 36593 #define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 36594 #define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 36595 #define MMEA6_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 36596 //MMEA6_ADDRDEC0_ADDR_CFG_CS23 36597 #define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 36598 #define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 36599 #define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 36600 #define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 36601 #define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 36602 #define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 36603 #define MMEA6_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 36604 #define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 36605 #define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 36606 #define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 36607 #define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 36608 #define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 36609 #define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 36610 #define MMEA6_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 36611 //MMEA6_ADDRDEC0_ADDR_SEL_CS01 36612 #define MMEA6_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 36613 #define MMEA6_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 36614 #define MMEA6_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 36615 #define MMEA6_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc 36616 #define MMEA6_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 36617 #define MMEA6_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 36618 #define MMEA6_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 36619 #define MMEA6_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 36620 #define MMEA6_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 36621 #define MMEA6_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 36622 #define MMEA6_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 36623 #define MMEA6_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 36624 #define MMEA6_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 36625 #define MMEA6_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 36626 //MMEA6_ADDRDEC0_ADDR_SEL_CS23 36627 #define MMEA6_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 36628 #define MMEA6_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 36629 #define MMEA6_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 36630 #define MMEA6_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc 36631 #define MMEA6_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 36632 #define MMEA6_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 36633 #define MMEA6_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 36634 #define MMEA6_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 36635 #define MMEA6_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 36636 #define MMEA6_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 36637 #define MMEA6_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 36638 #define MMEA6_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 36639 #define MMEA6_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 36640 #define MMEA6_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 36641 //MMEA6_ADDRDEC0_ADDR_SEL2_CS01 36642 #define MMEA6_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 36643 #define MMEA6_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 36644 //MMEA6_ADDRDEC0_ADDR_SEL2_CS23 36645 #define MMEA6_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 36646 #define MMEA6_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 36647 //MMEA6_ADDRDEC0_COL_SEL_LO_CS01 36648 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 36649 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 36650 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 36651 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc 36652 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 36653 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 36654 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 36655 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 36656 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 36657 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 36658 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 36659 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 36660 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 36661 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 36662 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 36663 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 36664 //MMEA6_ADDRDEC0_COL_SEL_LO_CS23 36665 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 36666 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 36667 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 36668 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc 36669 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 36670 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 36671 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 36672 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 36673 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 36674 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 36675 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 36676 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 36677 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 36678 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 36679 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 36680 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 36681 //MMEA6_ADDRDEC0_COL_SEL_HI_CS01 36682 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 36683 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 36684 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 36685 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc 36686 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 36687 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 36688 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 36689 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 36690 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 36691 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 36692 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 36693 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 36694 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 36695 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 36696 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 36697 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 36698 //MMEA6_ADDRDEC0_COL_SEL_HI_CS23 36699 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 36700 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 36701 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 36702 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc 36703 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 36704 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 36705 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 36706 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 36707 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 36708 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 36709 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 36710 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 36711 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 36712 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 36713 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 36714 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 36715 //MMEA6_ADDRDEC0_RM_SEL_CS01 36716 #define MMEA6_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 36717 #define MMEA6_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 36718 #define MMEA6_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 36719 #define MMEA6_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 36720 #define MMEA6_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 36721 #define MMEA6_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 36722 #define MMEA6_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL 36723 #define MMEA6_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L 36724 #define MMEA6_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L 36725 #define MMEA6_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 36726 #define MMEA6_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 36727 #define MMEA6_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 36728 //MMEA6_ADDRDEC0_RM_SEL_CS23 36729 #define MMEA6_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 36730 #define MMEA6_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 36731 #define MMEA6_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 36732 #define MMEA6_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 36733 #define MMEA6_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 36734 #define MMEA6_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 36735 #define MMEA6_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL 36736 #define MMEA6_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L 36737 #define MMEA6_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L 36738 #define MMEA6_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 36739 #define MMEA6_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 36740 #define MMEA6_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 36741 //MMEA6_ADDRDEC0_RM_SEL_SECCS01 36742 #define MMEA6_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 36743 #define MMEA6_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 36744 #define MMEA6_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 36745 #define MMEA6_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 36746 #define MMEA6_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 36747 #define MMEA6_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 36748 #define MMEA6_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 36749 #define MMEA6_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 36750 #define MMEA6_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 36751 #define MMEA6_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 36752 #define MMEA6_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 36753 #define MMEA6_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 36754 //MMEA6_ADDRDEC0_RM_SEL_SECCS23 36755 #define MMEA6_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 36756 #define MMEA6_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 36757 #define MMEA6_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 36758 #define MMEA6_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 36759 #define MMEA6_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 36760 #define MMEA6_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 36761 #define MMEA6_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 36762 #define MMEA6_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 36763 #define MMEA6_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 36764 #define MMEA6_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 36765 #define MMEA6_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 36766 #define MMEA6_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 36767 //MMEA6_ADDRDEC1_BASE_ADDR_CS0 36768 #define MMEA6_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 36769 #define MMEA6_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 36770 #define MMEA6_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 36771 #define MMEA6_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 36772 //MMEA6_ADDRDEC1_BASE_ADDR_CS1 36773 #define MMEA6_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 36774 #define MMEA6_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 36775 #define MMEA6_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 36776 #define MMEA6_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 36777 //MMEA6_ADDRDEC1_BASE_ADDR_CS2 36778 #define MMEA6_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 36779 #define MMEA6_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 36780 #define MMEA6_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 36781 #define MMEA6_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 36782 //MMEA6_ADDRDEC1_BASE_ADDR_CS3 36783 #define MMEA6_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 36784 #define MMEA6_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 36785 #define MMEA6_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 36786 #define MMEA6_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 36787 //MMEA6_ADDRDEC1_BASE_ADDR_SECCS0 36788 #define MMEA6_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 36789 #define MMEA6_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 36790 #define MMEA6_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 36791 #define MMEA6_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 36792 //MMEA6_ADDRDEC1_BASE_ADDR_SECCS1 36793 #define MMEA6_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 36794 #define MMEA6_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 36795 #define MMEA6_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 36796 #define MMEA6_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 36797 //MMEA6_ADDRDEC1_BASE_ADDR_SECCS2 36798 #define MMEA6_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 36799 #define MMEA6_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 36800 #define MMEA6_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 36801 #define MMEA6_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 36802 //MMEA6_ADDRDEC1_BASE_ADDR_SECCS3 36803 #define MMEA6_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 36804 #define MMEA6_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 36805 #define MMEA6_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 36806 #define MMEA6_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 36807 //MMEA6_ADDRDEC1_ADDR_MASK_CS01 36808 #define MMEA6_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 36809 #define MMEA6_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 36810 //MMEA6_ADDRDEC1_ADDR_MASK_CS23 36811 #define MMEA6_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 36812 #define MMEA6_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 36813 //MMEA6_ADDRDEC1_ADDR_MASK_SECCS01 36814 #define MMEA6_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 36815 #define MMEA6_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 36816 //MMEA6_ADDRDEC1_ADDR_MASK_SECCS23 36817 #define MMEA6_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 36818 #define MMEA6_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 36819 //MMEA6_ADDRDEC1_ADDR_CFG_CS01 36820 #define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 36821 #define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 36822 #define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 36823 #define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 36824 #define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 36825 #define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 36826 #define MMEA6_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 36827 #define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 36828 #define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 36829 #define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 36830 #define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 36831 #define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 36832 #define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 36833 #define MMEA6_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 36834 //MMEA6_ADDRDEC1_ADDR_CFG_CS23 36835 #define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 36836 #define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 36837 #define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 36838 #define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 36839 #define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 36840 #define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 36841 #define MMEA6_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 36842 #define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 36843 #define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 36844 #define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 36845 #define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 36846 #define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 36847 #define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 36848 #define MMEA6_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 36849 //MMEA6_ADDRDEC1_ADDR_SEL_CS01 36850 #define MMEA6_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 36851 #define MMEA6_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 36852 #define MMEA6_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 36853 #define MMEA6_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc 36854 #define MMEA6_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 36855 #define MMEA6_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 36856 #define MMEA6_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 36857 #define MMEA6_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 36858 #define MMEA6_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 36859 #define MMEA6_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 36860 #define MMEA6_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 36861 #define MMEA6_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 36862 #define MMEA6_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 36863 #define MMEA6_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 36864 //MMEA6_ADDRDEC1_ADDR_SEL_CS23 36865 #define MMEA6_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 36866 #define MMEA6_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 36867 #define MMEA6_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 36868 #define MMEA6_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc 36869 #define MMEA6_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 36870 #define MMEA6_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 36871 #define MMEA6_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 36872 #define MMEA6_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 36873 #define MMEA6_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 36874 #define MMEA6_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 36875 #define MMEA6_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 36876 #define MMEA6_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 36877 #define MMEA6_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 36878 #define MMEA6_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 36879 //MMEA6_ADDRDEC1_ADDR_SEL2_CS01 36880 #define MMEA6_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 36881 #define MMEA6_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 36882 //MMEA6_ADDRDEC1_ADDR_SEL2_CS23 36883 #define MMEA6_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 36884 #define MMEA6_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 36885 //MMEA6_ADDRDEC1_COL_SEL_LO_CS01 36886 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 36887 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 36888 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 36889 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc 36890 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 36891 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 36892 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 36893 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 36894 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 36895 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 36896 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 36897 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 36898 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 36899 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 36900 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 36901 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 36902 //MMEA6_ADDRDEC1_COL_SEL_LO_CS23 36903 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 36904 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 36905 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 36906 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc 36907 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 36908 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 36909 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 36910 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 36911 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 36912 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 36913 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 36914 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 36915 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 36916 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 36917 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 36918 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 36919 //MMEA6_ADDRDEC1_COL_SEL_HI_CS01 36920 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 36921 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 36922 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 36923 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc 36924 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 36925 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 36926 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 36927 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 36928 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 36929 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 36930 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 36931 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 36932 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 36933 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 36934 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 36935 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 36936 //MMEA6_ADDRDEC1_COL_SEL_HI_CS23 36937 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 36938 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 36939 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 36940 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc 36941 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 36942 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 36943 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 36944 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 36945 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 36946 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 36947 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 36948 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 36949 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 36950 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 36951 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 36952 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 36953 //MMEA6_ADDRDEC1_RM_SEL_CS01 36954 #define MMEA6_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 36955 #define MMEA6_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 36956 #define MMEA6_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 36957 #define MMEA6_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 36958 #define MMEA6_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 36959 #define MMEA6_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 36960 #define MMEA6_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL 36961 #define MMEA6_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L 36962 #define MMEA6_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L 36963 #define MMEA6_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 36964 #define MMEA6_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 36965 #define MMEA6_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 36966 //MMEA6_ADDRDEC1_RM_SEL_CS23 36967 #define MMEA6_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 36968 #define MMEA6_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 36969 #define MMEA6_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 36970 #define MMEA6_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 36971 #define MMEA6_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 36972 #define MMEA6_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 36973 #define MMEA6_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL 36974 #define MMEA6_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L 36975 #define MMEA6_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L 36976 #define MMEA6_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 36977 #define MMEA6_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 36978 #define MMEA6_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 36979 //MMEA6_ADDRDEC1_RM_SEL_SECCS01 36980 #define MMEA6_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 36981 #define MMEA6_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 36982 #define MMEA6_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 36983 #define MMEA6_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 36984 #define MMEA6_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 36985 #define MMEA6_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 36986 #define MMEA6_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 36987 #define MMEA6_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 36988 #define MMEA6_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 36989 #define MMEA6_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 36990 #define MMEA6_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 36991 #define MMEA6_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 36992 //MMEA6_ADDRDEC1_RM_SEL_SECCS23 36993 #define MMEA6_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 36994 #define MMEA6_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 36995 #define MMEA6_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 36996 #define MMEA6_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 36997 #define MMEA6_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 36998 #define MMEA6_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 36999 #define MMEA6_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 37000 #define MMEA6_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 37001 #define MMEA6_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 37002 #define MMEA6_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 37003 #define MMEA6_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 37004 #define MMEA6_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 37005 //MMEA6_ADDRDEC2_BASE_ADDR_CS0 37006 #define MMEA6_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 37007 #define MMEA6_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 37008 #define MMEA6_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 37009 #define MMEA6_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 37010 //MMEA6_ADDRDEC2_BASE_ADDR_CS1 37011 #define MMEA6_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 37012 #define MMEA6_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 37013 #define MMEA6_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 37014 #define MMEA6_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 37015 //MMEA6_ADDRDEC2_BASE_ADDR_CS2 37016 #define MMEA6_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 37017 #define MMEA6_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 37018 #define MMEA6_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 37019 #define MMEA6_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 37020 //MMEA6_ADDRDEC2_BASE_ADDR_CS3 37021 #define MMEA6_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 37022 #define MMEA6_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 37023 #define MMEA6_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 37024 #define MMEA6_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 37025 //MMEA6_ADDRDEC2_BASE_ADDR_SECCS0 37026 #define MMEA6_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 37027 #define MMEA6_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 37028 #define MMEA6_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 37029 #define MMEA6_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 37030 //MMEA6_ADDRDEC2_BASE_ADDR_SECCS1 37031 #define MMEA6_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 37032 #define MMEA6_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 37033 #define MMEA6_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 37034 #define MMEA6_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 37035 //MMEA6_ADDRDEC2_BASE_ADDR_SECCS2 37036 #define MMEA6_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 37037 #define MMEA6_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 37038 #define MMEA6_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 37039 #define MMEA6_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 37040 //MMEA6_ADDRDEC2_BASE_ADDR_SECCS3 37041 #define MMEA6_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 37042 #define MMEA6_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 37043 #define MMEA6_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 37044 #define MMEA6_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 37045 //MMEA6_ADDRDEC2_ADDR_MASK_CS01 37046 #define MMEA6_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 37047 #define MMEA6_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 37048 //MMEA6_ADDRDEC2_ADDR_MASK_CS23 37049 #define MMEA6_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 37050 #define MMEA6_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 37051 //MMEA6_ADDRDEC2_ADDR_MASK_SECCS01 37052 #define MMEA6_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 37053 #define MMEA6_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 37054 //MMEA6_ADDRDEC2_ADDR_MASK_SECCS23 37055 #define MMEA6_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 37056 #define MMEA6_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 37057 //MMEA6_ADDRDEC2_ADDR_CFG_CS01 37058 #define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 37059 #define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 37060 #define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 37061 #define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 37062 #define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 37063 #define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 37064 #define MMEA6_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 37065 #define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 37066 #define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 37067 #define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 37068 #define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 37069 #define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 37070 #define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 37071 #define MMEA6_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 37072 //MMEA6_ADDRDEC2_ADDR_CFG_CS23 37073 #define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 37074 #define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 37075 #define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 37076 #define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 37077 #define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 37078 #define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 37079 #define MMEA6_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 37080 #define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 37081 #define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 37082 #define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 37083 #define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 37084 #define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 37085 #define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 37086 #define MMEA6_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 37087 //MMEA6_ADDRDEC2_ADDR_SEL_CS01 37088 #define MMEA6_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT 0x0 37089 #define MMEA6_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT 0x4 37090 #define MMEA6_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT 0x8 37091 #define MMEA6_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT 0xc 37092 #define MMEA6_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT 0x10 37093 #define MMEA6_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 37094 #define MMEA6_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 37095 #define MMEA6_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 37096 #define MMEA6_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 37097 #define MMEA6_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 37098 #define MMEA6_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 37099 #define MMEA6_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 37100 #define MMEA6_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 37101 #define MMEA6_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 37102 //MMEA6_ADDRDEC2_ADDR_SEL_CS23 37103 #define MMEA6_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT 0x0 37104 #define MMEA6_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT 0x4 37105 #define MMEA6_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT 0x8 37106 #define MMEA6_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT 0xc 37107 #define MMEA6_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT 0x10 37108 #define MMEA6_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 37109 #define MMEA6_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 37110 #define MMEA6_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 37111 #define MMEA6_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 37112 #define MMEA6_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 37113 #define MMEA6_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 37114 #define MMEA6_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 37115 #define MMEA6_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 37116 #define MMEA6_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 37117 //MMEA6_ADDRDEC2_ADDR_SEL2_CS01 37118 #define MMEA6_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 37119 #define MMEA6_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 37120 //MMEA6_ADDRDEC2_ADDR_SEL2_CS23 37121 #define MMEA6_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 37122 #define MMEA6_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 37123 //MMEA6_ADDRDEC2_COL_SEL_LO_CS01 37124 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT 0x0 37125 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT 0x4 37126 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT 0x8 37127 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT 0xc 37128 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT 0x10 37129 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT 0x14 37130 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT 0x18 37131 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 37132 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 37133 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 37134 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 37135 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 37136 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 37137 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 37138 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 37139 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 37140 //MMEA6_ADDRDEC2_COL_SEL_LO_CS23 37141 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT 0x0 37142 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT 0x4 37143 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT 0x8 37144 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT 0xc 37145 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT 0x10 37146 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT 0x14 37147 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT 0x18 37148 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 37149 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 37150 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 37151 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 37152 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 37153 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 37154 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 37155 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 37156 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 37157 //MMEA6_ADDRDEC2_COL_SEL_HI_CS01 37158 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT 0x0 37159 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT 0x4 37160 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT 0x8 37161 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT 0xc 37162 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT 0x10 37163 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT 0x14 37164 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT 0x18 37165 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 37166 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 37167 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 37168 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 37169 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 37170 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 37171 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 37172 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 37173 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 37174 //MMEA6_ADDRDEC2_COL_SEL_HI_CS23 37175 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT 0x0 37176 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT 0x4 37177 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT 0x8 37178 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT 0xc 37179 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT 0x10 37180 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT 0x14 37181 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT 0x18 37182 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 37183 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 37184 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 37185 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 37186 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 37187 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 37188 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 37189 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 37190 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 37191 //MMEA6_ADDRDEC2_RM_SEL_CS01 37192 #define MMEA6_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT 0x0 37193 #define MMEA6_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT 0x4 37194 #define MMEA6_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT 0x8 37195 #define MMEA6_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 37196 #define MMEA6_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 37197 #define MMEA6_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 37198 #define MMEA6_ADDRDEC2_RM_SEL_CS01__RM0_MASK 0x0000000FL 37199 #define MMEA6_ADDRDEC2_RM_SEL_CS01__RM1_MASK 0x000000F0L 37200 #define MMEA6_ADDRDEC2_RM_SEL_CS01__RM2_MASK 0x00000F00L 37201 #define MMEA6_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 37202 #define MMEA6_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 37203 #define MMEA6_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 37204 //MMEA6_ADDRDEC2_RM_SEL_CS23 37205 #define MMEA6_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT 0x0 37206 #define MMEA6_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT 0x4 37207 #define MMEA6_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT 0x8 37208 #define MMEA6_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 37209 #define MMEA6_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 37210 #define MMEA6_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 37211 #define MMEA6_ADDRDEC2_RM_SEL_CS23__RM0_MASK 0x0000000FL 37212 #define MMEA6_ADDRDEC2_RM_SEL_CS23__RM1_MASK 0x000000F0L 37213 #define MMEA6_ADDRDEC2_RM_SEL_CS23__RM2_MASK 0x00000F00L 37214 #define MMEA6_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 37215 #define MMEA6_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 37216 #define MMEA6_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 37217 //MMEA6_ADDRDEC2_RM_SEL_SECCS01 37218 #define MMEA6_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT 0x0 37219 #define MMEA6_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT 0x4 37220 #define MMEA6_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT 0x8 37221 #define MMEA6_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 37222 #define MMEA6_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 37223 #define MMEA6_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 37224 #define MMEA6_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 37225 #define MMEA6_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 37226 #define MMEA6_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 37227 #define MMEA6_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 37228 #define MMEA6_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 37229 #define MMEA6_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 37230 //MMEA6_ADDRDEC2_RM_SEL_SECCS23 37231 #define MMEA6_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT 0x0 37232 #define MMEA6_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT 0x4 37233 #define MMEA6_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT 0x8 37234 #define MMEA6_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 37235 #define MMEA6_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 37236 #define MMEA6_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 37237 #define MMEA6_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 37238 #define MMEA6_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 37239 #define MMEA6_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 37240 #define MMEA6_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 37241 #define MMEA6_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 37242 #define MMEA6_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 37243 //MMEA6_ADDRNORMDRAM_GLOBAL_CNTL 37244 #define MMEA6_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT 0x14 37245 #define MMEA6_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT 0x15 37246 #define MMEA6_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT 0x16 37247 #define MMEA6_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK 0x00100000L 37248 #define MMEA6_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK 0x00200000L 37249 #define MMEA6_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK 0x00400000L 37250 //MMEA6_ADDRNORMGMI_GLOBAL_CNTL 37251 #define MMEA6_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT 0x14 37252 #define MMEA6_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT 0x15 37253 #define MMEA6_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT 0x16 37254 #define MMEA6_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK 0x00100000L 37255 #define MMEA6_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK 0x00200000L 37256 #define MMEA6_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK 0x00400000L 37257 //MMEA6_IO_RD_CLI2GRP_MAP0 37258 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 37259 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 37260 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 37261 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 37262 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 37263 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 37264 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 37265 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 37266 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 37267 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 37268 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 37269 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 37270 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 37271 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 37272 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 37273 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 37274 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 37275 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 37276 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 37277 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 37278 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 37279 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 37280 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 37281 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 37282 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 37283 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 37284 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 37285 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 37286 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 37287 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 37288 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 37289 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 37290 //MMEA6_IO_RD_CLI2GRP_MAP1 37291 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 37292 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 37293 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 37294 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 37295 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 37296 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 37297 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 37298 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 37299 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 37300 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 37301 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 37302 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 37303 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 37304 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 37305 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 37306 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 37307 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 37308 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 37309 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 37310 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 37311 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 37312 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 37313 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 37314 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 37315 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 37316 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 37317 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 37318 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 37319 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 37320 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 37321 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 37322 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 37323 //MMEA6_IO_WR_CLI2GRP_MAP0 37324 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 37325 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 37326 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 37327 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 37328 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 37329 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 37330 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 37331 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 37332 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 37333 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 37334 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 37335 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 37336 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 37337 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 37338 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 37339 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 37340 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 37341 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 37342 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 37343 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 37344 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 37345 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 37346 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 37347 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 37348 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 37349 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 37350 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 37351 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 37352 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 37353 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 37354 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 37355 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 37356 //MMEA6_IO_WR_CLI2GRP_MAP1 37357 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 37358 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 37359 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 37360 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 37361 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 37362 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 37363 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 37364 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 37365 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 37366 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 37367 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 37368 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 37369 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 37370 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 37371 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 37372 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 37373 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 37374 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 37375 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 37376 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 37377 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 37378 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 37379 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 37380 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 37381 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 37382 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 37383 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 37384 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 37385 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 37386 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 37387 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 37388 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 37389 //MMEA6_IO_RD_COMBINE_FLUSH 37390 #define MMEA6_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 37391 #define MMEA6_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 37392 #define MMEA6_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 37393 #define MMEA6_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 37394 #define MMEA6_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT 0x10 37395 #define MMEA6_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 37396 #define MMEA6_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 37397 #define MMEA6_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 37398 #define MMEA6_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 37399 #define MMEA6_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK 0x00010000L 37400 //MMEA6_IO_WR_COMBINE_FLUSH 37401 #define MMEA6_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 37402 #define MMEA6_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 37403 #define MMEA6_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 37404 #define MMEA6_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 37405 #define MMEA6_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT 0x10 37406 #define MMEA6_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 37407 #define MMEA6_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 37408 #define MMEA6_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 37409 #define MMEA6_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 37410 #define MMEA6_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK 0x00010000L 37411 //MMEA6_IO_GROUP_BURST 37412 #define MMEA6_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 37413 #define MMEA6_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 37414 #define MMEA6_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 37415 #define MMEA6_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 37416 #define MMEA6_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL 37417 #define MMEA6_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 37418 #define MMEA6_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 37419 #define MMEA6_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L 37420 //MMEA6_IO_RD_PRI_AGE 37421 #define MMEA6_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 37422 #define MMEA6_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 37423 #define MMEA6_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 37424 #define MMEA6_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 37425 #define MMEA6_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 37426 #define MMEA6_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 37427 #define MMEA6_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 37428 #define MMEA6_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 37429 #define MMEA6_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 37430 #define MMEA6_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 37431 #define MMEA6_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 37432 #define MMEA6_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 37433 #define MMEA6_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 37434 #define MMEA6_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 37435 #define MMEA6_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 37436 #define MMEA6_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 37437 //MMEA6_IO_WR_PRI_AGE 37438 #define MMEA6_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 37439 #define MMEA6_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 37440 #define MMEA6_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 37441 #define MMEA6_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 37442 #define MMEA6_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 37443 #define MMEA6_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 37444 #define MMEA6_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 37445 #define MMEA6_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 37446 #define MMEA6_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 37447 #define MMEA6_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 37448 #define MMEA6_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 37449 #define MMEA6_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 37450 #define MMEA6_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 37451 #define MMEA6_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 37452 #define MMEA6_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 37453 #define MMEA6_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 37454 //MMEA6_IO_RD_PRI_QUEUING 37455 #define MMEA6_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 37456 #define MMEA6_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 37457 #define MMEA6_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 37458 #define MMEA6_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 37459 #define MMEA6_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 37460 #define MMEA6_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 37461 #define MMEA6_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 37462 #define MMEA6_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 37463 //MMEA6_IO_WR_PRI_QUEUING 37464 #define MMEA6_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 37465 #define MMEA6_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 37466 #define MMEA6_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 37467 #define MMEA6_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 37468 #define MMEA6_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 37469 #define MMEA6_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 37470 #define MMEA6_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 37471 #define MMEA6_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 37472 //MMEA6_IO_RD_PRI_FIXED 37473 #define MMEA6_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 37474 #define MMEA6_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 37475 #define MMEA6_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 37476 #define MMEA6_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 37477 #define MMEA6_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 37478 #define MMEA6_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 37479 #define MMEA6_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 37480 #define MMEA6_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 37481 //MMEA6_IO_WR_PRI_FIXED 37482 #define MMEA6_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 37483 #define MMEA6_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 37484 #define MMEA6_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 37485 #define MMEA6_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 37486 #define MMEA6_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 37487 #define MMEA6_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 37488 #define MMEA6_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 37489 #define MMEA6_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 37490 //MMEA6_IO_RD_PRI_URGENCY 37491 #define MMEA6_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 37492 #define MMEA6_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 37493 #define MMEA6_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 37494 #define MMEA6_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 37495 #define MMEA6_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 37496 #define MMEA6_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 37497 #define MMEA6_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 37498 #define MMEA6_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 37499 #define MMEA6_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 37500 #define MMEA6_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 37501 #define MMEA6_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 37502 #define MMEA6_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 37503 #define MMEA6_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 37504 #define MMEA6_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 37505 #define MMEA6_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 37506 #define MMEA6_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 37507 //MMEA6_IO_WR_PRI_URGENCY 37508 #define MMEA6_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 37509 #define MMEA6_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 37510 #define MMEA6_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 37511 #define MMEA6_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 37512 #define MMEA6_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 37513 #define MMEA6_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 37514 #define MMEA6_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 37515 #define MMEA6_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 37516 #define MMEA6_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 37517 #define MMEA6_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 37518 #define MMEA6_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 37519 #define MMEA6_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 37520 #define MMEA6_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 37521 #define MMEA6_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 37522 #define MMEA6_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 37523 #define MMEA6_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 37524 //MMEA6_IO_RD_PRI_URGENCY_MASKING 37525 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 37526 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 37527 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 37528 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 37529 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 37530 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 37531 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 37532 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 37533 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 37534 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 37535 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 37536 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 37537 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 37538 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 37539 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 37540 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 37541 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 37542 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 37543 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 37544 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 37545 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 37546 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 37547 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 37548 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 37549 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 37550 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 37551 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 37552 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 37553 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 37554 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 37555 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 37556 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 37557 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 37558 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 37559 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 37560 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 37561 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 37562 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 37563 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 37564 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 37565 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 37566 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 37567 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 37568 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 37569 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 37570 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 37571 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 37572 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 37573 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 37574 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 37575 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 37576 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 37577 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 37578 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 37579 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 37580 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 37581 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 37582 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 37583 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 37584 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 37585 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 37586 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 37587 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 37588 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 37589 //MMEA6_IO_WR_PRI_URGENCY_MASKING 37590 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 37591 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 37592 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 37593 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 37594 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 37595 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 37596 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 37597 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 37598 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 37599 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 37600 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 37601 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 37602 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 37603 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 37604 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 37605 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 37606 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 37607 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 37608 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 37609 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 37610 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 37611 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 37612 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 37613 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 37614 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 37615 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 37616 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 37617 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 37618 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 37619 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 37620 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 37621 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 37622 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 37623 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 37624 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 37625 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 37626 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 37627 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 37628 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 37629 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 37630 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 37631 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 37632 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 37633 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 37634 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 37635 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 37636 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 37637 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 37638 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 37639 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 37640 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 37641 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 37642 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 37643 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 37644 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 37645 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 37646 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 37647 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 37648 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 37649 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 37650 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 37651 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 37652 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 37653 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 37654 //MMEA6_IO_RD_PRI_QUANT_PRI1 37655 #define MMEA6_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 37656 #define MMEA6_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 37657 #define MMEA6_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 37658 #define MMEA6_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 37659 #define MMEA6_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 37660 #define MMEA6_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 37661 #define MMEA6_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 37662 #define MMEA6_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 37663 //MMEA6_IO_RD_PRI_QUANT_PRI2 37664 #define MMEA6_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 37665 #define MMEA6_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 37666 #define MMEA6_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 37667 #define MMEA6_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 37668 #define MMEA6_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 37669 #define MMEA6_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 37670 #define MMEA6_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 37671 #define MMEA6_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 37672 //MMEA6_IO_RD_PRI_QUANT_PRI3 37673 #define MMEA6_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 37674 #define MMEA6_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 37675 #define MMEA6_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 37676 #define MMEA6_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 37677 #define MMEA6_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 37678 #define MMEA6_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 37679 #define MMEA6_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 37680 #define MMEA6_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 37681 //MMEA6_IO_WR_PRI_QUANT_PRI1 37682 #define MMEA6_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 37683 #define MMEA6_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 37684 #define MMEA6_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 37685 #define MMEA6_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 37686 #define MMEA6_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 37687 #define MMEA6_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 37688 #define MMEA6_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 37689 #define MMEA6_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 37690 //MMEA6_IO_WR_PRI_QUANT_PRI2 37691 #define MMEA6_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 37692 #define MMEA6_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 37693 #define MMEA6_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 37694 #define MMEA6_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 37695 #define MMEA6_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 37696 #define MMEA6_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 37697 #define MMEA6_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 37698 #define MMEA6_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 37699 //MMEA6_IO_WR_PRI_QUANT_PRI3 37700 #define MMEA6_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 37701 #define MMEA6_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 37702 #define MMEA6_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 37703 #define MMEA6_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 37704 #define MMEA6_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 37705 #define MMEA6_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 37706 #define MMEA6_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 37707 #define MMEA6_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 37708 //MMEA6_SDP_ARB_DRAM 37709 #define MMEA6_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 37710 #define MMEA6_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 37711 #define MMEA6_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 37712 #define MMEA6_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 37713 #define MMEA6_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 37714 #define MMEA6_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 37715 #define MMEA6_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 37716 #define MMEA6_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 37717 #define MMEA6_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL 37718 #define MMEA6_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L 37719 #define MMEA6_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L 37720 #define MMEA6_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L 37721 #define MMEA6_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L 37722 #define MMEA6_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L 37723 #define MMEA6_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L 37724 #define MMEA6_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L 37725 //MMEA6_SDP_ARB_GMI 37726 #define MMEA6_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 37727 #define MMEA6_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 37728 #define MMEA6_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT 0x10 37729 #define MMEA6_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT 0x11 37730 #define MMEA6_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT 0x12 37731 #define MMEA6_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT 0x13 37732 #define MMEA6_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT 0x14 37733 #define MMEA6_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 37734 #define MMEA6_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT 0x16 37735 #define MMEA6_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL 37736 #define MMEA6_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L 37737 #define MMEA6_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK 0x00010000L 37738 #define MMEA6_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK 0x00020000L 37739 #define MMEA6_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK 0x00040000L 37740 #define MMEA6_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK 0x00080000L 37741 #define MMEA6_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK 0x00100000L 37742 #define MMEA6_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L 37743 #define MMEA6_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK 0x00400000L 37744 //MMEA6_SDP_ARB_FINAL 37745 #define MMEA6_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 37746 #define MMEA6_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 37747 #define MMEA6_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa 37748 #define MMEA6_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf 37749 #define MMEA6_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 37750 #define MMEA6_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 37751 #define MMEA6_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 37752 #define MMEA6_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 37753 #define MMEA6_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 37754 #define MMEA6_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 37755 #define MMEA6_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 37756 #define MMEA6_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 37757 #define MMEA6_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 37758 #define MMEA6_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a 37759 #define MMEA6_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1b 37760 #define MMEA6_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL 37761 #define MMEA6_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L 37762 #define MMEA6_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L 37763 #define MMEA6_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L 37764 #define MMEA6_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L 37765 #define MMEA6_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L 37766 #define MMEA6_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L 37767 #define MMEA6_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L 37768 #define MMEA6_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L 37769 #define MMEA6_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L 37770 #define MMEA6_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L 37771 #define MMEA6_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L 37772 #define MMEA6_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L 37773 #define MMEA6_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L 37774 #define MMEA6_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x08000000L 37775 //MMEA6_SDP_DRAM_PRIORITY 37776 #define MMEA6_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 37777 #define MMEA6_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 37778 #define MMEA6_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 37779 #define MMEA6_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 37780 #define MMEA6_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 37781 #define MMEA6_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 37782 #define MMEA6_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 37783 #define MMEA6_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 37784 #define MMEA6_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 37785 #define MMEA6_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 37786 #define MMEA6_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 37787 #define MMEA6_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 37788 #define MMEA6_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 37789 #define MMEA6_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 37790 #define MMEA6_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 37791 #define MMEA6_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 37792 //MMEA6_SDP_GMI_PRIORITY 37793 #define MMEA6_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 37794 #define MMEA6_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 37795 #define MMEA6_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 37796 #define MMEA6_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 37797 #define MMEA6_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 37798 #define MMEA6_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 37799 #define MMEA6_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 37800 #define MMEA6_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 37801 #define MMEA6_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 37802 #define MMEA6_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 37803 #define MMEA6_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 37804 #define MMEA6_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 37805 #define MMEA6_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 37806 #define MMEA6_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 37807 #define MMEA6_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 37808 #define MMEA6_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 37809 //MMEA6_SDP_IO_PRIORITY 37810 #define MMEA6_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 37811 #define MMEA6_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 37812 #define MMEA6_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 37813 #define MMEA6_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 37814 #define MMEA6_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 37815 #define MMEA6_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 37816 #define MMEA6_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 37817 #define MMEA6_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 37818 #define MMEA6_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 37819 #define MMEA6_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 37820 #define MMEA6_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 37821 #define MMEA6_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 37822 #define MMEA6_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 37823 #define MMEA6_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 37824 #define MMEA6_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 37825 #define MMEA6_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 37826 //MMEA6_SDP_CREDITS 37827 #define MMEA6_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 37828 #define MMEA6_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 37829 #define MMEA6_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 37830 #define MMEA6_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL 37831 #define MMEA6_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L 37832 #define MMEA6_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L 37833 //MMEA6_SDP_TAG_RESERVE0 37834 #define MMEA6_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 37835 #define MMEA6_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 37836 #define MMEA6_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 37837 #define MMEA6_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 37838 #define MMEA6_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL 37839 #define MMEA6_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L 37840 #define MMEA6_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L 37841 #define MMEA6_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L 37842 //MMEA6_SDP_TAG_RESERVE1 37843 #define MMEA6_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 37844 #define MMEA6_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 37845 #define MMEA6_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 37846 #define MMEA6_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 37847 #define MMEA6_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL 37848 #define MMEA6_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L 37849 #define MMEA6_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L 37850 #define MMEA6_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L 37851 //MMEA6_SDP_VCC_RESERVE0 37852 #define MMEA6_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 37853 #define MMEA6_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 37854 #define MMEA6_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc 37855 #define MMEA6_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 37856 #define MMEA6_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 37857 #define MMEA6_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 37858 #define MMEA6_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 37859 #define MMEA6_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 37860 #define MMEA6_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 37861 #define MMEA6_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 37862 //MMEA6_SDP_VCC_RESERVE1 37863 #define MMEA6_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 37864 #define MMEA6_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 37865 #define MMEA6_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc 37866 #define MMEA6_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 37867 #define MMEA6_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 37868 #define MMEA6_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 37869 #define MMEA6_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 37870 #define MMEA6_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 37871 //MMEA6_SDP_VCD_RESERVE0 37872 #define MMEA6_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 37873 #define MMEA6_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 37874 #define MMEA6_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc 37875 #define MMEA6_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 37876 #define MMEA6_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 37877 #define MMEA6_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 37878 #define MMEA6_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 37879 #define MMEA6_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 37880 #define MMEA6_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 37881 #define MMEA6_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 37882 //MMEA6_SDP_VCD_RESERVE1 37883 #define MMEA6_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 37884 #define MMEA6_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 37885 #define MMEA6_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc 37886 #define MMEA6_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 37887 #define MMEA6_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 37888 #define MMEA6_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 37889 #define MMEA6_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 37890 #define MMEA6_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 37891 //MMEA6_SDP_REQ_CNTL 37892 #define MMEA6_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 37893 #define MMEA6_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 37894 #define MMEA6_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 37895 #define MMEA6_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 37896 #define MMEA6_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 37897 #define MMEA6_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 37898 #define MMEA6_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L 37899 #define MMEA6_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L 37900 #define MMEA6_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L 37901 #define MMEA6_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L 37902 #define MMEA6_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L 37903 #define MMEA6_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L 37904 //MMEA6_MISC 37905 #define MMEA6_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 37906 #define MMEA6_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 37907 #define MMEA6_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 37908 #define MMEA6_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 37909 #define MMEA6_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 37910 #define MMEA6_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 37911 #define MMEA6_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 37912 #define MMEA6_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 37913 #define MMEA6_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 37914 #define MMEA6_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 37915 #define MMEA6_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa 37916 #define MMEA6_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb 37917 #define MMEA6_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc 37918 #define MMEA6_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd 37919 #define MMEA6_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe 37920 #define MMEA6_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf 37921 #define MMEA6_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 37922 #define MMEA6_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 37923 #define MMEA6_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 37924 #define MMEA6_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a 37925 #define MMEA6_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b 37926 #define MMEA6_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c 37927 #define MMEA6_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d 37928 #define MMEA6_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e 37929 #define MMEA6_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f 37930 #define MMEA6_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L 37931 #define MMEA6_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L 37932 #define MMEA6_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L 37933 #define MMEA6_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L 37934 #define MMEA6_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L 37935 #define MMEA6_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L 37936 #define MMEA6_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L 37937 #define MMEA6_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L 37938 #define MMEA6_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L 37939 #define MMEA6_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L 37940 #define MMEA6_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L 37941 #define MMEA6_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L 37942 #define MMEA6_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L 37943 #define MMEA6_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L 37944 #define MMEA6_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L 37945 #define MMEA6_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L 37946 #define MMEA6_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L 37947 #define MMEA6_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L 37948 #define MMEA6_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L 37949 #define MMEA6_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L 37950 #define MMEA6_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L 37951 #define MMEA6_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L 37952 #define MMEA6_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L 37953 #define MMEA6_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L 37954 #define MMEA6_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L 37955 //MMEA6_LATENCY_SAMPLING 37956 #define MMEA6_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 37957 #define MMEA6_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 37958 #define MMEA6_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 37959 #define MMEA6_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 37960 #define MMEA6_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 37961 #define MMEA6_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 37962 #define MMEA6_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 37963 #define MMEA6_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 37964 #define MMEA6_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 37965 #define MMEA6_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 37966 #define MMEA6_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa 37967 #define MMEA6_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb 37968 #define MMEA6_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc 37969 #define MMEA6_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd 37970 #define MMEA6_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe 37971 #define MMEA6_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 37972 #define MMEA6_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L 37973 #define MMEA6_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L 37974 #define MMEA6_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L 37975 #define MMEA6_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L 37976 #define MMEA6_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L 37977 #define MMEA6_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L 37978 #define MMEA6_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L 37979 #define MMEA6_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L 37980 #define MMEA6_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L 37981 #define MMEA6_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L 37982 #define MMEA6_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L 37983 #define MMEA6_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L 37984 #define MMEA6_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L 37985 #define MMEA6_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L 37986 #define MMEA6_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L 37987 #define MMEA6_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L 37988 //MMEA6_PERFCOUNTER_LO 37989 #define MMEA6_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 37990 #define MMEA6_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 37991 //MMEA6_PERFCOUNTER_HI 37992 #define MMEA6_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 37993 #define MMEA6_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 37994 #define MMEA6_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 37995 #define MMEA6_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 37996 //MMEA6_PERFCOUNTER0_CFG 37997 #define MMEA6_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 37998 #define MMEA6_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 37999 #define MMEA6_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 38000 #define MMEA6_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 38001 #define MMEA6_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 38002 #define MMEA6_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 38003 #define MMEA6_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 38004 #define MMEA6_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 38005 #define MMEA6_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 38006 #define MMEA6_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 38007 //MMEA6_PERFCOUNTER1_CFG 38008 #define MMEA6_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 38009 #define MMEA6_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 38010 #define MMEA6_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 38011 #define MMEA6_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 38012 #define MMEA6_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 38013 #define MMEA6_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 38014 #define MMEA6_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 38015 #define MMEA6_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 38016 #define MMEA6_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 38017 #define MMEA6_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 38018 //MMEA6_PERFCOUNTER_RSLT_CNTL 38019 #define MMEA6_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 38020 #define MMEA6_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 38021 #define MMEA6_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 38022 #define MMEA6_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 38023 #define MMEA6_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 38024 #define MMEA6_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 38025 #define MMEA6_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 38026 #define MMEA6_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 38027 #define MMEA6_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 38028 #define MMEA6_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 38029 #define MMEA6_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 38030 #define MMEA6_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 38031 //MMEA6_EDC_CNT 38032 #define MMEA6_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 38033 #define MMEA6_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 38034 #define MMEA6_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 38035 #define MMEA6_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 38036 #define MMEA6_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 38037 #define MMEA6_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa 38038 #define MMEA6_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc 38039 #define MMEA6_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe 38040 #define MMEA6_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 38041 #define MMEA6_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 38042 #define MMEA6_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 38043 #define MMEA6_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 38044 #define MMEA6_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 38045 #define MMEA6_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a 38046 #define MMEA6_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c 38047 #define MMEA6_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 38048 #define MMEA6_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 38049 #define MMEA6_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 38050 #define MMEA6_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 38051 #define MMEA6_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 38052 #define MMEA6_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 38053 #define MMEA6_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L 38054 #define MMEA6_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L 38055 #define MMEA6_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L 38056 #define MMEA6_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L 38057 #define MMEA6_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L 38058 #define MMEA6_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L 38059 #define MMEA6_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L 38060 #define MMEA6_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L 38061 #define MMEA6_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L 38062 //MMEA6_EDC_CNT2 38063 #define MMEA6_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 38064 #define MMEA6_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 38065 #define MMEA6_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 38066 #define MMEA6_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 38067 #define MMEA6_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 38068 #define MMEA6_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa 38069 #define MMEA6_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc 38070 #define MMEA6_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe 38071 #define MMEA6_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10 38072 #define MMEA6_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12 38073 #define MMEA6_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14 38074 #define MMEA6_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16 38075 #define MMEA6_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT 0x18 38076 #define MMEA6_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT 0x1a 38077 #define MMEA6_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT 0x1c 38078 #define MMEA6_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT 0x1e 38079 #define MMEA6_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 38080 #define MMEA6_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 38081 #define MMEA6_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 38082 #define MMEA6_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 38083 #define MMEA6_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 38084 #define MMEA6_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 38085 #define MMEA6_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L 38086 #define MMEA6_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L 38087 #define MMEA6_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L 38088 #define MMEA6_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L 38089 #define MMEA6_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L 38090 #define MMEA6_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L 38091 #define MMEA6_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK 0x03000000L 38092 #define MMEA6_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK 0x0C000000L 38093 #define MMEA6_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK 0x30000000L 38094 #define MMEA6_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK 0xC0000000L 38095 //MMEA6_DSM_CNTL 38096 #define MMEA6_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 38097 #define MMEA6_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 38098 #define MMEA6_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 38099 #define MMEA6_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 38100 #define MMEA6_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 38101 #define MMEA6_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 38102 #define MMEA6_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 38103 #define MMEA6_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 38104 #define MMEA6_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 38105 #define MMEA6_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 38106 #define MMEA6_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 38107 #define MMEA6_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 38108 #define MMEA6_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 38109 #define MMEA6_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 38110 #define MMEA6_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 38111 #define MMEA6_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 38112 #define MMEA6_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 38113 #define MMEA6_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 38114 #define MMEA6_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 38115 #define MMEA6_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 38116 #define MMEA6_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 38117 #define MMEA6_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 38118 #define MMEA6_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 38119 #define MMEA6_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 38120 #define MMEA6_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 38121 #define MMEA6_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 38122 #define MMEA6_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 38123 #define MMEA6_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 38124 #define MMEA6_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 38125 #define MMEA6_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 38126 #define MMEA6_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L 38127 #define MMEA6_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L 38128 //MMEA6_DSM_CNTLA 38129 #define MMEA6_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 38130 #define MMEA6_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 38131 #define MMEA6_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 38132 #define MMEA6_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 38133 #define MMEA6_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 38134 #define MMEA6_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 38135 #define MMEA6_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 38136 #define MMEA6_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 38137 #define MMEA6_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 38138 #define MMEA6_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 38139 #define MMEA6_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 38140 #define MMEA6_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 38141 #define MMEA6_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 38142 #define MMEA6_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 38143 #define MMEA6_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 38144 #define MMEA6_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 38145 #define MMEA6_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 38146 #define MMEA6_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 38147 #define MMEA6_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 38148 #define MMEA6_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 38149 #define MMEA6_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 38150 #define MMEA6_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 38151 #define MMEA6_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 38152 #define MMEA6_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 38153 #define MMEA6_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 38154 #define MMEA6_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 38155 #define MMEA6_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 38156 #define MMEA6_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 38157 //MMEA6_DSM_CNTL2 38158 #define MMEA6_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 38159 #define MMEA6_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 38160 #define MMEA6_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 38161 #define MMEA6_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 38162 #define MMEA6_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 38163 #define MMEA6_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 38164 #define MMEA6_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 38165 #define MMEA6_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb 38166 #define MMEA6_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 38167 #define MMEA6_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe 38168 #define MMEA6_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 38169 #define MMEA6_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 38170 #define MMEA6_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 38171 #define MMEA6_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 38172 #define MMEA6_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 38173 #define MMEA6_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 38174 #define MMEA6_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a 38175 #define MMEA6_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 38176 #define MMEA6_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 38177 #define MMEA6_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 38178 #define MMEA6_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 38179 #define MMEA6_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 38180 #define MMEA6_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 38181 #define MMEA6_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 38182 #define MMEA6_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 38183 #define MMEA6_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 38184 #define MMEA6_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 38185 #define MMEA6_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 38186 #define MMEA6_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 38187 #define MMEA6_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 38188 #define MMEA6_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 38189 #define MMEA6_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L 38190 #define MMEA6_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L 38191 #define MMEA6_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L 38192 //MMEA6_DSM_CNTL2A 38193 #define MMEA6_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 38194 #define MMEA6_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 38195 #define MMEA6_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 38196 #define MMEA6_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 38197 #define MMEA6_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 38198 #define MMEA6_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 38199 #define MMEA6_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 38200 #define MMEA6_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb 38201 #define MMEA6_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 38202 #define MMEA6_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe 38203 #define MMEA6_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 38204 #define MMEA6_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 38205 #define MMEA6_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 38206 #define MMEA6_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 38207 #define MMEA6_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 38208 #define MMEA6_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 38209 #define MMEA6_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 38210 #define MMEA6_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 38211 #define MMEA6_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 38212 #define MMEA6_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 38213 #define MMEA6_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 38214 #define MMEA6_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 38215 #define MMEA6_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 38216 #define MMEA6_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 38217 #define MMEA6_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 38218 #define MMEA6_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 38219 #define MMEA6_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 38220 #define MMEA6_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 38221 //MMEA6_CGTT_CLK_CTRL 38222 #define MMEA6_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 38223 #define MMEA6_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 38224 #define MMEA6_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc 38225 #define MMEA6_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 38226 #define MMEA6_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 38227 #define MMEA6_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 38228 #define MMEA6_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 38229 #define MMEA6_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 38230 #define MMEA6_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c 38231 #define MMEA6_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d 38232 #define MMEA6_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e 38233 #define MMEA6_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f 38234 #define MMEA6_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 38235 #define MMEA6_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 38236 #define MMEA6_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L 38237 #define MMEA6_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L 38238 #define MMEA6_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L 38239 #define MMEA6_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L 38240 #define MMEA6_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L 38241 #define MMEA6_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 38242 #define MMEA6_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L 38243 #define MMEA6_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L 38244 #define MMEA6_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L 38245 #define MMEA6_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L 38246 //MMEA6_EDC_MODE 38247 #define MMEA6_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 38248 #define MMEA6_EDC_MODE__GATE_FUE__SHIFT 0x11 38249 #define MMEA6_EDC_MODE__DED_MODE__SHIFT 0x14 38250 #define MMEA6_EDC_MODE__PROP_FED__SHIFT 0x1d 38251 #define MMEA6_EDC_MODE__BYPASS__SHIFT 0x1f 38252 #define MMEA6_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L 38253 #define MMEA6_EDC_MODE__GATE_FUE_MASK 0x00020000L 38254 #define MMEA6_EDC_MODE__DED_MODE_MASK 0x00300000L 38255 #define MMEA6_EDC_MODE__PROP_FED_MASK 0x20000000L 38256 #define MMEA6_EDC_MODE__BYPASS_MASK 0x80000000L 38257 //MMEA6_ERR_STATUS 38258 #define MMEA6_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 38259 #define MMEA6_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 38260 #define MMEA6_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 38261 #define MMEA6_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa 38262 #define MMEA6_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb 38263 #define MMEA6_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc 38264 #define MMEA6_ERR_STATUS__FUE_FLAG__SHIFT 0xd 38265 #define MMEA6_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL 38266 #define MMEA6_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L 38267 #define MMEA6_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L 38268 #define MMEA6_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L 38269 #define MMEA6_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L 38270 #define MMEA6_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L 38271 #define MMEA6_ERR_STATUS__FUE_FLAG_MASK 0x00002000L 38272 //MMEA6_MISC2 38273 #define MMEA6_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 38274 #define MMEA6_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 38275 #define MMEA6_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 38276 #define MMEA6_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 38277 #define MMEA6_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc 38278 #define MMEA6_MISC2__RRET_SWAP_MODE__SHIFT 0xd 38279 #define MMEA6_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L 38280 #define MMEA6_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L 38281 #define MMEA6_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL 38282 #define MMEA6_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L 38283 #define MMEA6_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L 38284 #define MMEA6_MISC2__RRET_SWAP_MODE_MASK 0x00002000L 38285 //MMEA6_ADDRDEC_SELECT 38286 #define MMEA6_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0 38287 #define MMEA6_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5 38288 #define MMEA6_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa 38289 #define MMEA6_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf 38290 #define MMEA6_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL 38291 #define MMEA6_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L 38292 #define MMEA6_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L 38293 #define MMEA6_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L 38294 //MMEA6_EDC_CNT3 38295 #define MMEA6_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0 38296 #define MMEA6_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2 38297 #define MMEA6_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4 38298 #define MMEA6_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6 38299 #define MMEA6_EDC_CNT3__IOWR_DATAMEM_DED_COUNT__SHIFT 0x8 38300 #define MMEA6_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0xa 38301 #define MMEA6_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xc 38302 #define MMEA6_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L 38303 #define MMEA6_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL 38304 #define MMEA6_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L 38305 #define MMEA6_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 38306 #define MMEA6_EDC_CNT3__IOWR_DATAMEM_DED_COUNT_MASK 0x00000300L 38307 #define MMEA6_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000C00L 38308 #define MMEA6_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00003000L 38309 38310 38311 // addressBlock: mmhub_ea_mmeadec7 38312 //MMEA7_DRAM_RD_CLI2GRP_MAP0 38313 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 38314 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 38315 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 38316 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 38317 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 38318 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 38319 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 38320 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 38321 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 38322 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 38323 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 38324 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 38325 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 38326 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 38327 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 38328 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 38329 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 38330 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 38331 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 38332 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 38333 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 38334 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 38335 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 38336 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 38337 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 38338 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 38339 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 38340 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 38341 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 38342 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 38343 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 38344 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 38345 //MMEA7_DRAM_RD_CLI2GRP_MAP1 38346 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 38347 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 38348 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 38349 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 38350 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 38351 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 38352 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 38353 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 38354 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 38355 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 38356 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 38357 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 38358 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 38359 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 38360 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 38361 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 38362 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 38363 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 38364 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 38365 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 38366 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 38367 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 38368 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 38369 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 38370 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 38371 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 38372 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 38373 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 38374 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 38375 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 38376 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 38377 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 38378 //MMEA7_DRAM_WR_CLI2GRP_MAP0 38379 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 38380 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 38381 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 38382 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 38383 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 38384 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 38385 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 38386 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 38387 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 38388 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 38389 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 38390 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 38391 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 38392 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 38393 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 38394 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 38395 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 38396 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 38397 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 38398 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 38399 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 38400 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 38401 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 38402 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 38403 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 38404 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 38405 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 38406 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 38407 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 38408 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 38409 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 38410 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 38411 //MMEA7_DRAM_WR_CLI2GRP_MAP1 38412 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 38413 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 38414 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 38415 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 38416 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 38417 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 38418 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 38419 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 38420 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 38421 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 38422 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 38423 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 38424 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 38425 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 38426 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 38427 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 38428 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 38429 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 38430 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 38431 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 38432 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 38433 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 38434 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 38435 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 38436 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 38437 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 38438 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 38439 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 38440 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 38441 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 38442 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 38443 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 38444 //MMEA7_DRAM_RD_GRP2VC_MAP 38445 #define MMEA7_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 38446 #define MMEA7_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 38447 #define MMEA7_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 38448 #define MMEA7_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 38449 #define MMEA7_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 38450 #define MMEA7_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 38451 #define MMEA7_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 38452 #define MMEA7_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 38453 //MMEA7_DRAM_WR_GRP2VC_MAP 38454 #define MMEA7_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 38455 #define MMEA7_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 38456 #define MMEA7_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 38457 #define MMEA7_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 38458 #define MMEA7_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 38459 #define MMEA7_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 38460 #define MMEA7_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 38461 #define MMEA7_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 38462 //MMEA7_DRAM_RD_LAZY 38463 #define MMEA7_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 38464 #define MMEA7_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 38465 #define MMEA7_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 38466 #define MMEA7_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 38467 #define MMEA7_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 38468 #define MMEA7_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 38469 #define MMEA7_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 38470 #define MMEA7_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L 38471 #define MMEA7_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L 38472 #define MMEA7_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L 38473 #define MMEA7_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L 38474 #define MMEA7_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 38475 #define MMEA7_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 38476 #define MMEA7_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 38477 //MMEA7_DRAM_WR_LAZY 38478 #define MMEA7_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 38479 #define MMEA7_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 38480 #define MMEA7_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 38481 #define MMEA7_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 38482 #define MMEA7_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 38483 #define MMEA7_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 38484 #define MMEA7_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 38485 #define MMEA7_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L 38486 #define MMEA7_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L 38487 #define MMEA7_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L 38488 #define MMEA7_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L 38489 #define MMEA7_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 38490 #define MMEA7_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 38491 #define MMEA7_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 38492 //MMEA7_DRAM_RD_CAM_CNTL 38493 #define MMEA7_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 38494 #define MMEA7_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 38495 #define MMEA7_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 38496 #define MMEA7_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 38497 #define MMEA7_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 38498 #define MMEA7_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 38499 #define MMEA7_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 38500 #define MMEA7_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 38501 #define MMEA7_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 38502 #define MMEA7_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 38503 #define MMEA7_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 38504 #define MMEA7_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 38505 #define MMEA7_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 38506 #define MMEA7_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 38507 #define MMEA7_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 38508 #define MMEA7_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 38509 #define MMEA7_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 38510 #define MMEA7_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 38511 //MMEA7_DRAM_WR_CAM_CNTL 38512 #define MMEA7_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 38513 #define MMEA7_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 38514 #define MMEA7_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 38515 #define MMEA7_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 38516 #define MMEA7_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 38517 #define MMEA7_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 38518 #define MMEA7_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 38519 #define MMEA7_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 38520 #define MMEA7_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 38521 #define MMEA7_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 38522 #define MMEA7_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 38523 #define MMEA7_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 38524 #define MMEA7_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 38525 #define MMEA7_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 38526 #define MMEA7_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 38527 #define MMEA7_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 38528 #define MMEA7_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 38529 #define MMEA7_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 38530 //MMEA7_DRAM_PAGE_BURST 38531 #define MMEA7_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 38532 #define MMEA7_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 38533 #define MMEA7_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 38534 #define MMEA7_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 38535 #define MMEA7_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL 38536 #define MMEA7_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 38537 #define MMEA7_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 38538 #define MMEA7_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L 38539 //MMEA7_DRAM_RD_PRI_AGE 38540 #define MMEA7_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 38541 #define MMEA7_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 38542 #define MMEA7_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 38543 #define MMEA7_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 38544 #define MMEA7_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 38545 #define MMEA7_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 38546 #define MMEA7_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 38547 #define MMEA7_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 38548 #define MMEA7_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 38549 #define MMEA7_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 38550 #define MMEA7_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 38551 #define MMEA7_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 38552 #define MMEA7_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 38553 #define MMEA7_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 38554 #define MMEA7_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 38555 #define MMEA7_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 38556 //MMEA7_DRAM_WR_PRI_AGE 38557 #define MMEA7_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 38558 #define MMEA7_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 38559 #define MMEA7_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 38560 #define MMEA7_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 38561 #define MMEA7_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 38562 #define MMEA7_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 38563 #define MMEA7_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 38564 #define MMEA7_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 38565 #define MMEA7_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 38566 #define MMEA7_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 38567 #define MMEA7_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 38568 #define MMEA7_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 38569 #define MMEA7_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 38570 #define MMEA7_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 38571 #define MMEA7_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 38572 #define MMEA7_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 38573 //MMEA7_DRAM_RD_PRI_QUEUING 38574 #define MMEA7_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 38575 #define MMEA7_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 38576 #define MMEA7_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 38577 #define MMEA7_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 38578 #define MMEA7_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 38579 #define MMEA7_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 38580 #define MMEA7_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 38581 #define MMEA7_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 38582 //MMEA7_DRAM_WR_PRI_QUEUING 38583 #define MMEA7_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 38584 #define MMEA7_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 38585 #define MMEA7_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 38586 #define MMEA7_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 38587 #define MMEA7_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 38588 #define MMEA7_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 38589 #define MMEA7_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 38590 #define MMEA7_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 38591 //MMEA7_DRAM_RD_PRI_FIXED 38592 #define MMEA7_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 38593 #define MMEA7_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 38594 #define MMEA7_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 38595 #define MMEA7_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 38596 #define MMEA7_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 38597 #define MMEA7_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 38598 #define MMEA7_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 38599 #define MMEA7_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 38600 //MMEA7_DRAM_WR_PRI_FIXED 38601 #define MMEA7_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 38602 #define MMEA7_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 38603 #define MMEA7_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 38604 #define MMEA7_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 38605 #define MMEA7_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 38606 #define MMEA7_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 38607 #define MMEA7_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 38608 #define MMEA7_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 38609 //MMEA7_DRAM_RD_PRI_URGENCY 38610 #define MMEA7_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 38611 #define MMEA7_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 38612 #define MMEA7_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 38613 #define MMEA7_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 38614 #define MMEA7_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 38615 #define MMEA7_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 38616 #define MMEA7_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 38617 #define MMEA7_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 38618 #define MMEA7_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 38619 #define MMEA7_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 38620 #define MMEA7_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 38621 #define MMEA7_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 38622 #define MMEA7_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 38623 #define MMEA7_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 38624 #define MMEA7_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 38625 #define MMEA7_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 38626 //MMEA7_DRAM_WR_PRI_URGENCY 38627 #define MMEA7_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 38628 #define MMEA7_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 38629 #define MMEA7_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 38630 #define MMEA7_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 38631 #define MMEA7_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 38632 #define MMEA7_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 38633 #define MMEA7_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 38634 #define MMEA7_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 38635 #define MMEA7_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 38636 #define MMEA7_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 38637 #define MMEA7_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 38638 #define MMEA7_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 38639 #define MMEA7_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 38640 #define MMEA7_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 38641 #define MMEA7_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 38642 #define MMEA7_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 38643 //MMEA7_DRAM_RD_PRI_QUANT_PRI1 38644 #define MMEA7_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 38645 #define MMEA7_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 38646 #define MMEA7_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 38647 #define MMEA7_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 38648 #define MMEA7_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 38649 #define MMEA7_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 38650 #define MMEA7_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 38651 #define MMEA7_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 38652 //MMEA7_DRAM_RD_PRI_QUANT_PRI2 38653 #define MMEA7_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 38654 #define MMEA7_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 38655 #define MMEA7_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 38656 #define MMEA7_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 38657 #define MMEA7_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 38658 #define MMEA7_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 38659 #define MMEA7_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 38660 #define MMEA7_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 38661 //MMEA7_DRAM_RD_PRI_QUANT_PRI3 38662 #define MMEA7_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 38663 #define MMEA7_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 38664 #define MMEA7_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 38665 #define MMEA7_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 38666 #define MMEA7_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 38667 #define MMEA7_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 38668 #define MMEA7_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 38669 #define MMEA7_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 38670 //MMEA7_DRAM_WR_PRI_QUANT_PRI1 38671 #define MMEA7_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 38672 #define MMEA7_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 38673 #define MMEA7_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 38674 #define MMEA7_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 38675 #define MMEA7_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 38676 #define MMEA7_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 38677 #define MMEA7_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 38678 #define MMEA7_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 38679 //MMEA7_DRAM_WR_PRI_QUANT_PRI2 38680 #define MMEA7_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 38681 #define MMEA7_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 38682 #define MMEA7_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 38683 #define MMEA7_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 38684 #define MMEA7_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 38685 #define MMEA7_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 38686 #define MMEA7_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 38687 #define MMEA7_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 38688 //MMEA7_DRAM_WR_PRI_QUANT_PRI3 38689 #define MMEA7_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 38690 #define MMEA7_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 38691 #define MMEA7_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 38692 #define MMEA7_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 38693 #define MMEA7_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 38694 #define MMEA7_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 38695 #define MMEA7_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 38696 #define MMEA7_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 38697 //MMEA7_GMI_RD_CLI2GRP_MAP0 38698 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 38699 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 38700 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 38701 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 38702 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 38703 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 38704 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 38705 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 38706 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 38707 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 38708 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 38709 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 38710 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 38711 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 38712 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 38713 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 38714 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 38715 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 38716 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 38717 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 38718 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 38719 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 38720 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 38721 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 38722 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 38723 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 38724 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 38725 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 38726 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 38727 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 38728 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 38729 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 38730 //MMEA7_GMI_RD_CLI2GRP_MAP1 38731 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 38732 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 38733 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 38734 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 38735 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 38736 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 38737 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 38738 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 38739 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 38740 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 38741 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 38742 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 38743 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 38744 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 38745 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 38746 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 38747 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 38748 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 38749 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 38750 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 38751 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 38752 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 38753 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 38754 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 38755 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 38756 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 38757 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 38758 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 38759 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 38760 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 38761 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 38762 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 38763 //MMEA7_GMI_WR_CLI2GRP_MAP0 38764 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 38765 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 38766 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 38767 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 38768 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 38769 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 38770 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 38771 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 38772 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 38773 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 38774 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 38775 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 38776 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 38777 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 38778 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 38779 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 38780 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 38781 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 38782 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 38783 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 38784 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 38785 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 38786 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 38787 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 38788 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 38789 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 38790 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 38791 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 38792 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 38793 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 38794 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 38795 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 38796 //MMEA7_GMI_WR_CLI2GRP_MAP1 38797 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 38798 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 38799 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 38800 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 38801 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 38802 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 38803 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 38804 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 38805 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 38806 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 38807 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 38808 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 38809 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 38810 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 38811 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 38812 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 38813 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 38814 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 38815 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 38816 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 38817 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 38818 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 38819 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 38820 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 38821 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 38822 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 38823 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 38824 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 38825 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 38826 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 38827 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 38828 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 38829 //MMEA7_GMI_RD_GRP2VC_MAP 38830 #define MMEA7_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 38831 #define MMEA7_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 38832 #define MMEA7_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 38833 #define MMEA7_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 38834 #define MMEA7_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 38835 #define MMEA7_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 38836 #define MMEA7_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 38837 #define MMEA7_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 38838 //MMEA7_GMI_WR_GRP2VC_MAP 38839 #define MMEA7_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 38840 #define MMEA7_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 38841 #define MMEA7_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 38842 #define MMEA7_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 38843 #define MMEA7_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 38844 #define MMEA7_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 38845 #define MMEA7_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 38846 #define MMEA7_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 38847 //MMEA7_GMI_RD_LAZY 38848 #define MMEA7_GMI_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 38849 #define MMEA7_GMI_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 38850 #define MMEA7_GMI_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 38851 #define MMEA7_GMI_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 38852 #define MMEA7_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 38853 #define MMEA7_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 38854 #define MMEA7_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 38855 #define MMEA7_GMI_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L 38856 #define MMEA7_GMI_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L 38857 #define MMEA7_GMI_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L 38858 #define MMEA7_GMI_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L 38859 #define MMEA7_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 38860 #define MMEA7_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 38861 #define MMEA7_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 38862 //MMEA7_GMI_WR_LAZY 38863 #define MMEA7_GMI_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 38864 #define MMEA7_GMI_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 38865 #define MMEA7_GMI_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 38866 #define MMEA7_GMI_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 38867 #define MMEA7_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 38868 #define MMEA7_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 38869 #define MMEA7_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 38870 #define MMEA7_GMI_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L 38871 #define MMEA7_GMI_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L 38872 #define MMEA7_GMI_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L 38873 #define MMEA7_GMI_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L 38874 #define MMEA7_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 38875 #define MMEA7_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 38876 #define MMEA7_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 38877 //MMEA7_GMI_RD_CAM_CNTL 38878 #define MMEA7_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 38879 #define MMEA7_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 38880 #define MMEA7_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 38881 #define MMEA7_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 38882 #define MMEA7_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 38883 #define MMEA7_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 38884 #define MMEA7_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 38885 #define MMEA7_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 38886 #define MMEA7_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 38887 #define MMEA7_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d 38888 #define MMEA7_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 38889 #define MMEA7_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 38890 #define MMEA7_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 38891 #define MMEA7_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 38892 #define MMEA7_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 38893 #define MMEA7_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 38894 #define MMEA7_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 38895 #define MMEA7_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 38896 #define MMEA7_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 38897 #define MMEA7_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L 38898 //MMEA7_GMI_WR_CAM_CNTL 38899 #define MMEA7_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 38900 #define MMEA7_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 38901 #define MMEA7_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 38902 #define MMEA7_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 38903 #define MMEA7_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 38904 #define MMEA7_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 38905 #define MMEA7_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 38906 #define MMEA7_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 38907 #define MMEA7_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 38908 #define MMEA7_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d 38909 #define MMEA7_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 38910 #define MMEA7_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 38911 #define MMEA7_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 38912 #define MMEA7_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 38913 #define MMEA7_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 38914 #define MMEA7_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 38915 #define MMEA7_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 38916 #define MMEA7_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 38917 #define MMEA7_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 38918 #define MMEA7_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L 38919 //MMEA7_GMI_PAGE_BURST 38920 #define MMEA7_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 38921 #define MMEA7_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 38922 #define MMEA7_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 38923 #define MMEA7_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 38924 #define MMEA7_GMI_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL 38925 #define MMEA7_GMI_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 38926 #define MMEA7_GMI_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 38927 #define MMEA7_GMI_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L 38928 //MMEA7_GMI_RD_PRI_AGE 38929 #define MMEA7_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 38930 #define MMEA7_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 38931 #define MMEA7_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 38932 #define MMEA7_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 38933 #define MMEA7_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 38934 #define MMEA7_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 38935 #define MMEA7_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 38936 #define MMEA7_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 38937 #define MMEA7_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 38938 #define MMEA7_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 38939 #define MMEA7_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 38940 #define MMEA7_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 38941 #define MMEA7_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 38942 #define MMEA7_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 38943 #define MMEA7_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 38944 #define MMEA7_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 38945 //MMEA7_GMI_WR_PRI_AGE 38946 #define MMEA7_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 38947 #define MMEA7_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 38948 #define MMEA7_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 38949 #define MMEA7_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 38950 #define MMEA7_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 38951 #define MMEA7_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 38952 #define MMEA7_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 38953 #define MMEA7_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 38954 #define MMEA7_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 38955 #define MMEA7_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 38956 #define MMEA7_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 38957 #define MMEA7_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 38958 #define MMEA7_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 38959 #define MMEA7_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 38960 #define MMEA7_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 38961 #define MMEA7_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 38962 //MMEA7_GMI_RD_PRI_QUEUING 38963 #define MMEA7_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 38964 #define MMEA7_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 38965 #define MMEA7_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 38966 #define MMEA7_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 38967 #define MMEA7_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 38968 #define MMEA7_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 38969 #define MMEA7_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 38970 #define MMEA7_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 38971 //MMEA7_GMI_WR_PRI_QUEUING 38972 #define MMEA7_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 38973 #define MMEA7_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 38974 #define MMEA7_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 38975 #define MMEA7_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 38976 #define MMEA7_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 38977 #define MMEA7_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 38978 #define MMEA7_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 38979 #define MMEA7_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 38980 //MMEA7_GMI_RD_PRI_FIXED 38981 #define MMEA7_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 38982 #define MMEA7_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 38983 #define MMEA7_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 38984 #define MMEA7_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 38985 #define MMEA7_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 38986 #define MMEA7_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 38987 #define MMEA7_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 38988 #define MMEA7_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 38989 //MMEA7_GMI_WR_PRI_FIXED 38990 #define MMEA7_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 38991 #define MMEA7_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 38992 #define MMEA7_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 38993 #define MMEA7_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 38994 #define MMEA7_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 38995 #define MMEA7_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 38996 #define MMEA7_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 38997 #define MMEA7_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 38998 //MMEA7_GMI_RD_PRI_URGENCY 38999 #define MMEA7_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 39000 #define MMEA7_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 39001 #define MMEA7_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 39002 #define MMEA7_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 39003 #define MMEA7_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 39004 #define MMEA7_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 39005 #define MMEA7_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 39006 #define MMEA7_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 39007 #define MMEA7_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 39008 #define MMEA7_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 39009 #define MMEA7_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 39010 #define MMEA7_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 39011 #define MMEA7_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 39012 #define MMEA7_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 39013 #define MMEA7_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 39014 #define MMEA7_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 39015 //MMEA7_GMI_WR_PRI_URGENCY 39016 #define MMEA7_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 39017 #define MMEA7_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 39018 #define MMEA7_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 39019 #define MMEA7_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 39020 #define MMEA7_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 39021 #define MMEA7_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 39022 #define MMEA7_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 39023 #define MMEA7_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 39024 #define MMEA7_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 39025 #define MMEA7_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 39026 #define MMEA7_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 39027 #define MMEA7_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 39028 #define MMEA7_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 39029 #define MMEA7_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 39030 #define MMEA7_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 39031 #define MMEA7_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 39032 //MMEA7_GMI_RD_PRI_URGENCY_MASKING 39033 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 39034 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 39035 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 39036 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 39037 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 39038 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 39039 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 39040 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 39041 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 39042 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 39043 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 39044 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 39045 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 39046 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 39047 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 39048 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 39049 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 39050 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 39051 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 39052 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 39053 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 39054 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 39055 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 39056 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 39057 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 39058 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 39059 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 39060 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 39061 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 39062 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 39063 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 39064 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 39065 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 39066 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 39067 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 39068 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 39069 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 39070 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 39071 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 39072 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 39073 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 39074 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 39075 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 39076 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 39077 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 39078 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 39079 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 39080 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 39081 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 39082 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 39083 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 39084 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 39085 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 39086 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 39087 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 39088 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 39089 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 39090 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 39091 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 39092 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 39093 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 39094 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 39095 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 39096 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 39097 //MMEA7_GMI_WR_PRI_URGENCY_MASKING 39098 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 39099 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 39100 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 39101 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 39102 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 39103 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 39104 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 39105 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 39106 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 39107 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 39108 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 39109 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 39110 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 39111 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 39112 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 39113 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 39114 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 39115 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 39116 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 39117 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 39118 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 39119 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 39120 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 39121 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 39122 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 39123 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 39124 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 39125 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 39126 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 39127 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 39128 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 39129 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 39130 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 39131 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 39132 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 39133 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 39134 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 39135 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 39136 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 39137 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 39138 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 39139 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 39140 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 39141 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 39142 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 39143 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 39144 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 39145 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 39146 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 39147 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 39148 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 39149 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 39150 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 39151 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 39152 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 39153 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 39154 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 39155 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 39156 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 39157 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 39158 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 39159 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 39160 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 39161 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 39162 //MMEA7_GMI_RD_PRI_QUANT_PRI1 39163 #define MMEA7_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 39164 #define MMEA7_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 39165 #define MMEA7_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 39166 #define MMEA7_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 39167 #define MMEA7_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 39168 #define MMEA7_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 39169 #define MMEA7_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 39170 #define MMEA7_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 39171 //MMEA7_GMI_RD_PRI_QUANT_PRI2 39172 #define MMEA7_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 39173 #define MMEA7_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 39174 #define MMEA7_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 39175 #define MMEA7_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 39176 #define MMEA7_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 39177 #define MMEA7_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 39178 #define MMEA7_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 39179 #define MMEA7_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 39180 //MMEA7_GMI_RD_PRI_QUANT_PRI3 39181 #define MMEA7_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 39182 #define MMEA7_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 39183 #define MMEA7_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 39184 #define MMEA7_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 39185 #define MMEA7_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 39186 #define MMEA7_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 39187 #define MMEA7_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 39188 #define MMEA7_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 39189 //MMEA7_GMI_WR_PRI_QUANT_PRI1 39190 #define MMEA7_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 39191 #define MMEA7_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 39192 #define MMEA7_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 39193 #define MMEA7_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 39194 #define MMEA7_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 39195 #define MMEA7_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 39196 #define MMEA7_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 39197 #define MMEA7_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 39198 //MMEA7_GMI_WR_PRI_QUANT_PRI2 39199 #define MMEA7_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 39200 #define MMEA7_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 39201 #define MMEA7_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 39202 #define MMEA7_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 39203 #define MMEA7_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 39204 #define MMEA7_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 39205 #define MMEA7_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 39206 #define MMEA7_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 39207 //MMEA7_GMI_WR_PRI_QUANT_PRI3 39208 #define MMEA7_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 39209 #define MMEA7_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 39210 #define MMEA7_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 39211 #define MMEA7_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 39212 #define MMEA7_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 39213 #define MMEA7_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 39214 #define MMEA7_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 39215 #define MMEA7_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 39216 //MMEA7_ADDRNORM_BASE_ADDR0 39217 #define MMEA7_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 39218 #define MMEA7_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 39219 #define MMEA7_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 39220 #define MMEA7_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x6 39221 #define MMEA7_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 39222 #define MMEA7_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 39223 #define MMEA7_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc 39224 #define MMEA7_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L 39225 #define MMEA7_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 39226 #define MMEA7_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000003CL 39227 #define MMEA7_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x000000C0L 39228 #define MMEA7_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L 39229 #define MMEA7_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L 39230 #define MMEA7_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L 39231 //MMEA7_ADDRNORM_LIMIT_ADDR0 39232 #define MMEA7_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 39233 #define MMEA7_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc 39234 #define MMEA7_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL 39235 #define MMEA7_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L 39236 //MMEA7_ADDRNORM_BASE_ADDR1 39237 #define MMEA7_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 39238 #define MMEA7_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 39239 #define MMEA7_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 39240 #define MMEA7_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x6 39241 #define MMEA7_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 39242 #define MMEA7_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 39243 #define MMEA7_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc 39244 #define MMEA7_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L 39245 #define MMEA7_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 39246 #define MMEA7_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000003CL 39247 #define MMEA7_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x000000C0L 39248 #define MMEA7_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L 39249 #define MMEA7_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L 39250 #define MMEA7_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L 39251 //MMEA7_ADDRNORM_LIMIT_ADDR1 39252 #define MMEA7_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 39253 #define MMEA7_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc 39254 #define MMEA7_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL 39255 #define MMEA7_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L 39256 //MMEA7_ADDRNORM_OFFSET_ADDR1 39257 #define MMEA7_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 39258 #define MMEA7_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 39259 #define MMEA7_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L 39260 #define MMEA7_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L 39261 //MMEA7_ADDRNORM_BASE_ADDR2 39262 #define MMEA7_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT 0x0 39263 #define MMEA7_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT 0x1 39264 #define MMEA7_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT 0x2 39265 #define MMEA7_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT 0x6 39266 #define MMEA7_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT 0x8 39267 #define MMEA7_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT 0x9 39268 #define MMEA7_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT 0xc 39269 #define MMEA7_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK 0x00000001L 39270 #define MMEA7_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 39271 #define MMEA7_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK 0x0000003CL 39272 #define MMEA7_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK 0x000000C0L 39273 #define MMEA7_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK 0x00000100L 39274 #define MMEA7_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK 0x00000E00L 39275 #define MMEA7_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK 0xFFFFF000L 39276 //MMEA7_ADDRNORM_LIMIT_ADDR2 39277 #define MMEA7_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT 0x0 39278 #define MMEA7_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT 0xc 39279 #define MMEA7_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK 0x0000001FL 39280 #define MMEA7_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK 0xFFFFF000L 39281 //MMEA7_ADDRNORM_BASE_ADDR3 39282 #define MMEA7_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT 0x0 39283 #define MMEA7_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT 0x1 39284 #define MMEA7_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT 0x2 39285 #define MMEA7_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT 0x6 39286 #define MMEA7_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT 0x8 39287 #define MMEA7_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT 0x9 39288 #define MMEA7_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT 0xc 39289 #define MMEA7_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK 0x00000001L 39290 #define MMEA7_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 39291 #define MMEA7_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK 0x0000003CL 39292 #define MMEA7_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK 0x000000C0L 39293 #define MMEA7_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK 0x00000100L 39294 #define MMEA7_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK 0x00000E00L 39295 #define MMEA7_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK 0xFFFFF000L 39296 //MMEA7_ADDRNORM_LIMIT_ADDR3 39297 #define MMEA7_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT 0x0 39298 #define MMEA7_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT 0xc 39299 #define MMEA7_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK 0x0000001FL 39300 #define MMEA7_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK 0xFFFFF000L 39301 //MMEA7_ADDRNORM_OFFSET_ADDR3 39302 #define MMEA7_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT 0x0 39303 #define MMEA7_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT 0x14 39304 #define MMEA7_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK 0x00000001L 39305 #define MMEA7_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK 0xFFF00000L 39306 //MMEA7_ADDRNORM_BASE_ADDR4 39307 #define MMEA7_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL__SHIFT 0x0 39308 #define MMEA7_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN__SHIFT 0x1 39309 #define MMEA7_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN__SHIFT 0x2 39310 #define MMEA7_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES__SHIFT 0x6 39311 #define MMEA7_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS__SHIFT 0x8 39312 #define MMEA7_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL__SHIFT 0x9 39313 #define MMEA7_ADDRNORM_BASE_ADDR4__BASE_ADDR__SHIFT 0xc 39314 #define MMEA7_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL_MASK 0x00000001L 39315 #define MMEA7_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 39316 #define MMEA7_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN_MASK 0x0000003CL 39317 #define MMEA7_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES_MASK 0x000000C0L 39318 #define MMEA7_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS_MASK 0x00000100L 39319 #define MMEA7_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL_MASK 0x00000E00L 39320 #define MMEA7_ADDRNORM_BASE_ADDR4__BASE_ADDR_MASK 0xFFFFF000L 39321 //MMEA7_ADDRNORM_LIMIT_ADDR4 39322 #define MMEA7_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID__SHIFT 0x0 39323 #define MMEA7_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR__SHIFT 0xc 39324 #define MMEA7_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID_MASK 0x0000001FL 39325 #define MMEA7_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR_MASK 0xFFFFF000L 39326 //MMEA7_ADDRNORM_BASE_ADDR5 39327 #define MMEA7_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL__SHIFT 0x0 39328 #define MMEA7_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN__SHIFT 0x1 39329 #define MMEA7_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN__SHIFT 0x2 39330 #define MMEA7_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES__SHIFT 0x6 39331 #define MMEA7_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS__SHIFT 0x8 39332 #define MMEA7_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL__SHIFT 0x9 39333 #define MMEA7_ADDRNORM_BASE_ADDR5__BASE_ADDR__SHIFT 0xc 39334 #define MMEA7_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL_MASK 0x00000001L 39335 #define MMEA7_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 39336 #define MMEA7_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN_MASK 0x0000003CL 39337 #define MMEA7_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES_MASK 0x000000C0L 39338 #define MMEA7_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS_MASK 0x00000100L 39339 #define MMEA7_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL_MASK 0x00000E00L 39340 #define MMEA7_ADDRNORM_BASE_ADDR5__BASE_ADDR_MASK 0xFFFFF000L 39341 //MMEA7_ADDRNORM_LIMIT_ADDR5 39342 #define MMEA7_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID__SHIFT 0x0 39343 #define MMEA7_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR__SHIFT 0xc 39344 #define MMEA7_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID_MASK 0x0000001FL 39345 #define MMEA7_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR_MASK 0xFFFFF000L 39346 //MMEA7_ADDRNORM_OFFSET_ADDR5 39347 #define MMEA7_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN__SHIFT 0x0 39348 #define MMEA7_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET__SHIFT 0x14 39349 #define MMEA7_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN_MASK 0x00000001L 39350 #define MMEA7_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_MASK 0xFFF00000L 39351 //MMEA7_ADDRNORMDRAM_HOLE_CNTL 39352 #define MMEA7_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 39353 #define MMEA7_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 39354 #define MMEA7_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L 39355 #define MMEA7_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L 39356 //MMEA7_ADDRNORMGMI_HOLE_CNTL 39357 #define MMEA7_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 39358 #define MMEA7_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 39359 #define MMEA7_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L 39360 #define MMEA7_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L 39361 //MMEA7_ADDRNORMDRAM_NP2_CHANNEL_CFG 39362 #define MMEA7_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0 39363 #define MMEA7_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6 39364 #define MMEA7_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL 39365 #define MMEA7_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L 39366 //MMEA7_ADDRNORMGMI_NP2_CHANNEL_CFG 39367 #define MMEA7_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT 0x0 39368 #define MMEA7_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT 0x6 39369 #define MMEA7_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK 0x0000003FL 39370 #define MMEA7_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK 0x00000FC0L 39371 //MMEA7_ADDRDEC_BANK_CFG 39372 #define MMEA7_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 39373 #define MMEA7_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x6 39374 #define MMEA7_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xc 39375 #define MMEA7_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xf 39376 #define MMEA7_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x12 39377 #define MMEA7_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x13 39378 #define MMEA7_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000003FL 39379 #define MMEA7_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x00000FC0L 39380 #define MMEA7_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00007000L 39381 #define MMEA7_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x00038000L 39382 #define MMEA7_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00040000L 39383 #define MMEA7_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00080000L 39384 //MMEA7_ADDRDEC_MISC_CFG 39385 #define MMEA7_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 39386 #define MMEA7_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 39387 #define MMEA7_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 39388 #define MMEA7_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 39389 #define MMEA7_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 39390 #define MMEA7_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc 39391 #define MMEA7_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11 39392 #define MMEA7_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16 39393 #define MMEA7_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18 39394 #define MMEA7_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a 39395 #define MMEA7_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d 39396 #define MMEA7_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L 39397 #define MMEA7_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L 39398 #define MMEA7_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L 39399 #define MMEA7_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L 39400 #define MMEA7_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L 39401 #define MMEA7_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L 39402 #define MMEA7_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L 39403 #define MMEA7_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L 39404 #define MMEA7_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L 39405 #define MMEA7_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L 39406 #define MMEA7_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L 39407 //MMEA7_ADDRDECDRAM_ADDR_HASH_BANK0 39408 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 39409 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 39410 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe 39411 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L 39412 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL 39413 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L 39414 //MMEA7_ADDRDECDRAM_ADDR_HASH_BANK1 39415 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 39416 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 39417 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe 39418 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L 39419 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL 39420 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L 39421 //MMEA7_ADDRDECDRAM_ADDR_HASH_BANK2 39422 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 39423 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 39424 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe 39425 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L 39426 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL 39427 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L 39428 //MMEA7_ADDRDECDRAM_ADDR_HASH_BANK3 39429 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 39430 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 39431 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe 39432 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L 39433 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL 39434 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L 39435 //MMEA7_ADDRDECDRAM_ADDR_HASH_BANK4 39436 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 39437 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 39438 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe 39439 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L 39440 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL 39441 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L 39442 //MMEA7_ADDRDECDRAM_ADDR_HASH_BANK5 39443 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT 0x0 39444 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR__SHIFT 0x1 39445 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR__SHIFT 0xe 39446 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE_MASK 0x00000001L 39447 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR_MASK 0x00003FFEL 39448 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR_MASK 0xFFFFC000L 39449 //MMEA7_ADDRDECDRAM_ADDR_HASH_PC 39450 #define MMEA7_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 39451 #define MMEA7_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 39452 #define MMEA7_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe 39453 #define MMEA7_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L 39454 #define MMEA7_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL 39455 #define MMEA7_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L 39456 //MMEA7_ADDRDECDRAM_ADDR_HASH_PC2 39457 #define MMEA7_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 39458 #define MMEA7_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000003FL 39459 //MMEA7_ADDRDECDRAM_ADDR_HASH_CS0 39460 #define MMEA7_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 39461 #define MMEA7_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 39462 #define MMEA7_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L 39463 #define MMEA7_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL 39464 //MMEA7_ADDRDECDRAM_ADDR_HASH_CS1 39465 #define MMEA7_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 39466 #define MMEA7_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 39467 #define MMEA7_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L 39468 #define MMEA7_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL 39469 //MMEA7_ADDRDECDRAM_HARVEST_ENABLE 39470 #define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 39471 #define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 39472 #define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 39473 #define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 39474 #define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 39475 #define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 39476 #define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L 39477 #define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L 39478 #define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L 39479 #define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L 39480 #define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L 39481 #define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L 39482 //MMEA7_ADDRDECGMI_ADDR_HASH_BANK0 39483 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 39484 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 39485 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe 39486 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L 39487 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL 39488 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L 39489 //MMEA7_ADDRDECGMI_ADDR_HASH_BANK1 39490 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 39491 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 39492 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe 39493 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L 39494 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL 39495 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L 39496 //MMEA7_ADDRDECGMI_ADDR_HASH_BANK2 39497 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 39498 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 39499 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe 39500 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L 39501 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL 39502 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L 39503 //MMEA7_ADDRDECGMI_ADDR_HASH_BANK3 39504 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 39505 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 39506 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe 39507 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L 39508 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL 39509 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L 39510 //MMEA7_ADDRDECGMI_ADDR_HASH_BANK4 39511 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 39512 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 39513 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe 39514 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L 39515 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL 39516 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L 39517 //MMEA7_ADDRDECGMI_ADDR_HASH_BANK5 39518 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT 0x0 39519 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR__SHIFT 0x1 39520 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR__SHIFT 0xe 39521 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE_MASK 0x00000001L 39522 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR_MASK 0x00003FFEL 39523 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR_MASK 0xFFFFC000L 39524 //MMEA7_ADDRDECGMI_ADDR_HASH_PC 39525 #define MMEA7_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 39526 #define MMEA7_ADDRDECGMI_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 39527 #define MMEA7_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe 39528 #define MMEA7_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L 39529 #define MMEA7_ADDRDECGMI_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL 39530 #define MMEA7_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L 39531 //MMEA7_ADDRDECGMI_ADDR_HASH_PC2 39532 #define MMEA7_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 39533 #define MMEA7_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000003FL 39534 //MMEA7_ADDRDECGMI_ADDR_HASH_CS0 39535 #define MMEA7_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 39536 #define MMEA7_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 39537 #define MMEA7_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L 39538 #define MMEA7_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL 39539 //MMEA7_ADDRDECGMI_ADDR_HASH_CS1 39540 #define MMEA7_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 39541 #define MMEA7_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 39542 #define MMEA7_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L 39543 #define MMEA7_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL 39544 //MMEA7_ADDRDECGMI_HARVEST_ENABLE 39545 #define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 39546 #define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 39547 #define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 39548 #define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 39549 #define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 39550 #define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 39551 #define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L 39552 #define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L 39553 #define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L 39554 #define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L 39555 #define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L 39556 #define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L 39557 //MMEA7_ADDRDEC0_BASE_ADDR_CS0 39558 #define MMEA7_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 39559 #define MMEA7_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 39560 #define MMEA7_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 39561 #define MMEA7_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 39562 //MMEA7_ADDRDEC0_BASE_ADDR_CS1 39563 #define MMEA7_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 39564 #define MMEA7_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 39565 #define MMEA7_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 39566 #define MMEA7_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 39567 //MMEA7_ADDRDEC0_BASE_ADDR_CS2 39568 #define MMEA7_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 39569 #define MMEA7_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 39570 #define MMEA7_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 39571 #define MMEA7_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 39572 //MMEA7_ADDRDEC0_BASE_ADDR_CS3 39573 #define MMEA7_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 39574 #define MMEA7_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 39575 #define MMEA7_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 39576 #define MMEA7_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 39577 //MMEA7_ADDRDEC0_BASE_ADDR_SECCS0 39578 #define MMEA7_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 39579 #define MMEA7_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 39580 #define MMEA7_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 39581 #define MMEA7_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 39582 //MMEA7_ADDRDEC0_BASE_ADDR_SECCS1 39583 #define MMEA7_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 39584 #define MMEA7_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 39585 #define MMEA7_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 39586 #define MMEA7_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 39587 //MMEA7_ADDRDEC0_BASE_ADDR_SECCS2 39588 #define MMEA7_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 39589 #define MMEA7_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 39590 #define MMEA7_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 39591 #define MMEA7_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 39592 //MMEA7_ADDRDEC0_BASE_ADDR_SECCS3 39593 #define MMEA7_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 39594 #define MMEA7_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 39595 #define MMEA7_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 39596 #define MMEA7_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 39597 //MMEA7_ADDRDEC0_ADDR_MASK_CS01 39598 #define MMEA7_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 39599 #define MMEA7_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 39600 //MMEA7_ADDRDEC0_ADDR_MASK_CS23 39601 #define MMEA7_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 39602 #define MMEA7_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 39603 //MMEA7_ADDRDEC0_ADDR_MASK_SECCS01 39604 #define MMEA7_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 39605 #define MMEA7_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 39606 //MMEA7_ADDRDEC0_ADDR_MASK_SECCS23 39607 #define MMEA7_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 39608 #define MMEA7_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 39609 //MMEA7_ADDRDEC0_ADDR_CFG_CS01 39610 #define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 39611 #define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 39612 #define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 39613 #define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 39614 #define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 39615 #define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 39616 #define MMEA7_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 39617 #define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 39618 #define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 39619 #define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 39620 #define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 39621 #define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 39622 #define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 39623 #define MMEA7_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 39624 //MMEA7_ADDRDEC0_ADDR_CFG_CS23 39625 #define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 39626 #define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 39627 #define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 39628 #define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 39629 #define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 39630 #define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 39631 #define MMEA7_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 39632 #define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 39633 #define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 39634 #define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 39635 #define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 39636 #define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 39637 #define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 39638 #define MMEA7_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 39639 //MMEA7_ADDRDEC0_ADDR_SEL_CS01 39640 #define MMEA7_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 39641 #define MMEA7_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 39642 #define MMEA7_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 39643 #define MMEA7_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc 39644 #define MMEA7_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 39645 #define MMEA7_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 39646 #define MMEA7_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 39647 #define MMEA7_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 39648 #define MMEA7_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 39649 #define MMEA7_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 39650 #define MMEA7_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 39651 #define MMEA7_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 39652 #define MMEA7_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 39653 #define MMEA7_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 39654 //MMEA7_ADDRDEC0_ADDR_SEL_CS23 39655 #define MMEA7_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 39656 #define MMEA7_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 39657 #define MMEA7_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 39658 #define MMEA7_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc 39659 #define MMEA7_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 39660 #define MMEA7_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 39661 #define MMEA7_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 39662 #define MMEA7_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 39663 #define MMEA7_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 39664 #define MMEA7_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 39665 #define MMEA7_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 39666 #define MMEA7_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 39667 #define MMEA7_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 39668 #define MMEA7_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 39669 //MMEA7_ADDRDEC0_ADDR_SEL2_CS01 39670 #define MMEA7_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 39671 #define MMEA7_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 39672 //MMEA7_ADDRDEC0_ADDR_SEL2_CS23 39673 #define MMEA7_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 39674 #define MMEA7_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 39675 //MMEA7_ADDRDEC0_COL_SEL_LO_CS01 39676 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 39677 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 39678 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 39679 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc 39680 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 39681 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 39682 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 39683 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 39684 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 39685 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 39686 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 39687 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 39688 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 39689 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 39690 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 39691 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 39692 //MMEA7_ADDRDEC0_COL_SEL_LO_CS23 39693 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 39694 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 39695 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 39696 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc 39697 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 39698 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 39699 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 39700 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 39701 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 39702 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 39703 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 39704 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 39705 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 39706 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 39707 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 39708 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 39709 //MMEA7_ADDRDEC0_COL_SEL_HI_CS01 39710 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 39711 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 39712 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 39713 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc 39714 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 39715 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 39716 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 39717 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 39718 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 39719 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 39720 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 39721 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 39722 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 39723 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 39724 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 39725 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 39726 //MMEA7_ADDRDEC0_COL_SEL_HI_CS23 39727 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 39728 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 39729 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 39730 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc 39731 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 39732 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 39733 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 39734 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 39735 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 39736 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 39737 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 39738 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 39739 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 39740 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 39741 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 39742 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 39743 //MMEA7_ADDRDEC0_RM_SEL_CS01 39744 #define MMEA7_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 39745 #define MMEA7_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 39746 #define MMEA7_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 39747 #define MMEA7_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 39748 #define MMEA7_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 39749 #define MMEA7_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 39750 #define MMEA7_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL 39751 #define MMEA7_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L 39752 #define MMEA7_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L 39753 #define MMEA7_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 39754 #define MMEA7_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 39755 #define MMEA7_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 39756 //MMEA7_ADDRDEC0_RM_SEL_CS23 39757 #define MMEA7_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 39758 #define MMEA7_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 39759 #define MMEA7_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 39760 #define MMEA7_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 39761 #define MMEA7_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 39762 #define MMEA7_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 39763 #define MMEA7_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL 39764 #define MMEA7_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L 39765 #define MMEA7_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L 39766 #define MMEA7_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 39767 #define MMEA7_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 39768 #define MMEA7_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 39769 //MMEA7_ADDRDEC0_RM_SEL_SECCS01 39770 #define MMEA7_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 39771 #define MMEA7_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 39772 #define MMEA7_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 39773 #define MMEA7_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 39774 #define MMEA7_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 39775 #define MMEA7_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 39776 #define MMEA7_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 39777 #define MMEA7_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 39778 #define MMEA7_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 39779 #define MMEA7_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 39780 #define MMEA7_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 39781 #define MMEA7_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 39782 //MMEA7_ADDRDEC0_RM_SEL_SECCS23 39783 #define MMEA7_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 39784 #define MMEA7_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 39785 #define MMEA7_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 39786 #define MMEA7_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 39787 #define MMEA7_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 39788 #define MMEA7_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 39789 #define MMEA7_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 39790 #define MMEA7_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 39791 #define MMEA7_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 39792 #define MMEA7_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 39793 #define MMEA7_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 39794 #define MMEA7_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 39795 //MMEA7_ADDRDEC1_BASE_ADDR_CS0 39796 #define MMEA7_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 39797 #define MMEA7_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 39798 #define MMEA7_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 39799 #define MMEA7_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 39800 //MMEA7_ADDRDEC1_BASE_ADDR_CS1 39801 #define MMEA7_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 39802 #define MMEA7_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 39803 #define MMEA7_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 39804 #define MMEA7_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 39805 //MMEA7_ADDRDEC1_BASE_ADDR_CS2 39806 #define MMEA7_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 39807 #define MMEA7_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 39808 #define MMEA7_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 39809 #define MMEA7_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 39810 //MMEA7_ADDRDEC1_BASE_ADDR_CS3 39811 #define MMEA7_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 39812 #define MMEA7_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 39813 #define MMEA7_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 39814 #define MMEA7_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 39815 //MMEA7_ADDRDEC1_BASE_ADDR_SECCS0 39816 #define MMEA7_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 39817 #define MMEA7_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 39818 #define MMEA7_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 39819 #define MMEA7_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 39820 //MMEA7_ADDRDEC1_BASE_ADDR_SECCS1 39821 #define MMEA7_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 39822 #define MMEA7_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 39823 #define MMEA7_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 39824 #define MMEA7_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 39825 //MMEA7_ADDRDEC1_BASE_ADDR_SECCS2 39826 #define MMEA7_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 39827 #define MMEA7_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 39828 #define MMEA7_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 39829 #define MMEA7_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 39830 //MMEA7_ADDRDEC1_BASE_ADDR_SECCS3 39831 #define MMEA7_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 39832 #define MMEA7_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 39833 #define MMEA7_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 39834 #define MMEA7_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 39835 //MMEA7_ADDRDEC1_ADDR_MASK_CS01 39836 #define MMEA7_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 39837 #define MMEA7_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 39838 //MMEA7_ADDRDEC1_ADDR_MASK_CS23 39839 #define MMEA7_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 39840 #define MMEA7_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 39841 //MMEA7_ADDRDEC1_ADDR_MASK_SECCS01 39842 #define MMEA7_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 39843 #define MMEA7_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 39844 //MMEA7_ADDRDEC1_ADDR_MASK_SECCS23 39845 #define MMEA7_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 39846 #define MMEA7_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 39847 //MMEA7_ADDRDEC1_ADDR_CFG_CS01 39848 #define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 39849 #define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 39850 #define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 39851 #define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 39852 #define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 39853 #define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 39854 #define MMEA7_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 39855 #define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 39856 #define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 39857 #define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 39858 #define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 39859 #define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 39860 #define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 39861 #define MMEA7_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 39862 //MMEA7_ADDRDEC1_ADDR_CFG_CS23 39863 #define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 39864 #define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 39865 #define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 39866 #define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 39867 #define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 39868 #define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 39869 #define MMEA7_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 39870 #define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 39871 #define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 39872 #define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 39873 #define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 39874 #define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 39875 #define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 39876 #define MMEA7_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 39877 //MMEA7_ADDRDEC1_ADDR_SEL_CS01 39878 #define MMEA7_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 39879 #define MMEA7_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 39880 #define MMEA7_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 39881 #define MMEA7_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc 39882 #define MMEA7_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 39883 #define MMEA7_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 39884 #define MMEA7_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 39885 #define MMEA7_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 39886 #define MMEA7_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 39887 #define MMEA7_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 39888 #define MMEA7_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 39889 #define MMEA7_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 39890 #define MMEA7_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 39891 #define MMEA7_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 39892 //MMEA7_ADDRDEC1_ADDR_SEL_CS23 39893 #define MMEA7_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 39894 #define MMEA7_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 39895 #define MMEA7_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 39896 #define MMEA7_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc 39897 #define MMEA7_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 39898 #define MMEA7_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 39899 #define MMEA7_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 39900 #define MMEA7_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 39901 #define MMEA7_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 39902 #define MMEA7_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 39903 #define MMEA7_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 39904 #define MMEA7_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 39905 #define MMEA7_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 39906 #define MMEA7_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 39907 //MMEA7_ADDRDEC1_ADDR_SEL2_CS01 39908 #define MMEA7_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 39909 #define MMEA7_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 39910 //MMEA7_ADDRDEC1_ADDR_SEL2_CS23 39911 #define MMEA7_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 39912 #define MMEA7_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 39913 //MMEA7_ADDRDEC1_COL_SEL_LO_CS01 39914 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 39915 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 39916 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 39917 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc 39918 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 39919 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 39920 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 39921 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 39922 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 39923 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 39924 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 39925 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 39926 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 39927 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 39928 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 39929 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 39930 //MMEA7_ADDRDEC1_COL_SEL_LO_CS23 39931 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 39932 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 39933 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 39934 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc 39935 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 39936 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 39937 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 39938 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 39939 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 39940 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 39941 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 39942 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 39943 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 39944 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 39945 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 39946 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 39947 //MMEA7_ADDRDEC1_COL_SEL_HI_CS01 39948 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 39949 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 39950 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 39951 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc 39952 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 39953 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 39954 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 39955 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 39956 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 39957 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 39958 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 39959 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 39960 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 39961 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 39962 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 39963 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 39964 //MMEA7_ADDRDEC1_COL_SEL_HI_CS23 39965 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 39966 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 39967 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 39968 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc 39969 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 39970 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 39971 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 39972 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 39973 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 39974 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 39975 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 39976 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 39977 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 39978 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 39979 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 39980 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 39981 //MMEA7_ADDRDEC1_RM_SEL_CS01 39982 #define MMEA7_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 39983 #define MMEA7_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 39984 #define MMEA7_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 39985 #define MMEA7_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 39986 #define MMEA7_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 39987 #define MMEA7_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 39988 #define MMEA7_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL 39989 #define MMEA7_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L 39990 #define MMEA7_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L 39991 #define MMEA7_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 39992 #define MMEA7_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 39993 #define MMEA7_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 39994 //MMEA7_ADDRDEC1_RM_SEL_CS23 39995 #define MMEA7_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 39996 #define MMEA7_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 39997 #define MMEA7_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 39998 #define MMEA7_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 39999 #define MMEA7_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 40000 #define MMEA7_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 40001 #define MMEA7_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL 40002 #define MMEA7_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L 40003 #define MMEA7_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L 40004 #define MMEA7_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 40005 #define MMEA7_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 40006 #define MMEA7_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 40007 //MMEA7_ADDRDEC1_RM_SEL_SECCS01 40008 #define MMEA7_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 40009 #define MMEA7_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 40010 #define MMEA7_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 40011 #define MMEA7_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 40012 #define MMEA7_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 40013 #define MMEA7_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 40014 #define MMEA7_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 40015 #define MMEA7_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 40016 #define MMEA7_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 40017 #define MMEA7_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 40018 #define MMEA7_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 40019 #define MMEA7_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 40020 //MMEA7_ADDRDEC1_RM_SEL_SECCS23 40021 #define MMEA7_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 40022 #define MMEA7_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 40023 #define MMEA7_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 40024 #define MMEA7_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 40025 #define MMEA7_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 40026 #define MMEA7_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 40027 #define MMEA7_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 40028 #define MMEA7_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 40029 #define MMEA7_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 40030 #define MMEA7_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 40031 #define MMEA7_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 40032 #define MMEA7_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 40033 //MMEA7_ADDRDEC2_BASE_ADDR_CS0 40034 #define MMEA7_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 40035 #define MMEA7_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 40036 #define MMEA7_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 40037 #define MMEA7_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 40038 //MMEA7_ADDRDEC2_BASE_ADDR_CS1 40039 #define MMEA7_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 40040 #define MMEA7_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 40041 #define MMEA7_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 40042 #define MMEA7_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 40043 //MMEA7_ADDRDEC2_BASE_ADDR_CS2 40044 #define MMEA7_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 40045 #define MMEA7_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 40046 #define MMEA7_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 40047 #define MMEA7_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 40048 //MMEA7_ADDRDEC2_BASE_ADDR_CS3 40049 #define MMEA7_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 40050 #define MMEA7_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 40051 #define MMEA7_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 40052 #define MMEA7_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 40053 //MMEA7_ADDRDEC2_BASE_ADDR_SECCS0 40054 #define MMEA7_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 40055 #define MMEA7_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 40056 #define MMEA7_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 40057 #define MMEA7_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 40058 //MMEA7_ADDRDEC2_BASE_ADDR_SECCS1 40059 #define MMEA7_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 40060 #define MMEA7_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 40061 #define MMEA7_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 40062 #define MMEA7_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 40063 //MMEA7_ADDRDEC2_BASE_ADDR_SECCS2 40064 #define MMEA7_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 40065 #define MMEA7_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 40066 #define MMEA7_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 40067 #define MMEA7_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 40068 //MMEA7_ADDRDEC2_BASE_ADDR_SECCS3 40069 #define MMEA7_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 40070 #define MMEA7_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 40071 #define MMEA7_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 40072 #define MMEA7_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 40073 //MMEA7_ADDRDEC2_ADDR_MASK_CS01 40074 #define MMEA7_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 40075 #define MMEA7_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 40076 //MMEA7_ADDRDEC2_ADDR_MASK_CS23 40077 #define MMEA7_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 40078 #define MMEA7_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 40079 //MMEA7_ADDRDEC2_ADDR_MASK_SECCS01 40080 #define MMEA7_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 40081 #define MMEA7_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 40082 //MMEA7_ADDRDEC2_ADDR_MASK_SECCS23 40083 #define MMEA7_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 40084 #define MMEA7_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 40085 //MMEA7_ADDRDEC2_ADDR_CFG_CS01 40086 #define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 40087 #define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 40088 #define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 40089 #define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 40090 #define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 40091 #define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 40092 #define MMEA7_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 40093 #define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 40094 #define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 40095 #define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 40096 #define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 40097 #define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 40098 #define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 40099 #define MMEA7_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 40100 //MMEA7_ADDRDEC2_ADDR_CFG_CS23 40101 #define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 40102 #define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 40103 #define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 40104 #define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 40105 #define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 40106 #define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 40107 #define MMEA7_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 40108 #define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 40109 #define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 40110 #define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 40111 #define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 40112 #define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 40113 #define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 40114 #define MMEA7_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 40115 //MMEA7_ADDRDEC2_ADDR_SEL_CS01 40116 #define MMEA7_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT 0x0 40117 #define MMEA7_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT 0x4 40118 #define MMEA7_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT 0x8 40119 #define MMEA7_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT 0xc 40120 #define MMEA7_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT 0x10 40121 #define MMEA7_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 40122 #define MMEA7_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 40123 #define MMEA7_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 40124 #define MMEA7_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 40125 #define MMEA7_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 40126 #define MMEA7_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 40127 #define MMEA7_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 40128 #define MMEA7_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 40129 #define MMEA7_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 40130 //MMEA7_ADDRDEC2_ADDR_SEL_CS23 40131 #define MMEA7_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT 0x0 40132 #define MMEA7_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT 0x4 40133 #define MMEA7_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT 0x8 40134 #define MMEA7_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT 0xc 40135 #define MMEA7_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT 0x10 40136 #define MMEA7_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 40137 #define MMEA7_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 40138 #define MMEA7_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 40139 #define MMEA7_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 40140 #define MMEA7_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 40141 #define MMEA7_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 40142 #define MMEA7_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 40143 #define MMEA7_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 40144 #define MMEA7_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 40145 //MMEA7_ADDRDEC2_ADDR_SEL2_CS01 40146 #define MMEA7_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 40147 #define MMEA7_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 40148 //MMEA7_ADDRDEC2_ADDR_SEL2_CS23 40149 #define MMEA7_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 40150 #define MMEA7_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 40151 //MMEA7_ADDRDEC2_COL_SEL_LO_CS01 40152 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT 0x0 40153 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT 0x4 40154 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT 0x8 40155 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT 0xc 40156 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT 0x10 40157 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT 0x14 40158 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT 0x18 40159 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 40160 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 40161 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 40162 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 40163 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 40164 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 40165 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 40166 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 40167 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 40168 //MMEA7_ADDRDEC2_COL_SEL_LO_CS23 40169 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT 0x0 40170 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT 0x4 40171 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT 0x8 40172 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT 0xc 40173 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT 0x10 40174 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT 0x14 40175 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT 0x18 40176 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 40177 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 40178 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 40179 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 40180 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 40181 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 40182 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 40183 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 40184 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 40185 //MMEA7_ADDRDEC2_COL_SEL_HI_CS01 40186 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT 0x0 40187 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT 0x4 40188 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT 0x8 40189 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT 0xc 40190 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT 0x10 40191 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT 0x14 40192 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT 0x18 40193 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 40194 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 40195 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 40196 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 40197 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 40198 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 40199 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 40200 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 40201 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 40202 //MMEA7_ADDRDEC2_COL_SEL_HI_CS23 40203 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT 0x0 40204 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT 0x4 40205 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT 0x8 40206 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT 0xc 40207 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT 0x10 40208 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT 0x14 40209 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT 0x18 40210 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 40211 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 40212 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 40213 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 40214 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 40215 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 40216 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 40217 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 40218 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 40219 //MMEA7_ADDRDEC2_RM_SEL_CS01 40220 #define MMEA7_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT 0x0 40221 #define MMEA7_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT 0x4 40222 #define MMEA7_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT 0x8 40223 #define MMEA7_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 40224 #define MMEA7_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 40225 #define MMEA7_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 40226 #define MMEA7_ADDRDEC2_RM_SEL_CS01__RM0_MASK 0x0000000FL 40227 #define MMEA7_ADDRDEC2_RM_SEL_CS01__RM1_MASK 0x000000F0L 40228 #define MMEA7_ADDRDEC2_RM_SEL_CS01__RM2_MASK 0x00000F00L 40229 #define MMEA7_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 40230 #define MMEA7_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 40231 #define MMEA7_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 40232 //MMEA7_ADDRDEC2_RM_SEL_CS23 40233 #define MMEA7_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT 0x0 40234 #define MMEA7_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT 0x4 40235 #define MMEA7_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT 0x8 40236 #define MMEA7_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 40237 #define MMEA7_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 40238 #define MMEA7_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 40239 #define MMEA7_ADDRDEC2_RM_SEL_CS23__RM0_MASK 0x0000000FL 40240 #define MMEA7_ADDRDEC2_RM_SEL_CS23__RM1_MASK 0x000000F0L 40241 #define MMEA7_ADDRDEC2_RM_SEL_CS23__RM2_MASK 0x00000F00L 40242 #define MMEA7_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 40243 #define MMEA7_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 40244 #define MMEA7_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 40245 //MMEA7_ADDRDEC2_RM_SEL_SECCS01 40246 #define MMEA7_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT 0x0 40247 #define MMEA7_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT 0x4 40248 #define MMEA7_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT 0x8 40249 #define MMEA7_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 40250 #define MMEA7_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 40251 #define MMEA7_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 40252 #define MMEA7_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 40253 #define MMEA7_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 40254 #define MMEA7_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 40255 #define MMEA7_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 40256 #define MMEA7_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 40257 #define MMEA7_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 40258 //MMEA7_ADDRDEC2_RM_SEL_SECCS23 40259 #define MMEA7_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT 0x0 40260 #define MMEA7_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT 0x4 40261 #define MMEA7_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT 0x8 40262 #define MMEA7_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 40263 #define MMEA7_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 40264 #define MMEA7_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 40265 #define MMEA7_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 40266 #define MMEA7_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 40267 #define MMEA7_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 40268 #define MMEA7_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 40269 #define MMEA7_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 40270 #define MMEA7_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 40271 //MMEA7_ADDRNORMDRAM_GLOBAL_CNTL 40272 #define MMEA7_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT 0x14 40273 #define MMEA7_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT 0x15 40274 #define MMEA7_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT 0x16 40275 #define MMEA7_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK 0x00100000L 40276 #define MMEA7_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK 0x00200000L 40277 #define MMEA7_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK 0x00400000L 40278 //MMEA7_ADDRNORMGMI_GLOBAL_CNTL 40279 #define MMEA7_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT 0x14 40280 #define MMEA7_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT 0x15 40281 #define MMEA7_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT 0x16 40282 #define MMEA7_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK 0x00100000L 40283 #define MMEA7_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK 0x00200000L 40284 #define MMEA7_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK 0x00400000L 40285 //MMEA7_IO_RD_CLI2GRP_MAP0 40286 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 40287 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 40288 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 40289 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 40290 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 40291 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 40292 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 40293 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 40294 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 40295 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 40296 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 40297 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 40298 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 40299 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 40300 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 40301 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 40302 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 40303 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 40304 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 40305 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 40306 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 40307 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 40308 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 40309 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 40310 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 40311 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 40312 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 40313 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 40314 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 40315 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 40316 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 40317 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 40318 //MMEA7_IO_RD_CLI2GRP_MAP1 40319 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 40320 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 40321 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 40322 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 40323 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 40324 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 40325 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 40326 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 40327 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 40328 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 40329 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 40330 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 40331 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 40332 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 40333 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 40334 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 40335 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 40336 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 40337 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 40338 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 40339 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 40340 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 40341 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 40342 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 40343 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 40344 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 40345 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 40346 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 40347 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 40348 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 40349 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 40350 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 40351 //MMEA7_IO_WR_CLI2GRP_MAP0 40352 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 40353 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 40354 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 40355 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 40356 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 40357 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 40358 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 40359 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 40360 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 40361 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 40362 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 40363 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 40364 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 40365 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 40366 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 40367 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 40368 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 40369 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 40370 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 40371 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 40372 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 40373 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 40374 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 40375 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 40376 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 40377 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 40378 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 40379 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 40380 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 40381 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 40382 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 40383 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 40384 //MMEA7_IO_WR_CLI2GRP_MAP1 40385 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 40386 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 40387 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 40388 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 40389 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 40390 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 40391 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 40392 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 40393 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 40394 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 40395 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 40396 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 40397 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 40398 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 40399 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 40400 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 40401 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 40402 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 40403 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 40404 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 40405 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 40406 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 40407 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 40408 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 40409 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 40410 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 40411 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 40412 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 40413 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 40414 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 40415 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 40416 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 40417 //MMEA7_IO_RD_COMBINE_FLUSH 40418 #define MMEA7_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 40419 #define MMEA7_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 40420 #define MMEA7_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 40421 #define MMEA7_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 40422 #define MMEA7_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT 0x10 40423 #define MMEA7_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 40424 #define MMEA7_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 40425 #define MMEA7_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 40426 #define MMEA7_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 40427 #define MMEA7_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK 0x00010000L 40428 //MMEA7_IO_WR_COMBINE_FLUSH 40429 #define MMEA7_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 40430 #define MMEA7_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 40431 #define MMEA7_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 40432 #define MMEA7_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 40433 #define MMEA7_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT 0x10 40434 #define MMEA7_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 40435 #define MMEA7_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 40436 #define MMEA7_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 40437 #define MMEA7_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 40438 #define MMEA7_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK 0x00010000L 40439 //MMEA7_IO_GROUP_BURST 40440 #define MMEA7_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 40441 #define MMEA7_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 40442 #define MMEA7_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 40443 #define MMEA7_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 40444 #define MMEA7_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL 40445 #define MMEA7_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 40446 #define MMEA7_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 40447 #define MMEA7_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L 40448 //MMEA7_IO_RD_PRI_AGE 40449 #define MMEA7_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 40450 #define MMEA7_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 40451 #define MMEA7_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 40452 #define MMEA7_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 40453 #define MMEA7_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 40454 #define MMEA7_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 40455 #define MMEA7_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 40456 #define MMEA7_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 40457 #define MMEA7_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 40458 #define MMEA7_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 40459 #define MMEA7_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 40460 #define MMEA7_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 40461 #define MMEA7_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 40462 #define MMEA7_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 40463 #define MMEA7_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 40464 #define MMEA7_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 40465 //MMEA7_IO_WR_PRI_AGE 40466 #define MMEA7_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 40467 #define MMEA7_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 40468 #define MMEA7_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 40469 #define MMEA7_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 40470 #define MMEA7_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 40471 #define MMEA7_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 40472 #define MMEA7_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 40473 #define MMEA7_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 40474 #define MMEA7_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 40475 #define MMEA7_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 40476 #define MMEA7_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 40477 #define MMEA7_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 40478 #define MMEA7_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 40479 #define MMEA7_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 40480 #define MMEA7_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 40481 #define MMEA7_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 40482 //MMEA7_IO_RD_PRI_QUEUING 40483 #define MMEA7_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 40484 #define MMEA7_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 40485 #define MMEA7_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 40486 #define MMEA7_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 40487 #define MMEA7_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 40488 #define MMEA7_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 40489 #define MMEA7_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 40490 #define MMEA7_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 40491 //MMEA7_IO_WR_PRI_QUEUING 40492 #define MMEA7_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 40493 #define MMEA7_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 40494 #define MMEA7_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 40495 #define MMEA7_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 40496 #define MMEA7_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 40497 #define MMEA7_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 40498 #define MMEA7_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 40499 #define MMEA7_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 40500 //MMEA7_IO_RD_PRI_FIXED 40501 #define MMEA7_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 40502 #define MMEA7_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 40503 #define MMEA7_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 40504 #define MMEA7_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 40505 #define MMEA7_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 40506 #define MMEA7_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 40507 #define MMEA7_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 40508 #define MMEA7_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 40509 //MMEA7_IO_WR_PRI_FIXED 40510 #define MMEA7_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 40511 #define MMEA7_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 40512 #define MMEA7_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 40513 #define MMEA7_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 40514 #define MMEA7_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 40515 #define MMEA7_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 40516 #define MMEA7_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 40517 #define MMEA7_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 40518 //MMEA7_IO_RD_PRI_URGENCY 40519 #define MMEA7_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 40520 #define MMEA7_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 40521 #define MMEA7_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 40522 #define MMEA7_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 40523 #define MMEA7_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 40524 #define MMEA7_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 40525 #define MMEA7_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 40526 #define MMEA7_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 40527 #define MMEA7_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 40528 #define MMEA7_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 40529 #define MMEA7_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 40530 #define MMEA7_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 40531 #define MMEA7_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 40532 #define MMEA7_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 40533 #define MMEA7_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 40534 #define MMEA7_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 40535 //MMEA7_IO_WR_PRI_URGENCY 40536 #define MMEA7_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 40537 #define MMEA7_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 40538 #define MMEA7_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 40539 #define MMEA7_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 40540 #define MMEA7_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 40541 #define MMEA7_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 40542 #define MMEA7_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 40543 #define MMEA7_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 40544 #define MMEA7_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 40545 #define MMEA7_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 40546 #define MMEA7_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 40547 #define MMEA7_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 40548 #define MMEA7_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 40549 #define MMEA7_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 40550 #define MMEA7_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 40551 #define MMEA7_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 40552 //MMEA7_IO_RD_PRI_URGENCY_MASKING 40553 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 40554 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 40555 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 40556 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 40557 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 40558 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 40559 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 40560 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 40561 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 40562 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 40563 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 40564 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 40565 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 40566 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 40567 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 40568 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 40569 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 40570 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 40571 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 40572 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 40573 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 40574 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 40575 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 40576 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 40577 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 40578 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 40579 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 40580 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 40581 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 40582 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 40583 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 40584 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 40585 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 40586 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 40587 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 40588 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 40589 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 40590 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 40591 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 40592 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 40593 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 40594 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 40595 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 40596 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 40597 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 40598 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 40599 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 40600 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 40601 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 40602 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 40603 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 40604 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 40605 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 40606 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 40607 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 40608 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 40609 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 40610 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 40611 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 40612 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 40613 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 40614 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 40615 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 40616 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 40617 //MMEA7_IO_WR_PRI_URGENCY_MASKING 40618 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 40619 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 40620 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 40621 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 40622 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 40623 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 40624 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 40625 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 40626 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 40627 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 40628 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 40629 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 40630 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 40631 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 40632 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 40633 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 40634 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 40635 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 40636 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 40637 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 40638 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 40639 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 40640 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 40641 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 40642 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 40643 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 40644 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 40645 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 40646 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 40647 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 40648 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 40649 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 40650 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 40651 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 40652 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 40653 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 40654 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 40655 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 40656 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 40657 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 40658 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 40659 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 40660 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 40661 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 40662 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 40663 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 40664 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 40665 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 40666 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 40667 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 40668 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 40669 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 40670 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 40671 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 40672 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 40673 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 40674 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 40675 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 40676 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 40677 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 40678 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 40679 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 40680 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 40681 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 40682 //MMEA7_IO_RD_PRI_QUANT_PRI1 40683 #define MMEA7_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 40684 #define MMEA7_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 40685 #define MMEA7_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 40686 #define MMEA7_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 40687 #define MMEA7_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 40688 #define MMEA7_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 40689 #define MMEA7_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 40690 #define MMEA7_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 40691 //MMEA7_IO_RD_PRI_QUANT_PRI2 40692 #define MMEA7_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 40693 #define MMEA7_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 40694 #define MMEA7_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 40695 #define MMEA7_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 40696 #define MMEA7_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 40697 #define MMEA7_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 40698 #define MMEA7_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 40699 #define MMEA7_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 40700 //MMEA7_IO_RD_PRI_QUANT_PRI3 40701 #define MMEA7_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 40702 #define MMEA7_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 40703 #define MMEA7_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 40704 #define MMEA7_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 40705 #define MMEA7_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 40706 #define MMEA7_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 40707 #define MMEA7_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 40708 #define MMEA7_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 40709 //MMEA7_IO_WR_PRI_QUANT_PRI1 40710 #define MMEA7_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 40711 #define MMEA7_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 40712 #define MMEA7_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 40713 #define MMEA7_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 40714 #define MMEA7_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 40715 #define MMEA7_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 40716 #define MMEA7_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 40717 #define MMEA7_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 40718 //MMEA7_IO_WR_PRI_QUANT_PRI2 40719 #define MMEA7_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 40720 #define MMEA7_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 40721 #define MMEA7_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 40722 #define MMEA7_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 40723 #define MMEA7_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 40724 #define MMEA7_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 40725 #define MMEA7_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 40726 #define MMEA7_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 40727 //MMEA7_IO_WR_PRI_QUANT_PRI3 40728 #define MMEA7_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 40729 #define MMEA7_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 40730 #define MMEA7_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 40731 #define MMEA7_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 40732 #define MMEA7_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 40733 #define MMEA7_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 40734 #define MMEA7_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 40735 #define MMEA7_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 40736 //MMEA7_SDP_ARB_DRAM 40737 #define MMEA7_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 40738 #define MMEA7_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 40739 #define MMEA7_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 40740 #define MMEA7_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 40741 #define MMEA7_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 40742 #define MMEA7_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 40743 #define MMEA7_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 40744 #define MMEA7_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 40745 #define MMEA7_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL 40746 #define MMEA7_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L 40747 #define MMEA7_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L 40748 #define MMEA7_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L 40749 #define MMEA7_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L 40750 #define MMEA7_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L 40751 #define MMEA7_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L 40752 #define MMEA7_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L 40753 //MMEA7_SDP_ARB_GMI 40754 #define MMEA7_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 40755 #define MMEA7_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 40756 #define MMEA7_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT 0x10 40757 #define MMEA7_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT 0x11 40758 #define MMEA7_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT 0x12 40759 #define MMEA7_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT 0x13 40760 #define MMEA7_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT 0x14 40761 #define MMEA7_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 40762 #define MMEA7_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT 0x16 40763 #define MMEA7_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL 40764 #define MMEA7_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L 40765 #define MMEA7_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK 0x00010000L 40766 #define MMEA7_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK 0x00020000L 40767 #define MMEA7_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK 0x00040000L 40768 #define MMEA7_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK 0x00080000L 40769 #define MMEA7_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK 0x00100000L 40770 #define MMEA7_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L 40771 #define MMEA7_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK 0x00400000L 40772 //MMEA7_SDP_ARB_FINAL 40773 #define MMEA7_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 40774 #define MMEA7_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 40775 #define MMEA7_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa 40776 #define MMEA7_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf 40777 #define MMEA7_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 40778 #define MMEA7_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 40779 #define MMEA7_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 40780 #define MMEA7_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 40781 #define MMEA7_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 40782 #define MMEA7_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 40783 #define MMEA7_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 40784 #define MMEA7_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 40785 #define MMEA7_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 40786 #define MMEA7_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a 40787 #define MMEA7_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1b 40788 #define MMEA7_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL 40789 #define MMEA7_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L 40790 #define MMEA7_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L 40791 #define MMEA7_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L 40792 #define MMEA7_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L 40793 #define MMEA7_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L 40794 #define MMEA7_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L 40795 #define MMEA7_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L 40796 #define MMEA7_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L 40797 #define MMEA7_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L 40798 #define MMEA7_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L 40799 #define MMEA7_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L 40800 #define MMEA7_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L 40801 #define MMEA7_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L 40802 #define MMEA7_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x08000000L 40803 //MMEA7_SDP_DRAM_PRIORITY 40804 #define MMEA7_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 40805 #define MMEA7_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 40806 #define MMEA7_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 40807 #define MMEA7_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 40808 #define MMEA7_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 40809 #define MMEA7_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 40810 #define MMEA7_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 40811 #define MMEA7_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 40812 #define MMEA7_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 40813 #define MMEA7_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 40814 #define MMEA7_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 40815 #define MMEA7_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 40816 #define MMEA7_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 40817 #define MMEA7_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 40818 #define MMEA7_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 40819 #define MMEA7_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 40820 //MMEA7_SDP_GMI_PRIORITY 40821 #define MMEA7_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 40822 #define MMEA7_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 40823 #define MMEA7_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 40824 #define MMEA7_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 40825 #define MMEA7_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 40826 #define MMEA7_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 40827 #define MMEA7_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 40828 #define MMEA7_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 40829 #define MMEA7_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 40830 #define MMEA7_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 40831 #define MMEA7_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 40832 #define MMEA7_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 40833 #define MMEA7_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 40834 #define MMEA7_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 40835 #define MMEA7_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 40836 #define MMEA7_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 40837 //MMEA7_SDP_IO_PRIORITY 40838 #define MMEA7_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 40839 #define MMEA7_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 40840 #define MMEA7_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 40841 #define MMEA7_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 40842 #define MMEA7_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 40843 #define MMEA7_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 40844 #define MMEA7_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 40845 #define MMEA7_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 40846 #define MMEA7_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 40847 #define MMEA7_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 40848 #define MMEA7_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 40849 #define MMEA7_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 40850 #define MMEA7_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 40851 #define MMEA7_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 40852 #define MMEA7_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 40853 #define MMEA7_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 40854 //MMEA7_SDP_CREDITS 40855 #define MMEA7_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 40856 #define MMEA7_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 40857 #define MMEA7_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 40858 #define MMEA7_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL 40859 #define MMEA7_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L 40860 #define MMEA7_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L 40861 //MMEA7_SDP_TAG_RESERVE0 40862 #define MMEA7_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 40863 #define MMEA7_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 40864 #define MMEA7_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 40865 #define MMEA7_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 40866 #define MMEA7_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL 40867 #define MMEA7_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L 40868 #define MMEA7_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L 40869 #define MMEA7_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L 40870 //MMEA7_SDP_TAG_RESERVE1 40871 #define MMEA7_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 40872 #define MMEA7_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 40873 #define MMEA7_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 40874 #define MMEA7_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 40875 #define MMEA7_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL 40876 #define MMEA7_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L 40877 #define MMEA7_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L 40878 #define MMEA7_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L 40879 //MMEA7_SDP_VCC_RESERVE0 40880 #define MMEA7_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 40881 #define MMEA7_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 40882 #define MMEA7_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc 40883 #define MMEA7_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 40884 #define MMEA7_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 40885 #define MMEA7_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 40886 #define MMEA7_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 40887 #define MMEA7_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 40888 #define MMEA7_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 40889 #define MMEA7_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 40890 //MMEA7_SDP_VCC_RESERVE1 40891 #define MMEA7_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 40892 #define MMEA7_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 40893 #define MMEA7_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc 40894 #define MMEA7_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 40895 #define MMEA7_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 40896 #define MMEA7_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 40897 #define MMEA7_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 40898 #define MMEA7_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 40899 //MMEA7_SDP_VCD_RESERVE0 40900 #define MMEA7_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 40901 #define MMEA7_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 40902 #define MMEA7_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc 40903 #define MMEA7_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 40904 #define MMEA7_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 40905 #define MMEA7_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 40906 #define MMEA7_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 40907 #define MMEA7_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 40908 #define MMEA7_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 40909 #define MMEA7_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 40910 //MMEA7_SDP_VCD_RESERVE1 40911 #define MMEA7_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 40912 #define MMEA7_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 40913 #define MMEA7_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc 40914 #define MMEA7_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 40915 #define MMEA7_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 40916 #define MMEA7_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 40917 #define MMEA7_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 40918 #define MMEA7_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 40919 //MMEA7_SDP_REQ_CNTL 40920 #define MMEA7_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 40921 #define MMEA7_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 40922 #define MMEA7_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 40923 #define MMEA7_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 40924 #define MMEA7_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 40925 #define MMEA7_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 40926 #define MMEA7_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L 40927 #define MMEA7_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L 40928 #define MMEA7_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L 40929 #define MMEA7_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L 40930 #define MMEA7_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L 40931 #define MMEA7_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L 40932 //MMEA7_MISC 40933 #define MMEA7_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 40934 #define MMEA7_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 40935 #define MMEA7_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 40936 #define MMEA7_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 40937 #define MMEA7_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 40938 #define MMEA7_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 40939 #define MMEA7_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 40940 #define MMEA7_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 40941 #define MMEA7_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 40942 #define MMEA7_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 40943 #define MMEA7_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa 40944 #define MMEA7_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb 40945 #define MMEA7_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc 40946 #define MMEA7_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd 40947 #define MMEA7_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe 40948 #define MMEA7_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf 40949 #define MMEA7_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 40950 #define MMEA7_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 40951 #define MMEA7_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 40952 #define MMEA7_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a 40953 #define MMEA7_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b 40954 #define MMEA7_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c 40955 #define MMEA7_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d 40956 #define MMEA7_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e 40957 #define MMEA7_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f 40958 #define MMEA7_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L 40959 #define MMEA7_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L 40960 #define MMEA7_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L 40961 #define MMEA7_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L 40962 #define MMEA7_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L 40963 #define MMEA7_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L 40964 #define MMEA7_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L 40965 #define MMEA7_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L 40966 #define MMEA7_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L 40967 #define MMEA7_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L 40968 #define MMEA7_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L 40969 #define MMEA7_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L 40970 #define MMEA7_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L 40971 #define MMEA7_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L 40972 #define MMEA7_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L 40973 #define MMEA7_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L 40974 #define MMEA7_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L 40975 #define MMEA7_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L 40976 #define MMEA7_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L 40977 #define MMEA7_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L 40978 #define MMEA7_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L 40979 #define MMEA7_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L 40980 #define MMEA7_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L 40981 #define MMEA7_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L 40982 #define MMEA7_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L 40983 //MMEA7_LATENCY_SAMPLING 40984 #define MMEA7_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 40985 #define MMEA7_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 40986 #define MMEA7_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 40987 #define MMEA7_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 40988 #define MMEA7_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 40989 #define MMEA7_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 40990 #define MMEA7_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 40991 #define MMEA7_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 40992 #define MMEA7_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 40993 #define MMEA7_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 40994 #define MMEA7_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa 40995 #define MMEA7_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb 40996 #define MMEA7_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc 40997 #define MMEA7_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd 40998 #define MMEA7_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe 40999 #define MMEA7_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 41000 #define MMEA7_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L 41001 #define MMEA7_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L 41002 #define MMEA7_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L 41003 #define MMEA7_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L 41004 #define MMEA7_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L 41005 #define MMEA7_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L 41006 #define MMEA7_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L 41007 #define MMEA7_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L 41008 #define MMEA7_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L 41009 #define MMEA7_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L 41010 #define MMEA7_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L 41011 #define MMEA7_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L 41012 #define MMEA7_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L 41013 #define MMEA7_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L 41014 #define MMEA7_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L 41015 #define MMEA7_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L 41016 //MMEA7_PERFCOUNTER_LO 41017 #define MMEA7_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 41018 #define MMEA7_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 41019 //MMEA7_PERFCOUNTER_HI 41020 #define MMEA7_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 41021 #define MMEA7_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 41022 #define MMEA7_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 41023 #define MMEA7_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 41024 //MMEA7_PERFCOUNTER0_CFG 41025 #define MMEA7_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 41026 #define MMEA7_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 41027 #define MMEA7_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 41028 #define MMEA7_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 41029 #define MMEA7_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 41030 #define MMEA7_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 41031 #define MMEA7_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 41032 #define MMEA7_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 41033 #define MMEA7_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 41034 #define MMEA7_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 41035 //MMEA7_PERFCOUNTER1_CFG 41036 #define MMEA7_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 41037 #define MMEA7_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 41038 #define MMEA7_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 41039 #define MMEA7_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 41040 #define MMEA7_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 41041 #define MMEA7_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 41042 #define MMEA7_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 41043 #define MMEA7_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 41044 #define MMEA7_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 41045 #define MMEA7_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 41046 //MMEA7_PERFCOUNTER_RSLT_CNTL 41047 #define MMEA7_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 41048 #define MMEA7_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 41049 #define MMEA7_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 41050 #define MMEA7_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 41051 #define MMEA7_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 41052 #define MMEA7_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 41053 #define MMEA7_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 41054 #define MMEA7_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 41055 #define MMEA7_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 41056 #define MMEA7_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 41057 #define MMEA7_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 41058 #define MMEA7_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 41059 //MMEA7_EDC_CNT 41060 #define MMEA7_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 41061 #define MMEA7_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 41062 #define MMEA7_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 41063 #define MMEA7_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 41064 #define MMEA7_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 41065 #define MMEA7_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa 41066 #define MMEA7_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc 41067 #define MMEA7_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe 41068 #define MMEA7_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 41069 #define MMEA7_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 41070 #define MMEA7_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 41071 #define MMEA7_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 41072 #define MMEA7_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 41073 #define MMEA7_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a 41074 #define MMEA7_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c 41075 #define MMEA7_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 41076 #define MMEA7_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 41077 #define MMEA7_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 41078 #define MMEA7_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 41079 #define MMEA7_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 41080 #define MMEA7_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 41081 #define MMEA7_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L 41082 #define MMEA7_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L 41083 #define MMEA7_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L 41084 #define MMEA7_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L 41085 #define MMEA7_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L 41086 #define MMEA7_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L 41087 #define MMEA7_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L 41088 #define MMEA7_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L 41089 #define MMEA7_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L 41090 //MMEA7_EDC_CNT2 41091 #define MMEA7_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 41092 #define MMEA7_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 41093 #define MMEA7_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 41094 #define MMEA7_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 41095 #define MMEA7_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 41096 #define MMEA7_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa 41097 #define MMEA7_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc 41098 #define MMEA7_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe 41099 #define MMEA7_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10 41100 #define MMEA7_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12 41101 #define MMEA7_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14 41102 #define MMEA7_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16 41103 #define MMEA7_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT 0x18 41104 #define MMEA7_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT 0x1a 41105 #define MMEA7_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT 0x1c 41106 #define MMEA7_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT 0x1e 41107 #define MMEA7_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 41108 #define MMEA7_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 41109 #define MMEA7_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 41110 #define MMEA7_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 41111 #define MMEA7_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 41112 #define MMEA7_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 41113 #define MMEA7_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L 41114 #define MMEA7_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L 41115 #define MMEA7_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L 41116 #define MMEA7_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L 41117 #define MMEA7_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L 41118 #define MMEA7_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L 41119 #define MMEA7_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK 0x03000000L 41120 #define MMEA7_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK 0x0C000000L 41121 #define MMEA7_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK 0x30000000L 41122 #define MMEA7_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK 0xC0000000L 41123 //MMEA7_DSM_CNTL 41124 #define MMEA7_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 41125 #define MMEA7_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 41126 #define MMEA7_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 41127 #define MMEA7_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 41128 #define MMEA7_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 41129 #define MMEA7_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 41130 #define MMEA7_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 41131 #define MMEA7_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 41132 #define MMEA7_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 41133 #define MMEA7_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 41134 #define MMEA7_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 41135 #define MMEA7_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 41136 #define MMEA7_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 41137 #define MMEA7_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 41138 #define MMEA7_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 41139 #define MMEA7_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 41140 #define MMEA7_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 41141 #define MMEA7_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 41142 #define MMEA7_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 41143 #define MMEA7_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 41144 #define MMEA7_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 41145 #define MMEA7_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 41146 #define MMEA7_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 41147 #define MMEA7_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 41148 #define MMEA7_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 41149 #define MMEA7_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 41150 #define MMEA7_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 41151 #define MMEA7_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 41152 #define MMEA7_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 41153 #define MMEA7_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 41154 #define MMEA7_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L 41155 #define MMEA7_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L 41156 //MMEA7_DSM_CNTLA 41157 #define MMEA7_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 41158 #define MMEA7_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 41159 #define MMEA7_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 41160 #define MMEA7_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 41161 #define MMEA7_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 41162 #define MMEA7_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 41163 #define MMEA7_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 41164 #define MMEA7_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 41165 #define MMEA7_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 41166 #define MMEA7_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 41167 #define MMEA7_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 41168 #define MMEA7_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 41169 #define MMEA7_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 41170 #define MMEA7_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 41171 #define MMEA7_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 41172 #define MMEA7_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 41173 #define MMEA7_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 41174 #define MMEA7_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 41175 #define MMEA7_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 41176 #define MMEA7_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 41177 #define MMEA7_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 41178 #define MMEA7_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 41179 #define MMEA7_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 41180 #define MMEA7_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 41181 #define MMEA7_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 41182 #define MMEA7_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 41183 #define MMEA7_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 41184 #define MMEA7_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 41185 //MMEA7_DSM_CNTL2 41186 #define MMEA7_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 41187 #define MMEA7_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 41188 #define MMEA7_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 41189 #define MMEA7_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 41190 #define MMEA7_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 41191 #define MMEA7_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 41192 #define MMEA7_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 41193 #define MMEA7_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb 41194 #define MMEA7_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 41195 #define MMEA7_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe 41196 #define MMEA7_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 41197 #define MMEA7_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 41198 #define MMEA7_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 41199 #define MMEA7_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 41200 #define MMEA7_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 41201 #define MMEA7_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 41202 #define MMEA7_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a 41203 #define MMEA7_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 41204 #define MMEA7_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 41205 #define MMEA7_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 41206 #define MMEA7_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 41207 #define MMEA7_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 41208 #define MMEA7_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 41209 #define MMEA7_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 41210 #define MMEA7_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 41211 #define MMEA7_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 41212 #define MMEA7_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 41213 #define MMEA7_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 41214 #define MMEA7_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 41215 #define MMEA7_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 41216 #define MMEA7_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 41217 #define MMEA7_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L 41218 #define MMEA7_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L 41219 #define MMEA7_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L 41220 //MMEA7_DSM_CNTL2A 41221 #define MMEA7_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 41222 #define MMEA7_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 41223 #define MMEA7_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 41224 #define MMEA7_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 41225 #define MMEA7_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 41226 #define MMEA7_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 41227 #define MMEA7_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 41228 #define MMEA7_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb 41229 #define MMEA7_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 41230 #define MMEA7_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe 41231 #define MMEA7_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 41232 #define MMEA7_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 41233 #define MMEA7_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 41234 #define MMEA7_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 41235 #define MMEA7_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 41236 #define MMEA7_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 41237 #define MMEA7_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 41238 #define MMEA7_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 41239 #define MMEA7_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 41240 #define MMEA7_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 41241 #define MMEA7_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 41242 #define MMEA7_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 41243 #define MMEA7_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 41244 #define MMEA7_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 41245 #define MMEA7_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 41246 #define MMEA7_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 41247 #define MMEA7_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 41248 #define MMEA7_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 41249 //MMEA7_CGTT_CLK_CTRL 41250 #define MMEA7_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 41251 #define MMEA7_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 41252 #define MMEA7_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc 41253 #define MMEA7_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 41254 #define MMEA7_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 41255 #define MMEA7_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 41256 #define MMEA7_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 41257 #define MMEA7_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 41258 #define MMEA7_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c 41259 #define MMEA7_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d 41260 #define MMEA7_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e 41261 #define MMEA7_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f 41262 #define MMEA7_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 41263 #define MMEA7_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 41264 #define MMEA7_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L 41265 #define MMEA7_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L 41266 #define MMEA7_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L 41267 #define MMEA7_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L 41268 #define MMEA7_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L 41269 #define MMEA7_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 41270 #define MMEA7_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L 41271 #define MMEA7_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L 41272 #define MMEA7_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L 41273 #define MMEA7_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L 41274 //MMEA7_EDC_MODE 41275 #define MMEA7_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 41276 #define MMEA7_EDC_MODE__GATE_FUE__SHIFT 0x11 41277 #define MMEA7_EDC_MODE__DED_MODE__SHIFT 0x14 41278 #define MMEA7_EDC_MODE__PROP_FED__SHIFT 0x1d 41279 #define MMEA7_EDC_MODE__BYPASS__SHIFT 0x1f 41280 #define MMEA7_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L 41281 #define MMEA7_EDC_MODE__GATE_FUE_MASK 0x00020000L 41282 #define MMEA7_EDC_MODE__DED_MODE_MASK 0x00300000L 41283 #define MMEA7_EDC_MODE__PROP_FED_MASK 0x20000000L 41284 #define MMEA7_EDC_MODE__BYPASS_MASK 0x80000000L 41285 //MMEA7_ERR_STATUS 41286 #define MMEA7_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 41287 #define MMEA7_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 41288 #define MMEA7_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 41289 #define MMEA7_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa 41290 #define MMEA7_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb 41291 #define MMEA7_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc 41292 #define MMEA7_ERR_STATUS__FUE_FLAG__SHIFT 0xd 41293 #define MMEA7_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL 41294 #define MMEA7_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L 41295 #define MMEA7_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L 41296 #define MMEA7_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L 41297 #define MMEA7_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L 41298 #define MMEA7_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L 41299 #define MMEA7_ERR_STATUS__FUE_FLAG_MASK 0x00002000L 41300 //MMEA7_MISC2 41301 #define MMEA7_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 41302 #define MMEA7_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 41303 #define MMEA7_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 41304 #define MMEA7_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 41305 #define MMEA7_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc 41306 #define MMEA7_MISC2__RRET_SWAP_MODE__SHIFT 0xd 41307 #define MMEA7_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L 41308 #define MMEA7_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L 41309 #define MMEA7_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL 41310 #define MMEA7_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L 41311 #define MMEA7_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L 41312 #define MMEA7_MISC2__RRET_SWAP_MODE_MASK 0x00002000L 41313 //MMEA7_ADDRDEC_SELECT 41314 #define MMEA7_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0 41315 #define MMEA7_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5 41316 #define MMEA7_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa 41317 #define MMEA7_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf 41318 #define MMEA7_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL 41319 #define MMEA7_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L 41320 #define MMEA7_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L 41321 #define MMEA7_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L 41322 //MMEA7_EDC_CNT3 41323 #define MMEA7_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0 41324 #define MMEA7_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2 41325 #define MMEA7_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4 41326 #define MMEA7_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6 41327 #define MMEA7_EDC_CNT3__IOWR_DATAMEM_DED_COUNT__SHIFT 0x8 41328 #define MMEA7_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0xa 41329 #define MMEA7_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xc 41330 #define MMEA7_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L 41331 #define MMEA7_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL 41332 #define MMEA7_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L 41333 #define MMEA7_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 41334 #define MMEA7_EDC_CNT3__IOWR_DATAMEM_DED_COUNT_MASK 0x00000300L 41335 #define MMEA7_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000C00L 41336 #define MMEA7_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00003000L 41337 41338 41339 // addressBlock: mmhub_pctldec1 41340 //PCTL1_CTRL 41341 #define PCTL1_CTRL__PG_ENABLE__SHIFT 0x0 41342 #define PCTL1_CTRL__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x1 41343 #define PCTL1_CTRL__STCTRL_RSMU_IDLE_THRESHOLD__SHIFT 0x4 41344 #define PCTL1_CTRL__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT 0xb 41345 #define PCTL1_CTRL__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x10 41346 #define PCTL1_CTRL__OVR_EA0_SDP_PARTACK__SHIFT 0x11 41347 #define PCTL1_CTRL__OVR_EA1_SDP_PARTACK__SHIFT 0x12 41348 #define PCTL1_CTRL__OVR_EA2_SDP_PARTACK__SHIFT 0x13 41349 #define PCTL1_CTRL__OVR_EA3_SDP_PARTACK__SHIFT 0x14 41350 #define PCTL1_CTRL__OVR_EA4_SDP_PARTACK__SHIFT 0x15 41351 #define PCTL1_CTRL__OVR_EA0_SDP_FULLACK__SHIFT 0x16 41352 #define PCTL1_CTRL__OVR_EA1_SDP_FULLACK__SHIFT 0x17 41353 #define PCTL1_CTRL__OVR_EA2_SDP_FULLACK__SHIFT 0x18 41354 #define PCTL1_CTRL__OVR_EA3_SDP_FULLACK__SHIFT 0x19 41355 #define PCTL1_CTRL__OVR_EA4_SDP_FULLACK__SHIFT 0x1a 41356 #define PCTL1_CTRL__PGFSM_CMD_STATUS__SHIFT 0x1b 41357 #define PCTL1_CTRL__PG_ENABLE_MASK 0x00000001L 41358 #define PCTL1_CTRL__ALLOW_DEEP_SLEEP_MODE_MASK 0x0000000EL 41359 #define PCTL1_CTRL__STCTRL_RSMU_IDLE_THRESHOLD_MASK 0x000007F0L 41360 #define PCTL1_CTRL__STCTRL_DAGB_IDLE_THRESHOLD_MASK 0x0000F800L 41361 #define PCTL1_CTRL__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x00010000L 41362 #define PCTL1_CTRL__OVR_EA0_SDP_PARTACK_MASK 0x00020000L 41363 #define PCTL1_CTRL__OVR_EA1_SDP_PARTACK_MASK 0x00040000L 41364 #define PCTL1_CTRL__OVR_EA2_SDP_PARTACK_MASK 0x00080000L 41365 #define PCTL1_CTRL__OVR_EA3_SDP_PARTACK_MASK 0x00100000L 41366 #define PCTL1_CTRL__OVR_EA4_SDP_PARTACK_MASK 0x00200000L 41367 #define PCTL1_CTRL__OVR_EA0_SDP_FULLACK_MASK 0x00400000L 41368 #define PCTL1_CTRL__OVR_EA1_SDP_FULLACK_MASK 0x00800000L 41369 #define PCTL1_CTRL__OVR_EA2_SDP_FULLACK_MASK 0x01000000L 41370 #define PCTL1_CTRL__OVR_EA3_SDP_FULLACK_MASK 0x02000000L 41371 #define PCTL1_CTRL__OVR_EA4_SDP_FULLACK_MASK 0x04000000L 41372 #define PCTL1_CTRL__PGFSM_CMD_STATUS_MASK 0x18000000L 41373 //PCTL1_MMHUB_DEEPSLEEP_IB 41374 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS0__SHIFT 0x0 41375 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS1__SHIFT 0x1 41376 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS2__SHIFT 0x2 41377 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS3__SHIFT 0x3 41378 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS4__SHIFT 0x4 41379 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS5__SHIFT 0x5 41380 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS6__SHIFT 0x6 41381 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS7__SHIFT 0x7 41382 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS8__SHIFT 0x8 41383 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS9__SHIFT 0x9 41384 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS10__SHIFT 0xa 41385 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS11__SHIFT 0xb 41386 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS12__SHIFT 0xc 41387 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS13__SHIFT 0xd 41388 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS14__SHIFT 0xe 41389 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS15__SHIFT 0xf 41390 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS16__SHIFT 0x10 41391 #define PCTL1_MMHUB_DEEPSLEEP_IB__SETCLEAR__SHIFT 0x1f 41392 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS0_MASK 0x00000001L 41393 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS1_MASK 0x00000002L 41394 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS2_MASK 0x00000004L 41395 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS3_MASK 0x00000008L 41396 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS4_MASK 0x00000010L 41397 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS5_MASK 0x00000020L 41398 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS6_MASK 0x00000040L 41399 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS7_MASK 0x00000080L 41400 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS8_MASK 0x00000100L 41401 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS9_MASK 0x00000200L 41402 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS10_MASK 0x00000400L 41403 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS11_MASK 0x00000800L 41404 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS12_MASK 0x00001000L 41405 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS13_MASK 0x00002000L 41406 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS14_MASK 0x00004000L 41407 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS15_MASK 0x00008000L 41408 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS16_MASK 0x00010000L 41409 #define PCTL1_MMHUB_DEEPSLEEP_IB__SETCLEAR_MASK 0x80000000L 41410 //PCTL1_MMHUB_DEEPSLEEP_OVERRIDE 41411 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT 0x0 41412 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT 0x1 41413 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT 0x2 41414 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT 0x3 41415 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT 0x4 41416 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT 0x5 41417 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT 0x6 41418 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT 0x7 41419 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT 0x8 41420 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT 0x9 41421 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT 0xa 41422 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT 0xb 41423 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT 0xc 41424 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT 0xd 41425 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT 0xe 41426 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT 0xf 41427 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT 0x10 41428 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB__SHIFT 0x11 41429 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK 0x00000001L 41430 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK 0x00000002L 41431 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK 0x00000004L 41432 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK 0x00000008L 41433 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK 0x00000010L 41434 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK 0x00000020L 41435 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK 0x00000040L 41436 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK 0x00000080L 41437 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK 0x00000100L 41438 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK 0x00000200L 41439 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK 0x00000400L 41440 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK 0x00000800L 41441 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK 0x00001000L 41442 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK 0x00002000L 41443 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK 0x00004000L 41444 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK 0x00008000L 41445 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK 0x00010000L 41446 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB_MASK 0x00020000L 41447 //PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB 41448 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0__SHIFT 0x0 41449 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1__SHIFT 0x1 41450 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2__SHIFT 0x2 41451 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3__SHIFT 0x3 41452 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4__SHIFT 0x4 41453 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5__SHIFT 0x5 41454 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6__SHIFT 0x6 41455 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7__SHIFT 0x7 41456 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8__SHIFT 0x8 41457 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9__SHIFT 0x9 41458 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10__SHIFT 0xa 41459 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11__SHIFT 0xb 41460 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12__SHIFT 0xc 41461 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13__SHIFT 0xd 41462 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14__SHIFT 0xe 41463 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15__SHIFT 0xf 41464 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16__SHIFT 0x10 41465 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0_MASK 0x00000001L 41466 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1_MASK 0x00000002L 41467 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2_MASK 0x00000004L 41468 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3_MASK 0x00000008L 41469 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4_MASK 0x00000010L 41470 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5_MASK 0x00000020L 41471 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6_MASK 0x00000040L 41472 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7_MASK 0x00000080L 41473 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8_MASK 0x00000100L 41474 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9_MASK 0x00000200L 41475 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10_MASK 0x00000400L 41476 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11_MASK 0x00000800L 41477 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12_MASK 0x00001000L 41478 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13_MASK 0x00002000L 41479 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14_MASK 0x00004000L 41480 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15_MASK 0x00008000L 41481 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16_MASK 0x00010000L 41482 //PCTL1_PG_IGNORE_DEEPSLEEP 41483 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS0__SHIFT 0x0 41484 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS1__SHIFT 0x1 41485 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS2__SHIFT 0x2 41486 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS3__SHIFT 0x3 41487 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS4__SHIFT 0x4 41488 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS5__SHIFT 0x5 41489 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS6__SHIFT 0x6 41490 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS7__SHIFT 0x7 41491 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS8__SHIFT 0x8 41492 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS9__SHIFT 0x9 41493 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS10__SHIFT 0xa 41494 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS11__SHIFT 0xb 41495 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS12__SHIFT 0xc 41496 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS13__SHIFT 0xd 41497 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS14__SHIFT 0xe 41498 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS15__SHIFT 0xf 41499 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS16__SHIFT 0x10 41500 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS_ATHUB__SHIFT 0x11 41501 #define PCTL1_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT 0x12 41502 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS0_MASK 0x00000001L 41503 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS1_MASK 0x00000002L 41504 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS2_MASK 0x00000004L 41505 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS3_MASK 0x00000008L 41506 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS4_MASK 0x00000010L 41507 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS5_MASK 0x00000020L 41508 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS6_MASK 0x00000040L 41509 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS7_MASK 0x00000080L 41510 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS8_MASK 0x00000100L 41511 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS9_MASK 0x00000200L 41512 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS10_MASK 0x00000400L 41513 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS11_MASK 0x00000800L 41514 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS12_MASK 0x00001000L 41515 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS13_MASK 0x00002000L 41516 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS14_MASK 0x00004000L 41517 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS15_MASK 0x00008000L 41518 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS16_MASK 0x00010000L 41519 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS_ATHUB_MASK 0x00020000L 41520 #define PCTL1_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK 0x00040000L 41521 //PCTL1_PG_IGNORE_DEEPSLEEP_IB 41522 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS0__SHIFT 0x0 41523 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS1__SHIFT 0x1 41524 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS2__SHIFT 0x2 41525 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS3__SHIFT 0x3 41526 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS4__SHIFT 0x4 41527 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS5__SHIFT 0x5 41528 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS6__SHIFT 0x6 41529 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS7__SHIFT 0x7 41530 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS8__SHIFT 0x8 41531 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS9__SHIFT 0x9 41532 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS10__SHIFT 0xa 41533 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS11__SHIFT 0xb 41534 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS12__SHIFT 0xc 41535 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS13__SHIFT 0xd 41536 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS14__SHIFT 0xe 41537 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS15__SHIFT 0xf 41538 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS16__SHIFT 0x10 41539 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__ALLIPS__SHIFT 0x11 41540 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS0_MASK 0x00000001L 41541 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS1_MASK 0x00000002L 41542 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS2_MASK 0x00000004L 41543 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS3_MASK 0x00000008L 41544 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS4_MASK 0x00000010L 41545 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS5_MASK 0x00000020L 41546 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS6_MASK 0x00000040L 41547 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS7_MASK 0x00000080L 41548 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS8_MASK 0x00000100L 41549 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS9_MASK 0x00000200L 41550 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS10_MASK 0x00000400L 41551 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS11_MASK 0x00000800L 41552 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS12_MASK 0x00001000L 41553 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS13_MASK 0x00002000L 41554 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS14_MASK 0x00004000L 41555 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS15_MASK 0x00008000L 41556 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS16_MASK 0x00010000L 41557 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__ALLIPS_MASK 0x00020000L 41558 //PCTL1_SLICE0_CFG_DAGB_BUSY 41559 #define PCTL1_SLICE0_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0 41560 #define PCTL1_SLICE0_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL 41561 //PCTL1_SLICE0_CFG_DS_ALLOW 41562 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS0__SHIFT 0x0 41563 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS1__SHIFT 0x1 41564 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS2__SHIFT 0x2 41565 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS3__SHIFT 0x3 41566 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS4__SHIFT 0x4 41567 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS5__SHIFT 0x5 41568 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS6__SHIFT 0x6 41569 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS7__SHIFT 0x7 41570 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS8__SHIFT 0x8 41571 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS9__SHIFT 0x9 41572 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS10__SHIFT 0xa 41573 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS11__SHIFT 0xb 41574 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS12__SHIFT 0xc 41575 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS13__SHIFT 0xd 41576 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS14__SHIFT 0xe 41577 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS15__SHIFT 0xf 41578 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS16__SHIFT 0x10 41579 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS0_MASK 0x00000001L 41580 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS1_MASK 0x00000002L 41581 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS2_MASK 0x00000004L 41582 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS3_MASK 0x00000008L 41583 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS4_MASK 0x00000010L 41584 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS5_MASK 0x00000020L 41585 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS6_MASK 0x00000040L 41586 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS7_MASK 0x00000080L 41587 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS8_MASK 0x00000100L 41588 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS9_MASK 0x00000200L 41589 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS10_MASK 0x00000400L 41590 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS11_MASK 0x00000800L 41591 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS12_MASK 0x00001000L 41592 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS13_MASK 0x00002000L 41593 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS14_MASK 0x00004000L 41594 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS15_MASK 0x00008000L 41595 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS16_MASK 0x00010000L 41596 //PCTL1_SLICE0_CFG_DS_ALLOW_IB 41597 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 41598 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 41599 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 41600 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 41601 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 41602 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 41603 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 41604 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 41605 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 41606 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 41607 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa 41608 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb 41609 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc 41610 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd 41611 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe 41612 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf 41613 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 41614 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L 41615 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L 41616 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L 41617 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L 41618 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L 41619 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L 41620 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L 41621 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L 41622 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L 41623 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L 41624 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L 41625 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L 41626 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L 41627 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L 41628 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L 41629 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L 41630 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L 41631 //PCTL1_SLICE1_CFG_DAGB_BUSY 41632 #define PCTL1_SLICE1_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0 41633 #define PCTL1_SLICE1_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL 41634 //PCTL1_SLICE1_CFG_DS_ALLOW 41635 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS0__SHIFT 0x0 41636 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS1__SHIFT 0x1 41637 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS2__SHIFT 0x2 41638 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS3__SHIFT 0x3 41639 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS4__SHIFT 0x4 41640 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS5__SHIFT 0x5 41641 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS6__SHIFT 0x6 41642 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS7__SHIFT 0x7 41643 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS8__SHIFT 0x8 41644 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS9__SHIFT 0x9 41645 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS10__SHIFT 0xa 41646 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS11__SHIFT 0xb 41647 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS12__SHIFT 0xc 41648 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS13__SHIFT 0xd 41649 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS14__SHIFT 0xe 41650 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS15__SHIFT 0xf 41651 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS16__SHIFT 0x10 41652 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS0_MASK 0x00000001L 41653 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS1_MASK 0x00000002L 41654 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS2_MASK 0x00000004L 41655 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS3_MASK 0x00000008L 41656 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS4_MASK 0x00000010L 41657 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS5_MASK 0x00000020L 41658 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS6_MASK 0x00000040L 41659 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS7_MASK 0x00000080L 41660 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS8_MASK 0x00000100L 41661 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS9_MASK 0x00000200L 41662 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS10_MASK 0x00000400L 41663 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS11_MASK 0x00000800L 41664 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS12_MASK 0x00001000L 41665 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS13_MASK 0x00002000L 41666 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS14_MASK 0x00004000L 41667 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS15_MASK 0x00008000L 41668 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS16_MASK 0x00010000L 41669 //PCTL1_SLICE1_CFG_DS_ALLOW_IB 41670 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 41671 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 41672 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 41673 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 41674 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 41675 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 41676 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 41677 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 41678 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 41679 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 41680 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa 41681 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb 41682 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc 41683 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd 41684 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe 41685 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf 41686 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 41687 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L 41688 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L 41689 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L 41690 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L 41691 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L 41692 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L 41693 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L 41694 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L 41695 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L 41696 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L 41697 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L 41698 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L 41699 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L 41700 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L 41701 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L 41702 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L 41703 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L 41704 //PCTL1_SLICE2_CFG_DAGB_BUSY 41705 #define PCTL1_SLICE2_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0 41706 #define PCTL1_SLICE2_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL 41707 //PCTL1_SLICE2_CFG_DS_ALLOW 41708 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS0__SHIFT 0x0 41709 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS1__SHIFT 0x1 41710 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS2__SHIFT 0x2 41711 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS3__SHIFT 0x3 41712 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS4__SHIFT 0x4 41713 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS5__SHIFT 0x5 41714 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS6__SHIFT 0x6 41715 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS7__SHIFT 0x7 41716 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS8__SHIFT 0x8 41717 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS9__SHIFT 0x9 41718 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS10__SHIFT 0xa 41719 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS11__SHIFT 0xb 41720 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS12__SHIFT 0xc 41721 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS13__SHIFT 0xd 41722 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS14__SHIFT 0xe 41723 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS15__SHIFT 0xf 41724 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS16__SHIFT 0x10 41725 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS0_MASK 0x00000001L 41726 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS1_MASK 0x00000002L 41727 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS2_MASK 0x00000004L 41728 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS3_MASK 0x00000008L 41729 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS4_MASK 0x00000010L 41730 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS5_MASK 0x00000020L 41731 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS6_MASK 0x00000040L 41732 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS7_MASK 0x00000080L 41733 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS8_MASK 0x00000100L 41734 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS9_MASK 0x00000200L 41735 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS10_MASK 0x00000400L 41736 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS11_MASK 0x00000800L 41737 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS12_MASK 0x00001000L 41738 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS13_MASK 0x00002000L 41739 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS14_MASK 0x00004000L 41740 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS15_MASK 0x00008000L 41741 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS16_MASK 0x00010000L 41742 //PCTL1_SLICE2_CFG_DS_ALLOW_IB 41743 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 41744 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 41745 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 41746 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 41747 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 41748 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 41749 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 41750 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 41751 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 41752 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 41753 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa 41754 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb 41755 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc 41756 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd 41757 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe 41758 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf 41759 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 41760 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L 41761 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L 41762 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L 41763 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L 41764 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L 41765 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L 41766 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L 41767 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L 41768 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L 41769 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L 41770 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L 41771 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L 41772 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L 41773 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L 41774 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L 41775 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L 41776 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L 41777 //PCTL1_SLICE3_CFG_DAGB_BUSY 41778 #define PCTL1_SLICE3_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0 41779 #define PCTL1_SLICE3_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL 41780 //PCTL1_SLICE3_CFG_DS_ALLOW 41781 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS0__SHIFT 0x0 41782 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS1__SHIFT 0x1 41783 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS2__SHIFT 0x2 41784 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS3__SHIFT 0x3 41785 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS4__SHIFT 0x4 41786 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS5__SHIFT 0x5 41787 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS6__SHIFT 0x6 41788 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS7__SHIFT 0x7 41789 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS8__SHIFT 0x8 41790 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS9__SHIFT 0x9 41791 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS10__SHIFT 0xa 41792 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS11__SHIFT 0xb 41793 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS12__SHIFT 0xc 41794 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS13__SHIFT 0xd 41795 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS14__SHIFT 0xe 41796 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS15__SHIFT 0xf 41797 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS16__SHIFT 0x10 41798 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS0_MASK 0x00000001L 41799 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS1_MASK 0x00000002L 41800 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS2_MASK 0x00000004L 41801 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS3_MASK 0x00000008L 41802 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS4_MASK 0x00000010L 41803 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS5_MASK 0x00000020L 41804 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS6_MASK 0x00000040L 41805 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS7_MASK 0x00000080L 41806 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS8_MASK 0x00000100L 41807 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS9_MASK 0x00000200L 41808 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS10_MASK 0x00000400L 41809 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS11_MASK 0x00000800L 41810 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS12_MASK 0x00001000L 41811 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS13_MASK 0x00002000L 41812 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS14_MASK 0x00004000L 41813 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS15_MASK 0x00008000L 41814 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS16_MASK 0x00010000L 41815 //PCTL1_SLICE3_CFG_DS_ALLOW_IB 41816 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 41817 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 41818 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 41819 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 41820 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 41821 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 41822 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 41823 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 41824 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 41825 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 41826 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa 41827 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb 41828 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc 41829 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd 41830 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe 41831 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf 41832 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 41833 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L 41834 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L 41835 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L 41836 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L 41837 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L 41838 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L 41839 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L 41840 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L 41841 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L 41842 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L 41843 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L 41844 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L 41845 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L 41846 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L 41847 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L 41848 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L 41849 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L 41850 //PCTL1_SLICE4_CFG_DAGB_BUSY 41851 #define PCTL1_SLICE4_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0 41852 #define PCTL1_SLICE4_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL 41853 //PCTL1_SLICE4_CFG_DS_ALLOW 41854 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS0__SHIFT 0x0 41855 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS1__SHIFT 0x1 41856 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS2__SHIFT 0x2 41857 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS3__SHIFT 0x3 41858 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS4__SHIFT 0x4 41859 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS5__SHIFT 0x5 41860 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS6__SHIFT 0x6 41861 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS7__SHIFT 0x7 41862 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS8__SHIFT 0x8 41863 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS9__SHIFT 0x9 41864 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS10__SHIFT 0xa 41865 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS11__SHIFT 0xb 41866 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS12__SHIFT 0xc 41867 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS13__SHIFT 0xd 41868 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS14__SHIFT 0xe 41869 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS15__SHIFT 0xf 41870 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS16__SHIFT 0x10 41871 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS0_MASK 0x00000001L 41872 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS1_MASK 0x00000002L 41873 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS2_MASK 0x00000004L 41874 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS3_MASK 0x00000008L 41875 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS4_MASK 0x00000010L 41876 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS5_MASK 0x00000020L 41877 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS6_MASK 0x00000040L 41878 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS7_MASK 0x00000080L 41879 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS8_MASK 0x00000100L 41880 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS9_MASK 0x00000200L 41881 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS10_MASK 0x00000400L 41882 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS11_MASK 0x00000800L 41883 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS12_MASK 0x00001000L 41884 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS13_MASK 0x00002000L 41885 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS14_MASK 0x00004000L 41886 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS15_MASK 0x00008000L 41887 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS16_MASK 0x00010000L 41888 //PCTL1_SLICE4_CFG_DS_ALLOW_IB 41889 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 41890 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 41891 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 41892 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 41893 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 41894 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 41895 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 41896 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 41897 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 41898 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 41899 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa 41900 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb 41901 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc 41902 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd 41903 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe 41904 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf 41905 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 41906 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L 41907 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L 41908 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L 41909 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L 41910 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L 41911 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L 41912 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L 41913 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L 41914 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L 41915 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L 41916 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L 41917 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L 41918 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L 41919 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L 41920 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L 41921 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L 41922 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L 41923 //PCTL1_UTCL2_MISC 41924 #define PCTL1_UTCL2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xb 41925 #define PCTL1_UTCL2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xc 41926 #define PCTL1_UTCL2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xf 41927 #define PCTL1_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10 41928 #define PCTL1_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 41929 #define PCTL1_UTCL2_MISC__RD_TIMER_ENABLE__SHIFT 0x12 41930 #define PCTL1_UTCL2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000800L 41931 #define PCTL1_UTCL2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00007000L 41932 #define PCTL1_UTCL2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00008000L 41933 #define PCTL1_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00010000L 41934 #define PCTL1_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L 41935 #define PCTL1_UTCL2_MISC__RD_TIMER_ENABLE_MASK 0x00040000L 41936 //PCTL1_SLICE0_MISC 41937 #define PCTL1_SLICE0_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa 41938 #define PCTL1_SLICE0_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb 41939 #define PCTL1_SLICE0_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe 41940 #define PCTL1_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf 41941 #define PCTL1_SLICE0_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 41942 #define PCTL1_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 41943 #define PCTL1_SLICE0_MISC__RD_TIMER_ENABLE__SHIFT 0x12 41944 #define PCTL1_SLICE0_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L 41945 #define PCTL1_SLICE0_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L 41946 #define PCTL1_SLICE0_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L 41947 #define PCTL1_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L 41948 #define PCTL1_SLICE0_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L 41949 #define PCTL1_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L 41950 #define PCTL1_SLICE0_MISC__RD_TIMER_ENABLE_MASK 0x00040000L 41951 //PCTL1_SLICE1_MISC 41952 #define PCTL1_SLICE1_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa 41953 #define PCTL1_SLICE1_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb 41954 #define PCTL1_SLICE1_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe 41955 #define PCTL1_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf 41956 #define PCTL1_SLICE1_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 41957 #define PCTL1_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 41958 #define PCTL1_SLICE1_MISC__RD_TIMER_ENABLE__SHIFT 0x12 41959 #define PCTL1_SLICE1_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L 41960 #define PCTL1_SLICE1_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L 41961 #define PCTL1_SLICE1_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L 41962 #define PCTL1_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L 41963 #define PCTL1_SLICE1_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L 41964 #define PCTL1_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L 41965 #define PCTL1_SLICE1_MISC__RD_TIMER_ENABLE_MASK 0x00040000L 41966 //PCTL1_SLICE2_MISC 41967 #define PCTL1_SLICE2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa 41968 #define PCTL1_SLICE2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb 41969 #define PCTL1_SLICE2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe 41970 #define PCTL1_SLICE2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf 41971 #define PCTL1_SLICE2_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 41972 #define PCTL1_SLICE2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 41973 #define PCTL1_SLICE2_MISC__RD_TIMER_ENABLE__SHIFT 0x12 41974 #define PCTL1_SLICE2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L 41975 #define PCTL1_SLICE2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L 41976 #define PCTL1_SLICE2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L 41977 #define PCTL1_SLICE2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L 41978 #define PCTL1_SLICE2_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L 41979 #define PCTL1_SLICE2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L 41980 #define PCTL1_SLICE2_MISC__RD_TIMER_ENABLE_MASK 0x00040000L 41981 //PCTL1_SLICE3_MISC 41982 #define PCTL1_SLICE3_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa 41983 #define PCTL1_SLICE3_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb 41984 #define PCTL1_SLICE3_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe 41985 #define PCTL1_SLICE3_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf 41986 #define PCTL1_SLICE3_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 41987 #define PCTL1_SLICE3_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 41988 #define PCTL1_SLICE3_MISC__RD_TIMER_ENABLE__SHIFT 0x12 41989 #define PCTL1_SLICE3_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L 41990 #define PCTL1_SLICE3_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L 41991 #define PCTL1_SLICE3_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L 41992 #define PCTL1_SLICE3_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L 41993 #define PCTL1_SLICE3_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L 41994 #define PCTL1_SLICE3_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L 41995 #define PCTL1_SLICE3_MISC__RD_TIMER_ENABLE_MASK 0x00040000L 41996 //PCTL1_SLICE4_MISC 41997 #define PCTL1_SLICE4_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa 41998 #define PCTL1_SLICE4_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb 41999 #define PCTL1_SLICE4_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe 42000 #define PCTL1_SLICE4_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf 42001 #define PCTL1_SLICE4_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 42002 #define PCTL1_SLICE4_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 42003 #define PCTL1_SLICE4_MISC__RD_TIMER_ENABLE__SHIFT 0x12 42004 #define PCTL1_SLICE4_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L 42005 #define PCTL1_SLICE4_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L 42006 #define PCTL1_SLICE4_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L 42007 #define PCTL1_SLICE4_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L 42008 #define PCTL1_SLICE4_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L 42009 #define PCTL1_SLICE4_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L 42010 #define PCTL1_SLICE4_MISC__RD_TIMER_ENABLE_MASK 0x00040000L 42011 //PCTL1_UTCL2_RENG_EXECUTE 42012 #define PCTL1_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 42013 #define PCTL1_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 42014 #define PCTL1_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 42015 #define PCTL1_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xd 42016 #define PCTL1_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L 42017 #define PCTL1_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 42018 #define PCTL1_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00001FFCL 42019 #define PCTL1_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x00FFE000L 42020 //PCTL1_SLICE0_RENG_EXECUTE 42021 #define PCTL1_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 42022 #define PCTL1_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 42023 #define PCTL1_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 42024 #define PCTL1_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc 42025 #define PCTL1_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L 42026 #define PCTL1_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 42027 #define PCTL1_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL 42028 #define PCTL1_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L 42029 //PCTL1_SLICE1_RENG_EXECUTE 42030 #define PCTL1_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 42031 #define PCTL1_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 42032 #define PCTL1_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 42033 #define PCTL1_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc 42034 #define PCTL1_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L 42035 #define PCTL1_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 42036 #define PCTL1_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL 42037 #define PCTL1_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L 42038 //PCTL1_SLICE2_RENG_EXECUTE 42039 #define PCTL1_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 42040 #define PCTL1_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 42041 #define PCTL1_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 42042 #define PCTL1_SLICE2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc 42043 #define PCTL1_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L 42044 #define PCTL1_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 42045 #define PCTL1_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL 42046 #define PCTL1_SLICE2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L 42047 //PCTL1_SLICE3_RENG_EXECUTE 42048 #define PCTL1_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 42049 #define PCTL1_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 42050 #define PCTL1_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 42051 #define PCTL1_SLICE3_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc 42052 #define PCTL1_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L 42053 #define PCTL1_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 42054 #define PCTL1_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL 42055 #define PCTL1_SLICE3_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L 42056 //PCTL1_SLICE4_RENG_EXECUTE 42057 #define PCTL1_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 42058 #define PCTL1_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 42059 #define PCTL1_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 42060 #define PCTL1_SLICE4_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc 42061 #define PCTL1_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L 42062 #define PCTL1_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 42063 #define PCTL1_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL 42064 #define PCTL1_SLICE4_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L 42065 //PCTL1_UTCL2_RENG_RAM_INDEX 42066 #define PCTL1_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 42067 #define PCTL1_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000007FFL 42068 //PCTL1_UTCL2_RENG_RAM_DATA 42069 #define PCTL1_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 42070 #define PCTL1_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 42071 //PCTL1_SLICE0_RENG_RAM_INDEX 42072 #define PCTL1_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 42073 #define PCTL1_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL 42074 //PCTL1_SLICE0_RENG_RAM_DATA 42075 #define PCTL1_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 42076 #define PCTL1_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 42077 //PCTL1_SLICE1_RENG_RAM_INDEX 42078 #define PCTL1_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 42079 #define PCTL1_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL 42080 //PCTL1_SLICE1_RENG_RAM_DATA 42081 #define PCTL1_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 42082 #define PCTL1_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 42083 //PCTL1_SLICE2_RENG_RAM_INDEX 42084 #define PCTL1_SLICE2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 42085 #define PCTL1_SLICE2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL 42086 //PCTL1_SLICE2_RENG_RAM_DATA 42087 #define PCTL1_SLICE2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 42088 #define PCTL1_SLICE2_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 42089 //PCTL1_SLICE3_RENG_RAM_INDEX 42090 #define PCTL1_SLICE3_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 42091 #define PCTL1_SLICE3_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL 42092 //PCTL1_SLICE3_RENG_RAM_DATA 42093 #define PCTL1_SLICE3_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 42094 #define PCTL1_SLICE3_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 42095 //PCTL1_SLICE4_RENG_RAM_INDEX 42096 #define PCTL1_SLICE4_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 42097 #define PCTL1_SLICE4_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL 42098 //PCTL1_SLICE4_RENG_RAM_DATA 42099 #define PCTL1_SLICE4_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 42100 #define PCTL1_SLICE4_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 42101 //PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 42102 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 42103 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 42104 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 42105 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 42106 //PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 42107 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 42108 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 42109 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 42110 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 42111 //PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 42112 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 42113 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 42114 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 42115 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 42116 //PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 42117 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 42118 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 42119 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 42120 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 42121 //PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 42122 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 42123 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 42124 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 42125 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 42126 //PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 42127 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 42128 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 42129 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 42130 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 42131 //PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 42132 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 42133 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 42134 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 42135 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 42136 //PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 42137 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 42138 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 42139 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 42140 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 42141 //PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 42142 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 42143 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 42144 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 42145 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 42146 //PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 42147 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 42148 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 42149 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 42150 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 42151 //PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 42152 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 42153 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 42154 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 42155 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 42156 //PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 42157 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 42158 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 42159 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 42160 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 42161 //PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 42162 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 42163 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 42164 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 42165 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 42166 //PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 42167 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 42168 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 42169 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 42170 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 42171 //PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 42172 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 42173 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 42174 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 42175 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 42176 //PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 42177 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 42178 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 42179 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 42180 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 42181 //PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 42182 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 42183 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 42184 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 42185 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 42186 //PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 42187 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 42188 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 42189 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 42190 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 42191 //PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 42192 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 42193 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 42194 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 42195 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 42196 //PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 42197 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 42198 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 42199 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 42200 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 42201 //PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 42202 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 42203 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 42204 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 42205 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 42206 //PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0 42207 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 42208 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 42209 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 42210 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 42211 //PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1 42212 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 42213 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 42214 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 42215 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 42216 //PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2 42217 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 42218 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 42219 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 42220 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 42221 //PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3 42222 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 42223 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 42224 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 42225 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 42226 //PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4 42227 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 42228 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 42229 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 42230 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 42231 //PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0 42232 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 42233 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 42234 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 42235 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 42236 //PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1 42237 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 42238 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 42239 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 42240 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 42241 //PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0 42242 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 42243 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 42244 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 42245 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 42246 //PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1 42247 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 42248 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 42249 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 42250 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 42251 //PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2 42252 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 42253 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 42254 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 42255 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 42256 //PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3 42257 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 42258 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 42259 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 42260 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 42261 //PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4 42262 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 42263 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 42264 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 42265 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 42266 //PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0 42267 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 42268 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 42269 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 42270 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 42271 //PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1 42272 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 42273 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 42274 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 42275 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 42276 //PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0 42277 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 42278 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 42279 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 42280 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 42281 //PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1 42282 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 42283 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 42284 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 42285 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 42286 //PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2 42287 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 42288 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 42289 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 42290 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 42291 //PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3 42292 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 42293 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 42294 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 42295 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 42296 //PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4 42297 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 42298 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 42299 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 42300 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 42301 //PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0 42302 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 42303 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 42304 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 42305 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 42306 //PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1 42307 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 42308 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 42309 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 42310 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 42311 42312 42313 // addressBlock: mmhub_l1tlb_vml1dec:1 42314 //VML1_1_MC_VM_MX_L1_TLB0_STATUS 42315 #define VML1_1_MC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT 0x0 42316 #define VML1_1_MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 42317 #define VML1_1_MC_VM_MX_L1_TLB0_STATUS__BUSY_MASK 0x00000001L 42318 #define VML1_1_MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 42319 //VML1_1_MC_VM_MX_L1_TLB1_STATUS 42320 #define VML1_1_MC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT 0x0 42321 #define VML1_1_MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 42322 #define VML1_1_MC_VM_MX_L1_TLB1_STATUS__BUSY_MASK 0x00000001L 42323 #define VML1_1_MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 42324 //VML1_1_MC_VM_MX_L1_TLB2_STATUS 42325 #define VML1_1_MC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT 0x0 42326 #define VML1_1_MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 42327 #define VML1_1_MC_VM_MX_L1_TLB2_STATUS__BUSY_MASK 0x00000001L 42328 #define VML1_1_MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 42329 //VML1_1_MC_VM_MX_L1_TLB3_STATUS 42330 #define VML1_1_MC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT 0x0 42331 #define VML1_1_MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 42332 #define VML1_1_MC_VM_MX_L1_TLB3_STATUS__BUSY_MASK 0x00000001L 42333 #define VML1_1_MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 42334 //VML1_1_MC_VM_MX_L1_TLB4_STATUS 42335 #define VML1_1_MC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT 0x0 42336 #define VML1_1_MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 42337 #define VML1_1_MC_VM_MX_L1_TLB4_STATUS__BUSY_MASK 0x00000001L 42338 #define VML1_1_MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 42339 //VML1_1_MC_VM_MX_L1_TLB5_STATUS 42340 #define VML1_1_MC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT 0x0 42341 #define VML1_1_MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 42342 #define VML1_1_MC_VM_MX_L1_TLB5_STATUS__BUSY_MASK 0x00000001L 42343 #define VML1_1_MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 42344 //VML1_1_MC_VM_MX_L1_TLB6_STATUS 42345 #define VML1_1_MC_VM_MX_L1_TLB6_STATUS__BUSY__SHIFT 0x0 42346 #define VML1_1_MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 42347 #define VML1_1_MC_VM_MX_L1_TLB6_STATUS__BUSY_MASK 0x00000001L 42348 #define VML1_1_MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 42349 //VML1_1_MC_VM_MX_L1_TLB7_STATUS 42350 #define VML1_1_MC_VM_MX_L1_TLB7_STATUS__BUSY__SHIFT 0x0 42351 #define VML1_1_MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 42352 #define VML1_1_MC_VM_MX_L1_TLB7_STATUS__BUSY_MASK 0x00000001L 42353 #define VML1_1_MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 42354 42355 42356 // addressBlock: mmhub_l1tlb_vml1pldec:1 42357 //VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG 42358 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 42359 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 42360 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 42361 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 42362 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 42363 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 42364 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 42365 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 42366 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 42367 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 42368 //VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG 42369 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 42370 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 42371 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 42372 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 42373 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 42374 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 42375 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 42376 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 42377 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 42378 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 42379 //VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG 42380 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 42381 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 42382 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 42383 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 42384 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 42385 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 42386 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 42387 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 42388 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 42389 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 42390 //VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG 42391 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 42392 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 42393 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 42394 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 42395 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 42396 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 42397 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 42398 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 42399 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 42400 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 42401 //VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 42402 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 42403 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 42404 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 42405 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 42406 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 42407 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 42408 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 42409 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 42410 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 42411 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 42412 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 42413 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 42414 42415 42416 // addressBlock: mmhub_l1tlb_vml1prdec:1 42417 //VML1PR1_MC_VM_MX_L1_PERFCOUNTER_LO 42418 #define VML1PR1_MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 42419 #define VML1PR1_MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 42420 //VML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI 42421 #define VML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 42422 #define VML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 42423 #define VML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 42424 #define VML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 42425 42426 42427 // addressBlock: mmhub_utcl2_atcl2dec:1 42428 //ATCL2_1_ATC_L2_CNTL 42429 #define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 42430 #define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3 42431 #define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6 42432 #define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7 42433 #define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS__SHIFT 0x8 42434 #define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS__SHIFT 0xb 42435 #define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0xe 42436 #define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0xf 42437 #define ATCL2_1_ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x10 42438 #define ATCL2_1_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0x13 42439 #define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L 42440 #define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L 42441 #define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L 42442 #define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L 42443 #define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS_MASK 0x00000300L 42444 #define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS_MASK 0x00001800L 42445 #define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00004000L 42446 #define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00008000L 42447 #define ATCL2_1_ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00070000L 42448 #define ATCL2_1_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00080000L 42449 //ATCL2_1_ATC_L2_CNTL2 42450 #define ATCL2_1_ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 42451 #define ATCL2_1_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6 42452 #define ATCL2_1_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8 42453 #define ATCL2_1_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9 42454 #define ATCL2_1_ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc 42455 #define ATCL2_1_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf 42456 #define ATCL2_1_ATC_L2_CNTL2__L2_BIGK_FRAGMENT_SIZE__SHIFT 0x15 42457 #define ATCL2_1_ATC_L2_CNTL2__L2_4K_BIGK_SWAP_ENABLE__SHIFT 0x1b 42458 #define ATCL2_1_ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL 42459 #define ATCL2_1_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L 42460 #define ATCL2_1_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000100L 42461 #define ATCL2_1_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00000E00L 42462 #define ATCL2_1_ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00007000L 42463 #define ATCL2_1_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x001F8000L 42464 #define ATCL2_1_ATC_L2_CNTL2__L2_BIGK_FRAGMENT_SIZE_MASK 0x07E00000L 42465 #define ATCL2_1_ATC_L2_CNTL2__L2_4K_BIGK_SWAP_ENABLE_MASK 0x08000000L 42466 //ATCL2_1_ATC_L2_CACHE_DATA0 42467 #define ATCL2_1_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 42468 #define ATCL2_1_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 42469 #define ATCL2_1_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 42470 #define ATCL2_1_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x17 42471 #define ATCL2_1_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L 42472 #define ATCL2_1_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L 42473 #define ATCL2_1_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x007FFFFCL 42474 #define ATCL2_1_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x07800000L 42475 //ATCL2_1_ATC_L2_CACHE_DATA1 42476 #define ATCL2_1_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 42477 #define ATCL2_1_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL 42478 //ATCL2_1_ATC_L2_CACHE_DATA2 42479 #define ATCL2_1_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 42480 #define ATCL2_1_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL 42481 //ATCL2_1_ATC_L2_CNTL3 42482 #define ATCL2_1_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x0 42483 #define ATCL2_1_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x3 42484 #define ATCL2_1_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT 0x9 42485 #define ATCL2_1_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x00000007L 42486 #define ATCL2_1_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x000001F8L 42487 #define ATCL2_1_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK 0x00000E00L 42488 //ATCL2_1_ATC_L2_STATUS 42489 #define ATCL2_1_ATC_L2_STATUS__BUSY__SHIFT 0x0 42490 #define ATCL2_1_ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1 42491 #define ATCL2_1_ATC_L2_STATUS__BUSY_MASK 0x00000001L 42492 #define ATCL2_1_ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x7FFFFFFEL 42493 //ATCL2_1_ATC_L2_STATUS2 42494 #define ATCL2_1_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x0 42495 #define ATCL2_1_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x8 42496 #define ATCL2_1_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000FFL 42497 #define ATCL2_1_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000FF00L 42498 //ATCL2_1_ATC_L2_STATUS3 42499 #define ATCL2_1_ATC_L2_STATUS3__BUSY__SHIFT 0x0 42500 #define ATCL2_1_ATC_L2_STATUS3__PARITY_ERROR_INFO__SHIFT 0x1 42501 #define ATCL2_1_ATC_L2_STATUS3__BUSY_MASK 0x00000001L 42502 #define ATCL2_1_ATC_L2_STATUS3__PARITY_ERROR_INFO_MASK 0x7FFFFFFEL 42503 //ATCL2_1_ATC_L2_MISC_CG 42504 #define ATCL2_1_ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6 42505 #define ATCL2_1_ATC_L2_MISC_CG__ENABLE__SHIFT 0x12 42506 #define ATCL2_1_ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 42507 #define ATCL2_1_ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L 42508 #define ATCL2_1_ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L 42509 #define ATCL2_1_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L 42510 //ATCL2_1_ATC_L2_MEM_POWER_LS 42511 #define ATCL2_1_ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 42512 #define ATCL2_1_ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 42513 #define ATCL2_1_ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL 42514 #define ATCL2_1_ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L 42515 //ATCL2_1_ATC_L2_CGTT_CLK_CTRL 42516 #define ATCL2_1_ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 42517 #define ATCL2_1_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 42518 #define ATCL2_1_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf 42519 #define ATCL2_1_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 42520 #define ATCL2_1_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 42521 #define ATCL2_1_ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 42522 #define ATCL2_1_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 42523 #define ATCL2_1_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L 42524 #define ATCL2_1_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L 42525 #define ATCL2_1_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L 42526 //ATCL2_1_ATC_L2_CACHE_4K_DSM_INDEX 42527 #define ATCL2_1_ATC_L2_CACHE_4K_DSM_INDEX__INDEX__SHIFT 0x0 42528 #define ATCL2_1_ATC_L2_CACHE_4K_DSM_INDEX__INDEX_MASK 0x000000FFL 42529 //ATCL2_1_ATC_L2_CACHE_2M_DSM_INDEX 42530 #define ATCL2_1_ATC_L2_CACHE_2M_DSM_INDEX__INDEX__SHIFT 0x0 42531 #define ATCL2_1_ATC_L2_CACHE_2M_DSM_INDEX__INDEX_MASK 0x000000FFL 42532 //ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL 42533 #define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY__SHIFT 0x0 42534 #define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 42535 #define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 42536 #define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 42537 #define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb 42538 #define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS__SHIFT 0xc 42539 #define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT__SHIFT 0xd 42540 #define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT__SHIFT 0xf 42541 #define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE__SHIFT 0x11 42542 #define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY_MASK 0x0000003FL 42543 #define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L 42544 #define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L 42545 #define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L 42546 #define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L 42547 #define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS_MASK 0x00001000L 42548 #define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT_MASK 0x00006000L 42549 #define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT_MASK 0x00018000L 42550 #define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE_MASK 0x00020000L 42551 //ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL 42552 #define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY__SHIFT 0x0 42553 #define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 42554 #define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 42555 #define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 42556 #define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb 42557 #define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS__SHIFT 0xc 42558 #define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT__SHIFT 0xd 42559 #define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT__SHIFT 0xf 42560 #define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE__SHIFT 0x11 42561 #define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY_MASK 0x0000003FL 42562 #define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L 42563 #define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L 42564 #define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L 42565 #define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L 42566 #define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS_MASK 0x00001000L 42567 #define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT_MASK 0x00006000L 42568 #define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT_MASK 0x00018000L 42569 #define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE_MASK 0x00020000L 42570 //ATCL2_1_ATC_L2_CNTL4 42571 #define ATCL2_1_ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x0 42572 #define ATCL2_1_ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0xa 42573 #define ATCL2_1_ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000003FFL 42574 #define ATCL2_1_ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000FFC00L 42575 //ATCL2_1_ATC_L2_MM_GROUP_RT_CLASSES 42576 #define ATCL2_1_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS__SHIFT 0x0 42577 #define ATCL2_1_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS_MASK 0xFFFFFFFFL 42578 42579 42580 // addressBlock: mmhub_utcl2_vml2pfdec:1 42581 //VML2PF1_VM_L2_CNTL 42582 #define VML2PF1_VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 42583 #define VML2PF1_VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 42584 #define VML2PF1_VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 42585 #define VML2PF1_VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 42586 #define VML2PF1_VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 42587 #define VML2PF1_VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 42588 #define VML2PF1_VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa 42589 #define VML2PF1_VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb 42590 #define VML2PF1_VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc 42591 #define VML2PF1_VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf 42592 #define VML2PF1_VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 42593 #define VML2PF1_VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 42594 #define VML2PF1_VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 42595 #define VML2PF1_VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a 42596 #define VML2PF1_VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L 42597 #define VML2PF1_VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L 42598 #define VML2PF1_VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL 42599 #define VML2PF1_VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L 42600 #define VML2PF1_VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L 42601 #define VML2PF1_VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L 42602 #define VML2PF1_VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L 42603 #define VML2PF1_VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L 42604 #define VML2PF1_VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L 42605 #define VML2PF1_VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L 42606 #define VML2PF1_VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L 42607 #define VML2PF1_VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L 42608 #define VML2PF1_VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L 42609 #define VML2PF1_VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L 42610 //VML2PF1_VM_L2_CNTL2 42611 #define VML2PF1_VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 42612 #define VML2PF1_VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 42613 #define VML2PF1_VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 42614 #define VML2PF1_VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 42615 #define VML2PF1_VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 42616 #define VML2PF1_VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a 42617 #define VML2PF1_VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c 42618 #define VML2PF1_VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L 42619 #define VML2PF1_VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L 42620 #define VML2PF1_VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L 42621 #define VML2PF1_VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L 42622 #define VML2PF1_VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L 42623 #define VML2PF1_VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L 42624 #define VML2PF1_VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L 42625 //VML2PF1_VM_L2_CNTL3 42626 #define VML2PF1_VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 42627 #define VML2PF1_VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 42628 #define VML2PF1_VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 42629 #define VML2PF1_VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf 42630 #define VML2PF1_VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 42631 #define VML2PF1_VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 42632 #define VML2PF1_VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 42633 #define VML2PF1_VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c 42634 #define VML2PF1_VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d 42635 #define VML2PF1_VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e 42636 #define VML2PF1_VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f 42637 #define VML2PF1_VM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL 42638 #define VML2PF1_VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L 42639 #define VML2PF1_VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L 42640 #define VML2PF1_VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L 42641 #define VML2PF1_VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L 42642 #define VML2PF1_VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L 42643 #define VML2PF1_VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L 42644 #define VML2PF1_VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L 42645 #define VML2PF1_VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L 42646 #define VML2PF1_VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L 42647 #define VML2PF1_VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L 42648 //VML2PF1_VM_L2_STATUS 42649 #define VML2PF1_VM_L2_STATUS__L2_BUSY__SHIFT 0x0 42650 #define VML2PF1_VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 42651 #define VML2PF1_VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 42652 #define VML2PF1_VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 42653 #define VML2PF1_VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 42654 #define VML2PF1_VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 42655 #define VML2PF1_VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 42656 #define VML2PF1_VM_L2_STATUS__L2_BUSY_MASK 0x00000001L 42657 #define VML2PF1_VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL 42658 #define VML2PF1_VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L 42659 #define VML2PF1_VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L 42660 #define VML2PF1_VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L 42661 #define VML2PF1_VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L 42662 #define VML2PF1_VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L 42663 //VML2PF1_VM_DUMMY_PAGE_FAULT_CNTL 42664 #define VML2PF1_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 42665 #define VML2PF1_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 42666 #define VML2PF1_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 42667 #define VML2PF1_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L 42668 #define VML2PF1_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L 42669 #define VML2PF1_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL 42670 //VML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_LO32 42671 #define VML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 42672 #define VML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 42673 //VML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_HI32 42674 #define VML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0 42675 #define VML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL 42676 //VML2PF1_VM_L2_PROTECTION_FAULT_CNTL 42677 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 42678 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 42679 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 42680 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 42681 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 42682 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 42683 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 42684 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 42685 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 42686 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 42687 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 42688 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb 42689 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 42690 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd 42691 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d 42692 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e 42693 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f 42694 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L 42695 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L 42696 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L 42697 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L 42698 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L 42699 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L 42700 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L 42701 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L 42702 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L 42703 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L 42704 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 42705 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L 42706 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 42707 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L 42708 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L 42709 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L 42710 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L 42711 //VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2 42712 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 42713 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 42714 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 42715 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 42716 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 42717 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL 42718 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L 42719 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L 42720 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L 42721 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L 42722 //VML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL3 42723 #define VML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 42724 #define VML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL 42725 //VML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL4 42726 #define VML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 42727 #define VML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL 42728 //VML2PF1_VM_L2_PROTECTION_FAULT_STATUS 42729 #define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 42730 #define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1 42731 #define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4 42732 #define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8 42733 #define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9 42734 #define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12 42735 #define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13 42736 #define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14 42737 #define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18 42738 #define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19 42739 #define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L 42740 #define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL 42741 #define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L 42742 #define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L 42743 #define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L 42744 #define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L 42745 #define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L 42746 #define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L 42747 #define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L 42748 #define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L 42749 //VML2PF1_VM_L2_PROTECTION_FAULT_ADDR_LO32 42750 #define VML2PF1_VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 42751 #define VML2PF1_VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 42752 //VML2PF1_VM_L2_PROTECTION_FAULT_ADDR_HI32 42753 #define VML2PF1_VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 42754 #define VML2PF1_VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL 42755 //VML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 42756 #define VML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 42757 #define VML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 42758 //VML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 42759 #define VML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0 42760 #define VML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL 42761 //VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 42762 #define VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 42763 #define VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 42764 //VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 42765 #define VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 42766 #define VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 42767 //VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 42768 #define VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 42769 #define VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 42770 //VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 42771 #define VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 42772 #define VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 42773 //VML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 42774 #define VML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 42775 #define VML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL 42776 //VML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 42777 #define VML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0 42778 #define VML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL 42779 //VML2PF1_VM_L2_CNTL4 42780 #define VML2PF1_VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 42781 #define VML2PF1_VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 42782 #define VML2PF1_VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 42783 #define VML2PF1_VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 42784 #define VML2PF1_VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 42785 #define VML2PF1_VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c 42786 #define VML2PF1_VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL 42787 #define VML2PF1_VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L 42788 #define VML2PF1_VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L 42789 #define VML2PF1_VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L 42790 #define VML2PF1_VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L 42791 #define VML2PF1_VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L 42792 //VML2PF1_VM_L2_MM_GROUP_RT_CLASSES 42793 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 42794 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 42795 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 42796 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 42797 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 42798 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 42799 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 42800 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 42801 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 42802 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 42803 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa 42804 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb 42805 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc 42806 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd 42807 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe 42808 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf 42809 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 42810 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 42811 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 42812 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 42813 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 42814 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 42815 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 42816 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 42817 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 42818 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 42819 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a 42820 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b 42821 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c 42822 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d 42823 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e 42824 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f 42825 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L 42826 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L 42827 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L 42828 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L 42829 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L 42830 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L 42831 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L 42832 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L 42833 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L 42834 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L 42835 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L 42836 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L 42837 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L 42838 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L 42839 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L 42840 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L 42841 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L 42842 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L 42843 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L 42844 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L 42845 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L 42846 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L 42847 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L 42848 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L 42849 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L 42850 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L 42851 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L 42852 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L 42853 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L 42854 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L 42855 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L 42856 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L 42857 //VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID 42858 #define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 42859 #define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa 42860 #define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 42861 #define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 42862 #define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 42863 #define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL 42864 #define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L 42865 #define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L 42866 #define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L 42867 #define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L 42868 //VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2 42869 #define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 42870 #define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa 42871 #define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 42872 #define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 42873 #define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 42874 #define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL 42875 #define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L 42876 #define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L 42877 #define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L 42878 #define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L 42879 //VML2PF1_VM_L2_CACHE_PARITY_CNTL 42880 #define VML2PF1_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 42881 #define VML2PF1_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 42882 #define VML2PF1_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 42883 #define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 42884 #define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 42885 #define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 42886 #define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 42887 #define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 42888 #define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc 42889 #define VML2PF1_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L 42890 #define VML2PF1_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L 42891 #define VML2PF1_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L 42892 #define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L 42893 #define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L 42894 #define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L 42895 #define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L 42896 #define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L 42897 #define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L 42898 //VML2PF1_VM_L2_CGTT_CLK_CTRL 42899 #define VML2PF1_VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 42900 #define VML2PF1_VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 42901 #define VML2PF1_VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf 42902 #define VML2PF1_VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 42903 #define VML2PF1_VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 42904 #define VML2PF1_VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 42905 #define VML2PF1_VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 42906 #define VML2PF1_VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L 42907 #define VML2PF1_VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L 42908 #define VML2PF1_VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L 42909 42910 42911 // addressBlock: mmhub_utcl2_vml2vcdec:1 42912 //VML2VC1_VM_CONTEXT0_CNTL 42913 #define VML2VC1_VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 42914 #define VML2VC1_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 42915 #define VML2VC1_VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 42916 #define VML2VC1_VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 42917 #define VML2VC1_VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 42918 #define VML2VC1_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 42919 #define VML2VC1_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 42920 #define VML2VC1_VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 42921 #define VML2VC1_VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 42922 #define VML2VC1_VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 42923 #define VML2VC1_VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 42924 #define VML2VC1_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 42925 #define VML2VC1_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 42926 #define VML2VC1_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 42927 #define VML2VC1_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 42928 #define VML2VC1_VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 42929 #define VML2VC1_VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 42930 #define VML2VC1_VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 42931 #define VML2VC1_VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 42932 #define VML2VC1_VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 42933 #define VML2VC1_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 42934 #define VML2VC1_VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 42935 #define VML2VC1_VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 42936 #define VML2VC1_VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 42937 #define VML2VC1_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 42938 #define VML2VC1_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 42939 #define VML2VC1_VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 42940 #define VML2VC1_VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 42941 #define VML2VC1_VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 42942 #define VML2VC1_VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 42943 #define VML2VC1_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 42944 #define VML2VC1_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 42945 #define VML2VC1_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 42946 #define VML2VC1_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 42947 #define VML2VC1_VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 42948 #define VML2VC1_VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 42949 #define VML2VC1_VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 42950 #define VML2VC1_VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 42951 //VML2VC1_VM_CONTEXT1_CNTL 42952 #define VML2VC1_VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 42953 #define VML2VC1_VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 42954 #define VML2VC1_VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 42955 #define VML2VC1_VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 42956 #define VML2VC1_VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 42957 #define VML2VC1_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 42958 #define VML2VC1_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 42959 #define VML2VC1_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 42960 #define VML2VC1_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 42961 #define VML2VC1_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 42962 #define VML2VC1_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 42963 #define VML2VC1_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 42964 #define VML2VC1_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 42965 #define VML2VC1_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 42966 #define VML2VC1_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 42967 #define VML2VC1_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 42968 #define VML2VC1_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 42969 #define VML2VC1_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 42970 #define VML2VC1_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 42971 #define VML2VC1_VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 42972 #define VML2VC1_VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 42973 #define VML2VC1_VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 42974 #define VML2VC1_VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 42975 #define VML2VC1_VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 42976 #define VML2VC1_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 42977 #define VML2VC1_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 42978 #define VML2VC1_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 42979 #define VML2VC1_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 42980 #define VML2VC1_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 42981 #define VML2VC1_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 42982 #define VML2VC1_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 42983 #define VML2VC1_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 42984 #define VML2VC1_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 42985 #define VML2VC1_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 42986 #define VML2VC1_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 42987 #define VML2VC1_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 42988 #define VML2VC1_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 42989 #define VML2VC1_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 42990 //VML2VC1_VM_CONTEXT2_CNTL 42991 #define VML2VC1_VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 42992 #define VML2VC1_VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 42993 #define VML2VC1_VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 42994 #define VML2VC1_VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 42995 #define VML2VC1_VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 42996 #define VML2VC1_VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 42997 #define VML2VC1_VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 42998 #define VML2VC1_VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 42999 #define VML2VC1_VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 43000 #define VML2VC1_VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 43001 #define VML2VC1_VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 43002 #define VML2VC1_VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 43003 #define VML2VC1_VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 43004 #define VML2VC1_VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 43005 #define VML2VC1_VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 43006 #define VML2VC1_VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 43007 #define VML2VC1_VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 43008 #define VML2VC1_VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 43009 #define VML2VC1_VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 43010 #define VML2VC1_VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 43011 #define VML2VC1_VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 43012 #define VML2VC1_VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 43013 #define VML2VC1_VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 43014 #define VML2VC1_VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 43015 #define VML2VC1_VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 43016 #define VML2VC1_VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 43017 #define VML2VC1_VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 43018 #define VML2VC1_VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 43019 #define VML2VC1_VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 43020 #define VML2VC1_VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 43021 #define VML2VC1_VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 43022 #define VML2VC1_VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 43023 #define VML2VC1_VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 43024 #define VML2VC1_VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 43025 #define VML2VC1_VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 43026 #define VML2VC1_VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 43027 #define VML2VC1_VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 43028 #define VML2VC1_VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 43029 //VML2VC1_VM_CONTEXT3_CNTL 43030 #define VML2VC1_VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 43031 #define VML2VC1_VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 43032 #define VML2VC1_VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 43033 #define VML2VC1_VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 43034 #define VML2VC1_VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 43035 #define VML2VC1_VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 43036 #define VML2VC1_VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 43037 #define VML2VC1_VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 43038 #define VML2VC1_VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 43039 #define VML2VC1_VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 43040 #define VML2VC1_VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 43041 #define VML2VC1_VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 43042 #define VML2VC1_VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 43043 #define VML2VC1_VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 43044 #define VML2VC1_VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 43045 #define VML2VC1_VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 43046 #define VML2VC1_VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 43047 #define VML2VC1_VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 43048 #define VML2VC1_VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 43049 #define VML2VC1_VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 43050 #define VML2VC1_VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 43051 #define VML2VC1_VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 43052 #define VML2VC1_VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 43053 #define VML2VC1_VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 43054 #define VML2VC1_VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 43055 #define VML2VC1_VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 43056 #define VML2VC1_VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 43057 #define VML2VC1_VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 43058 #define VML2VC1_VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 43059 #define VML2VC1_VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 43060 #define VML2VC1_VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 43061 #define VML2VC1_VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 43062 #define VML2VC1_VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 43063 #define VML2VC1_VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 43064 #define VML2VC1_VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 43065 #define VML2VC1_VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 43066 #define VML2VC1_VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 43067 #define VML2VC1_VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 43068 //VML2VC1_VM_CONTEXT4_CNTL 43069 #define VML2VC1_VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 43070 #define VML2VC1_VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 43071 #define VML2VC1_VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 43072 #define VML2VC1_VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 43073 #define VML2VC1_VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 43074 #define VML2VC1_VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 43075 #define VML2VC1_VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 43076 #define VML2VC1_VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 43077 #define VML2VC1_VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 43078 #define VML2VC1_VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 43079 #define VML2VC1_VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 43080 #define VML2VC1_VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 43081 #define VML2VC1_VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 43082 #define VML2VC1_VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 43083 #define VML2VC1_VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 43084 #define VML2VC1_VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 43085 #define VML2VC1_VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 43086 #define VML2VC1_VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 43087 #define VML2VC1_VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 43088 #define VML2VC1_VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 43089 #define VML2VC1_VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 43090 #define VML2VC1_VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 43091 #define VML2VC1_VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 43092 #define VML2VC1_VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 43093 #define VML2VC1_VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 43094 #define VML2VC1_VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 43095 #define VML2VC1_VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 43096 #define VML2VC1_VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 43097 #define VML2VC1_VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 43098 #define VML2VC1_VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 43099 #define VML2VC1_VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 43100 #define VML2VC1_VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 43101 #define VML2VC1_VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 43102 #define VML2VC1_VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 43103 #define VML2VC1_VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 43104 #define VML2VC1_VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 43105 #define VML2VC1_VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 43106 #define VML2VC1_VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 43107 //VML2VC1_VM_CONTEXT5_CNTL 43108 #define VML2VC1_VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 43109 #define VML2VC1_VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 43110 #define VML2VC1_VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 43111 #define VML2VC1_VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 43112 #define VML2VC1_VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 43113 #define VML2VC1_VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 43114 #define VML2VC1_VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 43115 #define VML2VC1_VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 43116 #define VML2VC1_VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 43117 #define VML2VC1_VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 43118 #define VML2VC1_VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 43119 #define VML2VC1_VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 43120 #define VML2VC1_VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 43121 #define VML2VC1_VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 43122 #define VML2VC1_VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 43123 #define VML2VC1_VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 43124 #define VML2VC1_VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 43125 #define VML2VC1_VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 43126 #define VML2VC1_VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 43127 #define VML2VC1_VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 43128 #define VML2VC1_VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 43129 #define VML2VC1_VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 43130 #define VML2VC1_VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 43131 #define VML2VC1_VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 43132 #define VML2VC1_VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 43133 #define VML2VC1_VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 43134 #define VML2VC1_VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 43135 #define VML2VC1_VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 43136 #define VML2VC1_VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 43137 #define VML2VC1_VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 43138 #define VML2VC1_VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 43139 #define VML2VC1_VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 43140 #define VML2VC1_VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 43141 #define VML2VC1_VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 43142 #define VML2VC1_VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 43143 #define VML2VC1_VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 43144 #define VML2VC1_VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 43145 #define VML2VC1_VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 43146 //VML2VC1_VM_CONTEXT6_CNTL 43147 #define VML2VC1_VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 43148 #define VML2VC1_VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 43149 #define VML2VC1_VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 43150 #define VML2VC1_VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 43151 #define VML2VC1_VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 43152 #define VML2VC1_VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 43153 #define VML2VC1_VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 43154 #define VML2VC1_VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 43155 #define VML2VC1_VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 43156 #define VML2VC1_VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 43157 #define VML2VC1_VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 43158 #define VML2VC1_VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 43159 #define VML2VC1_VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 43160 #define VML2VC1_VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 43161 #define VML2VC1_VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 43162 #define VML2VC1_VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 43163 #define VML2VC1_VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 43164 #define VML2VC1_VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 43165 #define VML2VC1_VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 43166 #define VML2VC1_VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 43167 #define VML2VC1_VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 43168 #define VML2VC1_VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 43169 #define VML2VC1_VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 43170 #define VML2VC1_VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 43171 #define VML2VC1_VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 43172 #define VML2VC1_VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 43173 #define VML2VC1_VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 43174 #define VML2VC1_VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 43175 #define VML2VC1_VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 43176 #define VML2VC1_VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 43177 #define VML2VC1_VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 43178 #define VML2VC1_VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 43179 #define VML2VC1_VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 43180 #define VML2VC1_VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 43181 #define VML2VC1_VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 43182 #define VML2VC1_VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 43183 #define VML2VC1_VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 43184 #define VML2VC1_VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 43185 //VML2VC1_VM_CONTEXT7_CNTL 43186 #define VML2VC1_VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 43187 #define VML2VC1_VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 43188 #define VML2VC1_VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 43189 #define VML2VC1_VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 43190 #define VML2VC1_VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 43191 #define VML2VC1_VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 43192 #define VML2VC1_VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 43193 #define VML2VC1_VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 43194 #define VML2VC1_VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 43195 #define VML2VC1_VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 43196 #define VML2VC1_VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 43197 #define VML2VC1_VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 43198 #define VML2VC1_VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 43199 #define VML2VC1_VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 43200 #define VML2VC1_VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 43201 #define VML2VC1_VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 43202 #define VML2VC1_VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 43203 #define VML2VC1_VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 43204 #define VML2VC1_VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 43205 #define VML2VC1_VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 43206 #define VML2VC1_VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 43207 #define VML2VC1_VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 43208 #define VML2VC1_VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 43209 #define VML2VC1_VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 43210 #define VML2VC1_VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 43211 #define VML2VC1_VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 43212 #define VML2VC1_VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 43213 #define VML2VC1_VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 43214 #define VML2VC1_VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 43215 #define VML2VC1_VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 43216 #define VML2VC1_VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 43217 #define VML2VC1_VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 43218 #define VML2VC1_VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 43219 #define VML2VC1_VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 43220 #define VML2VC1_VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 43221 #define VML2VC1_VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 43222 #define VML2VC1_VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 43223 #define VML2VC1_VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 43224 //VML2VC1_VM_CONTEXT8_CNTL 43225 #define VML2VC1_VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 43226 #define VML2VC1_VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 43227 #define VML2VC1_VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 43228 #define VML2VC1_VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 43229 #define VML2VC1_VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 43230 #define VML2VC1_VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 43231 #define VML2VC1_VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 43232 #define VML2VC1_VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 43233 #define VML2VC1_VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 43234 #define VML2VC1_VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 43235 #define VML2VC1_VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 43236 #define VML2VC1_VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 43237 #define VML2VC1_VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 43238 #define VML2VC1_VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 43239 #define VML2VC1_VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 43240 #define VML2VC1_VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 43241 #define VML2VC1_VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 43242 #define VML2VC1_VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 43243 #define VML2VC1_VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 43244 #define VML2VC1_VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 43245 #define VML2VC1_VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 43246 #define VML2VC1_VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 43247 #define VML2VC1_VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 43248 #define VML2VC1_VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 43249 #define VML2VC1_VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 43250 #define VML2VC1_VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 43251 #define VML2VC1_VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 43252 #define VML2VC1_VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 43253 #define VML2VC1_VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 43254 #define VML2VC1_VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 43255 #define VML2VC1_VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 43256 #define VML2VC1_VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 43257 #define VML2VC1_VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 43258 #define VML2VC1_VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 43259 #define VML2VC1_VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 43260 #define VML2VC1_VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 43261 #define VML2VC1_VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 43262 #define VML2VC1_VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 43263 //VML2VC1_VM_CONTEXT9_CNTL 43264 #define VML2VC1_VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 43265 #define VML2VC1_VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 43266 #define VML2VC1_VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 43267 #define VML2VC1_VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 43268 #define VML2VC1_VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 43269 #define VML2VC1_VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 43270 #define VML2VC1_VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 43271 #define VML2VC1_VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 43272 #define VML2VC1_VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 43273 #define VML2VC1_VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 43274 #define VML2VC1_VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 43275 #define VML2VC1_VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 43276 #define VML2VC1_VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 43277 #define VML2VC1_VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 43278 #define VML2VC1_VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 43279 #define VML2VC1_VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 43280 #define VML2VC1_VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 43281 #define VML2VC1_VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 43282 #define VML2VC1_VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 43283 #define VML2VC1_VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 43284 #define VML2VC1_VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 43285 #define VML2VC1_VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 43286 #define VML2VC1_VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 43287 #define VML2VC1_VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 43288 #define VML2VC1_VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 43289 #define VML2VC1_VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 43290 #define VML2VC1_VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 43291 #define VML2VC1_VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 43292 #define VML2VC1_VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 43293 #define VML2VC1_VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 43294 #define VML2VC1_VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 43295 #define VML2VC1_VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 43296 #define VML2VC1_VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 43297 #define VML2VC1_VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 43298 #define VML2VC1_VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 43299 #define VML2VC1_VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 43300 #define VML2VC1_VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 43301 #define VML2VC1_VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 43302 //VML2VC1_VM_CONTEXT10_CNTL 43303 #define VML2VC1_VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 43304 #define VML2VC1_VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 43305 #define VML2VC1_VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 43306 #define VML2VC1_VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 43307 #define VML2VC1_VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 43308 #define VML2VC1_VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 43309 #define VML2VC1_VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 43310 #define VML2VC1_VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 43311 #define VML2VC1_VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 43312 #define VML2VC1_VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 43313 #define VML2VC1_VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 43314 #define VML2VC1_VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 43315 #define VML2VC1_VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 43316 #define VML2VC1_VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 43317 #define VML2VC1_VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 43318 #define VML2VC1_VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 43319 #define VML2VC1_VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 43320 #define VML2VC1_VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 43321 #define VML2VC1_VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 43322 #define VML2VC1_VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 43323 #define VML2VC1_VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 43324 #define VML2VC1_VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 43325 #define VML2VC1_VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 43326 #define VML2VC1_VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 43327 #define VML2VC1_VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 43328 #define VML2VC1_VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 43329 #define VML2VC1_VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 43330 #define VML2VC1_VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 43331 #define VML2VC1_VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 43332 #define VML2VC1_VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 43333 #define VML2VC1_VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 43334 #define VML2VC1_VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 43335 #define VML2VC1_VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 43336 #define VML2VC1_VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 43337 #define VML2VC1_VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 43338 #define VML2VC1_VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 43339 #define VML2VC1_VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 43340 #define VML2VC1_VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 43341 //VML2VC1_VM_CONTEXT11_CNTL 43342 #define VML2VC1_VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 43343 #define VML2VC1_VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 43344 #define VML2VC1_VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 43345 #define VML2VC1_VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 43346 #define VML2VC1_VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 43347 #define VML2VC1_VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 43348 #define VML2VC1_VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 43349 #define VML2VC1_VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 43350 #define VML2VC1_VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 43351 #define VML2VC1_VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 43352 #define VML2VC1_VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 43353 #define VML2VC1_VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 43354 #define VML2VC1_VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 43355 #define VML2VC1_VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 43356 #define VML2VC1_VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 43357 #define VML2VC1_VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 43358 #define VML2VC1_VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 43359 #define VML2VC1_VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 43360 #define VML2VC1_VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 43361 #define VML2VC1_VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 43362 #define VML2VC1_VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 43363 #define VML2VC1_VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 43364 #define VML2VC1_VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 43365 #define VML2VC1_VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 43366 #define VML2VC1_VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 43367 #define VML2VC1_VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 43368 #define VML2VC1_VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 43369 #define VML2VC1_VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 43370 #define VML2VC1_VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 43371 #define VML2VC1_VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 43372 #define VML2VC1_VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 43373 #define VML2VC1_VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 43374 #define VML2VC1_VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 43375 #define VML2VC1_VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 43376 #define VML2VC1_VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 43377 #define VML2VC1_VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 43378 #define VML2VC1_VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 43379 #define VML2VC1_VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 43380 //VML2VC1_VM_CONTEXT12_CNTL 43381 #define VML2VC1_VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 43382 #define VML2VC1_VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 43383 #define VML2VC1_VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 43384 #define VML2VC1_VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 43385 #define VML2VC1_VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 43386 #define VML2VC1_VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 43387 #define VML2VC1_VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 43388 #define VML2VC1_VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 43389 #define VML2VC1_VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 43390 #define VML2VC1_VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 43391 #define VML2VC1_VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 43392 #define VML2VC1_VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 43393 #define VML2VC1_VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 43394 #define VML2VC1_VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 43395 #define VML2VC1_VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 43396 #define VML2VC1_VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 43397 #define VML2VC1_VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 43398 #define VML2VC1_VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 43399 #define VML2VC1_VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 43400 #define VML2VC1_VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 43401 #define VML2VC1_VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 43402 #define VML2VC1_VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 43403 #define VML2VC1_VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 43404 #define VML2VC1_VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 43405 #define VML2VC1_VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 43406 #define VML2VC1_VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 43407 #define VML2VC1_VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 43408 #define VML2VC1_VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 43409 #define VML2VC1_VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 43410 #define VML2VC1_VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 43411 #define VML2VC1_VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 43412 #define VML2VC1_VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 43413 #define VML2VC1_VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 43414 #define VML2VC1_VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 43415 #define VML2VC1_VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 43416 #define VML2VC1_VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 43417 #define VML2VC1_VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 43418 #define VML2VC1_VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 43419 //VML2VC1_VM_CONTEXT13_CNTL 43420 #define VML2VC1_VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 43421 #define VML2VC1_VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 43422 #define VML2VC1_VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 43423 #define VML2VC1_VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 43424 #define VML2VC1_VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 43425 #define VML2VC1_VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 43426 #define VML2VC1_VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 43427 #define VML2VC1_VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 43428 #define VML2VC1_VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 43429 #define VML2VC1_VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 43430 #define VML2VC1_VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 43431 #define VML2VC1_VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 43432 #define VML2VC1_VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 43433 #define VML2VC1_VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 43434 #define VML2VC1_VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 43435 #define VML2VC1_VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 43436 #define VML2VC1_VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 43437 #define VML2VC1_VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 43438 #define VML2VC1_VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 43439 #define VML2VC1_VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 43440 #define VML2VC1_VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 43441 #define VML2VC1_VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 43442 #define VML2VC1_VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 43443 #define VML2VC1_VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 43444 #define VML2VC1_VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 43445 #define VML2VC1_VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 43446 #define VML2VC1_VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 43447 #define VML2VC1_VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 43448 #define VML2VC1_VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 43449 #define VML2VC1_VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 43450 #define VML2VC1_VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 43451 #define VML2VC1_VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 43452 #define VML2VC1_VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 43453 #define VML2VC1_VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 43454 #define VML2VC1_VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 43455 #define VML2VC1_VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 43456 #define VML2VC1_VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 43457 #define VML2VC1_VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 43458 //VML2VC1_VM_CONTEXT14_CNTL 43459 #define VML2VC1_VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 43460 #define VML2VC1_VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 43461 #define VML2VC1_VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 43462 #define VML2VC1_VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 43463 #define VML2VC1_VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 43464 #define VML2VC1_VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 43465 #define VML2VC1_VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 43466 #define VML2VC1_VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 43467 #define VML2VC1_VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 43468 #define VML2VC1_VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 43469 #define VML2VC1_VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 43470 #define VML2VC1_VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 43471 #define VML2VC1_VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 43472 #define VML2VC1_VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 43473 #define VML2VC1_VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 43474 #define VML2VC1_VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 43475 #define VML2VC1_VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 43476 #define VML2VC1_VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 43477 #define VML2VC1_VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 43478 #define VML2VC1_VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 43479 #define VML2VC1_VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 43480 #define VML2VC1_VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 43481 #define VML2VC1_VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 43482 #define VML2VC1_VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 43483 #define VML2VC1_VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 43484 #define VML2VC1_VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 43485 #define VML2VC1_VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 43486 #define VML2VC1_VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 43487 #define VML2VC1_VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 43488 #define VML2VC1_VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 43489 #define VML2VC1_VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 43490 #define VML2VC1_VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 43491 #define VML2VC1_VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 43492 #define VML2VC1_VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 43493 #define VML2VC1_VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 43494 #define VML2VC1_VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 43495 #define VML2VC1_VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 43496 #define VML2VC1_VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 43497 //VML2VC1_VM_CONTEXT15_CNTL 43498 #define VML2VC1_VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 43499 #define VML2VC1_VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 43500 #define VML2VC1_VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 43501 #define VML2VC1_VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 43502 #define VML2VC1_VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 43503 #define VML2VC1_VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 43504 #define VML2VC1_VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 43505 #define VML2VC1_VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 43506 #define VML2VC1_VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 43507 #define VML2VC1_VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 43508 #define VML2VC1_VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 43509 #define VML2VC1_VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 43510 #define VML2VC1_VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 43511 #define VML2VC1_VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 43512 #define VML2VC1_VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 43513 #define VML2VC1_VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 43514 #define VML2VC1_VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 43515 #define VML2VC1_VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 43516 #define VML2VC1_VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 43517 #define VML2VC1_VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 43518 #define VML2VC1_VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 43519 #define VML2VC1_VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 43520 #define VML2VC1_VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 43521 #define VML2VC1_VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 43522 #define VML2VC1_VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 43523 #define VML2VC1_VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 43524 #define VML2VC1_VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 43525 #define VML2VC1_VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 43526 #define VML2VC1_VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 43527 #define VML2VC1_VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 43528 #define VML2VC1_VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 43529 #define VML2VC1_VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 43530 #define VML2VC1_VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 43531 #define VML2VC1_VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 43532 #define VML2VC1_VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 43533 #define VML2VC1_VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 43534 #define VML2VC1_VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 43535 #define VML2VC1_VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 43536 //VML2VC1_VM_CONTEXTS_DISABLE 43537 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 43538 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 43539 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 43540 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 43541 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 43542 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 43543 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 43544 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 43545 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 43546 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 43547 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa 43548 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb 43549 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc 43550 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd 43551 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe 43552 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf 43553 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L 43554 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L 43555 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L 43556 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L 43557 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L 43558 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L 43559 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L 43560 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L 43561 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L 43562 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L 43563 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L 43564 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L 43565 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L 43566 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L 43567 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L 43568 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L 43569 //VML2VC1_VM_INVALIDATE_ENG0_SEM 43570 #define VML2VC1_VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 43571 #define VML2VC1_VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L 43572 //VML2VC1_VM_INVALIDATE_ENG1_SEM 43573 #define VML2VC1_VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 43574 #define VML2VC1_VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L 43575 //VML2VC1_VM_INVALIDATE_ENG2_SEM 43576 #define VML2VC1_VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 43577 #define VML2VC1_VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L 43578 //VML2VC1_VM_INVALIDATE_ENG3_SEM 43579 #define VML2VC1_VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 43580 #define VML2VC1_VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L 43581 //VML2VC1_VM_INVALIDATE_ENG4_SEM 43582 #define VML2VC1_VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 43583 #define VML2VC1_VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L 43584 //VML2VC1_VM_INVALIDATE_ENG5_SEM 43585 #define VML2VC1_VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 43586 #define VML2VC1_VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L 43587 //VML2VC1_VM_INVALIDATE_ENG6_SEM 43588 #define VML2VC1_VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 43589 #define VML2VC1_VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L 43590 //VML2VC1_VM_INVALIDATE_ENG7_SEM 43591 #define VML2VC1_VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 43592 #define VML2VC1_VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L 43593 //VML2VC1_VM_INVALIDATE_ENG8_SEM 43594 #define VML2VC1_VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 43595 #define VML2VC1_VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L 43596 //VML2VC1_VM_INVALIDATE_ENG9_SEM 43597 #define VML2VC1_VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 43598 #define VML2VC1_VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L 43599 //VML2VC1_VM_INVALIDATE_ENG10_SEM 43600 #define VML2VC1_VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 43601 #define VML2VC1_VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L 43602 //VML2VC1_VM_INVALIDATE_ENG11_SEM 43603 #define VML2VC1_VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 43604 #define VML2VC1_VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L 43605 //VML2VC1_VM_INVALIDATE_ENG12_SEM 43606 #define VML2VC1_VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 43607 #define VML2VC1_VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L 43608 //VML2VC1_VM_INVALIDATE_ENG13_SEM 43609 #define VML2VC1_VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 43610 #define VML2VC1_VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L 43611 //VML2VC1_VM_INVALIDATE_ENG14_SEM 43612 #define VML2VC1_VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 43613 #define VML2VC1_VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L 43614 //VML2VC1_VM_INVALIDATE_ENG15_SEM 43615 #define VML2VC1_VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 43616 #define VML2VC1_VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L 43617 //VML2VC1_VM_INVALIDATE_ENG16_SEM 43618 #define VML2VC1_VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 43619 #define VML2VC1_VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L 43620 //VML2VC1_VM_INVALIDATE_ENG17_SEM 43621 #define VML2VC1_VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 43622 #define VML2VC1_VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L 43623 //VML2VC1_VM_INVALIDATE_ENG0_REQ 43624 #define VML2VC1_VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 43625 #define VML2VC1_VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 43626 #define VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 43627 #define VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 43628 #define VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 43629 #define VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 43630 #define VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 43631 #define VML2VC1_VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 43632 #define VML2VC1_VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 43633 #define VML2VC1_VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00030000L 43634 #define VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 43635 #define VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 43636 #define VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 43637 #define VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 43638 #define VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 43639 #define VML2VC1_VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 43640 //VML2VC1_VM_INVALIDATE_ENG1_REQ 43641 #define VML2VC1_VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 43642 #define VML2VC1_VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 43643 #define VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 43644 #define VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 43645 #define VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 43646 #define VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 43647 #define VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 43648 #define VML2VC1_VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 43649 #define VML2VC1_VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 43650 #define VML2VC1_VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00030000L 43651 #define VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 43652 #define VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 43653 #define VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 43654 #define VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 43655 #define VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 43656 #define VML2VC1_VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 43657 //VML2VC1_VM_INVALIDATE_ENG2_REQ 43658 #define VML2VC1_VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 43659 #define VML2VC1_VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 43660 #define VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 43661 #define VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 43662 #define VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 43663 #define VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 43664 #define VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 43665 #define VML2VC1_VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 43666 #define VML2VC1_VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 43667 #define VML2VC1_VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00030000L 43668 #define VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 43669 #define VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 43670 #define VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 43671 #define VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 43672 #define VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 43673 #define VML2VC1_VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 43674 //VML2VC1_VM_INVALIDATE_ENG3_REQ 43675 #define VML2VC1_VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 43676 #define VML2VC1_VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 43677 #define VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 43678 #define VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 43679 #define VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 43680 #define VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 43681 #define VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 43682 #define VML2VC1_VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 43683 #define VML2VC1_VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 43684 #define VML2VC1_VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00030000L 43685 #define VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 43686 #define VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 43687 #define VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 43688 #define VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 43689 #define VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 43690 #define VML2VC1_VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 43691 //VML2VC1_VM_INVALIDATE_ENG4_REQ 43692 #define VML2VC1_VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 43693 #define VML2VC1_VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 43694 #define VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 43695 #define VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 43696 #define VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 43697 #define VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 43698 #define VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 43699 #define VML2VC1_VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 43700 #define VML2VC1_VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 43701 #define VML2VC1_VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00030000L 43702 #define VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 43703 #define VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 43704 #define VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 43705 #define VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 43706 #define VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 43707 #define VML2VC1_VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 43708 //VML2VC1_VM_INVALIDATE_ENG5_REQ 43709 #define VML2VC1_VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 43710 #define VML2VC1_VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 43711 #define VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 43712 #define VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 43713 #define VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 43714 #define VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 43715 #define VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 43716 #define VML2VC1_VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 43717 #define VML2VC1_VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 43718 #define VML2VC1_VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00030000L 43719 #define VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 43720 #define VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 43721 #define VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 43722 #define VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 43723 #define VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 43724 #define VML2VC1_VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 43725 //VML2VC1_VM_INVALIDATE_ENG6_REQ 43726 #define VML2VC1_VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 43727 #define VML2VC1_VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 43728 #define VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 43729 #define VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 43730 #define VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 43731 #define VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 43732 #define VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 43733 #define VML2VC1_VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 43734 #define VML2VC1_VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 43735 #define VML2VC1_VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00030000L 43736 #define VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 43737 #define VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 43738 #define VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 43739 #define VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 43740 #define VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 43741 #define VML2VC1_VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 43742 //VML2VC1_VM_INVALIDATE_ENG7_REQ 43743 #define VML2VC1_VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 43744 #define VML2VC1_VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 43745 #define VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 43746 #define VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 43747 #define VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 43748 #define VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 43749 #define VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 43750 #define VML2VC1_VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 43751 #define VML2VC1_VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 43752 #define VML2VC1_VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00030000L 43753 #define VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 43754 #define VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 43755 #define VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 43756 #define VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 43757 #define VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 43758 #define VML2VC1_VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 43759 //VML2VC1_VM_INVALIDATE_ENG8_REQ 43760 #define VML2VC1_VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 43761 #define VML2VC1_VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 43762 #define VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 43763 #define VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 43764 #define VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 43765 #define VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 43766 #define VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 43767 #define VML2VC1_VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 43768 #define VML2VC1_VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 43769 #define VML2VC1_VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00030000L 43770 #define VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 43771 #define VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 43772 #define VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 43773 #define VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 43774 #define VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 43775 #define VML2VC1_VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 43776 //VML2VC1_VM_INVALIDATE_ENG9_REQ 43777 #define VML2VC1_VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 43778 #define VML2VC1_VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 43779 #define VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 43780 #define VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 43781 #define VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 43782 #define VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 43783 #define VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 43784 #define VML2VC1_VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 43785 #define VML2VC1_VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 43786 #define VML2VC1_VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00030000L 43787 #define VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 43788 #define VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 43789 #define VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 43790 #define VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 43791 #define VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 43792 #define VML2VC1_VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 43793 //VML2VC1_VM_INVALIDATE_ENG10_REQ 43794 #define VML2VC1_VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 43795 #define VML2VC1_VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 43796 #define VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 43797 #define VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 43798 #define VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 43799 #define VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 43800 #define VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 43801 #define VML2VC1_VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 43802 #define VML2VC1_VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 43803 #define VML2VC1_VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00030000L 43804 #define VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 43805 #define VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 43806 #define VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 43807 #define VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 43808 #define VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 43809 #define VML2VC1_VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 43810 //VML2VC1_VM_INVALIDATE_ENG11_REQ 43811 #define VML2VC1_VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 43812 #define VML2VC1_VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 43813 #define VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 43814 #define VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 43815 #define VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 43816 #define VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 43817 #define VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 43818 #define VML2VC1_VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 43819 #define VML2VC1_VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 43820 #define VML2VC1_VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00030000L 43821 #define VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 43822 #define VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 43823 #define VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 43824 #define VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 43825 #define VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 43826 #define VML2VC1_VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 43827 //VML2VC1_VM_INVALIDATE_ENG12_REQ 43828 #define VML2VC1_VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 43829 #define VML2VC1_VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 43830 #define VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 43831 #define VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 43832 #define VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 43833 #define VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 43834 #define VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 43835 #define VML2VC1_VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 43836 #define VML2VC1_VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 43837 #define VML2VC1_VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00030000L 43838 #define VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 43839 #define VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 43840 #define VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 43841 #define VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 43842 #define VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 43843 #define VML2VC1_VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 43844 //VML2VC1_VM_INVALIDATE_ENG13_REQ 43845 #define VML2VC1_VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 43846 #define VML2VC1_VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 43847 #define VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 43848 #define VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 43849 #define VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 43850 #define VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 43851 #define VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 43852 #define VML2VC1_VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 43853 #define VML2VC1_VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 43854 #define VML2VC1_VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00030000L 43855 #define VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 43856 #define VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 43857 #define VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 43858 #define VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 43859 #define VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 43860 #define VML2VC1_VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 43861 //VML2VC1_VM_INVALIDATE_ENG14_REQ 43862 #define VML2VC1_VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 43863 #define VML2VC1_VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 43864 #define VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 43865 #define VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 43866 #define VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 43867 #define VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 43868 #define VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 43869 #define VML2VC1_VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 43870 #define VML2VC1_VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 43871 #define VML2VC1_VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00030000L 43872 #define VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 43873 #define VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 43874 #define VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 43875 #define VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 43876 #define VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 43877 #define VML2VC1_VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 43878 //VML2VC1_VM_INVALIDATE_ENG15_REQ 43879 #define VML2VC1_VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 43880 #define VML2VC1_VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 43881 #define VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 43882 #define VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 43883 #define VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 43884 #define VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 43885 #define VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 43886 #define VML2VC1_VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 43887 #define VML2VC1_VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 43888 #define VML2VC1_VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00030000L 43889 #define VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 43890 #define VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 43891 #define VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 43892 #define VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 43893 #define VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 43894 #define VML2VC1_VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 43895 //VML2VC1_VM_INVALIDATE_ENG16_REQ 43896 #define VML2VC1_VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 43897 #define VML2VC1_VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 43898 #define VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 43899 #define VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 43900 #define VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 43901 #define VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 43902 #define VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 43903 #define VML2VC1_VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 43904 #define VML2VC1_VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 43905 #define VML2VC1_VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00030000L 43906 #define VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 43907 #define VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 43908 #define VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 43909 #define VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 43910 #define VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 43911 #define VML2VC1_VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 43912 //VML2VC1_VM_INVALIDATE_ENG17_REQ 43913 #define VML2VC1_VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 43914 #define VML2VC1_VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 43915 #define VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 43916 #define VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 43917 #define VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 43918 #define VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 43919 #define VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 43920 #define VML2VC1_VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 43921 #define VML2VC1_VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 43922 #define VML2VC1_VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00030000L 43923 #define VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 43924 #define VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 43925 #define VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 43926 #define VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 43927 #define VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 43928 #define VML2VC1_VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 43929 //VML2VC1_VM_INVALIDATE_ENG0_ACK 43930 #define VML2VC1_VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 43931 #define VML2VC1_VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 43932 #define VML2VC1_VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 43933 #define VML2VC1_VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L 43934 //VML2VC1_VM_INVALIDATE_ENG1_ACK 43935 #define VML2VC1_VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 43936 #define VML2VC1_VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 43937 #define VML2VC1_VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 43938 #define VML2VC1_VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L 43939 //VML2VC1_VM_INVALIDATE_ENG2_ACK 43940 #define VML2VC1_VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 43941 #define VML2VC1_VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 43942 #define VML2VC1_VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 43943 #define VML2VC1_VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L 43944 //VML2VC1_VM_INVALIDATE_ENG3_ACK 43945 #define VML2VC1_VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 43946 #define VML2VC1_VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 43947 #define VML2VC1_VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 43948 #define VML2VC1_VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L 43949 //VML2VC1_VM_INVALIDATE_ENG4_ACK 43950 #define VML2VC1_VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 43951 #define VML2VC1_VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 43952 #define VML2VC1_VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 43953 #define VML2VC1_VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L 43954 //VML2VC1_VM_INVALIDATE_ENG5_ACK 43955 #define VML2VC1_VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 43956 #define VML2VC1_VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 43957 #define VML2VC1_VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 43958 #define VML2VC1_VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L 43959 //VML2VC1_VM_INVALIDATE_ENG6_ACK 43960 #define VML2VC1_VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 43961 #define VML2VC1_VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 43962 #define VML2VC1_VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 43963 #define VML2VC1_VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L 43964 //VML2VC1_VM_INVALIDATE_ENG7_ACK 43965 #define VML2VC1_VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 43966 #define VML2VC1_VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 43967 #define VML2VC1_VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 43968 #define VML2VC1_VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L 43969 //VML2VC1_VM_INVALIDATE_ENG8_ACK 43970 #define VML2VC1_VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 43971 #define VML2VC1_VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 43972 #define VML2VC1_VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 43973 #define VML2VC1_VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L 43974 //VML2VC1_VM_INVALIDATE_ENG9_ACK 43975 #define VML2VC1_VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 43976 #define VML2VC1_VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 43977 #define VML2VC1_VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 43978 #define VML2VC1_VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L 43979 //VML2VC1_VM_INVALIDATE_ENG10_ACK 43980 #define VML2VC1_VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 43981 #define VML2VC1_VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 43982 #define VML2VC1_VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 43983 #define VML2VC1_VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L 43984 //VML2VC1_VM_INVALIDATE_ENG11_ACK 43985 #define VML2VC1_VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 43986 #define VML2VC1_VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 43987 #define VML2VC1_VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 43988 #define VML2VC1_VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L 43989 //VML2VC1_VM_INVALIDATE_ENG12_ACK 43990 #define VML2VC1_VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 43991 #define VML2VC1_VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 43992 #define VML2VC1_VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 43993 #define VML2VC1_VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L 43994 //VML2VC1_VM_INVALIDATE_ENG13_ACK 43995 #define VML2VC1_VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 43996 #define VML2VC1_VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 43997 #define VML2VC1_VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 43998 #define VML2VC1_VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L 43999 //VML2VC1_VM_INVALIDATE_ENG14_ACK 44000 #define VML2VC1_VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 44001 #define VML2VC1_VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 44002 #define VML2VC1_VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 44003 #define VML2VC1_VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L 44004 //VML2VC1_VM_INVALIDATE_ENG15_ACK 44005 #define VML2VC1_VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 44006 #define VML2VC1_VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 44007 #define VML2VC1_VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 44008 #define VML2VC1_VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L 44009 //VML2VC1_VM_INVALIDATE_ENG16_ACK 44010 #define VML2VC1_VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 44011 #define VML2VC1_VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 44012 #define VML2VC1_VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 44013 #define VML2VC1_VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L 44014 //VML2VC1_VM_INVALIDATE_ENG17_ACK 44015 #define VML2VC1_VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 44016 #define VML2VC1_VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 44017 #define VML2VC1_VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 44018 #define VML2VC1_VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L 44019 //VML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32 44020 #define VML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 44021 #define VML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 44022 #define VML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 44023 #define VML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 44024 //VML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32 44025 #define VML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 44026 #define VML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 44027 //VML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 44028 #define VML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 44029 #define VML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 44030 #define VML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 44031 #define VML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 44032 //VML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32 44033 #define VML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 44034 #define VML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 44035 //VML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32 44036 #define VML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 44037 #define VML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 44038 #define VML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 44039 #define VML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 44040 //VML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32 44041 #define VML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 44042 #define VML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 44043 //VML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32 44044 #define VML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 44045 #define VML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 44046 #define VML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 44047 #define VML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 44048 //VML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32 44049 #define VML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 44050 #define VML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 44051 //VML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32 44052 #define VML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 44053 #define VML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 44054 #define VML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 44055 #define VML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 44056 //VML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32 44057 #define VML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 44058 #define VML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 44059 //VML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32 44060 #define VML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 44061 #define VML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 44062 #define VML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 44063 #define VML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 44064 //VML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32 44065 #define VML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 44066 #define VML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 44067 //VML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32 44068 #define VML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 44069 #define VML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 44070 #define VML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 44071 #define VML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 44072 //VML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32 44073 #define VML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 44074 #define VML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 44075 //VML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32 44076 #define VML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 44077 #define VML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 44078 #define VML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 44079 #define VML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 44080 //VML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32 44081 #define VML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 44082 #define VML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 44083 //VML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32 44084 #define VML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 44085 #define VML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 44086 #define VML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 44087 #define VML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 44088 //VML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32 44089 #define VML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 44090 #define VML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 44091 //VML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32 44092 #define VML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 44093 #define VML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 44094 #define VML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 44095 #define VML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 44096 //VML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32 44097 #define VML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 44098 #define VML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 44099 //VML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32 44100 #define VML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 44101 #define VML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 44102 #define VML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 44103 #define VML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 44104 //VML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32 44105 #define VML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 44106 #define VML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 44107 //VML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32 44108 #define VML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 44109 #define VML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 44110 #define VML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 44111 #define VML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 44112 //VML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32 44113 #define VML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 44114 #define VML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 44115 //VML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32 44116 #define VML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 44117 #define VML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 44118 #define VML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 44119 #define VML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 44120 //VML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32 44121 #define VML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 44122 #define VML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 44123 //VML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32 44124 #define VML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 44125 #define VML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 44126 #define VML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 44127 #define VML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 44128 //VML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32 44129 #define VML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 44130 #define VML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 44131 //VML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32 44132 #define VML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 44133 #define VML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 44134 #define VML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 44135 #define VML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 44136 //VML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32 44137 #define VML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 44138 #define VML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 44139 //VML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32 44140 #define VML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 44141 #define VML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 44142 #define VML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 44143 #define VML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 44144 //VML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32 44145 #define VML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 44146 #define VML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 44147 //VML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 44148 #define VML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 44149 #define VML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 44150 #define VML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 44151 #define VML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 44152 //VML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 44153 #define VML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 44154 #define VML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 44155 //VML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32 44156 #define VML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 44157 #define VML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 44158 #define VML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 44159 #define VML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 44160 //VML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32 44161 #define VML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 44162 #define VML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 44163 //VML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 44164 #define VML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 44165 #define VML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 44166 //VML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 44167 #define VML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 44168 #define VML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 44169 //VML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 44170 #define VML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 44171 #define VML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 44172 //VML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 44173 #define VML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 44174 #define VML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 44175 //VML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 44176 #define VML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 44177 #define VML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 44178 //VML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 44179 #define VML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 44180 #define VML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 44181 //VML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 44182 #define VML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 44183 #define VML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 44184 //VML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 44185 #define VML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 44186 #define VML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 44187 //VML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 44188 #define VML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 44189 #define VML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 44190 //VML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 44191 #define VML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 44192 #define VML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 44193 //VML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 44194 #define VML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 44195 #define VML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 44196 //VML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 44197 #define VML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 44198 #define VML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 44199 //VML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 44200 #define VML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 44201 #define VML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 44202 //VML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 44203 #define VML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 44204 #define VML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 44205 //VML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 44206 #define VML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 44207 #define VML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 44208 //VML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 44209 #define VML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 44210 #define VML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 44211 //VML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 44212 #define VML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 44213 #define VML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 44214 //VML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 44215 #define VML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 44216 #define VML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 44217 //VML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 44218 #define VML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 44219 #define VML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 44220 //VML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 44221 #define VML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 44222 #define VML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 44223 //VML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 44224 #define VML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 44225 #define VML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 44226 //VML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 44227 #define VML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 44228 #define VML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 44229 //VML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 44230 #define VML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 44231 #define VML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 44232 //VML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 44233 #define VML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 44234 #define VML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 44235 //VML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 44236 #define VML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 44237 #define VML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 44238 //VML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 44239 #define VML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 44240 #define VML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 44241 //VML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 44242 #define VML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 44243 #define VML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 44244 //VML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 44245 #define VML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 44246 #define VML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 44247 //VML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 44248 #define VML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 44249 #define VML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 44250 //VML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 44251 #define VML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 44252 #define VML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 44253 //VML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 44254 #define VML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 44255 #define VML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 44256 //VML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 44257 #define VML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 44258 #define VML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 44259 //VML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 44260 #define VML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 44261 #define VML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 44262 //VML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 44263 #define VML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 44264 #define VML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 44265 //VML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 44266 #define VML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 44267 #define VML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 44268 //VML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 44269 #define VML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 44270 #define VML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 44271 //VML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 44272 #define VML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 44273 #define VML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 44274 //VML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 44275 #define VML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 44276 #define VML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 44277 //VML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 44278 #define VML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 44279 #define VML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 44280 //VML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 44281 #define VML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 44282 #define VML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 44283 //VML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 44284 #define VML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 44285 #define VML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 44286 //VML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 44287 #define VML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 44288 #define VML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 44289 //VML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 44290 #define VML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 44291 #define VML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 44292 //VML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 44293 #define VML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 44294 #define VML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 44295 //VML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 44296 #define VML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 44297 #define VML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 44298 //VML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 44299 #define VML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 44300 #define VML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 44301 //VML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 44302 #define VML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 44303 #define VML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 44304 //VML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 44305 #define VML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 44306 #define VML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 44307 //VML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 44308 #define VML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 44309 #define VML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 44310 //VML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 44311 #define VML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 44312 #define VML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 44313 //VML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 44314 #define VML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 44315 #define VML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 44316 //VML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 44317 #define VML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 44318 #define VML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 44319 //VML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 44320 #define VML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 44321 #define VML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 44322 //VML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 44323 #define VML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 44324 #define VML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 44325 //VML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 44326 #define VML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 44327 #define VML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 44328 //VML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 44329 #define VML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 44330 #define VML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 44331 //VML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 44332 #define VML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 44333 #define VML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 44334 //VML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 44335 #define VML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 44336 #define VML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 44337 //VML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 44338 #define VML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 44339 #define VML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 44340 //VML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 44341 #define VML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 44342 #define VML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 44343 //VML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 44344 #define VML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 44345 #define VML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 44346 //VML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 44347 #define VML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 44348 #define VML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 44349 //VML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 44350 #define VML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 44351 #define VML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 44352 //VML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 44353 #define VML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 44354 #define VML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 44355 //VML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 44356 #define VML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 44357 #define VML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 44358 //VML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 44359 #define VML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 44360 #define VML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 44361 //VML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 44362 #define VML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 44363 #define VML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 44364 //VML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 44365 #define VML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 44366 #define VML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 44367 //VML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 44368 #define VML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 44369 #define VML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 44370 //VML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 44371 #define VML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 44372 #define VML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 44373 //VML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 44374 #define VML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 44375 #define VML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 44376 //VML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 44377 #define VML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 44378 #define VML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 44379 //VML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 44380 #define VML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 44381 #define VML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 44382 //VML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 44383 #define VML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 44384 #define VML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 44385 //VML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 44386 #define VML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 44387 #define VML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 44388 //VML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 44389 #define VML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 44390 #define VML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 44391 //VML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 44392 #define VML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 44393 #define VML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 44394 //VML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 44395 #define VML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 44396 #define VML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 44397 //VML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 44398 #define VML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 44399 #define VML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 44400 //VML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 44401 #define VML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 44402 #define VML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 44403 //VML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 44404 #define VML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 44405 #define VML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 44406 //VML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 44407 #define VML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 44408 #define VML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 44409 //VML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 44410 #define VML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 44411 #define VML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 44412 //VML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 44413 #define VML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 44414 #define VML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 44415 //VML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 44416 #define VML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 44417 #define VML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 44418 //VML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 44419 #define VML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 44420 #define VML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 44421 //VML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 44422 #define VML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 44423 #define VML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 44424 //VML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 44425 #define VML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 44426 #define VML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 44427 //VML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 44428 #define VML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 44429 #define VML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 44430 //VML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 44431 #define VML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 44432 #define VML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 44433 //VML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 44434 #define VML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 44435 #define VML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 44436 //VML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 44437 #define VML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 44438 #define VML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 44439 //VML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 44440 #define VML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 44441 #define VML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 44442 //VML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 44443 #define VML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 44444 #define VML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 44445 //VML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 44446 #define VML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 44447 #define VML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 44448 //VML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 44449 #define VML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 44450 #define VML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 44451 44452 44453 // addressBlock: mmhub_utcl2_vmsharedpfdec:1 44454 //VMSHAREDPF1_MC_VM_NB_MMIOBASE 44455 #define VMSHAREDPF1_MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0 44456 #define VMSHAREDPF1_MC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL 44457 //VMSHAREDPF1_MC_VM_NB_MMIOLIMIT 44458 #define VMSHAREDPF1_MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 44459 #define VMSHAREDPF1_MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL 44460 //VMSHAREDPF1_MC_VM_NB_PCI_CTRL 44461 #define VMSHAREDPF1_MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17 44462 #define VMSHAREDPF1_MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L 44463 //VMSHAREDPF1_MC_VM_NB_PCI_ARB 44464 #define VMSHAREDPF1_MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 44465 #define VMSHAREDPF1_MC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L 44466 //VMSHAREDPF1_MC_VM_NB_TOP_OF_DRAM_SLOT1 44467 #define VMSHAREDPF1_MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 44468 #define VMSHAREDPF1_MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L 44469 //VMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2 44470 #define VMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 44471 #define VMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 44472 #define VMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L 44473 #define VMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L 44474 //VMSHAREDPF1_MC_VM_NB_UPPER_TOP_OF_DRAM2 44475 #define VMSHAREDPF1_MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 44476 #define VMSHAREDPF1_MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x00000FFFL 44477 //VMSHAREDPF1_MC_VM_FB_OFFSET 44478 #define VMSHAREDPF1_MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 44479 #define VMSHAREDPF1_MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL 44480 //VMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 44481 #define VMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 44482 #define VMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL 44483 //VMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 44484 #define VMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 44485 #define VMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL 44486 //VMSHAREDPF1_MC_VM_STEERING 44487 #define VMSHAREDPF1_MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 44488 #define VMSHAREDPF1_MC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L 44489 //VMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ 44490 #define VMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 44491 #define VMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f 44492 #define VMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 44493 #define VMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L 44494 //VMSHAREDPF1_MC_MEM_POWER_LS 44495 #define VMSHAREDPF1_MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 44496 #define VMSHAREDPF1_MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 44497 #define VMSHAREDPF1_MC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL 44498 #define VMSHAREDPF1_MC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L 44499 //VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_START 44500 #define VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 44501 #define VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL 44502 //VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_END 44503 #define VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 44504 #define VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL 44505 //VMSHAREDPF1_MC_VM_APT_CNTL 44506 #define VMSHAREDPF1_MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 44507 #define VMSHAREDPF1_MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 44508 #define VMSHAREDPF1_MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L 44509 #define VMSHAREDPF1_MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L 44510 //VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_START 44511 #define VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0 44512 #define VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL 44513 //VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_END 44514 #define VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0 44515 #define VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL 44516 //VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 44517 #define VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 44518 #define VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L 44519 //VMSHAREDPF1_MC_VM_XGMI_LFB_CNTL 44520 #define VMSHAREDPF1_MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT 0x0 44521 #define VMSHAREDPF1_MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT 0x4 44522 #define VMSHAREDPF1_MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK 0x0000000FL 44523 #define VMSHAREDPF1_MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK 0x000000F0L 44524 //VMSHAREDPF1_MC_VM_XGMI_LFB_SIZE 44525 #define VMSHAREDPF1_MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT 0x0 44526 #define VMSHAREDPF1_MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK 0x0001FFFFL 44527 //VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_CNTL 44528 #define VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE__SHIFT 0x0 44529 #define VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE_MASK 0x00000001L 44530 44531 44532 // addressBlock: mmhub_utcl2_vmsharedvcdec:1 44533 //VMSHAREDVC1_MC_VM_FB_LOCATION_BASE 44534 #define VMSHAREDVC1_MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 44535 #define VMSHAREDVC1_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL 44536 //VMSHAREDVC1_MC_VM_FB_LOCATION_TOP 44537 #define VMSHAREDVC1_MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 44538 #define VMSHAREDVC1_MC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL 44539 //VMSHAREDVC1_MC_VM_AGP_TOP 44540 #define VMSHAREDVC1_MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 44541 #define VMSHAREDVC1_MC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL 44542 //VMSHAREDVC1_MC_VM_AGP_BOT 44543 #define VMSHAREDVC1_MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 44544 #define VMSHAREDVC1_MC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL 44545 //VMSHAREDVC1_MC_VM_AGP_BASE 44546 #define VMSHAREDVC1_MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 44547 #define VMSHAREDVC1_MC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL 44548 //VMSHAREDVC1_MC_VM_SYSTEM_APERTURE_LOW_ADDR 44549 #define VMSHAREDVC1_MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0 44550 #define VMSHAREDVC1_MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL 44551 //VMSHAREDVC1_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 44552 #define VMSHAREDVC1_MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0 44553 #define VMSHAREDVC1_MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL 44554 //VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL 44555 #define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 44556 #define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 44557 #define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 44558 #define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 44559 #define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 44560 #define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb 44561 #define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT 0xd 44562 #define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L 44563 #define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L 44564 #define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L 44565 #define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L 44566 #define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L 44567 #define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00001800L 44568 #define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK 0x00002000L 44569 44570 44571 // addressBlock: mmhub_utcl2_vmsharedhvdec:1 44572 //VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0 44573 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 44574 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 44575 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL 44576 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L 44577 //VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1 44578 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 44579 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 44580 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL 44581 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L 44582 //VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2 44583 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 44584 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 44585 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL 44586 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L 44587 //VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3 44588 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 44589 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 44590 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL 44591 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L 44592 //VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4 44593 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 44594 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 44595 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL 44596 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L 44597 //VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5 44598 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 44599 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 44600 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL 44601 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L 44602 //VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6 44603 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 44604 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 44605 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL 44606 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L 44607 //VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7 44608 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 44609 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 44610 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL 44611 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L 44612 //VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8 44613 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0 44614 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10 44615 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL 44616 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L 44617 //VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9 44618 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0 44619 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10 44620 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL 44621 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L 44622 //VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10 44623 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0 44624 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10 44625 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL 44626 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L 44627 //VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11 44628 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0 44629 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10 44630 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL 44631 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L 44632 //VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12 44633 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0 44634 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10 44635 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL 44636 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L 44637 //VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13 44638 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0 44639 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10 44640 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL 44641 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L 44642 //VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14 44643 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0 44644 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10 44645 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL 44646 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L 44647 //VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15 44648 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0 44649 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10 44650 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL 44651 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L 44652 //VMSHAREDHV1_VM_IOMMU_MMIO_CNTRL_1 44653 #define VMSHAREDHV1_VM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT 0x8 44654 #define VMSHAREDHV1_VM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK 0x00000100L 44655 //VMSHAREDHV1_MC_VM_MARC_BASE_LO_0 44656 #define VMSHAREDHV1_MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc 44657 #define VMSHAREDHV1_MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L 44658 //VMSHAREDHV1_MC_VM_MARC_BASE_LO_1 44659 #define VMSHAREDHV1_MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc 44660 #define VMSHAREDHV1_MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L 44661 //VMSHAREDHV1_MC_VM_MARC_BASE_LO_2 44662 #define VMSHAREDHV1_MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc 44663 #define VMSHAREDHV1_MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L 44664 //VMSHAREDHV1_MC_VM_MARC_BASE_LO_3 44665 #define VMSHAREDHV1_MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc 44666 #define VMSHAREDHV1_MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L 44667 //VMSHAREDHV1_MC_VM_MARC_BASE_HI_0 44668 #define VMSHAREDHV1_MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0 44669 #define VMSHAREDHV1_MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL 44670 //VMSHAREDHV1_MC_VM_MARC_BASE_HI_1 44671 #define VMSHAREDHV1_MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0 44672 #define VMSHAREDHV1_MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL 44673 //VMSHAREDHV1_MC_VM_MARC_BASE_HI_2 44674 #define VMSHAREDHV1_MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0 44675 #define VMSHAREDHV1_MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL 44676 //VMSHAREDHV1_MC_VM_MARC_BASE_HI_3 44677 #define VMSHAREDHV1_MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0 44678 #define VMSHAREDHV1_MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL 44679 //VMSHAREDHV1_MC_VM_MARC_RELOC_LO_0 44680 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0 44681 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1 44682 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc 44683 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L 44684 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L 44685 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L 44686 //VMSHAREDHV1_MC_VM_MARC_RELOC_LO_1 44687 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0 44688 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1 44689 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc 44690 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L 44691 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L 44692 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L 44693 //VMSHAREDHV1_MC_VM_MARC_RELOC_LO_2 44694 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0 44695 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1 44696 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc 44697 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L 44698 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L 44699 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L 44700 //VMSHAREDHV1_MC_VM_MARC_RELOC_LO_3 44701 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0 44702 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1 44703 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc 44704 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L 44705 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L 44706 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L 44707 //VMSHAREDHV1_MC_VM_MARC_RELOC_HI_0 44708 #define VMSHAREDHV1_MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0 44709 #define VMSHAREDHV1_MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL 44710 //VMSHAREDHV1_MC_VM_MARC_RELOC_HI_1 44711 #define VMSHAREDHV1_MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0 44712 #define VMSHAREDHV1_MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL 44713 //VMSHAREDHV1_MC_VM_MARC_RELOC_HI_2 44714 #define VMSHAREDHV1_MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0 44715 #define VMSHAREDHV1_MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL 44716 //VMSHAREDHV1_MC_VM_MARC_RELOC_HI_3 44717 #define VMSHAREDHV1_MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0 44718 #define VMSHAREDHV1_MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL 44719 //VMSHAREDHV1_MC_VM_MARC_LEN_LO_0 44720 #define VMSHAREDHV1_MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc 44721 #define VMSHAREDHV1_MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L 44722 //VMSHAREDHV1_MC_VM_MARC_LEN_LO_1 44723 #define VMSHAREDHV1_MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc 44724 #define VMSHAREDHV1_MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L 44725 //VMSHAREDHV1_MC_VM_MARC_LEN_LO_2 44726 #define VMSHAREDHV1_MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc 44727 #define VMSHAREDHV1_MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L 44728 //VMSHAREDHV1_MC_VM_MARC_LEN_LO_3 44729 #define VMSHAREDHV1_MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc 44730 #define VMSHAREDHV1_MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L 44731 //VMSHAREDHV1_MC_VM_MARC_LEN_HI_0 44732 #define VMSHAREDHV1_MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0 44733 #define VMSHAREDHV1_MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL 44734 //VMSHAREDHV1_MC_VM_MARC_LEN_HI_1 44735 #define VMSHAREDHV1_MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0 44736 #define VMSHAREDHV1_MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL 44737 //VMSHAREDHV1_MC_VM_MARC_LEN_HI_2 44738 #define VMSHAREDHV1_MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0 44739 #define VMSHAREDHV1_MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL 44740 //VMSHAREDHV1_MC_VM_MARC_LEN_HI_3 44741 #define VMSHAREDHV1_MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0 44742 #define VMSHAREDHV1_MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL 44743 //VMSHAREDHV1_VM_IOMMU_CONTROL_REGISTER 44744 #define VMSHAREDHV1_VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0 44745 #define VMSHAREDHV1_VM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L 44746 //VMSHAREDHV1_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 44747 #define VMSHAREDHV1_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd 44748 #define VMSHAREDHV1_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L 44749 //VMSHAREDHV1_VM_PCIE_ATS_CNTL 44750 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL__STU__SHIFT 0x10 44751 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f 44752 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L 44753 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L 44754 //VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_0 44755 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f 44756 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L 44757 //VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_1 44758 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f 44759 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L 44760 //VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_2 44761 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f 44762 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L 44763 //VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_3 44764 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f 44765 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L 44766 //VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_4 44767 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f 44768 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L 44769 //VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_5 44770 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f 44771 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L 44772 //VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_6 44773 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f 44774 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L 44775 //VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_7 44776 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f 44777 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L 44778 //VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_8 44779 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f 44780 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L 44781 //VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_9 44782 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f 44783 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L 44784 //VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_10 44785 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f 44786 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L 44787 //VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_11 44788 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f 44789 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L 44790 //VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_12 44791 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f 44792 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L 44793 //VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_13 44794 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f 44795 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L 44796 //VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_14 44797 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f 44798 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L 44799 //VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_15 44800 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f 44801 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L 44802 //VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL 44803 #define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 44804 #define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 44805 #define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT 0xc 44806 #define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf 44807 #define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 44808 #define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 44809 #define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 44810 #define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 44811 #define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK 0x00007000L 44812 #define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L 44813 #define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L 44814 #define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L 44815 //VMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID 44816 #define VMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 44817 #define VMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f 44818 #define VMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 44819 #define VMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L 44820 //VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE 44821 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0__SHIFT 0x0 44822 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1__SHIFT 0x1 44823 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2__SHIFT 0x2 44824 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3__SHIFT 0x3 44825 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4__SHIFT 0x4 44826 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5__SHIFT 0x5 44827 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6__SHIFT 0x6 44828 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7__SHIFT 0x7 44829 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8__SHIFT 0x8 44830 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9__SHIFT 0x9 44831 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10__SHIFT 0xa 44832 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11__SHIFT 0xb 44833 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12__SHIFT 0xc 44834 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13__SHIFT 0xd 44835 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14__SHIFT 0xe 44836 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15__SHIFT 0xf 44837 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF__SHIFT 0x1f 44838 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0_MASK 0x00000001L 44839 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1_MASK 0x00000002L 44840 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2_MASK 0x00000004L 44841 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3_MASK 0x00000008L 44842 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4_MASK 0x00000010L 44843 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5_MASK 0x00000020L 44844 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6_MASK 0x00000040L 44845 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7_MASK 0x00000080L 44846 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8_MASK 0x00000100L 44847 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9_MASK 0x00000200L 44848 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10_MASK 0x00000400L 44849 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11_MASK 0x00000800L 44850 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12_MASK 0x00001000L 44851 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13_MASK 0x00002000L 44852 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14_MASK 0x00004000L 44853 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15_MASK 0x00008000L 44854 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF_MASK 0x80000000L 44855 44856 44857 // addressBlock: mmhub_utcl2_atcl2pfcntrdec:1 44858 //ATCL2PFCNTR1_ATC_L2_PERFCOUNTER_LO 44859 #define ATCL2PFCNTR1_ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 44860 #define ATCL2PFCNTR1_ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 44861 //ATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI 44862 #define ATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 44863 #define ATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 44864 #define ATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 44865 #define ATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 44866 44867 44868 // addressBlock: mmhub_utcl2_atcl2pfcntldec:1 44869 //ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG 44870 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 44871 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 44872 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 44873 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 44874 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 44875 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 44876 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 44877 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 44878 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 44879 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 44880 //ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG 44881 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 44882 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 44883 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 44884 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 44885 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 44886 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 44887 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 44888 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 44889 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 44890 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 44891 //ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL 44892 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 44893 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 44894 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 44895 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 44896 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 44897 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 44898 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 44899 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 44900 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 44901 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 44902 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 44903 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 44904 44905 44906 // addressBlock: mmhub_utcl2_vml2pldec:1 44907 //VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG 44908 #define VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 44909 #define VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 44910 #define VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 44911 #define VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 44912 #define VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 44913 #define VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 44914 #define VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 44915 #define VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 44916 #define VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 44917 #define VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 44918 //VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG 44919 #define VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 44920 #define VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 44921 #define VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 44922 #define VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 44923 #define VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 44924 #define VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 44925 #define VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 44926 #define VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 44927 #define VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 44928 #define VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 44929 //VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG 44930 #define VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 44931 #define VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 44932 #define VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 44933 #define VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 44934 #define VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 44935 #define VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 44936 #define VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 44937 #define VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 44938 #define VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 44939 #define VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 44940 //VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG 44941 #define VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 44942 #define VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 44943 #define VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 44944 #define VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 44945 #define VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 44946 #define VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 44947 #define VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 44948 #define VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 44949 #define VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 44950 #define VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 44951 //VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG 44952 #define VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 44953 #define VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 44954 #define VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 44955 #define VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c 44956 #define VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d 44957 #define VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL 44958 #define VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L 44959 #define VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L 44960 #define VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L 44961 #define VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L 44962 //VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG 44963 #define VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 44964 #define VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 44965 #define VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 44966 #define VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c 44967 #define VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d 44968 #define VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL 44969 #define VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L 44970 #define VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L 44971 #define VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L 44972 #define VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L 44973 //VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG 44974 #define VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 44975 #define VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 44976 #define VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 44977 #define VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c 44978 #define VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d 44979 #define VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL 44980 #define VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L 44981 #define VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L 44982 #define VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L 44983 #define VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L 44984 //VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG 44985 #define VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 44986 #define VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 44987 #define VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 44988 #define VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c 44989 #define VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d 44990 #define VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL 44991 #define VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L 44992 #define VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L 44993 #define VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L 44994 #define VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L 44995 //VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL 44996 #define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 44997 #define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 44998 #define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 44999 #define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 45000 #define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 45001 #define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 45002 #define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 45003 #define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 45004 #define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 45005 #define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 45006 #define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 45007 #define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 45008 45009 45010 // addressBlock: mmhub_utcl2_vml2prdec:1 45011 //VML2PR1_MC_VM_L2_PERFCOUNTER_LO 45012 #define VML2PR1_MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 45013 #define VML2PR1_MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 45014 //VML2PR1_MC_VM_L2_PERFCOUNTER_HI 45015 #define VML2PR1_MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 45016 #define VML2PR1_MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 45017 #define VML2PR1_MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 45018 #define VML2PR1_MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 45019 45020 #endif 45021