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Searched refs:DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK (Results 1 – 17 of 17) sorted by relevance

/linux-6.14.4/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_0_1_sh_mask.h3941 #define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK … macro
Ddcn_3_0_3_sh_mask.h9112 #define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK … macro
Ddcn_2_1_0_sh_mask.h12745 #define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK … macro
Ddcn_1_0_sh_mask.h12671 #define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK … macro
Ddcn_3_0_1_sh_mask.h12788 #define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK … macro
Ddcn_3_2_1_sh_mask.h11568 #define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK … macro
Ddcn_3_5_0_sh_mask.h15635 #define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK … macro
Ddcn_3_1_5_sh_mask.h13727 #define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK … macro
Ddcn_3_5_1_sh_mask.h15614 #define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK … macro
Ddcn_3_1_2_sh_mask.h15724 #define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK … macro
Ddcn_3_1_6_sh_mask.h16468 #define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK … macro
Ddcn_3_0_2_sh_mask.h13629 #define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK … macro
Ddcn_3_1_4_sh_mask.h21014 #define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK … macro
Ddcn_2_0_0_sh_mask.h15813 #define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK … macro
Ddcn_3_0_0_sh_mask.h14700 #define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK … macro
Ddcn_4_1_0_sh_mask.h12378 #define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK … macro
Ddcn_3_2_0_sh_mask.h11568 #define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK … macro