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Searched refs:CSI2_SIP_TOP_CSI_RX_PORT_BASE_0 (Results 1 – 2 of 2) sorted by relevance

/linux-6.14.4/drivers/media/pci/intel/ipu6/
Dipu6-platform-isys-csi2-reg.h162 #define CSI2_SIP_TOP_CSI_RX_PORT_BASE_0(port) (0x23805c + ((port) / 2) * 0x48) macro
Dipu6-isys-jsl-phy.c180 CSI2_SIP_TOP_CSI_RX_PORT_BASE_0(port); in ipu6_isys_csi2_set_timing()