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Searched refs:AMDGPU_VCN_STACK_SIZE (Results 1 – 11 of 11) sorted by relevance

/linux-6.14.4/drivers/gpu/drm/amd/amdgpu/
Dvcn_v5_0_1.c299 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); in vcn_v5_0_1_mc_resume()
303 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v5_0_1_mc_resume()
305 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v5_0_1_mc_resume()
397 VCN, 0, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
403 AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
407 AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
Dvcn_v2_0.c407 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); in vcn_v2_0_mc_resume()
411 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_0_mc_resume()
413 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_0_mc_resume()
493 UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
498 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
501 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
1972 AMDGPU_VCN_STACK_SIZE); in vcn_v2_0_start_sriov()
1978 AMDGPU_VCN_STACK_SIZE)); in vcn_v2_0_start_sriov()
1983 AMDGPU_VCN_STACK_SIZE)); in vcn_v2_0_start_sriov()
Dvcn_v5_0_0.c380 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); in vcn_v5_0_0_mc_resume()
384 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v5_0_0_mc_resume()
386 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v5_0_0_mc_resume()
476 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
481 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
484 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
Dvcn_v4_0_3.c445 AMDGPU_VCN_STACK_SIZE); in vcn_v4_0_3_mc_resume()
450 AMDGPU_VCN_STACK_SIZE)); in vcn_v4_0_3_mc_resume()
453 AMDGPU_VCN_STACK_SIZE)); in vcn_v4_0_3_mc_resume()
549 VCN, 0, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
555 AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
559 AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
1013 regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE); in vcn_v4_0_3_start_sriov()
1016 AMDGPU_VCN_STACK_SIZE; in vcn_v4_0_3_start_sriov()
Dvcn_v2_5.c494 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); in vcn_v2_5_mc_resume()
498 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_5_mc_resume()
500 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_5_mc_resume()
579 VCN, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
584 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
587 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
1335 AMDGPU_VCN_STACK_SIZE); in vcn_v2_5_sriov_start()
1340 AMDGPU_VCN_STACK_SIZE)); in vcn_v2_5_sriov_start()
1345 AMDGPU_VCN_STACK_SIZE)); in vcn_v2_5_sriov_start()
Dvcn_v4_0_5.c400 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); in vcn_v4_0_5_mc_resume()
404 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v4_0_5_mc_resume()
406 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v4_0_5_mc_resume()
499 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
504 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), in vcn_v4_0_5_mc_resume_dpg_mode()
508 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), in vcn_v4_0_5_mc_resume_dpg_mode()
Dvcn_v4_0.c461 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); in vcn_v4_0_mc_resume()
465 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v4_0_mc_resume()
467 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v4_0_mc_resume()
556 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
561 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
564 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
1388 AMDGPU_VCN_STACK_SIZE); in vcn_v4_0_start_sriov()
1391 AMDGPU_VCN_STACK_SIZE; in vcn_v4_0_start_sriov()
Dvcn_v3_0.c521 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); in vcn_v3_0_mc_resume()
525 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v3_0_mc_resume()
527 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v3_0_mc_resume()
605 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
610 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
613 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
1420 AMDGPU_VCN_STACK_SIZE); in vcn_v3_0_start_sriov()
1423 AMDGPU_VCN_STACK_SIZE; in vcn_v3_0_start_sriov()
Dvcn_v1_0.c377 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); in vcn_v1_0_mc_resume_spg_mode()
381 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v1_0_mc_resume_spg_mode()
383 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v1_0_mc_resume_spg_mode()
448 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE, in vcn_v1_0_mc_resume_dpg_mode()
453 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), in vcn_v1_0_mc_resume_dpg_mode()
456 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), in vcn_v1_0_mc_resume_dpg_mode()
Damdgpu_vcn.h29 #define AMDGPU_VCN_STACK_SIZE (128*1024) macro
Damdgpu_vcn.c190 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE; in amdgpu_vcn_sw_init()