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Searched refs:R_SYSTEM_PLL2CCR_PL2IDIV_Pos (Results 1 – 2 of 2) sorted by relevance

/btstack/port/renesas-ek-ra6m4a-da14531/e2-project/ra/fsp/src/bsp/mcu/all/
H A Dbsp_clocks.c203 (BSP_CFG_PLL2_DIV << R_SYSTEM_PLL2CCR_PL2IDIV_Pos) | \
/btstack/port/renesas-ek-ra6m4a-da14531/e2-project/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
H A Drenesas.h42945 …#define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) … macro