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Searched refs:u_bit_consecutive64 (Results 1 – 11 of 11) sorted by relevance

/aosp_15_r20/external/mesa3d/src/compiler/nir/
H A Dnir_search_helpers.h631 uint64_t high_bits = u_bit_consecutive64(half_bit_size, half_bit_size); in is_upper_half_zero()
656 uint64_t low_bits = u_bit_consecutive64(0, nir_src_bit_size(instr->src[src].src) / 2); in is_lower_half_zero()
674 uint64_t high_bits = u_bit_consecutive64(half_bit_size, half_bit_size); in is_upper_half_negative_one()
694 uint64_t low_bits = u_bit_consecutive64(0, nir_src_bit_size(instr->src[src].src) / 2); in is_lower_half_negative_one()
/aosp_15_r20/external/virglrenderer/src/mesa/util/
H A Dbitscan.h291 u_bit_consecutive64(unsigned start, unsigned count) in u_bit_consecutive64() function
/aosp_15_r20/external/mesa3d/src/util/
H A Dbitscan.h313 u_bit_consecutive64(unsigned start, unsigned count) in u_bit_consecutive64() function
/aosp_15_r20/external/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_descriptors.c1732 u_bit_consecutive64(SI_NUM_SHADER_BUFFERS, SI_NUM_CONST_BUFFERS), in si_rebind_buffer()
1743 u_bit_consecutive64(0, SI_NUM_SHADER_BUFFERS), buf, in si_rebind_buffer()
3148 new_active_mask == u_bit_consecutive64(desc->first_active_slot, desc->num_active_slots)) in si_set_active_descriptors()
H A Dsi_state_shaders.cpp3444 *const_and_shader_buffers = u_bit_consecutive64(start, num_shaderbufs + num_constbufs); in si_get_active_slot_masks()
3459 *samplers_and_images = u_bit_consecutive64(start, num_images / 2 + num_samplers); in si_get_active_slot_masks()
/aosp_15_r20/external/mesa3d/src/mesa/vbo/
H A Dvbo_exec_api.c1130 exec->vtx.enabled = u_bit_consecutive64(0, VBO_ATTRIB_MAX); /* reset all */ in vbo_exec_vtx_init()
/aosp_15_r20/external/mesa3d/src/amd/compiler/
H A Daco_register_allocation.cpp2892 sgpr_operands[reg / 64u] |= u_bit_consecutive64(reg % 64u, size); in emit_parallel_copy_internal()
2896 if (sgpr_operands[reg / 64u] & u_bit_consecutive64(reg % 64u, size)) in emit_parallel_copy_internal()
/aosp_15_r20/external/mesa3d/src/amd/vulkan/
H A Dradv_shader_info.c202 info->inline_push_constant_mask |= u_bit_consecutive64(start, size); in gather_push_constant_info()
H A Dradv_cmd_buffer.c5913 if (mask == u_bit_consecutive64(base, util_last_bit64(mask) - base)) { in radv_emit_all_inline_push_consts()
/aosp_15_r20/external/mesa3d/src/amd/common/
H A Dac_nir_lower_ngg.c3890 unsigned mapped_location = util_bitcount64(out->mask & u_bit_consecutive64(0, io_sem.location)); in ms_store_arrayed_output()
4009 unsigned mapped_location = util_bitcount64(out->mask & u_bit_consecutive64(0, location)); in ms_load_arrayed_output()
/aosp_15_r20/external/mesa3d/src/gallium/drivers/iris/
H A Diris_state.c3270 ~u_bit_consecutive64(start_slot, count + unbind_num_trailing_slots); in iris_set_shader_images()