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Searched refs:u_bit_consecutive (Results 1 – 25 of 46) sorted by relevance

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/aosp_15_r20/external/mesa3d/src/gallium/auxiliary/tgsi/
H A Dtgsi_util.c235 read_mask = u_bit_consecutive(0, dim); in tgsi_util_get_src_usage_mask()
237 read_mask = u_bit_consecutive(0, dim_layer_shadow) & 0xf; in tgsi_util_get_src_usage_mask()
251 read_mask = u_bit_consecutive(0, dim); in tgsi_util_get_src_usage_mask()
261 read_mask = u_bit_consecutive(0, dim); in tgsi_util_get_src_usage_mask()
272 read_mask = u_bit_consecutive(0, dim); in tgsi_util_get_src_usage_mask()
279 read_mask = u_bit_consecutive(0, dim); in tgsi_util_get_src_usage_mask()
300 read_mask = u_bit_consecutive(0, dim); in tgsi_util_get_src_usage_mask()
/aosp_15_r20/external/mesa3d/src/gallium/drivers/lima/ir/pp/
H A Dnir.c45 dest->write_mask = u_bit_consecutive(0, ssa->num_components); in ppir_node_create_ssa()
113 u_bit_consecutive(0, 4)); in ppir_node_add_src()
266 &instr->src[0], u_bit_consecutive(0, instr->num_components)); in ppir_emit_discard_if()
300 mask = u_bit_consecutive(0, instr->num_components); in ppir_emit_intrinsic()
321 mask = u_bit_consecutive(0, instr->num_components); in ppir_emit_intrinsic()
349 mask = u_bit_consecutive(0, instr->num_components); in ppir_emit_intrinsic()
402 dest->write_mask = u_bit_consecutive(0, 4); in ppir_emit_intrinsic()
417 dest->write_mask = u_bit_consecutive(0, 4); in ppir_emit_intrinsic()
426 u_bit_consecutive(0, 4)); in ppir_emit_intrinsic()
519 mask = u_bit_consecutive(0, nir_tex_instr_dest_size(instr)); in ppir_emit_tex()
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H A Dregalloc.c214 ld_dest->write_mask = u_bit_consecutive(0, num_components); in ppir_update_spilled_src()
249 alu_dest->write_mask = u_bit_consecutive(0, num_components); in ppir_update_spilled_src()
298 load->dest.write_mask = u_bit_consecutive(0, num_components); in ppir_update_spilled_dest_load()
321 move_alu->dest.write_mask = u_bit_consecutive(0, num_components); in ppir_update_spilled_dest_load()
/aosp_15_r20/external/mesa3d/src/mesa/state_tracker/
H A Dst_atom_blend.c146 bool same = ctx->DrawBuffer->_IsRGB == u_bit_consecutive(0, num_cb) && in allow_rgb_colormask_promotion()
167 GLbitfield cb_mask = u_bit_consecutive(0, num_cb); in blend_per_rt()
/aosp_15_r20/external/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_blit.c289 unsigned level_mask = u_bit_consecutive(first_level, last_level - first_level + 1); in si_decompress_depth()
445 unsigned level_mask = u_bit_consecutive(first_level, last_level - first_level + 1); in si_blit_decompress_color()
767 u_bit_consecutive(0, info->base.num_images)); in si_check_render_feedback()
861 if (shader_mask & u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS)) { in gfx6_decompress_textures()
899 if (shader_mask & u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS)) { in gfx11_decompress_textures()
1387 stex->dirty_level_mask &= ~u_bit_consecutive(base_level + 1, last_level - base_level); in si_generate_mipmap()
H A Dsi_debug.c779 enabled_constbuf = u_bit_consecutive(0, info->base.num_ubos); in si_dump_descriptors()
780 enabled_shaderbuf = u_bit_consecutive(0, info->base.num_ssbos); in si_dump_descriptors()
782 enabled_images = u_bit_consecutive(0, info->base.num_images); in si_dump_descriptors()
H A Dsi_gfx_cs.c551 u_bit_consecutive(0, ctx->framebuffer.state.nr_cbufs); in si_begin_new_gfx_cs()
555 ctx->framebuffer.dirty_cbufs = u_bit_consecutive(0, 8); in si_begin_new_gfx_cs()
H A Dsi_shader_info.c865 u_bit_consecutive(0, info->base.clip_distance_array_size); in si_nir_scan_shader()
866 info->culldist_mask = u_bit_consecutive(0, info->base.cull_distance_array_size) << in si_nir_scan_shader()
H A Dsi_descriptors.c2034 u_bit_consecutive(SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS, SI_NUM_SHADER_DESCS); in si_mark_shader_pointers_dirty()
2045 u_bit_consecutive(SI_DESCS_FIRST_SHADER, SI_NUM_DESCS - SI_DESCS_FIRST_SHADER); in si_shader_pointers_mark_dirty()
2955 sctx->descriptors_dirty = u_bit_consecutive(0, SI_NUM_DESCS); in si_init_all_descriptors()
3027 … u_bit_consecutive(0, current_shader->cso->info.base.num_images)); in si_gfx_resources_check_encrypted()
3111 …si_image_views_check_encrypted(sctx, &sctx->images[sh], u_bit_consecutive(0, info->base.num_images… in si_compute_resources_check_encrypted()
H A Dsi_compute.c133 unsigned non_fmask_images = u_bit_consecutive(0, sel->info.base.num_images); in si_create_compute_state_async()
1154 mask = u_bit_consecutive(0, info->base.num_images) & images->enabled_mask; in si_check_needs_implicit_sync()
H A Dsi_state.h503 u_bit_consecutive(SI_DESCS_FIRST_SHADER + PIPE_SHADER_##name * SI_NUM_SHADER_DESCS, \
H A Dsi_clear.c220 int max = u_bit_consecutive(0, desc->channel[i].size - 1); in gfx8_get_dcc_clear_parameters()
228 unsigned max = u_bit_consecutive(0, desc->channel[i].size); in gfx8_get_dcc_clear_parameters()
/aosp_15_r20/external/virglrenderer/src/mesa/util/
H A Dbitscan.h282 u_bit_consecutive(unsigned start, unsigned count) in u_bit_consecutive() function
/aosp_15_r20/external/mesa3d/src/util/
H A Dbitscan.h304 u_bit_consecutive(unsigned start, unsigned count) in u_bit_consecutive() function
/aosp_15_r20/external/mesa3d/src/compiler/nir/
H A Dnir_lower_clip_disable.c172 if (clip_plane_enable == u_bit_consecutive(0, shader->info.clip_distance_array_size)) in nir_lower_clip_disable()
/aosp_15_r20/external/mesa3d/src/amd/vulkan/nir/
H A Dradv_nir_lower_vs_inputs.c227 …const unsigned desc_index = util_bitcount(s->info->vs.vb_desc_usage_mask & u_bit_consecutive(0, bi… in lower_load_vs_input()
/aosp_15_r20/external/mesa3d/src/gallium/drivers/virgl/
H A Dvirgl_context.c1351 vctx->atomic_buffer_enabled_mask &= ~u_bit_consecutive(start_slot, count); in virgl_set_hw_atomic_buffers()
1381 binding->ssbo_enabled_mask &= ~u_bit_consecutive(start_slot, count); in virgl_set_shader_buffers()
1437 binding->image_enabled_mask &= ~u_bit_consecutive(start_slot, count); in virgl_set_shader_images()
/aosp_15_r20/external/mesa3d/src/gallium/drivers/lima/
H A Dlima_job.c759 wb[wb_idx].mrt_bits = u_bit_consecutive(0, nr_samples); in lima_pack_wb_zsbuf_reg()
794 wb[wb_idx].mrt_bits = u_bit_consecutive(0, nr_samples); in lima_pack_wb_cbuf_reg()
/aosp_15_r20/external/mesa3d/src/mesa/main/
H A Dstate.c376 if (ctx->Scissor.EnableFlags & u_bit_consecutive(0, num_viewports)) in update_program()
/aosp_15_r20/external/mesa3d/src/gallium/auxiliary/util/
H A Du_vbuf.c376 mgr->allowed_vb_mask = u_bit_consecutive(0, mgr->caps.max_vertex_buffers); in u_vbuf_create()
960 ve->incompatible_elem_mask = u_bit_consecutive(0, count); in u_vbuf_create_vertex_elements()
/aosp_15_r20/external/mesa3d/src/amd/common/
H A Dac_surface.c1120 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8)); in gfx6_surface_settings()
1540 assert(xout.tileSwizzle <= u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8)); in gfx6_compute_surface()
2109 assert(xout.pipeBankXor <= u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8)); in gfx9_compute_miptree()
2311 assert(xout.pipeBankXor <= u_bit_consecutive(0, sizeof(surf->fmask_tile_swizzle) * 8)); in gfx9_compute_miptree()
3172 assert(xout.pipeBankXor <= u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8 + 2)); in gfx12_compute_miptree()
/aosp_15_r20/external/mesa3d/src/gallium/winsys/radeon/drm/
H A Dradeon_drm_winsys.c423 ws->info.enabled_rb_mask = u_bit_consecutive(0, ws->info.max_render_backends); in do_winsys_init()
/aosp_15_r20/external/mesa3d/src/gallium/drivers/freedreno/
H A Dfreedreno_state.c164 const unsigned modified_bits = u_bit_consecutive(start, count); in fd_set_shader_buffers()
/aosp_15_r20/external/mesa3d/src/amd/compiler/
H A Daco_insert_NOPs.cpp389 writemask |= u_bit_consecutive(start, end - start); in handle_raw_hazard_instr()
417 HandleRawHazardBlockState block = {u_bit_consecutive(0, op.size()), min_states}; in handle_raw_hazard()
/aosp_15_r20/external/mesa3d/src/gallium/drivers/r300/compiler/
H A Dnir_to_rc.c520 return u_bit_consecutive(var->data.location_frac, num_components); in ntr_tgsi_var_usage_mask()
555 uint32_t usage_mask = u_bit_consecutive(*frac, instr->num_components); in ntr_output_decl()

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