Searched refs:num_tcs_input_cp (Results 1 – 4 of 4) sorted by relevance
302 uint32_t ac_compute_num_tess_patches(const struct radeon_info *info, uint32_t num_tcs_input_cp,
1135 uint32_t ac_compute_num_tess_patches(const struct radeon_info *info, uint32_t num_tcs_input_cp, in ac_compute_num_tess_patches() argument1159 const unsigned max_verts_per_patch = MAX2(num_tcs_input_cp, num_tcs_output_cp); in ac_compute_num_tess_patches()
4657 uint8_t num_tcs_input_cp = sctx->patch_vertices; in si_update_tess_io_layout_state() local4674 sctx->last_tes_sh_base == tes_sh_base && sctx->last_num_tcs_input_cp == num_tcs_input_cp && in si_update_tess_io_layout_state()4681 sctx->last_num_tcs_input_cp = num_tcs_input_cp; in si_update_tess_io_layout_state()4693 unsigned input_patch_size = num_tcs_input_cp * input_vertex_size; in si_update_tess_io_layout_state()4714 ac_compute_num_tess_patches(&sctx->screen->info, num_tcs_input_cp, in si_update_tess_io_layout_state()4725 assert(num_tcs_input_cp <= 32); in si_update_tess_io_layout_state()4740 (num_patches - 1) | ((num_tcs_output_cp - 1) << 7) | ((num_tcs_input_cp - 1) << 12) | in si_update_tess_io_layout_state()4773 sctx->ls_hs_config |= S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp); in si_update_tess_io_layout_state()
4607 unsigned num_tcs_input_cp = rctx->patch_vertices; in evergreen_setup_tess_constants() local4635 rctx->last_num_tcs_input_cp == num_tcs_input_cp && in evergreen_setup_tess_constants()4647 num_tcs_output_cp = num_tcs_input_cp; in evergreen_setup_tess_constants()4655 input_patch_size = num_tcs_input_cp * input_vertex_size; in evergreen_setup_tess_constants()4667 values[2] = num_tcs_input_cp; in evergreen_setup_tess_constants()4683 rctx->last_num_tcs_input_cp = num_tcs_input_cp; in evergreen_setup_tess_constants()