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Searched refs:getVGPRClassForBitWidth (Results 1 – 4 of 4) sorted by relevance

/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h173 const TargetRegisterClass *getVGPRClassForBitWidth(unsigned BitWidth) const;
H A DSIRegisterInfo.cpp2583 SIRegisterInfo::getVGPRClassForBitWidth(unsigned BitWidth) const { in getVGPRClassForBitWidth() function in SIRegisterInfo
2792 const TargetRegisterClass *VRC = getVGPRClassForBitWidth(Size); in getEquivalentVGPRClass()
3000 return getVGPRClassForBitWidth(std::max(32u, Size)); in getRegClassForSizeOnBank()
3133 return RC.hasSuperClassEq(getVGPRClassForBitWidth(getRegSizeInBits(RC))); in isProperlyAlignedRC()
H A DSIISelLowering.cpp97 addRegisterClass(MVT::v3f32, TRI->getVGPRClassForBitWidth(96)); in SITargetLowering()
103 addRegisterClass(MVT::v4f32, TRI->getVGPRClassForBitWidth(128)); in SITargetLowering()
106 addRegisterClass(MVT::v5f32, TRI->getVGPRClassForBitWidth(160)); in SITargetLowering()
109 addRegisterClass(MVT::v6f32, TRI->getVGPRClassForBitWidth(192)); in SITargetLowering()
112 addRegisterClass(MVT::v3f64, TRI->getVGPRClassForBitWidth(192)); in SITargetLowering()
115 addRegisterClass(MVT::v7f32, TRI->getVGPRClassForBitWidth(224)); in SITargetLowering()
118 addRegisterClass(MVT::v8f32, TRI->getVGPRClassForBitWidth(256)); in SITargetLowering()
121 addRegisterClass(MVT::v4f64, TRI->getVGPRClassForBitWidth(256)); in SITargetLowering()
124 addRegisterClass(MVT::v9f32, TRI->getVGPRClassForBitWidth(288)); in SITargetLowering()
127 addRegisterClass(MVT::v10f32, TRI->getVGPRClassForBitWidth(320)); in SITargetLowering()
[all …]
H A DSILoadStoreOptimizer.cpp1848 : TRI->getVGPRClassForBitWidth(BitWidth); in getTargetRegisterClass()