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Searched refs:getOpcodeDef (Results 1 – 25 of 25) sorted by relevance

/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerCombiner.cpp66 auto *FAddMI = getOpcodeDef(TargetOpcode::G_FADD, Src1, MRI); in matchExtractVecEltPairwiseAdd()
78 getOpcodeDef(TargetOpcode::G_SHUFFLE_VECTOR, Src1Op2, MRI); in matchExtractVecEltPairwiseAdd()
81 Shuffle = getOpcodeDef(TargetOpcode::G_SHUFFLE_VECTOR, Src1Op1, MRI); in matchExtractVecEltPairwiseAdd()
H A DAArch64PostLegalizerLowering.cpp325 auto *InsMI = getOpcodeDef(TargetOpcode::G_INSERT_VECTOR_ELT, in matchDupFromInsertVectorElt()
330 if (!getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, InsMI->getOperand(1).getReg(), in matchDupFromInsertVectorElt()
350 auto *BuildVecMI = getOpcodeDef(TargetOpcode::G_BUILD_VECTOR, in matchDupFromBuildVector()
419 if (!getOpcodeDef<GImplicitDef>(V2, MRI) || in matchEXT()
H A DAArch64InstructionSelector.cpp1658 MachineInstr *AndInst = getOpcodeDef(TargetOpcode::G_AND, LHS, MRI); in tryOptCompareBranchFedByICmp()
1702 AndInst = getOpcodeDef(TargetOpcode::G_AND, LHS, MRI); in tryOptCompareBranchFedByICmp()
2284 return getOpcodeDef(TargetOpcode::G_ICMP, Reg, MRI); in earlySelect()
2291 auto *Cmp = getOpcodeDef(TargetOpcode::G_ICMP, ZExt, MRI); in earlySelect()
3269 auto *LoadMI = getOpcodeDef(TargetOpcode::G_LOAD, SrcReg, MRI); in select()
5297 MachineInstr *Extract = getOpcodeDef(TargetOpcode::G_EXTRACT_VECTOR_ELT, in selectUSMovFromExtend()
5474 getOpcodeDef(TargetOpcode::G_CONSTANT, I.getOperand(Idx).getReg(), MRI); in tryOptConstantBuildVec()
5478 else if ((OpMI = getOpcodeDef(TargetOpcode::G_FCONSTANT, in tryOptConstantBuildVec()
5509 return !getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, Op.getReg(), in tryOptBuildVecToSubregToReg()
6233 getOpcodeDef(TargetOpcode::G_PTR_ADD, Root.getReg(), MRI); in selectAddrModeShiftedExtendXReg()
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp475 MachineInstr *llvm::getOpcodeDef(unsigned Opcode, Register Reg, in getOpcodeDef() function in llvm
617 auto *SrcVec2 = getOpcodeDef<GBuildVector>(Op2, MRI); in ConstantFoldVectorBinop()
621 auto *SrcVec1 = getOpcodeDef<GBuildVector>(Op1, MRI); in ConstantFoldVectorBinop()
804 auto *BV = getOpcodeDef<GBuildVector>(Src, MRI); in ConstantFoldCTLZ()
1185 getOpcodeDef<GImplicitDef>(BV->getSourceReg(SrcIdx), MRI)) in isConstantOrConstantVector()
H A DCombinerHelper.cpp816 if (auto *LoadMI = getOpcodeDef<GSExtLoad>(LoadUser, MRI)) { in matchSextTruncSextLoad()
846 auto *LoadDef = getOpcodeDef<GLoad>(SrcReg, MRI); in matchSextInRegOfLoad()
990 MachineInstr *AddrDef = getOpcodeDef(TargetOpcode::G_PTR_ADD, Addr, MRI); in findPreIndexCandidate()
1707 auto *Unmerge = getOpcodeDef<GUnmerge>(MergedValues[0], MRI); in matchCombineMergeUnmerge()
1734 auto *SrcInstr = getOpcodeDef<GMergeLikeInstr>(SrcReg, MRI); in matchCombineUnmergeMergeToPlainValues()
2377 getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MO.getReg(), MRI); in matchAnyExplicitUseIsUndef()
2384 getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MO.getReg(), MRI); in matchAllExplicitUsesAreUndef()
2396 return getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MI.getOperand(0).getReg(), in matchUndefStore()
2402 return getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MI.getOperand(1).getReg(), in matchUndefSelectCmp()
2584 getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MO.getReg(), MRI); in matchOperandIsUndef()
[all …]
H A DLegalizerHelper.cpp7727 MachineInstr *FIDef = getOpcodeDef(TargetOpcode::G_FRAME_INDEX, Dst, MRI); in lowerMemset()
7882 MachineInstr *FIDef = getOpcodeDef(TargetOpcode::G_FRAME_INDEX, Dst, MRI); in lowerMemcpy()
7990 MachineInstr *FIDef = getOpcodeDef(TargetOpcode::G_FRAME_INDEX, Dst, MRI); in lowerMemmove()
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r522817/include/llvm/CodeGen/GlobalISel/
DUtils.h218 MachineInstr *getOpcodeDef(unsigned Opcode, Register Reg,
255 T *getOpcodeDef(Register Reg, const MachineRegisterInfo &MRI) { in getOpcodeDef() function
DLegalizationArtifactCombiner.h370 if (MachineInstr *DefMI = getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, in tryFoldImplicitDef()
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/include/llvm/CodeGen/GlobalISel/
H A DUtils.h214 MachineInstr *getOpcodeDef(unsigned Opcode, Register Reg,
251 T *getOpcodeDef(Register Reg, const MachineRegisterInfo &MRI) { in getOpcodeDef() function
H A DLegalizationArtifactCombiner.h339 if (MachineInstr *DefMI = getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, in tryFoldImplicitDef()
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567/include/llvm/CodeGen/GlobalISel/
DUtils.h219 MachineInstr *getOpcodeDef(unsigned Opcode, Register Reg,
274 T *getOpcodeDef(Register Reg, const MachineRegisterInfo &MRI) { in getOpcodeDef() function
DLegalizationArtifactCombiner.h370 if (MachineInstr *DefMI = getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, in tryFoldImplicitDef()
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r536225/include/llvm/CodeGen/GlobalISel/
DUtils.h219 MachineInstr *getOpcodeDef(unsigned Opcode, Register Reg,
274 T *getOpcodeDef(Register Reg, const MachineRegisterInfo &MRI) { in getOpcodeDef() function
DLegalizationArtifactCombiner.h370 if (MachineInstr *DefMI = getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, in tryFoldImplicitDef()
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567b/include/llvm/CodeGen/GlobalISel/
DUtils.h219 MachineInstr *getOpcodeDef(unsigned Opcode, Register Reg,
274 T *getOpcodeDef(Register Reg, const MachineRegisterInfo &MRI) { in getOpcodeDef() function
DLegalizationArtifactCombiner.h370 if (MachineInstr *DefMI = getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, in tryFoldImplicitDef()
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp663 MachineInstr *AddrDef = getOpcodeDef(TargetOpcode::G_PTR_ADD, Addr, MRI); in findPreIndexCandidate()
977 MachineInstr *FIDef = getOpcodeDef(TargetOpcode::G_FRAME_INDEX, Dst, MRI); in optimizeMemset()
1092 MachineInstr *FIDef = getOpcodeDef(TargetOpcode::G_FRAME_INDEX, Dst, MRI); in optimizeMemcpy()
1200 MachineInstr *FIDef = getOpcodeDef(TargetOpcode::G_FRAME_INDEX, Dst, MRI); in optimizeMemmove()
H A DUtils.cpp319 llvm::MachineInstr *llvm::getOpcodeDef(unsigned Opcode, Register Reg, in getOpcodeDef() function in llvm
H A DLegalizerHelper.cpp3202 getOpcodeDef(TargetOpcode::G_CONSTANT, Amt, MRI)) { in narrowScalarShift()
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
H A DUtils.h138 MachineInstr *getOpcodeDef(unsigned Opcode, Register Reg,
H A DLegalizationArtifactCombiner.h203 if (MachineInstr *DefMI = getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, in tryFoldImplicitDef()
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64InstructionSelector.cpp2181 auto *LoadMI = getOpcodeDef(TargetOpcode::G_LOAD, SrcReg, MRI); in select()
3685 getOpcodeDef(G_INSERT_VECTOR_ELT, I.getOperand(1).getReg(), MRI); in tryOptVectorDup()
3690 getOpcodeDef(G_IMPLICIT_DEF, InsMI->getOperand(1).getReg(), MRI); in tryOptVectorDup()
4410 getOpcodeDef(TargetOpcode::G_PTR_ADD, Root.getReg(), MRI); in selectAddrModeShiftedExtendXReg()
4496 getOpcodeDef(TargetOpcode::G_PTR_ADD, Root.getReg(), MRI); in selectAddrModeWRO()
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp2794 if (MachineInstr *SrcFNeg = getOpcodeDef(AMDGPU::G_FNEG, ModSrc, MRI)) { in stripAnySourceMods()
2796 if (MachineInstr *SrcFAbs = getOpcodeDef(AMDGPU::G_FABS, ModSrc, MRI)) in stripAnySourceMods()
2798 } else if (MachineInstr *SrcFAbs = getOpcodeDef(AMDGPU::G_FABS, ModSrc, MRI)) in stripAnySourceMods()
H A DAMDGPUInstructionSelector.cpp2527 MachineInstr *Fabs = getOpcodeDef(TargetOpcode::G_FABS, Src, *MRI); in selectG_FNEG()
4570 = getOpcodeDef(TargetOpcode::G_PTR_ADD, Data.N0, *MRI)) { in parseMUBUFAddress()
H A DAMDGPURegisterBankInfo.cpp1299 MachineInstr *Add = getOpcodeDef(AMDGPU::G_ADD, CombinedOffset, *MRI); in setBufferOffsets()