Searched refs:ddr_pll_ctl (Results 1 – 1 of 1) sorted by relevance
858 bdk_lmcx_ddr_pll_ctl_t ddr_pll_ctl; in initialize_ddr_clock() local1004 ddr_pll_ctl.u = BDK_CSR_READ(node, BDK_LMCX_DDR_PLL_CTL(0)); in initialize_ddr_clock()1006 ddr_pll_ctl.cn83xx.reset_n = 0; in initialize_ddr_clock()1007 ddr_pll_ctl.cn83xx.ddr_div_reset = 1; in initialize_ddr_clock()1008 ddr_pll_ctl.cn83xx.phy_dcok = 0; in initialize_ddr_clock()1009 ddr_pll_ctl.cn83xx.dclk_invert = 0; in initialize_ddr_clock()1013 ddr_pll_ctl.cn83xx.dclk_invert = !!strtoul(s, NULL, 0); in initialize_ddr_clock()1015 ddr_pll_ctl.cn83xx.dclk_invert); in initialize_ddr_clock()1019 DRAM_CSR_WRITE(node, BDK_LMCX_DDR_PLL_CTL(0), ddr_pll_ctl.u); in initialize_ddr_clock()1020 ddr_print("%-45s : 0x%016llx\n", "LMC0: DDR_PLL_CTL", ddr_pll_ctl.u); in initialize_ddr_clock()[all …]