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Searched refs:ddr_freq (Results 1 – 25 of 55) sorted by relevance

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/aosp_15_r20/external/coreboot/src/northbridge/intel/pineview/
H A Draminit.c503 u8 ddr_freq, fsb_freq; in sdram_clk_crossing() local
515 ddr_freq = s->selected_timings.mem_clock; in sdram_clk_crossing()
518 mchbar_write32(HMCCMP, clkcross[fsb_freq][ddr_freq][0]); in sdram_clk_crossing()
519 mchbar_write32(HMDCMP, clkcross[fsb_freq][ddr_freq][1]); in sdram_clk_crossing()
520 mchbar_write32(HMBYPCP, clkcross[fsb_freq][ddr_freq][2]); in sdram_clk_crossing()
522 mchbar_write32(HMDCPEXT, clkcross[fsb_freq][ddr_freq][3]); in sdram_clk_crossing()
526 if ((fsb_freq == 0) && (ddr_freq == 1)) { in sdram_clk_crossing()
555 mchbar_write32(CLKXSSH2MCBYP, clkcross2[fsb_freq][ddr_freq][0]); in sdram_clk_crossing()
556 mchbar_write32(CLKXSSH2MCRDQ, clkcross2[fsb_freq][ddr_freq][0]); in sdram_clk_crossing()
557 mchbar_write32(CLKXSSH2MCRDCST, clkcross2[fsb_freq][ddr_freq][0]); in sdram_clk_crossing()
[all …]
/aosp_15_r20/external/arm-trusted-firmware/plat/hisilicon/hikey/
H A Dhikey_ddr.c1408 void hikey_ddr_init(unsigned int ddr_freq) in hikey_ddr_init() argument
1412 assert((ddr_freq == DDR_FREQ_150M) || (ddr_freq == DDR_FREQ_266M) || in hikey_ddr_init()
1413 (ddr_freq == DDR_FREQ_400M) || (ddr_freq == DDR_FREQ_533M) || in hikey_ddr_init()
1414 (ddr_freq == DDR_FREQ_800M)); in hikey_ddr_init()
1418 init_ddr(ddr_freq); in hikey_ddr_init()
1420 ddrc_common_init(ddr_freq); in hikey_ddr_init()
1424 if ((ddr_freq == DDR_FREQ_400M) || (ddr_freq == DDR_FREQ_800M)) { in hikey_ddr_init()
1428 } else if ((ddr_freq == DDR_FREQ_266M) || (ddr_freq == DDR_FREQ_533M)) { in hikey_ddr_init()
H A Dhikey_private.h45 void hikey_ddr_init(unsigned int ddr_freq);
/aosp_15_r20/external/trusty/arm-trusted-firmware/plat/hisilicon/hikey/
Dhikey_ddr.c1408 void hikey_ddr_init(unsigned int ddr_freq) in hikey_ddr_init() argument
1412 assert((ddr_freq == DDR_FREQ_150M) || (ddr_freq == DDR_FREQ_266M) || in hikey_ddr_init()
1413 (ddr_freq == DDR_FREQ_400M) || (ddr_freq == DDR_FREQ_533M) || in hikey_ddr_init()
1414 (ddr_freq == DDR_FREQ_800M)); in hikey_ddr_init()
1418 init_ddr(ddr_freq); in hikey_ddr_init()
1420 ddrc_common_init(ddr_freq); in hikey_ddr_init()
1424 if ((ddr_freq == DDR_FREQ_400M) || (ddr_freq == DDR_FREQ_800M)) { in hikey_ddr_init()
1428 } else if ((ddr_freq == DDR_FREQ_266M) || (ddr_freq == DDR_FREQ_533M)) { in hikey_ddr_init()
Dhikey_private.h45 void hikey_ddr_init(unsigned int ddr_freq);
/aosp_15_r20/external/arm-trusted-firmware/drivers/nxp/ddr/nxp-ddr/
H A Dddrc.c200 unsigned long ddr_freq; in ddrc_set_regs() local
362 ddr_freq = clk / 1000000U; in ddrc_set_regs()
365 tmp |= ddr_freq <= 1333U ? U(0x0080006a) : in ddrc_set_regs()
366 (ddr_freq <= 1600U ? U(0x0070006f) : in ddrc_set_regs()
367 (ddr_freq <= 1867U ? U(0x00700076) : U(0x0060007b))); in ddrc_set_regs()
378 ddr_freq = clk / 1000000U; in ddrc_set_regs()
379 if ((ddr_freq > 1900) && (ddr_freq < 2300)) { in ddrc_set_regs()
/aosp_15_r20/external/trusty/arm-trusted-firmware/drivers/nxp/ddr/nxp-ddr/
Dddrc.c200 unsigned long ddr_freq; in ddrc_set_regs() local
362 ddr_freq = clk / 1000000U; in ddrc_set_regs()
365 tmp |= ddr_freq <= 1333U ? U(0x0080006a) : in ddrc_set_regs()
366 (ddr_freq <= 1600U ? U(0x0070006f) : in ddrc_set_regs()
367 (ddr_freq <= 1867U ? U(0x00700076) : U(0x0060007b))); in ddrc_set_regs()
378 ddr_freq = clk / 1000000U; in ddrc_set_regs()
379 if ((ddr_freq > 1900) && (ddr_freq < 2300)) { in ddrc_set_regs()
/aosp_15_r20/external/coreboot/src/soc/rockchip/rk3399/
H A Dsdram.c454 if (params->ddr_freq < 400 * MHz) in phy_io_config()
456 else if (params->ddr_freq < 800 * MHz) in phy_io_config()
458 else if (params->ddr_freq < 1200 * MHz) in phy_io_config()
1112 unsigned int ddr_freq = params->ddr_freq; in sdram_init() local
1117 if ((dramtype == DDR3 && ddr_freq > 800*MHz) || in sdram_init()
1118 (dramtype == LPDDR3 && ddr_freq > 933*MHz) || in sdram_init()
1119 (dramtype == LPDDR4 && ddr_freq > 800*MHz)) in sdram_init()
1122 rkclk_configure_ddr(ddr_freq); in sdram_init()
1126 phy_dll_bypass_set(rk3399_ddr_publ[channel], ddr_freq); in sdram_init()
/aosp_15_r20/external/coreboot/src/soc/rockchip/rk3288/
H A Dsdram.c633 u32 dinit2 = DIV_ROUND_UP(sdram_params->ddr_freq/MHz * 200000, 1000); in phy_cfg()
647 PRT_DLLLOCK(DIV_ROUND_UP(sdram_params->ddr_freq / MHz * 5120, 1000)) in phy_cfg()
648 | PRT_DLLSRST(DIV_ROUND_UP(sdram_params->ddr_freq / MHz * 50, 1000)) in phy_cfg()
651 PRT_DINIT0(DIV_ROUND_UP(sdram_params->ddr_freq / MHz * 500000, 1000)) in phy_cfg()
652 | PRT_DINIT1(DIV_ROUND_UP(sdram_params->ddr_freq / MHz * 400, 1000))); in phy_cfg()
654 | PRT_DINIT3(DIV_ROUND_UP(sdram_params->ddr_freq / MHz * 1000, 1000))); in phy_cfg()
958 && sdram_params->ddr_freq > 800*MHz) in sdram_init()
960 && sdram_params->ddr_freq > 533*MHz)) in sdram_init()
963 rkclk_configure_ddr(sdram_params->ddr_freq); in sdram_init()
972 phy_dll_bypass_set(ddr_publ_regs, sdram_params->ddr_freq); in sdram_init()
/aosp_15_r20/external/trusty/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/
Dsuspend.c717 sdram_params->ddr_freq = ((fbdiv * 24) / in dmc_suspend()
720 INFO("sdram_params->ddr_freq = %d\n", sdram_params->ddr_freq); in dmc_suspend()
818 phy_dll_bypass_set(channel, sdram_params->ddr_freq); in dmc_resume()
Ddram.h141 uint32_t ddr_freq; member
/aosp_15_r20/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/
H A Dsuspend.c717 sdram_params->ddr_freq = ((fbdiv * 24) / in dmc_suspend()
720 INFO("sdram_params->ddr_freq = %d\n", sdram_params->ddr_freq); in dmc_suspend()
818 phy_dll_bypass_set(channel, sdram_params->ddr_freq); in dmc_resume()
H A Ddram.h141 uint32_t ddr_freq; member
/aosp_15_r20/external/coreboot/src/northbridge/intel/sandybridge/
H A Draminit.c102 const u16 ddr_freq = (1000 << 8) / ctrl->tCK; in setup_sdram_meminfo() local
105 enum cb_err ret = spd_add_smbios17(channel, slot, ddr_freq, in setup_sdram_meminfo()
/aosp_15_r20/external/coreboot/src/mainboard/google/gru/sdram_params/
H A Dsdram-lpddr3-generic-2GB-800.c46 .ddr_freq = 800*MHz,
H A Dsdram-lpddr3-generic-2GB-928.c46 .ddr_freq = 933*MHz,
H A Dsdram-lpddr3-generic-4GB-928.c46 .ddr_freq = 933*MHz,
H A Dsdram-lpddr3-generic-4GB-800.c46 .ddr_freq = 800*MHz,
/aosp_15_r20/external/trusty/arm-trusted-firmware/plat/imx/imx8ulp/
Ddram.c582 static void set_ddr_clk(uint32_t ddr_freq) in set_ddr_clk() argument
586 switch (ddr_freq) { in set_ddr_clk()
/aosp_15_r20/external/coreboot/src/mainboard/google/veyron/sdram_inf/
H A Dsdram-lpddr3-samsung-4GB.inc72 .ddr_freq = 533*MHz,
H A Dsdram-lpddr3-hynix-4GB.inc72 .ddr_freq = 533*MHz,
H A Dsdram-lpddr3-elpida-2GB.inc73 .ddr_freq = 533*MHz,
H A Dsdram-ddr3-hynix-4GB.inc73 .ddr_freq = 666*MHz,
/aosp_15_r20/external/coreboot/src/mainboard/google/veyron_rialto/sdram_inf/
H A Dsdram-lpddr3-K4E8E304EE-1GB.inc72 .ddr_freq = 533*MHz,
/aosp_15_r20/external/coreboot/src/mainboard/google/veyron_mickey/sdram_inf/
H A Dsdram-lpddr3-samsung-2GB-24EB.inc73 .ddr_freq = 533*MHz,

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