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Searched refs:ddr_div_reset (Results 1 – 2 of 2) sorted by relevance

/aosp_15_r20/external/coreboot/src/vendorcode/cavium/bdk/libdram/
H A Dlib_octeon_shared.c1007 ddr_pll_ctl.cn83xx.ddr_div_reset = 1; in initialize_ddr_clock()
1265 c.cn83xx.ddr_div_reset = 1); in initialize_ddr_clock()
1367 c.cn83xx.ddr_div_reset = 0); in initialize_ddr_clock()
/aosp_15_r20/external/coreboot/src/vendorcode/cavium/include/bdk/libbdk-arch/
H A Dbdk-csrs-lmc.h4677 uint64_t ddr_div_reset : 1; /**< [ 22: 22](R/W) DDR postscalar divider reset. */ member
4729 uint64_t ddr_div_reset : 1; /**< [ 22: 22](R/W) DDR postscalar divider reset. */
4776 uint64_t ddr_div_reset : 1; /**< [ 22: 22](R/W) DDR postscalar divider reset. */ member
4828 uint64_t ddr_div_reset : 1; /**< [ 22: 22](R/W) DDR postscalar divider reset. */