Home
last modified time | relevance | path

Searched refs:ddr4_mode (Results 1 – 3 of 3) sorted by relevance

/aosp_15_r20/external/coreboot/src/vendorcode/cavium/bdk/libbdk-dram/
H A Dbdk-dram-size.c158 return (lmcx_ddr_pll_ctl.cn83xx.ddr4_mode != 0); in __bdk_dram_is_ddr4()
/aosp_15_r20/external/coreboot/src/vendorcode/cavium/bdk/libdram/
H A Dlib_octeon_shared.c1273 c.cn83xx.ddr4_mode = (ddr_type == DDR4_DRAM) ? 1 : 0); in initialize_ddr_clock()
1704 if ((ddr_pll_ctl.cn83xx.ddr4_mode == 0) || in dbi_switchover_interface()
/aosp_15_r20/external/coreboot/src/vendorcode/cavium/include/bdk/libbdk-arch/
H A Dbdk-csrs-lmc.h4541 uint64_t ddr4_mode : 1; /**< [ 40: 40](R/W) Reserved. member
4646 uint64_t ddr4_mode : 1; /**< [ 40: 40](R/W) Reserved.
4662 … uint64_t ddr4_mode : 1; /**< [ 29: 29](R/W) DDR4 mode select: 1 = DDR4, 0 = DDR3. */ member
4744 … uint64_t ddr4_mode : 1; /**< [ 29: 29](R/W) DDR4 mode select: 1 = DDR4, 0 = DDR3. */
4761 … uint64_t ddr4_mode : 1; /**< [ 29: 29](R/W) DDR4 mode select: 1 = DDR4, 0 = DDR3. */ member
4843 … uint64_t ddr4_mode : 1; /**< [ 29: 29](R/W) DDR4 mode select: 1 = DDR4, 0 = DDR3. */