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Searched refs:ddr3pwarm (Results 1 – 2 of 2) sorted by relevance

/aosp_15_r20/external/coreboot/src/vendorcode/cavium/bdk/libdram/
H A Dlib_octeon_shared.c848 reset_ctl.cn8.ddr3pwarm = 0; in initialize_ddr_clock()
/aosp_15_r20/external/coreboot/src/vendorcode/cavium/include/bdk/libbdk-arch/
H A Dbdk-csrs-lmc.h16242 …uint64_t ddr3pwarm : 1; /**< [ 1: 1](R/W/H) Memory reset. 1 = Enable preserve mode … member
16276 …uint64_t ddr3pwarm : 1; /**< [ 1: 1](R/W/H) Memory reset. 1 = Enable preserve mode …