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Searched refs:clk_enb_w_clr (Results 1 – 4 of 4) sorted by relevance

/aosp_15_r20/external/coreboot/src/soc/nvidia/tegra124/include/soc/
H A Dclk_rst.h195 u32 clk_enb_w_clr; /* _CLK_ENB_W_CLR, 0x44c */ member
/aosp_15_r20/external/coreboot/src/soc/nvidia/tegra210/include/soc/
H A Dclk_rst.h204 u32 clk_enb_w_clr; /* _CLK_ENB_W_CLR, 0x44c */ member
/aosp_15_r20/external/coreboot/src/soc/nvidia/tegra210/
H A Dclock.c657 CLK_RST_REG(clk_enb_w_clr),
H A Dsdram.c97 write32(&clk_rst->clk_enb_w_clr, param->ClearClk2Mc1); in sdram_start_clocks()