1 #ifndef __BDK_CSRS_IOBN_H__
2 #define __BDK_CSRS_IOBN_H__
3 /* This file is auto-generated. Do not edit */
4
5 /***********************license start***************
6 * Copyright (c) 2003-2017 Cavium Inc. ([email protected]). All rights
7 * reserved.
8 *
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions are
12 * met:
13 *
14 * * Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 *
17 * * Redistributions in binary form must reproduce the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials provided
20 * with the distribution.
21
22 * * Neither the name of Cavium Inc. nor the names of
23 * its contributors may be used to endorse or promote products
24 * derived from this software without specific prior written
25 * permission.
26
27 * This Software, including technical data, may be subject to U.S. export control
28 * laws, including the U.S. Export Administration Act and its associated
29 * regulations, and may be subject to export or import regulations in other
30 * countries.
31
32 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
33 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
34 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
35 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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37 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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40 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
41 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
42 ***********************license end**************************************/
43
44
45 /**
46 * @file
47 *
48 * Configuration and status register (CSR) address and type definitions for
49 * Cavium IOBN.
50 *
51 * This file is auto generated. Do not edit.
52 *
53 */
54
55 /**
56 * Enumeration iobn_bar_e
57 *
58 * IOBN Base Address Register Enumeration
59 * Enumerates the base address registers.
60 */
61 #define BDK_IOBN_BAR_E_IOBNX_PF_BAR0_CN8(a) (0x87e0f0000000ll + 0x1000000ll * (a))
62 #define BDK_IOBN_BAR_E_IOBNX_PF_BAR0_CN8_SIZE 0x800000ull
63 #define BDK_IOBN_BAR_E_IOBNX_PF_BAR0_CN9(a) (0x87e0f0000000ll + 0x1000000ll * (a))
64 #define BDK_IOBN_BAR_E_IOBNX_PF_BAR0_CN9_SIZE 0x100000ull
65 #define BDK_IOBN_BAR_E_IOBNX_PF_BAR4(a) (0x87e0f0f00000ll + 0x1000000ll * (a))
66 #define BDK_IOBN_BAR_E_IOBNX_PF_BAR4_SIZE 0x100000ull
67
68 /**
69 * Enumeration iobn_int_vec_e
70 *
71 * IOBN MSI-X Vector Enumeration
72 * Enumerates the MSI-X interrupt vectors.
73 */
74 #define BDK_IOBN_INT_VEC_E_INTS (0)
75 #define BDK_IOBN_INT_VEC_E_INTS1 (1)
76
77 /**
78 * Enumeration iobn_ncbi_ro_mod_e
79 *
80 * IOBN NCBI Relax Order Modification Enumeration
81 * Enumerates the controls for when CR's are allowed to pass PRs, see
82 * IOBN()_ARBID()_CTL[CRPPR_ENA].
83 */
84 #define BDK_IOBN_NCBI_RO_MOD_E_BUS_CTL (0)
85 #define BDK_IOBN_NCBI_RO_MOD_E_OFF (2)
86 #define BDK_IOBN_NCBI_RO_MOD_E_ON (3)
87 #define BDK_IOBN_NCBI_RO_MOD_E_RSVD (1)
88
89 /**
90 * Enumeration iobn_psb_acc_e
91 *
92 * IOBN Power Serial Bus Accumulator Enumeration
93 * Enumerates the IOB accumulators for IOB slaves, which correspond to index {b} of
94 * PSBS_SYS()_ACCUM().
95 */
96 #define BDK_IOBN_PSB_ACC_E_NCBI_RD_CMD_ACTIVE (0)
97 #define BDK_IOBN_PSB_ACC_E_NCBI_WR_CMD_ACTIVE (1)
98 #define BDK_IOBN_PSB_ACC_E_NCBO_CMD_ACTIVE (2)
99
100 /**
101 * Enumeration iobn_psb_event_e
102 *
103 * IOBN Power Serial Bus Event Enumeration
104 * Enumerates the event numbers for IOB slaves, which correspond to index {b} of
105 * PSBS_SYS()_EVENT()_CFG.
106 */
107 #define BDK_IOBN_PSB_EVENT_E_NCBI_CMD_ACTIVE_BUS0 (8)
108 #define BDK_IOBN_PSB_EVENT_E_NCBI_CMD_ACTIVE_BUS1 (9)
109 #define BDK_IOBN_PSB_EVENT_E_NCBI_CMD_ACTIVE_BUS2 (0xa)
110 #define BDK_IOBN_PSB_EVENT_E_NCBI_CMD_ACTIVE_BUS_RSV0 (0xb)
111 #define BDK_IOBN_PSB_EVENT_E_NCBI_DATA_ACTIVE_BUS0 (0xc)
112 #define BDK_IOBN_PSB_EVENT_E_NCBI_DATA_ACTIVE_BUS1 (0xd)
113 #define BDK_IOBN_PSB_EVENT_E_NCBI_DATA_ACTIVE_BUS2 (0xe)
114 #define BDK_IOBN_PSB_EVENT_E_NCBI_DATA_ACTIVE_BUS_RSV0 (0xf)
115 #define BDK_IOBN_PSB_EVENT_E_NCBI_RD_CMD_ACTIVE_BUS0 (0)
116 #define BDK_IOBN_PSB_EVENT_E_NCBI_RD_CMD_ACTIVE_BUS1 (1)
117 #define BDK_IOBN_PSB_EVENT_E_NCBI_RD_CMD_ACTIVE_BUS2 (2)
118 #define BDK_IOBN_PSB_EVENT_E_NCBI_RD_CMD_ACTIVE_BUS_RSV0 (3)
119 #define BDK_IOBN_PSB_EVENT_E_NCBI_WR_CMD_ACTIVE_BUS0 (4)
120 #define BDK_IOBN_PSB_EVENT_E_NCBI_WR_CMD_ACTIVE_BUS1 (5)
121 #define BDK_IOBN_PSB_EVENT_E_NCBI_WR_CMD_ACTIVE_BUS2 (6)
122 #define BDK_IOBN_PSB_EVENT_E_NCBI_WR_CMD_ACTIVE_BUS_RSV0 (7)
123 #define BDK_IOBN_PSB_EVENT_E_NCBO_CMD_ACTIVE_BUS0 (0x10)
124 #define BDK_IOBN_PSB_EVENT_E_NCBO_CMD_ACTIVE_BUS1 (0x11)
125 #define BDK_IOBN_PSB_EVENT_E_NCBO_CMD_ACTIVE_BUS2 (0x12)
126 #define BDK_IOBN_PSB_EVENT_E_NCBO_CMD_ACTIVE_BUS_RSV0 (0x13)
127 #define BDK_IOBN_PSB_EVENT_E_NCBO_DATA_ACTIVE_BUS0 (0x14)
128 #define BDK_IOBN_PSB_EVENT_E_NCBO_DATA_ACTIVE_BUS1 (0x15)
129 #define BDK_IOBN_PSB_EVENT_E_NCBO_DATA_ACTIVE_BUS2 (0x16)
130 #define BDK_IOBN_PSB_EVENT_E_NCBO_DATA_ACTIVE_BUS_RSV0 (0x17)
131
132 /**
133 * Register (RSL) iobn#_arbid#_ctl
134 *
135 * IOBN NCB Constant Registers
136 * This register set properties for each of the flat ARBIDs.
137 */
138 union bdk_iobnx_arbidx_ctl
139 {
140 uint64_t u;
141 struct bdk_iobnx_arbidx_ctl_s
142 {
143 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
144 uint64_t reserved_10_63 : 54;
145 uint64_t fast_ord : 1; /**< [ 9: 9](R/W) When set IOB will send commits for PR's to IOW as soon as PR is sent to mesh,
146 rather than waiting for ordering. This bit should only be set for non-PEM
147 devices */
148 uint64_t sow_dis : 1; /**< [ 8: 8](R/W) Disables the PCIe store widget for memory store performance. Does not affect
149 observable ordering. No impact on IO stores. For diagnostic use only.
150 0 = Performance optimization on. Issue prefetches on stores to improve
151 store-store ordering.
152 1 = Performance optimization off. No prefetches.
153
154 Internal:
155 The SOW is only available on the NCB2/256b devices which include PEMs, CPT,
156 DPI. The expectation is that CPT and DPI use the RelaxOrder bit so they will
157 only use the widget when the VA address CAM detects and promotes two
158 transactions to the same memory cacheline. */
159 uint64_t crppr_ena : 2; /**< [ 7: 6](R/W) Controls when a CR is allowed to pass a PR for NCBO and NCBI. Enumerated by IOBN_NCBI_RO_MOD_E. */
160 uint64_t prefetch_dis : 1; /**< [ 5: 5](R/W) Disables mesh prefetches. For diagnostic use only.
161 0 = Store-store ordered transactions will issue prefetches before the second
162 store to improve performance.
163 1 = No prefetches. */
164 uint64_t pr_iova_dis : 1; /**< [ 4: 4](R/W) PR queue IOVA comparison disable. For diagnostic use only.
165 0 = PR will not pass a younger PR with the same IOVA.
166 1 = PR may pass a younger PR with the same IOVA, if the relaxed ordering request
167 and [RO_DIS] bit allow it. */
168 uint64_t ro_dis : 1; /**< [ 3: 3](R/W) Disable relaxed ordering. For diagnostic use only.
169 0 = Relaxed ordering is performed if the NCB device requests it.
170 1 = IOB ignores the relaxed ordering request bit and treats all requests as
171 strictly ordered. */
172 uint64_t st_ld_ord : 1; /**< [ 2: 2](R/W) If enabled, NP queue loaded in order it arrives from NCBI. [ST_ST_ORD] should also be
173 set when this bit is set. NP queue will not pass PS queue.
174
175 Internal:
176 FIXME check meaning */
177 uint64_t st_st_ord : 1; /**< [ 1: 1](R/W) If enabled, PS queue used (ignore RO bit). Placed in order store arrives.
178 Internal:
179 FIXME check meaning */
180 uint64_t ld_ld_ord : 1; /**< [ 0: 0](R/W) Load-load ordering. For diagnostic use only.
181 0 = NPR may pass NPR under some cases. The ordering is based on SMMU completion
182 ordering.
183 1 = NPR never passes NPR; the NPR ordering is based strictly on NCB arrival order.
184 This may harm performance. */
185 #else /* Word 0 - Little Endian */
186 uint64_t ld_ld_ord : 1; /**< [ 0: 0](R/W) Load-load ordering. For diagnostic use only.
187 0 = NPR may pass NPR under some cases. The ordering is based on SMMU completion
188 ordering.
189 1 = NPR never passes NPR; the NPR ordering is based strictly on NCB arrival order.
190 This may harm performance. */
191 uint64_t st_st_ord : 1; /**< [ 1: 1](R/W) If enabled, PS queue used (ignore RO bit). Placed in order store arrives.
192 Internal:
193 FIXME check meaning */
194 uint64_t st_ld_ord : 1; /**< [ 2: 2](R/W) If enabled, NP queue loaded in order it arrives from NCBI. [ST_ST_ORD] should also be
195 set when this bit is set. NP queue will not pass PS queue.
196
197 Internal:
198 FIXME check meaning */
199 uint64_t ro_dis : 1; /**< [ 3: 3](R/W) Disable relaxed ordering. For diagnostic use only.
200 0 = Relaxed ordering is performed if the NCB device requests it.
201 1 = IOB ignores the relaxed ordering request bit and treats all requests as
202 strictly ordered. */
203 uint64_t pr_iova_dis : 1; /**< [ 4: 4](R/W) PR queue IOVA comparison disable. For diagnostic use only.
204 0 = PR will not pass a younger PR with the same IOVA.
205 1 = PR may pass a younger PR with the same IOVA, if the relaxed ordering request
206 and [RO_DIS] bit allow it. */
207 uint64_t prefetch_dis : 1; /**< [ 5: 5](R/W) Disables mesh prefetches. For diagnostic use only.
208 0 = Store-store ordered transactions will issue prefetches before the second
209 store to improve performance.
210 1 = No prefetches. */
211 uint64_t crppr_ena : 2; /**< [ 7: 6](R/W) Controls when a CR is allowed to pass a PR for NCBO and NCBI. Enumerated by IOBN_NCBI_RO_MOD_E. */
212 uint64_t sow_dis : 1; /**< [ 8: 8](R/W) Disables the PCIe store widget for memory store performance. Does not affect
213 observable ordering. No impact on IO stores. For diagnostic use only.
214 0 = Performance optimization on. Issue prefetches on stores to improve
215 store-store ordering.
216 1 = Performance optimization off. No prefetches.
217
218 Internal:
219 The SOW is only available on the NCB2/256b devices which include PEMs, CPT,
220 DPI. The expectation is that CPT and DPI use the RelaxOrder bit so they will
221 only use the widget when the VA address CAM detects and promotes two
222 transactions to the same memory cacheline. */
223 uint64_t fast_ord : 1; /**< [ 9: 9](R/W) When set IOB will send commits for PR's to IOW as soon as PR is sent to mesh,
224 rather than waiting for ordering. This bit should only be set for non-PEM
225 devices */
226 uint64_t reserved_10_63 : 54;
227 #endif /* Word 0 - End */
228 } s;
229 /* struct bdk_iobnx_arbidx_ctl_s cn; */
230 };
231 typedef union bdk_iobnx_arbidx_ctl bdk_iobnx_arbidx_ctl_t;
232
233 static inline uint64_t BDK_IOBNX_ARBIDX_CTL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_IOBNX_ARBIDX_CTL(unsigned long a,unsigned long b)234 static inline uint64_t BDK_IOBNX_ARBIDX_CTL(unsigned long a, unsigned long b)
235 {
236 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b<=19)))
237 return 0x87e0f0002100ll + 0x1000000ll * ((a) & 0x1) + 8ll * ((b) & 0x1f);
238 __bdk_csr_fatal("IOBNX_ARBIDX_CTL", 2, a, b, 0, 0);
239 }
240
241 #define typedef_BDK_IOBNX_ARBIDX_CTL(a,b) bdk_iobnx_arbidx_ctl_t
242 #define bustype_BDK_IOBNX_ARBIDX_CTL(a,b) BDK_CSR_TYPE_RSL
243 #define basename_BDK_IOBNX_ARBIDX_CTL(a,b) "IOBNX_ARBIDX_CTL"
244 #define device_bar_BDK_IOBNX_ARBIDX_CTL(a,b) 0x0 /* PF_BAR0 */
245 #define busnum_BDK_IOBNX_ARBIDX_CTL(a,b) (a)
246 #define arguments_BDK_IOBNX_ARBIDX_CTL(a,b) (a),(b),-1,-1
247
248 /**
249 * Register (RSL) iobn#_bistr_reg
250 *
251 * IOBN BIST Status Register
252 * This register contains the result of the BIST run on the IOB rclk memories.
253 */
254 union bdk_iobnx_bistr_reg
255 {
256 uint64_t u;
257 struct bdk_iobnx_bistr_reg_s
258 {
259 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
260 uint64_t reserved_22_63 : 42;
261 uint64_t status : 22; /**< [ 21: 0](RO/H) Memory BIST status.
262 Internal:
263 \<18\> = gmr_ixofifo_bstatus_rclk.
264 \<17\> = sli_preq_2_ffifo_bstatus_rclk.
265 \<16\> = sli_req_2_ffifo_bstatus_rclk.
266 \<15\> = sli_preq_1_ffifo_bstatus_rclk.
267 \<14\> = sli_req_1_ffifo_bstatus_rclk.
268 \<13\> = sli_preq_0_ffifo_bstatus_rclk.
269 \<12\> = sli_req_0_ffifo_bstatus_rclk.
270 \<11\> = iop_ffifo_bstatus_rclk.
271 \<10\> = ixo_icc_fifo0_bstatus_rclk.
272 \<9\> = ixo_icc_fifo1_bstatus_rclk.
273 \<8\> = ixo_ics_mem_bstatus_rclk.
274 \<7\> = iob_mem_data_xmd0_bstatus_rclk.
275 \<6\> = iob_mem_data_xmd1_bstatus_rclk.
276 \<5\> = ics_cmd_fifo_bstatus_rclk.
277 \<4\> = ixo_xmd_mem0_bstatus_rclk.
278 \<3\> = ixo_xmd_mem1_bstatus_rclk.
279 \<2\> = iobn_iorn_ffifo0_bstatus_rclk.
280 \<1\> = iobn_iorn_ffifo1_bstatus_rclk.
281 \<0\> = ixo_smmu_mem0_bstatus_rclk. */
282 #else /* Word 0 - Little Endian */
283 uint64_t status : 22; /**< [ 21: 0](RO/H) Memory BIST status.
284 Internal:
285 \<18\> = gmr_ixofifo_bstatus_rclk.
286 \<17\> = sli_preq_2_ffifo_bstatus_rclk.
287 \<16\> = sli_req_2_ffifo_bstatus_rclk.
288 \<15\> = sli_preq_1_ffifo_bstatus_rclk.
289 \<14\> = sli_req_1_ffifo_bstatus_rclk.
290 \<13\> = sli_preq_0_ffifo_bstatus_rclk.
291 \<12\> = sli_req_0_ffifo_bstatus_rclk.
292 \<11\> = iop_ffifo_bstatus_rclk.
293 \<10\> = ixo_icc_fifo0_bstatus_rclk.
294 \<9\> = ixo_icc_fifo1_bstatus_rclk.
295 \<8\> = ixo_ics_mem_bstatus_rclk.
296 \<7\> = iob_mem_data_xmd0_bstatus_rclk.
297 \<6\> = iob_mem_data_xmd1_bstatus_rclk.
298 \<5\> = ics_cmd_fifo_bstatus_rclk.
299 \<4\> = ixo_xmd_mem0_bstatus_rclk.
300 \<3\> = ixo_xmd_mem1_bstatus_rclk.
301 \<2\> = iobn_iorn_ffifo0_bstatus_rclk.
302 \<1\> = iobn_iorn_ffifo1_bstatus_rclk.
303 \<0\> = ixo_smmu_mem0_bstatus_rclk. */
304 uint64_t reserved_22_63 : 42;
305 #endif /* Word 0 - End */
306 } s;
307 struct bdk_iobnx_bistr_reg_cn81xx
308 {
309 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
310 uint64_t reserved_19_63 : 45;
311 uint64_t status : 19; /**< [ 18: 0](RO/H) Memory BIST status.
312 Internal:
313 \<18\> = gmr_ixofifo_bstatus_rclk.
314 \<17\> = sli_preq_2_ffifo_bstatus_rclk.
315 \<16\> = sli_req_2_ffifo_bstatus_rclk.
316 \<15\> = sli_preq_1_ffifo_bstatus_rclk.
317 \<14\> = sli_req_1_ffifo_bstatus_rclk.
318 \<13\> = sli_preq_0_ffifo_bstatus_rclk.
319 \<12\> = sli_req_0_ffifo_bstatus_rclk.
320 \<11\> = iop_ffifo_bstatus_rclk.
321 \<10\> = ixo_icc_fifo0_bstatus_rclk.
322 \<9\> = ixo_icc_fifo1_bstatus_rclk.
323 \<8\> = ixo_ics_mem_bstatus_rclk.
324 \<7\> = iob_mem_data_xmd0_bstatus_rclk.
325 \<6\> = 0 unused.
326 \<5\> = ics_cmd_fifo_bstatus_rclk.
327 \<4\> = ixo_xmd_mem0_bstatus_rclk.
328 \<3\> = ixo_xmd_mem1_bstatus_rclk.
329 \<2\> = iobn_iorn_ffifo0_bstatus_rclk.
330 \<1\> = iobn_iorn_ffifo1_bstatus_rclk.
331 \<0\> = ixo_smmu_mem0_bstatus_rclk. */
332 #else /* Word 0 - Little Endian */
333 uint64_t status : 19; /**< [ 18: 0](RO/H) Memory BIST status.
334 Internal:
335 \<18\> = gmr_ixofifo_bstatus_rclk.
336 \<17\> = sli_preq_2_ffifo_bstatus_rclk.
337 \<16\> = sli_req_2_ffifo_bstatus_rclk.
338 \<15\> = sli_preq_1_ffifo_bstatus_rclk.
339 \<14\> = sli_req_1_ffifo_bstatus_rclk.
340 \<13\> = sli_preq_0_ffifo_bstatus_rclk.
341 \<12\> = sli_req_0_ffifo_bstatus_rclk.
342 \<11\> = iop_ffifo_bstatus_rclk.
343 \<10\> = ixo_icc_fifo0_bstatus_rclk.
344 \<9\> = ixo_icc_fifo1_bstatus_rclk.
345 \<8\> = ixo_ics_mem_bstatus_rclk.
346 \<7\> = iob_mem_data_xmd0_bstatus_rclk.
347 \<6\> = 0 unused.
348 \<5\> = ics_cmd_fifo_bstatus_rclk.
349 \<4\> = ixo_xmd_mem0_bstatus_rclk.
350 \<3\> = ixo_xmd_mem1_bstatus_rclk.
351 \<2\> = iobn_iorn_ffifo0_bstatus_rclk.
352 \<1\> = iobn_iorn_ffifo1_bstatus_rclk.
353 \<0\> = ixo_smmu_mem0_bstatus_rclk. */
354 uint64_t reserved_19_63 : 45;
355 #endif /* Word 0 - End */
356 } cn81xx;
357 struct bdk_iobnx_bistr_reg_cn88xx
358 {
359 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
360 uint64_t reserved_19_63 : 45;
361 uint64_t status : 19; /**< [ 18: 0](RO/H) Memory BIST status.
362 Internal:
363 \<18\> = gmr_ixofifo_bstatus_rclk.
364 \<17\> = sli_preq_2_ffifo_bstatus_rclk.
365 \<16\> = sli_req_2_ffifo_bstatus_rclk.
366 \<15\> = sli_preq_1_ffifo_bstatus_rclk.
367 \<14\> = sli_req_1_ffifo_bstatus_rclk.
368 \<13\> = sli_preq_0_ffifo_bstatus_rclk.
369 \<12\> = sli_req_0_ffifo_bstatus_rclk.
370 \<11\> = iop_ffifo_bstatus_rclk.
371 \<10\> = ixo_icc_fifo0_bstatus_rclk.
372 \<9\> = ixo_icc_fifo1_bstatus_rclk.
373 \<8\> = ixo_ics_mem_bstatus_rclk.
374 \<7\> = iob_mem_data_xmd0_bstatus_rclk.
375 \<6\> = iob_mem_data_xmd1_bstatus_rclk.
376 \<5\> = ics_cmd_fifo_bstatus_rclk.
377 \<4\> = ixo_xmd_mem0_bstatus_rclk.
378 \<3\> = ixo_xmd_mem1_bstatus_rclk.
379 \<2\> = iobn_iorn_ffifo0_bstatus_rclk.
380 \<1\> = iobn_iorn_ffifo1_bstatus_rclk.
381 \<0\> = ixo_smmu_mem0_bstatus_rclk. */
382 #else /* Word 0 - Little Endian */
383 uint64_t status : 19; /**< [ 18: 0](RO/H) Memory BIST status.
384 Internal:
385 \<18\> = gmr_ixofifo_bstatus_rclk.
386 \<17\> = sli_preq_2_ffifo_bstatus_rclk.
387 \<16\> = sli_req_2_ffifo_bstatus_rclk.
388 \<15\> = sli_preq_1_ffifo_bstatus_rclk.
389 \<14\> = sli_req_1_ffifo_bstatus_rclk.
390 \<13\> = sli_preq_0_ffifo_bstatus_rclk.
391 \<12\> = sli_req_0_ffifo_bstatus_rclk.
392 \<11\> = iop_ffifo_bstatus_rclk.
393 \<10\> = ixo_icc_fifo0_bstatus_rclk.
394 \<9\> = ixo_icc_fifo1_bstatus_rclk.
395 \<8\> = ixo_ics_mem_bstatus_rclk.
396 \<7\> = iob_mem_data_xmd0_bstatus_rclk.
397 \<6\> = iob_mem_data_xmd1_bstatus_rclk.
398 \<5\> = ics_cmd_fifo_bstatus_rclk.
399 \<4\> = ixo_xmd_mem0_bstatus_rclk.
400 \<3\> = ixo_xmd_mem1_bstatus_rclk.
401 \<2\> = iobn_iorn_ffifo0_bstatus_rclk.
402 \<1\> = iobn_iorn_ffifo1_bstatus_rclk.
403 \<0\> = ixo_smmu_mem0_bstatus_rclk. */
404 uint64_t reserved_19_63 : 45;
405 #endif /* Word 0 - End */
406 } cn88xx;
407 struct bdk_iobnx_bistr_reg_cn83xx
408 {
409 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
410 uint64_t reserved_22_63 : 42;
411 uint64_t status : 22; /**< [ 21: 0](RO/H) Memory BIST status.
412 Internal:
413 \<21\> = gmr_sli_ixofifo_bstatus_rclk.
414 \<20\> = sli_preq_2_ffifo_bstatus_rclk.
415 \<19\> = sli_req_2_ffifo_bstatus_rclk.
416 \<18\> = gmr_ixofifo_bstatus_rclk.
417 \<17\> = sli_preq_2_ffifo_bstatus_rclk.
418 \<16\> = sli_req_2_ffifo_bstatus_rclk.
419 \<15\> = sli_preq_1_ffifo_bstatus_rclk.
420 \<14\> = sli_req_1_ffifo_bstatus_rclk.
421 \<13\> = sli_preq_0_ffifo_bstatus_rclk.
422 \<12\> = sli_req_0_ffifo_bstatus_rclk.
423 \<11\> = iop_ffifo_bstatus_rclk.
424 \<10\> = ixo_icc_fifo0_bstatus_rclk.
425 \<9\> = ixo_icc_fifo1_bstatus_rclk.
426 \<8\> = ixo_ics_mem_bstatus_rclk.
427 \<7\> = iob_mem_data_xmd0_bstatus_rclk.
428 \<6\> = iob_mem_data_xmd1_bstatus_rclk.
429 \<5\> = ics_cmd_fifo_bstatus_rclk.
430 \<4\> = ixo_xmd_mem0_bstatus_rclk.
431 \<3\> = ixo_xmd_mem1_bstatus_rclk.
432 \<2\> = iobn_iorn_ffifo0_bstatus_rclk.
433 \<1\> = iobn_iorn_ffifo1_bstatus_rclk.
434 \<0\> = ixo_smmu_mem0_bstatus_rclk. */
435 #else /* Word 0 - Little Endian */
436 uint64_t status : 22; /**< [ 21: 0](RO/H) Memory BIST status.
437 Internal:
438 \<21\> = gmr_sli_ixofifo_bstatus_rclk.
439 \<20\> = sli_preq_2_ffifo_bstatus_rclk.
440 \<19\> = sli_req_2_ffifo_bstatus_rclk.
441 \<18\> = gmr_ixofifo_bstatus_rclk.
442 \<17\> = sli_preq_2_ffifo_bstatus_rclk.
443 \<16\> = sli_req_2_ffifo_bstatus_rclk.
444 \<15\> = sli_preq_1_ffifo_bstatus_rclk.
445 \<14\> = sli_req_1_ffifo_bstatus_rclk.
446 \<13\> = sli_preq_0_ffifo_bstatus_rclk.
447 \<12\> = sli_req_0_ffifo_bstatus_rclk.
448 \<11\> = iop_ffifo_bstatus_rclk.
449 \<10\> = ixo_icc_fifo0_bstatus_rclk.
450 \<9\> = ixo_icc_fifo1_bstatus_rclk.
451 \<8\> = ixo_ics_mem_bstatus_rclk.
452 \<7\> = iob_mem_data_xmd0_bstatus_rclk.
453 \<6\> = iob_mem_data_xmd1_bstatus_rclk.
454 \<5\> = ics_cmd_fifo_bstatus_rclk.
455 \<4\> = ixo_xmd_mem0_bstatus_rclk.
456 \<3\> = ixo_xmd_mem1_bstatus_rclk.
457 \<2\> = iobn_iorn_ffifo0_bstatus_rclk.
458 \<1\> = iobn_iorn_ffifo1_bstatus_rclk.
459 \<0\> = ixo_smmu_mem0_bstatus_rclk. */
460 uint64_t reserved_22_63 : 42;
461 #endif /* Word 0 - End */
462 } cn83xx;
463 };
464 typedef union bdk_iobnx_bistr_reg bdk_iobnx_bistr_reg_t;
465
466 static inline uint64_t BDK_IOBNX_BISTR_REG(unsigned long a) __attribute__ ((pure, always_inline));
BDK_IOBNX_BISTR_REG(unsigned long a)467 static inline uint64_t BDK_IOBNX_BISTR_REG(unsigned long a)
468 {
469 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
470 return 0x87e0f0005080ll + 0x1000000ll * ((a) & 0x0);
471 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
472 return 0x87e0f0005080ll + 0x1000000ll * ((a) & 0x1);
473 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
474 return 0x87e0f0005080ll + 0x1000000ll * ((a) & 0x1);
475 __bdk_csr_fatal("IOBNX_BISTR_REG", 1, a, 0, 0, 0);
476 }
477
478 #define typedef_BDK_IOBNX_BISTR_REG(a) bdk_iobnx_bistr_reg_t
479 #define bustype_BDK_IOBNX_BISTR_REG(a) BDK_CSR_TYPE_RSL
480 #define basename_BDK_IOBNX_BISTR_REG(a) "IOBNX_BISTR_REG"
481 #define device_bar_BDK_IOBNX_BISTR_REG(a) 0x0 /* PF_BAR0 */
482 #define busnum_BDK_IOBNX_BISTR_REG(a) (a)
483 #define arguments_BDK_IOBNX_BISTR_REG(a) (a),-1,-1,-1
484
485 /**
486 * Register (RSL) iobn#_bists_reg
487 *
488 * IOBN BIST Status Register
489 * This register contains the result of the BIST run on the IOB sclk memories.
490 */
491 union bdk_iobnx_bists_reg
492 {
493 uint64_t u;
494 struct bdk_iobnx_bists_reg_s
495 {
496 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
497 uint64_t reserved_11_63 : 53;
498 uint64_t status : 11; /**< [ 10: 0](RO/H) Memory BIST status.
499 Internal:
500 \<10\> = irp0_flid_mem_status.
501 \<9\> = irp1_flid_mem_status.
502 \<8\> = icc0_xmc_fifo_ecc_bstatus.
503 \<7\> = icc1_xmc_fifo_ecc_bstatus.
504 \<6\> = icc_xmc_fifo_ecc_bstatus.
505 \<5\> = rsd_mem0_bstatus.
506 \<4\> = rsd_mem1_bstatus.
507 \<3\> = iop_breq_fifo0_bstatus.
508 \<2\> = iop_breq_fifo1_bstatus.
509 \<1\> = iop_breq_fifo2_bstatus.
510 \<0\> = iop_breq_fifo3_bstatus. */
511 #else /* Word 0 - Little Endian */
512 uint64_t status : 11; /**< [ 10: 0](RO/H) Memory BIST status.
513 Internal:
514 \<10\> = irp0_flid_mem_status.
515 \<9\> = irp1_flid_mem_status.
516 \<8\> = icc0_xmc_fifo_ecc_bstatus.
517 \<7\> = icc1_xmc_fifo_ecc_bstatus.
518 \<6\> = icc_xmc_fifo_ecc_bstatus.
519 \<5\> = rsd_mem0_bstatus.
520 \<4\> = rsd_mem1_bstatus.
521 \<3\> = iop_breq_fifo0_bstatus.
522 \<2\> = iop_breq_fifo1_bstatus.
523 \<1\> = iop_breq_fifo2_bstatus.
524 \<0\> = iop_breq_fifo3_bstatus. */
525 uint64_t reserved_11_63 : 53;
526 #endif /* Word 0 - End */
527 } s;
528 struct bdk_iobnx_bists_reg_cn81xx
529 {
530 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
531 uint64_t reserved_11_63 : 53;
532 uint64_t status : 11; /**< [ 10: 0](RO/H) Memory BIST status.
533 Internal:
534 \<10\> = irp0_flid_mem_status.
535 \<9\> = 0.
536 \<8\> = icc0_xmc_fifo_ecc_bstatus.
537 \<7\> = 0 unused.
538 \<6\> = icc_xmc_fifo_ecc_bstatus.
539 \<5\> = rsd_mem0_bstatus.
540 \<4\> = 0 un used
541 \<3\> = iop_breq_fifo0_bstatus.
542 \<2\> = 0 Unused
543 \<1\> = iop_breq_fifo2_bstatus.
544 \<0\> = iop_breq_fifo3_bstatus. */
545 #else /* Word 0 - Little Endian */
546 uint64_t status : 11; /**< [ 10: 0](RO/H) Memory BIST status.
547 Internal:
548 \<10\> = irp0_flid_mem_status.
549 \<9\> = 0.
550 \<8\> = icc0_xmc_fifo_ecc_bstatus.
551 \<7\> = 0 unused.
552 \<6\> = icc_xmc_fifo_ecc_bstatus.
553 \<5\> = rsd_mem0_bstatus.
554 \<4\> = 0 un used
555 \<3\> = iop_breq_fifo0_bstatus.
556 \<2\> = 0 Unused
557 \<1\> = iop_breq_fifo2_bstatus.
558 \<0\> = iop_breq_fifo3_bstatus. */
559 uint64_t reserved_11_63 : 53;
560 #endif /* Word 0 - End */
561 } cn81xx;
562 /* struct bdk_iobnx_bists_reg_s cn88xx; */
563 /* struct bdk_iobnx_bists_reg_s cn83xx; */
564 };
565 typedef union bdk_iobnx_bists_reg bdk_iobnx_bists_reg_t;
566
567 static inline uint64_t BDK_IOBNX_BISTS_REG(unsigned long a) __attribute__ ((pure, always_inline));
BDK_IOBNX_BISTS_REG(unsigned long a)568 static inline uint64_t BDK_IOBNX_BISTS_REG(unsigned long a)
569 {
570 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
571 return 0x87e0f0005000ll + 0x1000000ll * ((a) & 0x0);
572 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
573 return 0x87e0f0005000ll + 0x1000000ll * ((a) & 0x1);
574 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
575 return 0x87e0f0005000ll + 0x1000000ll * ((a) & 0x1);
576 __bdk_csr_fatal("IOBNX_BISTS_REG", 1, a, 0, 0, 0);
577 }
578
579 #define typedef_BDK_IOBNX_BISTS_REG(a) bdk_iobnx_bists_reg_t
580 #define bustype_BDK_IOBNX_BISTS_REG(a) BDK_CSR_TYPE_RSL
581 #define basename_BDK_IOBNX_BISTS_REG(a) "IOBNX_BISTS_REG"
582 #define device_bar_BDK_IOBNX_BISTS_REG(a) 0x0 /* PF_BAR0 */
583 #define busnum_BDK_IOBNX_BISTS_REG(a) (a)
584 #define arguments_BDK_IOBNX_BISTS_REG(a) (a),-1,-1,-1
585
586 /**
587 * Register (RSL) iobn#_bp_test#
588 *
589 * INTERNAL: IOBN Backpressure Test Registers
590 */
591 union bdk_iobnx_bp_testx
592 {
593 uint64_t u;
594 struct bdk_iobnx_bp_testx_s
595 {
596 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
597 uint64_t enable : 8; /**< [ 63: 56](R/W) Enable test mode. For diagnostic use only.
598 Internal:
599 Once a bit is set, random backpressure is generated
600 at the corresponding point to allow for more frequent backpressure.
601
602 IOBN()_BP_TEST(0) - INRF: Defined by iobn_defs::inrf_bp_test_t
603 \<63\> = TBD.
604 \<62\> = TBD.
605 \<61\> = TBD.
606 \<60\> = TBD.
607 \<59\> = TBD.
608 \<58\> = TBD.
609 \<57\> = TBD.
610 \<56\> = TBD.
611
612 IOBN()_BP_TEST(1) - INRM: Defined by iobn_defs::inrm_bp_test_t
613 \<63\> = Stall CMT processing for outbound LBK transactions
614 \<62\> = Stall CMT processing for outbound MSH transactions
615 \<61\> = omp_vcc_ret.
616 \<60\> = imi_dat_fif - Backpressure VCC return counters(OMP)
617 \<59\> = TBD.
618 \<58\> = TBD.
619 \<57\> = TBD.
620 \<56\> = TBD.
621
622 IOBN()_BP_TEST(2) - INRF: Defined by iobn_defs::inrf_bp_test_t
623 \<63\> = TBD.
624 \<62\> = TBD.
625 \<61\> = TBD.
626 \<60\> = TBD.
627 \<59\> = TBD.
628 \<58\> = TBD.
629 \<57\> = TBD.
630 \<56\> = TBD.
631
632 IOBN()_BP_TEST(3) - INRF: Defined by iobn_defs::inrm_bp_test_t
633 \<63\> = VCC - Victim DAT.
634 \<62\> = VCC - Victim REQ (CMD).
635 \<61\> = VCC - DAT (REQ/REQH).
636 \<60\> = VCC - CMD (REQ/RQH).
637 \<59\> = SLC - VCC.
638 \<58\> = SLC - ACK.
639 \<57\> = SLC - DAT.
640 \<56\> = SLC - CMD. */
641 uint64_t reserved_32_55 : 24;
642 uint64_t bp_cfg : 16; /**< [ 31: 16](R/W) Backpressure weight. For diagnostic use only.
643 Internal:
644 There are 2 backpressure configuration bits per enable, with the two bits
645 defined as 0x0=100% of the time, 0x1=75% of the time, 0x2=50% of the time,
646 0x3=25% of the time.
647 \<31:30\> = Config 7.
648 \<29:28\> = Config 6.
649 \<27:26\> = Config 5.
650 \<25:24\> = Config 4.
651 \<23:22\> = Config 3.
652 \<21:20\> = Config 2.
653 \<19:18\> = Config 1.
654 \<17:16\> = Config 0. */
655 uint64_t reserved_12_15 : 4;
656 uint64_t lfsr_freq : 12; /**< [ 11: 0](R/W) Test LFSR update frequency in coprocessor-clocks minus one. */
657 #else /* Word 0 - Little Endian */
658 uint64_t lfsr_freq : 12; /**< [ 11: 0](R/W) Test LFSR update frequency in coprocessor-clocks minus one. */
659 uint64_t reserved_12_15 : 4;
660 uint64_t bp_cfg : 16; /**< [ 31: 16](R/W) Backpressure weight. For diagnostic use only.
661 Internal:
662 There are 2 backpressure configuration bits per enable, with the two bits
663 defined as 0x0=100% of the time, 0x1=75% of the time, 0x2=50% of the time,
664 0x3=25% of the time.
665 \<31:30\> = Config 7.
666 \<29:28\> = Config 6.
667 \<27:26\> = Config 5.
668 \<25:24\> = Config 4.
669 \<23:22\> = Config 3.
670 \<21:20\> = Config 2.
671 \<19:18\> = Config 1.
672 \<17:16\> = Config 0. */
673 uint64_t reserved_32_55 : 24;
674 uint64_t enable : 8; /**< [ 63: 56](R/W) Enable test mode. For diagnostic use only.
675 Internal:
676 Once a bit is set, random backpressure is generated
677 at the corresponding point to allow for more frequent backpressure.
678
679 IOBN()_BP_TEST(0) - INRF: Defined by iobn_defs::inrf_bp_test_t
680 \<63\> = TBD.
681 \<62\> = TBD.
682 \<61\> = TBD.
683 \<60\> = TBD.
684 \<59\> = TBD.
685 \<58\> = TBD.
686 \<57\> = TBD.
687 \<56\> = TBD.
688
689 IOBN()_BP_TEST(1) - INRM: Defined by iobn_defs::inrm_bp_test_t
690 \<63\> = Stall CMT processing for outbound LBK transactions
691 \<62\> = Stall CMT processing for outbound MSH transactions
692 \<61\> = omp_vcc_ret.
693 \<60\> = imi_dat_fif - Backpressure VCC return counters(OMP)
694 \<59\> = TBD.
695 \<58\> = TBD.
696 \<57\> = TBD.
697 \<56\> = TBD.
698
699 IOBN()_BP_TEST(2) - INRF: Defined by iobn_defs::inrf_bp_test_t
700 \<63\> = TBD.
701 \<62\> = TBD.
702 \<61\> = TBD.
703 \<60\> = TBD.
704 \<59\> = TBD.
705 \<58\> = TBD.
706 \<57\> = TBD.
707 \<56\> = TBD.
708
709 IOBN()_BP_TEST(3) - INRF: Defined by iobn_defs::inrm_bp_test_t
710 \<63\> = VCC - Victim DAT.
711 \<62\> = VCC - Victim REQ (CMD).
712 \<61\> = VCC - DAT (REQ/REQH).
713 \<60\> = VCC - CMD (REQ/RQH).
714 \<59\> = SLC - VCC.
715 \<58\> = SLC - ACK.
716 \<57\> = SLC - DAT.
717 \<56\> = SLC - CMD. */
718 #endif /* Word 0 - End */
719 } s;
720 /* struct bdk_iobnx_bp_testx_s cn; */
721 };
722 typedef union bdk_iobnx_bp_testx bdk_iobnx_bp_testx_t;
723
724 static inline uint64_t BDK_IOBNX_BP_TESTX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_IOBNX_BP_TESTX(unsigned long a,unsigned long b)725 static inline uint64_t BDK_IOBNX_BP_TESTX(unsigned long a, unsigned long b)
726 {
727 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b<=3)))
728 return 0x87e0f0003800ll + 0x1000000ll * ((a) & 0x1) + 8ll * ((b) & 0x3);
729 __bdk_csr_fatal("IOBNX_BP_TESTX", 2, a, b, 0, 0);
730 }
731
732 #define typedef_BDK_IOBNX_BP_TESTX(a,b) bdk_iobnx_bp_testx_t
733 #define bustype_BDK_IOBNX_BP_TESTX(a,b) BDK_CSR_TYPE_RSL
734 #define basename_BDK_IOBNX_BP_TESTX(a,b) "IOBNX_BP_TESTX"
735 #define device_bar_BDK_IOBNX_BP_TESTX(a,b) 0x0 /* PF_BAR0 */
736 #define busnum_BDK_IOBNX_BP_TESTX(a,b) (a)
737 #define arguments_BDK_IOBNX_BP_TESTX(a,b) (a),(b),-1,-1
738
739 /**
740 * Register (RSL) iobn#_cfg0
741 *
742 * IOBN General Configuration 0 Register
743 */
744 union bdk_iobnx_cfg0
745 {
746 uint64_t u;
747 struct bdk_iobnx_cfg0_s
748 {
749 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
750 uint64_t reserved_5_63 : 59;
751 uint64_t force_gibm_ncbi_clk_en : 1; /**< [ 4: 4](R/W) Force on GIBM NCBI clocks. For diagnostic use only. */
752 uint64_t force_immx_sclk_cond_clk_en : 1;/**< [ 3: 3](R/W) Force on IMMX clocks. For diagnostic use only. */
753 uint64_t force_inrm_sclk_cond_clk_en : 1;/**< [ 2: 2](R/W) Force on INRM clocks. For diagnostic use only. */
754 uint64_t force_inrf_sclk_cond_clk_en : 1;/**< [ 1: 1](R/W) Force on INRF clocks. For diagnostic use only. */
755 uint64_t force_ins_sclk_cond_clk_en : 1;/**< [ 0: 0](R/W) Force on INS clocks. For diagnostic use only. */
756 #else /* Word 0 - Little Endian */
757 uint64_t force_ins_sclk_cond_clk_en : 1;/**< [ 0: 0](R/W) Force on INS clocks. For diagnostic use only. */
758 uint64_t force_inrf_sclk_cond_clk_en : 1;/**< [ 1: 1](R/W) Force on INRF clocks. For diagnostic use only. */
759 uint64_t force_inrm_sclk_cond_clk_en : 1;/**< [ 2: 2](R/W) Force on INRM clocks. For diagnostic use only. */
760 uint64_t force_immx_sclk_cond_clk_en : 1;/**< [ 3: 3](R/W) Force on IMMX clocks. For diagnostic use only. */
761 uint64_t force_gibm_ncbi_clk_en : 1; /**< [ 4: 4](R/W) Force on GIBM NCBI clocks. For diagnostic use only. */
762 uint64_t reserved_5_63 : 59;
763 #endif /* Word 0 - End */
764 } s;
765 /* struct bdk_iobnx_cfg0_s cn; */
766 };
767 typedef union bdk_iobnx_cfg0 bdk_iobnx_cfg0_t;
768
769 static inline uint64_t BDK_IOBNX_CFG0(unsigned long a) __attribute__ ((pure, always_inline));
BDK_IOBNX_CFG0(unsigned long a)770 static inline uint64_t BDK_IOBNX_CFG0(unsigned long a)
771 {
772 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
773 return 0x87e0f0002000ll + 0x1000000ll * ((a) & 0x1);
774 __bdk_csr_fatal("IOBNX_CFG0", 1, a, 0, 0, 0);
775 }
776
777 #define typedef_BDK_IOBNX_CFG0(a) bdk_iobnx_cfg0_t
778 #define bustype_BDK_IOBNX_CFG0(a) BDK_CSR_TYPE_RSL
779 #define basename_BDK_IOBNX_CFG0(a) "IOBNX_CFG0"
780 #define device_bar_BDK_IOBNX_CFG0(a) 0x0 /* PF_BAR0 */
781 #define busnum_BDK_IOBNX_CFG0(a) (a)
782 #define arguments_BDK_IOBNX_CFG0(a) (a),-1,-1,-1
783
784 /**
785 * Register (RSL) iobn#_cfg1
786 *
787 * IOBN General Configuration 1 Register
788 */
789 union bdk_iobnx_cfg1
790 {
791 uint64_t u;
792 struct bdk_iobnx_cfg1_s
793 {
794 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
795 uint64_t reserved_3_63 : 61;
796 uint64_t force_immx_rclk_cond_clk_en : 1;/**< [ 2: 2](R/W) For debug only. Must be zero during normal operation.
797 Internal:
798 Force the conditional clock active */
799 uint64_t force_inrm_rclk_cond_clk_en : 1;/**< [ 1: 1](R/W) For debug only. Must be zero during normal operation.
800 Internal:
801 Force the conditional clock active */
802 uint64_t force_inrf_rclk_cond_clk_en : 1;/**< [ 0: 0](R/W) For debug only. Must be zero during normal operation.
803 Internal:
804 Force the conditional clock active */
805 #else /* Word 0 - Little Endian */
806 uint64_t force_inrf_rclk_cond_clk_en : 1;/**< [ 0: 0](R/W) For debug only. Must be zero during normal operation.
807 Internal:
808 Force the conditional clock active */
809 uint64_t force_inrm_rclk_cond_clk_en : 1;/**< [ 1: 1](R/W) For debug only. Must be zero during normal operation.
810 Internal:
811 Force the conditional clock active */
812 uint64_t force_immx_rclk_cond_clk_en : 1;/**< [ 2: 2](R/W) For debug only. Must be zero during normal operation.
813 Internal:
814 Force the conditional clock active */
815 uint64_t reserved_3_63 : 61;
816 #endif /* Word 0 - End */
817 } s;
818 /* struct bdk_iobnx_cfg1_s cn; */
819 };
820 typedef union bdk_iobnx_cfg1 bdk_iobnx_cfg1_t;
821
822 static inline uint64_t BDK_IOBNX_CFG1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_IOBNX_CFG1(unsigned long a)823 static inline uint64_t BDK_IOBNX_CFG1(unsigned long a)
824 {
825 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
826 return 0x87e0f0002010ll + 0x1000000ll * ((a) & 0x1);
827 __bdk_csr_fatal("IOBNX_CFG1", 1, a, 0, 0, 0);
828 }
829
830 #define typedef_BDK_IOBNX_CFG1(a) bdk_iobnx_cfg1_t
831 #define bustype_BDK_IOBNX_CFG1(a) BDK_CSR_TYPE_RSL
832 #define basename_BDK_IOBNX_CFG1(a) "IOBNX_CFG1"
833 #define device_bar_BDK_IOBNX_CFG1(a) 0x0 /* PF_BAR0 */
834 #define busnum_BDK_IOBNX_CFG1(a) (a)
835 #define arguments_BDK_IOBNX_CFG1(a) (a),-1,-1,-1
836
837 /**
838 * Register (RSL) iobn#_chip_cur_pwr
839 *
840 * INTERNAL: IOBN Chip Current Power Register
841 *
842 * For diagnostic use only.
843 * This register contains the current power setting.
844 * Only index zero (IOB(0)) is used.
845 */
846 union bdk_iobnx_chip_cur_pwr
847 {
848 uint64_t u;
849 struct bdk_iobnx_chip_cur_pwr_s
850 {
851 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
852 uint64_t reserved_8_63 : 56;
853 uint64_t current_power_setting : 8; /**< [ 7: 0](RO/H) Global throttling value currently being used. Throttling can force units (CPU cores, in
854 particular) idle for a portion of time, which will reduce power consumption. When
855 [CURRENT_POWER_SETTING] is equal to zero, the unit is idle most of the time and consumes
856 minimum power. When [CURRENT_POWER_SETTING] is equal to 0xFF, units are never idled to
857 reduce power. The hardware generally uses a [CURRENT_POWER_SETTING] value that is as large
858 as possible (in order to maximize performance) subject to the following constraints (in
859 priority order):
860 * PWR_MIN \<= [CURRENT_POWER_SETTING] \<= PWR_MAX.
861 * Power limits from the PWR_SETTING feedback control system.
862
863 In the case of the CPU cores, [CURRENT_POWER_SETTING] effectively limits the CP0
864 PowThrottle[POWLIM] value: effective POWLIM = MINIMUM([CURRENT_POWER_SETTING],
865 PowThrottle[POWLIM]) */
866 #else /* Word 0 - Little Endian */
867 uint64_t current_power_setting : 8; /**< [ 7: 0](RO/H) Global throttling value currently being used. Throttling can force units (CPU cores, in
868 particular) idle for a portion of time, which will reduce power consumption. When
869 [CURRENT_POWER_SETTING] is equal to zero, the unit is idle most of the time and consumes
870 minimum power. When [CURRENT_POWER_SETTING] is equal to 0xFF, units are never idled to
871 reduce power. The hardware generally uses a [CURRENT_POWER_SETTING] value that is as large
872 as possible (in order to maximize performance) subject to the following constraints (in
873 priority order):
874 * PWR_MIN \<= [CURRENT_POWER_SETTING] \<= PWR_MAX.
875 * Power limits from the PWR_SETTING feedback control system.
876
877 In the case of the CPU cores, [CURRENT_POWER_SETTING] effectively limits the CP0
878 PowThrottle[POWLIM] value: effective POWLIM = MINIMUM([CURRENT_POWER_SETTING],
879 PowThrottle[POWLIM]) */
880 uint64_t reserved_8_63 : 56;
881 #endif /* Word 0 - End */
882 } s;
883 /* struct bdk_iobnx_chip_cur_pwr_s cn; */
884 };
885 typedef union bdk_iobnx_chip_cur_pwr bdk_iobnx_chip_cur_pwr_t;
886
887 static inline uint64_t BDK_IOBNX_CHIP_CUR_PWR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_IOBNX_CHIP_CUR_PWR(unsigned long a)888 static inline uint64_t BDK_IOBNX_CHIP_CUR_PWR(unsigned long a)
889 {
890 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
891 return 0x87e0f000a110ll + 0x1000000ll * ((a) & 0x0);
892 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
893 return 0x87e0f000a110ll + 0x1000000ll * ((a) & 0x1);
894 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
895 return 0x87e0f000a110ll + 0x1000000ll * ((a) & 0x1);
896 __bdk_csr_fatal("IOBNX_CHIP_CUR_PWR", 1, a, 0, 0, 0);
897 }
898
899 #define typedef_BDK_IOBNX_CHIP_CUR_PWR(a) bdk_iobnx_chip_cur_pwr_t
900 #define bustype_BDK_IOBNX_CHIP_CUR_PWR(a) BDK_CSR_TYPE_RSL
901 #define basename_BDK_IOBNX_CHIP_CUR_PWR(a) "IOBNX_CHIP_CUR_PWR"
902 #define device_bar_BDK_IOBNX_CHIP_CUR_PWR(a) 0x0 /* PF_BAR0 */
903 #define busnum_BDK_IOBNX_CHIP_CUR_PWR(a) (a)
904 #define arguments_BDK_IOBNX_CHIP_CUR_PWR(a) (a),-1,-1,-1
905
906 /**
907 * Register (RSL) iobn#_chip_glb_pwr_throttle
908 *
909 * INTERNAL: IOBN Chip Global Power Throttle Register
910 *
911 * For diagnostic use only.
912 * This register controls the min/max power settings.
913 * Only index zero (IOB(0)) is used.
914 */
915 union bdk_iobnx_chip_glb_pwr_throttle
916 {
917 uint64_t u;
918 struct bdk_iobnx_chip_glb_pwr_throttle_s
919 {
920 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
921 uint64_t reserved_34_63 : 30;
922 uint64_t pwr_bw : 2; /**< [ 33: 32](R/W) Configures the reaction time of the closed-loop feedback control system for the
923 AVG_CHIP_POWER power approximation. Higher numbers decrease bandwidth, reducing response
924 time, which could lead to greater tracking error, but reduce ringing. */
925 uint64_t pwr_max : 8; /**< [ 31: 24](R/W) Reserved. */
926 uint64_t pwr_min : 8; /**< [ 23: 16](R/W) Reserved. */
927 uint64_t pwr_setting : 16; /**< [ 15: 0](R/W) A power limiter for the chip. A limiter of the power consumption of the
928 chip. This power limiting is implemented by a closed-loop feedback control
929 system for the AVG_CHIP_POWER power approximation. The direct output of the
930 [PWR_SETTING] feedback control system is the CURRENT_POWER_SETTING value. The
931 power consumed by the chip (estimated currently by the AVG_CHIP_POWER value) is
932 an indirect output of the PWR_SETTING feedback control system. [PWR_SETTING] is
933 not used by the hardware when [PWR_MIN] equals [PWR_MAX]. [PWR_MIN] and
934 [PWR_MAX] threshold requirements always supersede [PWR_SETTING] limits. (For
935 maximum [PWR_SETTING] feedback control freedom, set [PWR_MIN]=0 and
936 [PWR_MAX]=0xff.)
937
938 [PWR_SETTING] equal to 0 forces the chip to consume near minimum
939 power. Increasing [PWR_SETTING] value from 0 to 0xFFFF increases the power that
940 the chip is allowed to consume linearly (roughly) from minimum to maximum. */
941 #else /* Word 0 - Little Endian */
942 uint64_t pwr_setting : 16; /**< [ 15: 0](R/W) A power limiter for the chip. A limiter of the power consumption of the
943 chip. This power limiting is implemented by a closed-loop feedback control
944 system for the AVG_CHIP_POWER power approximation. The direct output of the
945 [PWR_SETTING] feedback control system is the CURRENT_POWER_SETTING value. The
946 power consumed by the chip (estimated currently by the AVG_CHIP_POWER value) is
947 an indirect output of the PWR_SETTING feedback control system. [PWR_SETTING] is
948 not used by the hardware when [PWR_MIN] equals [PWR_MAX]. [PWR_MIN] and
949 [PWR_MAX] threshold requirements always supersede [PWR_SETTING] limits. (For
950 maximum [PWR_SETTING] feedback control freedom, set [PWR_MIN]=0 and
951 [PWR_MAX]=0xff.)
952
953 [PWR_SETTING] equal to 0 forces the chip to consume near minimum
954 power. Increasing [PWR_SETTING] value from 0 to 0xFFFF increases the power that
955 the chip is allowed to consume linearly (roughly) from minimum to maximum. */
956 uint64_t pwr_min : 8; /**< [ 23: 16](R/W) Reserved. */
957 uint64_t pwr_max : 8; /**< [ 31: 24](R/W) Reserved. */
958 uint64_t pwr_bw : 2; /**< [ 33: 32](R/W) Configures the reaction time of the closed-loop feedback control system for the
959 AVG_CHIP_POWER power approximation. Higher numbers decrease bandwidth, reducing response
960 time, which could lead to greater tracking error, but reduce ringing. */
961 uint64_t reserved_34_63 : 30;
962 #endif /* Word 0 - End */
963 } s;
964 /* struct bdk_iobnx_chip_glb_pwr_throttle_s cn; */
965 };
966 typedef union bdk_iobnx_chip_glb_pwr_throttle bdk_iobnx_chip_glb_pwr_throttle_t;
967
968 static inline uint64_t BDK_IOBNX_CHIP_GLB_PWR_THROTTLE(unsigned long a) __attribute__ ((pure, always_inline));
BDK_IOBNX_CHIP_GLB_PWR_THROTTLE(unsigned long a)969 static inline uint64_t BDK_IOBNX_CHIP_GLB_PWR_THROTTLE(unsigned long a)
970 {
971 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
972 return 0x87e0f000a100ll + 0x1000000ll * ((a) & 0x0);
973 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
974 return 0x87e0f000a100ll + 0x1000000ll * ((a) & 0x1);
975 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
976 return 0x87e0f000a100ll + 0x1000000ll * ((a) & 0x1);
977 __bdk_csr_fatal("IOBNX_CHIP_GLB_PWR_THROTTLE", 1, a, 0, 0, 0);
978 }
979
980 #define typedef_BDK_IOBNX_CHIP_GLB_PWR_THROTTLE(a) bdk_iobnx_chip_glb_pwr_throttle_t
981 #define bustype_BDK_IOBNX_CHIP_GLB_PWR_THROTTLE(a) BDK_CSR_TYPE_RSL
982 #define basename_BDK_IOBNX_CHIP_GLB_PWR_THROTTLE(a) "IOBNX_CHIP_GLB_PWR_THROTTLE"
983 #define device_bar_BDK_IOBNX_CHIP_GLB_PWR_THROTTLE(a) 0x0 /* PF_BAR0 */
984 #define busnum_BDK_IOBNX_CHIP_GLB_PWR_THROTTLE(a) (a)
985 #define arguments_BDK_IOBNX_CHIP_GLB_PWR_THROTTLE(a) (a),-1,-1,-1
986
987 /**
988 * Register (RSL) iobn#_chip_pwr_out
989 *
990 * IOBN Chip Power Out Register
991 * This register contains power numbers from the various partitions on the chip.
992 * Only index zero (IOB(0)) is used.
993 */
994 union bdk_iobnx_chip_pwr_out
995 {
996 uint64_t u;
997 struct bdk_iobnx_chip_pwr_out_s
998 {
999 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1000 uint64_t cpu_pwr : 16; /**< [ 63: 48](RO/H) An estimate of the current CPU core complex power consumption, including a sum
1001 of all processor's AP_CVM_POWER_EL1[AVERAGE_POWER]. The CPU core complex
1002 includes the caches and DRAM controller(s), as well as all CPU cores. Linearly
1003 larger values indicate linearly higher power consumption. */
1004 uint64_t chip_power : 16; /**< [ 47: 32](RO/H) An estimate of the current total power consumption by the chip. Linearly larger values
1005 indicate linearly higher power consumption. [CHIP_POWER] is the sum of [CPU_PWR] and
1006 [COPROC_POWER]. */
1007 uint64_t coproc_power : 16; /**< [ 31: 16](RO/H) An estimate of the current coprocessor power consumption. Linearly larger values indicate
1008 linearly higher power consumption. This estimate is energy per core clock, and will
1009 generally decrease as the ratio of core to coprocessor clock speed increases. */
1010 uint64_t avg_chip_power : 16; /**< [ 15: 0](RO/H) Average chip power.
1011 An average of [CHIP_POWER], calculated using an IIR filter with an average
1012 weight of 16K core clocks, in mA/GHz.
1013
1014 Accurate power numbers should be calculated using a platform-specific method which
1015 e.g. reads the current consumption of the VRM.
1016
1017 Otherwise an approximation of this chip's power is calculated with:
1018
1019 _ power = chip_const + core_const * cores_powered_on + [AVG_CHIP_POWER] * voltage
1020
1021 Where:
1022
1023 _ power is in mW.
1024
1025 _ chip_const is in mW and represents the I/O power and chip excluding core_const.
1026 This may vary as I/O and coprocessor loads vary, therefore only
1027 platform methods can be used for accurate estimates.
1028
1029 _ core_const is a per-core constant leakage from the HRM power application note, and is in
1030 mA.
1031
1032 _ cores_powered_on is a population count of all bits set in RST_PP_POWER.
1033
1034 _ voltage is determined by the platform, perhaps by reading a VRM setting. */
1035 #else /* Word 0 - Little Endian */
1036 uint64_t avg_chip_power : 16; /**< [ 15: 0](RO/H) Average chip power.
1037 An average of [CHIP_POWER], calculated using an IIR filter with an average
1038 weight of 16K core clocks, in mA/GHz.
1039
1040 Accurate power numbers should be calculated using a platform-specific method which
1041 e.g. reads the current consumption of the VRM.
1042
1043 Otherwise an approximation of this chip's power is calculated with:
1044
1045 _ power = chip_const + core_const * cores_powered_on + [AVG_CHIP_POWER] * voltage
1046
1047 Where:
1048
1049 _ power is in mW.
1050
1051 _ chip_const is in mW and represents the I/O power and chip excluding core_const.
1052 This may vary as I/O and coprocessor loads vary, therefore only
1053 platform methods can be used for accurate estimates.
1054
1055 _ core_const is a per-core constant leakage from the HRM power application note, and is in
1056 mA.
1057
1058 _ cores_powered_on is a population count of all bits set in RST_PP_POWER.
1059
1060 _ voltage is determined by the platform, perhaps by reading a VRM setting. */
1061 uint64_t coproc_power : 16; /**< [ 31: 16](RO/H) An estimate of the current coprocessor power consumption. Linearly larger values indicate
1062 linearly higher power consumption. This estimate is energy per core clock, and will
1063 generally decrease as the ratio of core to coprocessor clock speed increases. */
1064 uint64_t chip_power : 16; /**< [ 47: 32](RO/H) An estimate of the current total power consumption by the chip. Linearly larger values
1065 indicate linearly higher power consumption. [CHIP_POWER] is the sum of [CPU_PWR] and
1066 [COPROC_POWER]. */
1067 uint64_t cpu_pwr : 16; /**< [ 63: 48](RO/H) An estimate of the current CPU core complex power consumption, including a sum
1068 of all processor's AP_CVM_POWER_EL1[AVERAGE_POWER]. The CPU core complex
1069 includes the caches and DRAM controller(s), as well as all CPU cores. Linearly
1070 larger values indicate linearly higher power consumption. */
1071 #endif /* Word 0 - End */
1072 } s;
1073 /* struct bdk_iobnx_chip_pwr_out_s cn; */
1074 };
1075 typedef union bdk_iobnx_chip_pwr_out bdk_iobnx_chip_pwr_out_t;
1076
1077 static inline uint64_t BDK_IOBNX_CHIP_PWR_OUT(unsigned long a) __attribute__ ((pure, always_inline));
BDK_IOBNX_CHIP_PWR_OUT(unsigned long a)1078 static inline uint64_t BDK_IOBNX_CHIP_PWR_OUT(unsigned long a)
1079 {
1080 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
1081 return 0x87e0f000a108ll + 0x1000000ll * ((a) & 0x0);
1082 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
1083 return 0x87e0f000a108ll + 0x1000000ll * ((a) & 0x1);
1084 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
1085 return 0x87e0f000a108ll + 0x1000000ll * ((a) & 0x1);
1086 __bdk_csr_fatal("IOBNX_CHIP_PWR_OUT", 1, a, 0, 0, 0);
1087 }
1088
1089 #define typedef_BDK_IOBNX_CHIP_PWR_OUT(a) bdk_iobnx_chip_pwr_out_t
1090 #define bustype_BDK_IOBNX_CHIP_PWR_OUT(a) BDK_CSR_TYPE_RSL
1091 #define basename_BDK_IOBNX_CHIP_PWR_OUT(a) "IOBNX_CHIP_PWR_OUT"
1092 #define device_bar_BDK_IOBNX_CHIP_PWR_OUT(a) 0x0 /* PF_BAR0 */
1093 #define busnum_BDK_IOBNX_CHIP_PWR_OUT(a) (a)
1094 #define arguments_BDK_IOBNX_CHIP_PWR_OUT(a) (a),-1,-1,-1
1095
1096 /**
1097 * Register (RSL) iobn#_cond_clk_cap#
1098 *
1099 * INTERNAL: IOBN Conditional Clock Capacitance Register
1100 *
1101 * This register is for diagnostic use only.
1102 * Internal:
1103 * Each index corresponds to a different net as follows:
1104 * 0 = bgx0___bgx___bgx_clk___csclk_drv.
1105 * 1 = bgx0___bgx___bgx_clk___ssclk_drv.
1106 * 2 = bgx0___bgx___bgx_clk___gsclk_drv.
1107 * 3 = bgx1___bgx___bgx_clk___csclk_drv.
1108 * 4 = bgx1___bgx___bgx_clk___ssclk_drv.
1109 * 5 = bgx1___bgx___bgx_clk___gsclk_drv.
1110 * 6 = bgx2___bgx___bgx_clk___csclk_drv.
1111 * 7 = bgx2___bgx___bgx_clk___ssclk_drv.
1112 * 8 = bgx2___bgx___bgx_clk___gsclk_drv.
1113 * 9 = bgx3___bgx___bgx_clk___csclk_drv.
1114 * 10 = bgx3___bgx___bgx_clk___ssclk_drv.
1115 * 11 = bgx3___bgx___bgx_clk___gsclk_drv.
1116 * 12 = dpi___dpi___csclk_drv.
1117 * 13 = fpa___fpa___gbl___csclk_drv.
1118 * 14 = lbk___lbk___lbk_core_p0x0___csclk_drv.
1119 * 15 = lbk___lbk___lbk_core_p0x1___csclk_drv.
1120 * 16 = lbk___lbk___lbk_core_p1x0___csclk_drv.
1121 * 17 = lbk___lbk___lbk_core_p1x1___csclk_drv.
1122 * 18 = mio___mio___uaa0___u_csclk_drv.
1123 * 19 = mio___mio___uaa1___u_csclk_drv.
1124 * 20 = mio___mio___uaa2___u_csclk_drv.
1125 * 21 = mio___mio___uaa3___u_csclk_drv.
1126 * 22 = nic___nic___nic_l___nic_l1___nic_clk___csclk_drv.
1127 * 23 = nic___nic___nic_l___nic_l2___nic_clk___csclk_drv.
1128 * 24 = nic___nic___nic_u___nic_u1___nic_clk___csclk_drv.
1129 * 25 = pem0___pem___pem_clks___csclk_drv.
1130 * 26 = pem0___pem___pem_clks___sync_pwr_thr_pclk.
1131 * 27 = pem1___pem___pem_clks___csclk_drv.
1132 * 28 = pem1___pem___pem_clks___sync_pwr_thr_pclk.
1133 * 29 = pem2___pem___pem_clks___csclk_drv.
1134 * 30 = pem2___pem___pem_clks___sync_pwr_thr_pclk.
1135 * 31 = pem3___pem___pem_clks___csclk_drv.
1136 * 32 = pem3___pem___pem_clks___sync_pwr_thr_pclk.
1137 * 33 = pki___pki___pdp___pfe___csclk_drv.
1138 * 34 = pki___pki___pdp___pbe___csclk_drv.
1139 * 35 = pki___pki___pix___ipec0___csclk_drv.
1140 * 36 = pki___pki___pix___ipec1___csclk_drv.
1141 * 37 = pki___pki___pix___mech___csclk_drv.
1142 * 38 = roc_ocla___roc_ocla___core___clks___csclk_drv.
1143 * 39 = rst___rst___mio_clk_ctl___csclk_drv.
1144 * 40 = sata0___sata___u_csclk_drv.
1145 * 41 = sata0___sata___u_csclk_drv.
1146 * 42 = sata0___sata___u_csclk_drv.
1147 * 43 = sata0___sata___u_csclk_drv.
1148 * 44 = sata0___sata___u_csclk_drv.
1149 * 45 = sata0___sata___u_csclk_drv.
1150 * 46 = smmu___smmu___wcsr___gbl___crclk_drv.
1151 * 47 = smmu___smmu___wcsr___gbl___u_c2rclk_drv.
1152 * 48 = smmu___smmu___wcsr___gbl___u_c2rclk_drv_n.
1153 * 49 = smmu___smmu___xl___ctl___crclk_drv.
1154 * 50 = sso___sso___sso_pnr___sso_aw___clk___csclk_drv.
1155 * 51 = sso___sso___sso_pnr___sso_gw___clk___csclk_drv.
1156 * 52 = sso___sso___sso_pnr___sso_ws___clk___csclk_drv.
1157 * 53 = usbdrd0___usbdrd_i___u_csclk_drv.
1158 * 54 = usbdrd0___usbdrd_i___u_csclk_drv.
1159 * 55 = zipc0___zipc___zipc_clk___zip_hash_csclk_drv.
1160 * 56 = zipc0___zipc___zipc_clk___zip_history_csclk_drv.
1161 * 57 = zipc0___zipc___zipc_clk___zip_state_csclk_drv.
1162 * 58 = zipc0___zipc___zipc_clk___zip_sha_csclk_drv.
1163 * 59 = zipc1___zipc___zipc_clk___zip_hash_csclk_drv.
1164 * 60 = zipc1___zipc___zipc_clk___zip_history_csclk_drv.
1165 * 61 = zipc1___zipc___zipc_clk___zip_state_csclk_drv.
1166 * 62 = zipc1___zipc___zipc_clk___zip_sha_csclk_drv.
1167 * 63 = zipc2___zipc___zipc_clk___zip_hash_csclk_drv.
1168 * 64 = zipc2___zipc___zipc_clk___zip_history_csclk_drv.
1169 * 65 = zipc2___zipc___zipc_clk___zip_state_csclk_drv.
1170 * 66 = zipc2___zipc___zipc_clk___zip_sha_csclk_drv.
1171 * 67 = zipd3___zipd___zipd_clk___zip_history_csclk_drv.
1172 * 68 = zipd3___zipd___zipd_clk___zip_state_csclk_drv.
1173 * 69 = zipd3___zipd___zipd_clk___zip_sha_csclk_drv.
1174 * 70 = zipd4___zipd___zipd_clk___zip_history_csclk_drv.
1175 * 71 = zipd4___zipd___zipd_clk___zip_state_csclk_drv.
1176 * 72 = zipd4___zipd___zipd_clk___zip_sha_csclk_drv.
1177 * 73 = zipd5___zipd___zipd_clk___zip_history_csclk_drv.
1178 * 74 = zipd5___zipd___zipd_clk___zip_state_csclk_drv.
1179 * 75 = zipd5___zipd___zipd_clk___zip_sha_csclk_drv.
1180 */
1181 union bdk_iobnx_cond_clk_capx
1182 {
1183 uint64_t u;
1184 struct bdk_iobnx_cond_clk_capx_s
1185 {
1186 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1187 uint64_t reserved_16_63 : 48;
1188 uint64_t cap : 16; /**< [ 15: 0](R/W) Conditional clock capacitance for drivers. (cap value * 0.9/128.)
1189 For diagnostic use only. */
1190 #else /* Word 0 - Little Endian */
1191 uint64_t cap : 16; /**< [ 15: 0](R/W) Conditional clock capacitance for drivers. (cap value * 0.9/128.)
1192 For diagnostic use only. */
1193 uint64_t reserved_16_63 : 48;
1194 #endif /* Word 0 - End */
1195 } s;
1196 /* struct bdk_iobnx_cond_clk_capx_s cn; */
1197 };
1198 typedef union bdk_iobnx_cond_clk_capx bdk_iobnx_cond_clk_capx_t;
1199
1200 static inline uint64_t BDK_IOBNX_COND_CLK_CAPX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_IOBNX_COND_CLK_CAPX(unsigned long a,unsigned long b)1201 static inline uint64_t BDK_IOBNX_COND_CLK_CAPX(unsigned long a, unsigned long b)
1202 {
1203 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b<=75)))
1204 return 0x87e0f000f000ll + 0x1000000ll * ((a) & 0x1) + 8ll * ((b) & 0x7f);
1205 __bdk_csr_fatal("IOBNX_COND_CLK_CAPX", 2, a, b, 0, 0);
1206 }
1207
1208 #define typedef_BDK_IOBNX_COND_CLK_CAPX(a,b) bdk_iobnx_cond_clk_capx_t
1209 #define bustype_BDK_IOBNX_COND_CLK_CAPX(a,b) BDK_CSR_TYPE_RSL
1210 #define basename_BDK_IOBNX_COND_CLK_CAPX(a,b) "IOBNX_COND_CLK_CAPX"
1211 #define device_bar_BDK_IOBNX_COND_CLK_CAPX(a,b) 0x0 /* PF_BAR0 */
1212 #define busnum_BDK_IOBNX_COND_CLK_CAPX(a,b) (a)
1213 #define arguments_BDK_IOBNX_COND_CLK_CAPX(a,b) (a),(b),-1,-1
1214
1215 /**
1216 * Register (RSL) iobn#_const
1217 *
1218 * IOBN Constant Registers
1219 * This register returns discovery information.
1220 */
1221 union bdk_iobnx_const
1222 {
1223 uint64_t u;
1224 struct bdk_iobnx_const_s
1225 {
1226 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1227 uint64_t reserved_24_63 : 40;
1228 uint64_t arbs : 8; /**< [ 23: 16](RO) Maximum number of grants on any NCB bus attached to this IOB. */
1229 uint64_t ncbs : 8; /**< [ 15: 8](RO) Number of physical NCB busses attached to this IOB. */
1230 uint64_t iobs : 8; /**< [ 7: 0](RO) Number of IOBs. */
1231 #else /* Word 0 - Little Endian */
1232 uint64_t iobs : 8; /**< [ 7: 0](RO) Number of IOBs. */
1233 uint64_t ncbs : 8; /**< [ 15: 8](RO) Number of physical NCB busses attached to this IOB. */
1234 uint64_t arbs : 8; /**< [ 23: 16](RO) Maximum number of grants on any NCB bus attached to this IOB. */
1235 uint64_t reserved_24_63 : 40;
1236 #endif /* Word 0 - End */
1237 } s;
1238 /* struct bdk_iobnx_const_s cn; */
1239 };
1240 typedef union bdk_iobnx_const bdk_iobnx_const_t;
1241
1242 static inline uint64_t BDK_IOBNX_CONST(unsigned long a) __attribute__ ((pure, always_inline));
BDK_IOBNX_CONST(unsigned long a)1243 static inline uint64_t BDK_IOBNX_CONST(unsigned long a)
1244 {
1245 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
1246 return 0x87e0f0000000ll + 0x1000000ll * ((a) & 0x1);
1247 __bdk_csr_fatal("IOBNX_CONST", 1, a, 0, 0, 0);
1248 }
1249
1250 #define typedef_BDK_IOBNX_CONST(a) bdk_iobnx_const_t
1251 #define bustype_BDK_IOBNX_CONST(a) BDK_CSR_TYPE_RSL
1252 #define basename_BDK_IOBNX_CONST(a) "IOBNX_CONST"
1253 #define device_bar_BDK_IOBNX_CONST(a) 0x0 /* PF_BAR0 */
1254 #define busnum_BDK_IOBNX_CONST(a) (a)
1255 #define arguments_BDK_IOBNX_CONST(a) (a),-1,-1,-1
1256
1257 /**
1258 * Register (RSL) iobn#_core_bist_status
1259 *
1260 * IOBN Cores BIST Status Register
1261 * This register contains the result of the BIST run on the cores.
1262 */
1263 union bdk_iobnx_core_bist_status
1264 {
1265 uint64_t u;
1266 struct bdk_iobnx_core_bist_status_s
1267 {
1268 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1269 uint64_t reserved_24_63 : 40;
1270 uint64_t core_bstat : 24; /**< [ 23: 0](RO/H) BIST status of the cores. IOBN0 contains the BIST status for the even numbered cores and
1271 IOBN1 contains the BIST status for the odd numbered cores.
1272
1273 \<pre\>
1274 BIT IOBN0 IOBN0 MASK BIT IOBN1 IOBN1 MASK BIT
1275 [0] Core 0 \<0\> Core 1 \<1\>
1276 [1] Core 2 \<2\> Core 3 \<3\>
1277 ...
1278 [23] Core 46 \<46\> Core 47 \<47\>
1279 \</pre\>
1280
1281 Software must logically AND CORE_BSTAT bits with appropriate bits from RST_PP_AVAILABLE
1282 before using them. The "IOBN0 MASK BIT" column in the table above shows the
1283 RST_PP_AVAILABLE bits to use with IOBN0. The "IOBN1 MASK BIT" column in the
1284 table above shows the RST_PP_AVAILABLE bits to use with IOBN1. */
1285 #else /* Word 0 - Little Endian */
1286 uint64_t core_bstat : 24; /**< [ 23: 0](RO/H) BIST status of the cores. IOBN0 contains the BIST status for the even numbered cores and
1287 IOBN1 contains the BIST status for the odd numbered cores.
1288
1289 \<pre\>
1290 BIT IOBN0 IOBN0 MASK BIT IOBN1 IOBN1 MASK BIT
1291 [0] Core 0 \<0\> Core 1 \<1\>
1292 [1] Core 2 \<2\> Core 3 \<3\>
1293 ...
1294 [23] Core 46 \<46\> Core 47 \<47\>
1295 \</pre\>
1296
1297 Software must logically AND CORE_BSTAT bits with appropriate bits from RST_PP_AVAILABLE
1298 before using them. The "IOBN0 MASK BIT" column in the table above shows the
1299 RST_PP_AVAILABLE bits to use with IOBN0. The "IOBN1 MASK BIT" column in the
1300 table above shows the RST_PP_AVAILABLE bits to use with IOBN1. */
1301 uint64_t reserved_24_63 : 40;
1302 #endif /* Word 0 - End */
1303 } s;
1304 struct bdk_iobnx_core_bist_status_cn81xx
1305 {
1306 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1307 uint64_t reserved_4_63 : 60;
1308 uint64_t core_bstat : 4; /**< [ 3: 0](RO/H) BIST status of the cores. IOBN0 contains the BIST status for the even numbered cores and
1309 IOBN1 contains the BIST status for the odd numbered cores.
1310
1311 \<pre\>
1312 BIT IOBN
1313 [0] Core 0
1314 [1] Core 1
1315 [2] Core 2
1316 [3] Core 3
1317 \</pre\>
1318
1319 Software must bit-wise logical AND CORE_BSTAT with RST_PP_AVAILABLE before using it. */
1320 #else /* Word 0 - Little Endian */
1321 uint64_t core_bstat : 4; /**< [ 3: 0](RO/H) BIST status of the cores. IOBN0 contains the BIST status for the even numbered cores and
1322 IOBN1 contains the BIST status for the odd numbered cores.
1323
1324 \<pre\>
1325 BIT IOBN
1326 [0] Core 0
1327 [1] Core 1
1328 [2] Core 2
1329 [3] Core 3
1330 \</pre\>
1331
1332 Software must bit-wise logical AND CORE_BSTAT with RST_PP_AVAILABLE before using it. */
1333 uint64_t reserved_4_63 : 60;
1334 #endif /* Word 0 - End */
1335 } cn81xx;
1336 /* struct bdk_iobnx_core_bist_status_s cn88xx; */
1337 struct bdk_iobnx_core_bist_status_cn83xx
1338 {
1339 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1340 uint64_t reserved_24_63 : 40;
1341 uint64_t core_bstat : 24; /**< [ 23: 0](RO/H) BIST status of the cores. IOBN0 contains the BIST status for all cores. IOBN1
1342 always returns 0x0.
1343
1344 Software must bit-wise logical and CORE_BSTAT with RST_PP_AVAILABLE before using
1345 it. */
1346 #else /* Word 0 - Little Endian */
1347 uint64_t core_bstat : 24; /**< [ 23: 0](RO/H) BIST status of the cores. IOBN0 contains the BIST status for all cores. IOBN1
1348 always returns 0x0.
1349
1350 Software must bit-wise logical and CORE_BSTAT with RST_PP_AVAILABLE before using
1351 it. */
1352 uint64_t reserved_24_63 : 40;
1353 #endif /* Word 0 - End */
1354 } cn83xx;
1355 };
1356 typedef union bdk_iobnx_core_bist_status bdk_iobnx_core_bist_status_t;
1357
1358 static inline uint64_t BDK_IOBNX_CORE_BIST_STATUS(unsigned long a) __attribute__ ((pure, always_inline));
BDK_IOBNX_CORE_BIST_STATUS(unsigned long a)1359 static inline uint64_t BDK_IOBNX_CORE_BIST_STATUS(unsigned long a)
1360 {
1361 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
1362 return 0x87e0f0005008ll + 0x1000000ll * ((a) & 0x0);
1363 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
1364 return 0x87e0f0005008ll + 0x1000000ll * ((a) & 0x1);
1365 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
1366 return 0x87e0f0005008ll + 0x1000000ll * ((a) & 0x1);
1367 __bdk_csr_fatal("IOBNX_CORE_BIST_STATUS", 1, a, 0, 0, 0);
1368 }
1369
1370 #define typedef_BDK_IOBNX_CORE_BIST_STATUS(a) bdk_iobnx_core_bist_status_t
1371 #define bustype_BDK_IOBNX_CORE_BIST_STATUS(a) BDK_CSR_TYPE_RSL
1372 #define basename_BDK_IOBNX_CORE_BIST_STATUS(a) "IOBNX_CORE_BIST_STATUS"
1373 #define device_bar_BDK_IOBNX_CORE_BIST_STATUS(a) 0x0 /* PF_BAR0 */
1374 #define busnum_BDK_IOBNX_CORE_BIST_STATUS(a) (a)
1375 #define arguments_BDK_IOBNX_CORE_BIST_STATUS(a) (a),-1,-1,-1
1376
1377 /**
1378 * Register (RSL) iobn#_dis_ncbi_io
1379 *
1380 * IOBN Disable NCBI IO Register
1381 * IOBN control.
1382 */
1383 union bdk_iobnx_dis_ncbi_io
1384 {
1385 uint64_t u;
1386 struct bdk_iobnx_dis_ncbi_io_s
1387 {
1388 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1389 uint64_t reserved_6_63 : 58;
1390 uint64_t sli_key_mem : 1; /**< [ 5: 5](R/W) SLI KEY memory isolation.
1391 0 = SLI initiated requests are allowed.
1392 1 = SLI initiated read and write requests are allowed to
1393 KEY_MEM(0..2047) (e.g. 16KB, not all of KEY_MEM) only.
1394 SLI requests to any other address (non-KEY_MEM(0..2047))
1395 will be redirected to ECAM0_NOP_ZF. */
1396 uint64_t sli_off : 1; /**< [ 4: 4](R/W) SLI isolation.
1397 Resets to one in trusted mode, else zero.
1398 0 = Operation of NCBI transactions are not impacted.
1399 1 = NCBI transactions initiating at the SLI are disabled and
1400 turn into accesses to ECAM0_NOP_ZF. When set, this bit
1401 overrides [SLI_KEY_MEM]. */
1402 uint64_t tlb_sync_dis : 1; /**< [ 3: 3](R/W) When set the IOBN will return SYNC-RDY to the SMMU without waiting for
1403 outstanding request to receive responses. */
1404 uint64_t oci_key_only : 1; /**< [ 2: 2](RO) Restrict CCPI-sourced I/O write requests.
1405
1406 0 = CCPI-sourced I/O read and write requests are allowed to any device through
1407 IOB, including allowing read/writes to all of KEY_MEM().
1408
1409 1 = CCPI-sourced I/O write requests allowed to KEY_MEM(0..2047) (e.g. 16KB, not
1410 all of KEY_MEM) only. CCPI-sourced writes to __any__ other address
1411 (non-KEY_MEM(0..2047)), or any CCPI-source read will be redirected to
1412 ECAM0_NOP_ZF (for non-ECAM) or ECAM0_NOP_ONNF (for-ECAM).
1413
1414 This setting does not affect local-node originated traffic.
1415
1416 In pass 1, read-only. */
1417 uint64_t all_gic : 1; /**< [ 1: 1](R/W) All-to-GIC. For diagnostic use only.
1418 Internal:
1419 0 = Normal operation. NCBI traffic to GIC interrupt delivery registers will be ordered
1420 with other interrupt delivery traffic and over the RIB bus. NCBI traffic to normal non-
1421 interrupt-delivery GIC registers will go via RSL.
1422 1 = All NCBI traffic to the GIC DID will be assumed to be interrupt delivery traffic.
1423 This will break NCBI write transactions to non-interrupt-delivery GIC registers, but may
1424 work around bugs whereby interrupt-delivery CSRs are mis-catagorized inside IOB. */
1425 uint64_t ncbi_off : 1; /**< [ 0: 0](R/W) When set NCBI translation to I/O space (with exception of GIC traffic) will be disabled.
1426 Disabled traffic will turn into access to ECAM0_NOP_ZF. */
1427 #else /* Word 0 - Little Endian */
1428 uint64_t ncbi_off : 1; /**< [ 0: 0](R/W) When set NCBI translation to I/O space (with exception of GIC traffic) will be disabled.
1429 Disabled traffic will turn into access to ECAM0_NOP_ZF. */
1430 uint64_t all_gic : 1; /**< [ 1: 1](R/W) All-to-GIC. For diagnostic use only.
1431 Internal:
1432 0 = Normal operation. NCBI traffic to GIC interrupt delivery registers will be ordered
1433 with other interrupt delivery traffic and over the RIB bus. NCBI traffic to normal non-
1434 interrupt-delivery GIC registers will go via RSL.
1435 1 = All NCBI traffic to the GIC DID will be assumed to be interrupt delivery traffic.
1436 This will break NCBI write transactions to non-interrupt-delivery GIC registers, but may
1437 work around bugs whereby interrupt-delivery CSRs are mis-catagorized inside IOB. */
1438 uint64_t oci_key_only : 1; /**< [ 2: 2](RO) Restrict CCPI-sourced I/O write requests.
1439
1440 0 = CCPI-sourced I/O read and write requests are allowed to any device through
1441 IOB, including allowing read/writes to all of KEY_MEM().
1442
1443 1 = CCPI-sourced I/O write requests allowed to KEY_MEM(0..2047) (e.g. 16KB, not
1444 all of KEY_MEM) only. CCPI-sourced writes to __any__ other address
1445 (non-KEY_MEM(0..2047)), or any CCPI-source read will be redirected to
1446 ECAM0_NOP_ZF (for non-ECAM) or ECAM0_NOP_ONNF (for-ECAM).
1447
1448 This setting does not affect local-node originated traffic.
1449
1450 In pass 1, read-only. */
1451 uint64_t tlb_sync_dis : 1; /**< [ 3: 3](R/W) When set the IOBN will return SYNC-RDY to the SMMU without waiting for
1452 outstanding request to receive responses. */
1453 uint64_t sli_off : 1; /**< [ 4: 4](R/W) SLI isolation.
1454 Resets to one in trusted mode, else zero.
1455 0 = Operation of NCBI transactions are not impacted.
1456 1 = NCBI transactions initiating at the SLI are disabled and
1457 turn into accesses to ECAM0_NOP_ZF. When set, this bit
1458 overrides [SLI_KEY_MEM]. */
1459 uint64_t sli_key_mem : 1; /**< [ 5: 5](R/W) SLI KEY memory isolation.
1460 0 = SLI initiated requests are allowed.
1461 1 = SLI initiated read and write requests are allowed to
1462 KEY_MEM(0..2047) (e.g. 16KB, not all of KEY_MEM) only.
1463 SLI requests to any other address (non-KEY_MEM(0..2047))
1464 will be redirected to ECAM0_NOP_ZF. */
1465 uint64_t reserved_6_63 : 58;
1466 #endif /* Word 0 - End */
1467 } s;
1468 struct bdk_iobnx_dis_ncbi_io_cn88xxp1
1469 {
1470 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1471 uint64_t reserved_4_63 : 60;
1472 uint64_t tlb_sync_dis : 1; /**< [ 3: 3](R/W) When set the IOBN will return SYNC-RDY to the SMMU without waiting for
1473 outstanding request to receive responses. */
1474 uint64_t oci_key_only : 1; /**< [ 2: 2](RO) Restrict CCPI-sourced I/O write requests.
1475
1476 0 = CCPI-sourced I/O read and write requests are allowed to any device through
1477 IOB, including allowing read/writes to all of KEY_MEM().
1478
1479 1 = CCPI-sourced I/O write requests allowed to KEY_MEM(0..2047) (e.g. 16KB, not
1480 all of KEY_MEM) only. CCPI-sourced writes to __any__ other address
1481 (non-KEY_MEM(0..2047)), or any CCPI-source read will be redirected to
1482 ECAM0_NOP_ZF (for non-ECAM) or ECAM0_NOP_ONNF (for-ECAM).
1483
1484 This setting does not affect local-node originated traffic.
1485
1486 In pass 1, read-only. */
1487 uint64_t all_gic : 1; /**< [ 1: 1](R/W) All-to-GIC. For diagnostic use only.
1488 Internal:
1489 0 = Normal operation. NCBI traffic to GIC interrupt delivery registers will be ordered
1490 with other interrupt delivery traffic and over the RIB bus. NCBI traffic to normal non-
1491 interrupt-delivery GIC registers will go via RSL.
1492 1 = All NCBI traffic to the GIC DID will be assumed to be interrupt delivery traffic.
1493 This will break NCBI write transactions to non-interrupt-delivery GIC registers, but may
1494 work around bugs whereby interrupt-delivery CSRs are mis-catagorized inside IOB. */
1495 uint64_t ncbi_off : 1; /**< [ 0: 0](R/W) When set NCBI translation to I/O space (with exception of GIC traffic) will be disabled.
1496 Disabled traffic will turn into access to ECAM0_NOP_ZF. */
1497 #else /* Word 0 - Little Endian */
1498 uint64_t ncbi_off : 1; /**< [ 0: 0](R/W) When set NCBI translation to I/O space (with exception of GIC traffic) will be disabled.
1499 Disabled traffic will turn into access to ECAM0_NOP_ZF. */
1500 uint64_t all_gic : 1; /**< [ 1: 1](R/W) All-to-GIC. For diagnostic use only.
1501 Internal:
1502 0 = Normal operation. NCBI traffic to GIC interrupt delivery registers will be ordered
1503 with other interrupt delivery traffic and over the RIB bus. NCBI traffic to normal non-
1504 interrupt-delivery GIC registers will go via RSL.
1505 1 = All NCBI traffic to the GIC DID will be assumed to be interrupt delivery traffic.
1506 This will break NCBI write transactions to non-interrupt-delivery GIC registers, but may
1507 work around bugs whereby interrupt-delivery CSRs are mis-catagorized inside IOB. */
1508 uint64_t oci_key_only : 1; /**< [ 2: 2](RO) Restrict CCPI-sourced I/O write requests.
1509
1510 0 = CCPI-sourced I/O read and write requests are allowed to any device through
1511 IOB, including allowing read/writes to all of KEY_MEM().
1512
1513 1 = CCPI-sourced I/O write requests allowed to KEY_MEM(0..2047) (e.g. 16KB, not
1514 all of KEY_MEM) only. CCPI-sourced writes to __any__ other address
1515 (non-KEY_MEM(0..2047)), or any CCPI-source read will be redirected to
1516 ECAM0_NOP_ZF (for non-ECAM) or ECAM0_NOP_ONNF (for-ECAM).
1517
1518 This setting does not affect local-node originated traffic.
1519
1520 In pass 1, read-only. */
1521 uint64_t tlb_sync_dis : 1; /**< [ 3: 3](R/W) When set the IOBN will return SYNC-RDY to the SMMU without waiting for
1522 outstanding request to receive responses. */
1523 uint64_t reserved_4_63 : 60;
1524 #endif /* Word 0 - End */
1525 } cn88xxp1;
1526 struct bdk_iobnx_dis_ncbi_io_cn81xx
1527 {
1528 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1529 uint64_t reserved_4_63 : 60;
1530 uint64_t tlb_sync_dis : 1; /**< [ 3: 3](R/W) When set the IOBN will return SYNC-RDY to the SMMU without waiting for
1531 outstanding request to receive responses. */
1532 uint64_t oci_key_only : 1; /**< [ 2: 2](R/W) Restrict CCPI-sourced I/O write requests.
1533
1534 0 = CCPI-sourced I/O read and write requests are allowed to any device through
1535 IOB, including allowing read/writes to all of KEY_MEM().
1536
1537 1 = CCPI-sourced I/O write requests allowed to KEY_MEM(0..2047) (e.g. 16KB, not
1538 all of KEY_MEM) only. CCPI-sourced writes to __any__ other address
1539 (non-KEY_MEM(0..2047)), or any CCPI-source read will be redirected to
1540 ECAM0_NOP_ZF (for non-ECAM) or ECAM0_NOP_ONNF (for-ECAM).
1541
1542 This setting does not affect local-node originated traffic.
1543
1544 In pass 1, read-only. */
1545 uint64_t all_gic : 1; /**< [ 1: 1](R/W) All-to-GIC. For diagnostic use only.
1546 Internal:
1547 0 = Normal operation. NCBI traffic to GIC interrupt delivery registers will be ordered
1548 with other interrupt delivery traffic and over the RIB bus. NCBI traffic to normal non-
1549 interrupt-delivery GIC registers will go via RSL.
1550 1 = All NCBI traffic to the GIC DID will be assumed to be interrupt delivery traffic.
1551 This will break NCBI write transactions to non-interrupt-delivery GIC registers, but may
1552 work around bugs whereby interrupt-delivery CSRs are mis-catagorized inside IOB. */
1553 uint64_t ncbi_off : 1; /**< [ 0: 0](R/W) When set NCBI translation to I/O space (with exception of GIC traffic) will be disabled.
1554 Disabled traffic will turn into access to ECAM0_NOP_ZF. */
1555 #else /* Word 0 - Little Endian */
1556 uint64_t ncbi_off : 1; /**< [ 0: 0](R/W) When set NCBI translation to I/O space (with exception of GIC traffic) will be disabled.
1557 Disabled traffic will turn into access to ECAM0_NOP_ZF. */
1558 uint64_t all_gic : 1; /**< [ 1: 1](R/W) All-to-GIC. For diagnostic use only.
1559 Internal:
1560 0 = Normal operation. NCBI traffic to GIC interrupt delivery registers will be ordered
1561 with other interrupt delivery traffic and over the RIB bus. NCBI traffic to normal non-
1562 interrupt-delivery GIC registers will go via RSL.
1563 1 = All NCBI traffic to the GIC DID will be assumed to be interrupt delivery traffic.
1564 This will break NCBI write transactions to non-interrupt-delivery GIC registers, but may
1565 work around bugs whereby interrupt-delivery CSRs are mis-catagorized inside IOB. */
1566 uint64_t oci_key_only : 1; /**< [ 2: 2](R/W) Restrict CCPI-sourced I/O write requests.
1567
1568 0 = CCPI-sourced I/O read and write requests are allowed to any device through
1569 IOB, including allowing read/writes to all of KEY_MEM().
1570
1571 1 = CCPI-sourced I/O write requests allowed to KEY_MEM(0..2047) (e.g. 16KB, not
1572 all of KEY_MEM) only. CCPI-sourced writes to __any__ other address
1573 (non-KEY_MEM(0..2047)), or any CCPI-source read will be redirected to
1574 ECAM0_NOP_ZF (for non-ECAM) or ECAM0_NOP_ONNF (for-ECAM).
1575
1576 This setting does not affect local-node originated traffic.
1577
1578 In pass 1, read-only. */
1579 uint64_t tlb_sync_dis : 1; /**< [ 3: 3](R/W) When set the IOBN will return SYNC-RDY to the SMMU without waiting for
1580 outstanding request to receive responses. */
1581 uint64_t reserved_4_63 : 60;
1582 #endif /* Word 0 - End */
1583 } cn81xx;
1584 struct bdk_iobnx_dis_ncbi_io_cn83xx
1585 {
1586 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1587 uint64_t reserved_6_63 : 58;
1588 uint64_t sli_key_mem : 1; /**< [ 5: 5](R/W) SLI KEY memory isolation.
1589 0 = SLI initiated requests are allowed.
1590 1 = SLI initiated read and write requests are allowed to
1591 KEY_MEM(0..2047) (e.g. 16KB, not all of KEY_MEM) only.
1592 SLI requests to any other address (non-KEY_MEM(0..2047))
1593 will be redirected to ECAM0_NOP_ZF. */
1594 uint64_t sli_off : 1; /**< [ 4: 4](R/W) SLI isolation.
1595 Resets to one in trusted mode, else zero.
1596 0 = Operation of NCBI transactions are not impacted.
1597 1 = NCBI transactions initiating at the SLI are disabled and
1598 turn into accesses to ECAM0_NOP_ZF. When set, this bit
1599 overrides [SLI_KEY_MEM]. */
1600 uint64_t tlb_sync_dis : 1; /**< [ 3: 3](R/W) When set the IOBN will return SYNC-RDY to the SMMU without waiting for
1601 outstanding request to receive responses. */
1602 uint64_t oci_key_only : 1; /**< [ 2: 2](R/W) Restrict CCPI-sourced I/O write requests.
1603
1604 0 = CCPI-sourced I/O read and write requests are allowed to any device through
1605 IOB, including allowing read/writes to all of KEY_MEM().
1606
1607 1 = CCPI-sourced I/O write requests allowed to KEY_MEM(0..2047) (e.g. 16KB, not
1608 all of KEY_MEM) only. CCPI-sourced writes to __any__ other address
1609 (non-KEY_MEM(0..2047)), or any CCPI-source read will be redirected to
1610 ECAM0_NOP_ZF (for non-ECAM) or ECAM0_NOP_ONNF (for-ECAM).
1611
1612 This setting does not affect local-node originated traffic.
1613
1614 In pass 1, read-only. */
1615 uint64_t all_gic : 1; /**< [ 1: 1](R/W) All-to-GIC. For diagnostic use only.
1616 Internal:
1617 0 = Normal operation. NCBI traffic to GIC interrupt delivery registers will be ordered
1618 with other interrupt delivery traffic and over the RIB bus. NCBI traffic to normal non-
1619 interrupt-delivery GIC registers will go via RSL.
1620 1 = All NCBI traffic to the GIC DID will be assumed to be interrupt delivery traffic.
1621 This will break NCBI write transactions to non-interrupt-delivery GIC registers, but may
1622 work around bugs whereby interrupt-delivery CSRs are mis-catagorized inside IOB. */
1623 uint64_t ncbi_off : 1; /**< [ 0: 0](R/W) When set NCBI translation to I/O space (with exception of GIC traffic) will be disabled.
1624 Disabled traffic will turn into access to ECAM0_NOP_ZF. */
1625 #else /* Word 0 - Little Endian */
1626 uint64_t ncbi_off : 1; /**< [ 0: 0](R/W) When set NCBI translation to I/O space (with exception of GIC traffic) will be disabled.
1627 Disabled traffic will turn into access to ECAM0_NOP_ZF. */
1628 uint64_t all_gic : 1; /**< [ 1: 1](R/W) All-to-GIC. For diagnostic use only.
1629 Internal:
1630 0 = Normal operation. NCBI traffic to GIC interrupt delivery registers will be ordered
1631 with other interrupt delivery traffic and over the RIB bus. NCBI traffic to normal non-
1632 interrupt-delivery GIC registers will go via RSL.
1633 1 = All NCBI traffic to the GIC DID will be assumed to be interrupt delivery traffic.
1634 This will break NCBI write transactions to non-interrupt-delivery GIC registers, but may
1635 work around bugs whereby interrupt-delivery CSRs are mis-catagorized inside IOB. */
1636 uint64_t oci_key_only : 1; /**< [ 2: 2](R/W) Restrict CCPI-sourced I/O write requests.
1637
1638 0 = CCPI-sourced I/O read and write requests are allowed to any device through
1639 IOB, including allowing read/writes to all of KEY_MEM().
1640
1641 1 = CCPI-sourced I/O write requests allowed to KEY_MEM(0..2047) (e.g. 16KB, not
1642 all of KEY_MEM) only. CCPI-sourced writes to __any__ other address
1643 (non-KEY_MEM(0..2047)), or any CCPI-source read will be redirected to
1644 ECAM0_NOP_ZF (for non-ECAM) or ECAM0_NOP_ONNF (for-ECAM).
1645
1646 This setting does not affect local-node originated traffic.
1647
1648 In pass 1, read-only. */
1649 uint64_t tlb_sync_dis : 1; /**< [ 3: 3](R/W) When set the IOBN will return SYNC-RDY to the SMMU without waiting for
1650 outstanding request to receive responses. */
1651 uint64_t sli_off : 1; /**< [ 4: 4](R/W) SLI isolation.
1652 Resets to one in trusted mode, else zero.
1653 0 = Operation of NCBI transactions are not impacted.
1654 1 = NCBI transactions initiating at the SLI are disabled and
1655 turn into accesses to ECAM0_NOP_ZF. When set, this bit
1656 overrides [SLI_KEY_MEM]. */
1657 uint64_t sli_key_mem : 1; /**< [ 5: 5](R/W) SLI KEY memory isolation.
1658 0 = SLI initiated requests are allowed.
1659 1 = SLI initiated read and write requests are allowed to
1660 KEY_MEM(0..2047) (e.g. 16KB, not all of KEY_MEM) only.
1661 SLI requests to any other address (non-KEY_MEM(0..2047))
1662 will be redirected to ECAM0_NOP_ZF. */
1663 uint64_t reserved_6_63 : 58;
1664 #endif /* Word 0 - End */
1665 } cn83xx;
1666 /* struct bdk_iobnx_dis_ncbi_io_cn81xx cn88xxp2; */
1667 };
1668 typedef union bdk_iobnx_dis_ncbi_io bdk_iobnx_dis_ncbi_io_t;
1669
1670 static inline uint64_t BDK_IOBNX_DIS_NCBI_IO(unsigned long a) __attribute__ ((pure, always_inline));
BDK_IOBNX_DIS_NCBI_IO(unsigned long a)1671 static inline uint64_t BDK_IOBNX_DIS_NCBI_IO(unsigned long a)
1672 {
1673 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
1674 return 0x87e0f0003000ll + 0x1000000ll * ((a) & 0x0);
1675 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
1676 return 0x87e0f0003000ll + 0x1000000ll * ((a) & 0x1);
1677 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
1678 return 0x87e0f0003000ll + 0x1000000ll * ((a) & 0x1);
1679 __bdk_csr_fatal("IOBNX_DIS_NCBI_IO", 1, a, 0, 0, 0);
1680 }
1681
1682 #define typedef_BDK_IOBNX_DIS_NCBI_IO(a) bdk_iobnx_dis_ncbi_io_t
1683 #define bustype_BDK_IOBNX_DIS_NCBI_IO(a) BDK_CSR_TYPE_RSL
1684 #define basename_BDK_IOBNX_DIS_NCBI_IO(a) "IOBNX_DIS_NCBI_IO"
1685 #define device_bar_BDK_IOBNX_DIS_NCBI_IO(a) 0x0 /* PF_BAR0 */
1686 #define busnum_BDK_IOBNX_DIS_NCBI_IO(a) (a)
1687 #define arguments_BDK_IOBNX_DIS_NCBI_IO(a) (a),-1,-1,-1
1688
1689 /**
1690 * Register (RSL) iobn#_dll
1691 *
1692 * INTERNAL: IOBN Core-Clock DLL Status Register
1693 *
1694 * Status of the CCU core-clock DLL. For diagnostic use only.
1695 */
1696 union bdk_iobnx_dll
1697 {
1698 uint64_t u;
1699 struct bdk_iobnx_dll_s
1700 {
1701 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1702 uint64_t reserved_35_63 : 29;
1703 uint64_t dbg_window : 3; /**< [ 34: 32](R/W/H) Defines a debug window, during which the DLL settings and the phase detector
1704 outputs will be monitored. The min and the max DLL setting during that window is
1705 going to be reported as well as any illegal phase detector outputs. Every write
1706 to the [DBG_WINDOW] resets [ILLEGAL_PD_REVERSED], [ILLEGAL_PD_LATE],
1707 [ILLEGAL_PD_EARLY], [MAX_DLL_SETTING] and [MIN_DLL_SETTING]. The debug window
1708 will correspond to the following number of rclk cycles based on the [DBG_WINDOW]
1709 value.
1710 0x0 = Indefinetly.
1711 0x1 = 2 ^ 8 core clock cycles.
1712 0x2 = 2 ^ 12 core clock cycles.
1713 0x3 = 2 ^ 16 core clock cycles.
1714 0x4 = 2 ^ 20 core clock cycles.
1715 0x5 = 2 ^ 24 core clock cycles.
1716 0x6 = 2 ^ 28 core clock cycles.
1717 0x7 = 2 ^ 32 core clock cycles. */
1718 uint64_t dbg_window_done : 1; /**< [ 31: 31](RO/H) Indicates if the debug window set by [DBG_WINDOW] is completed. */
1719 uint64_t illegal_pd_reversed : 1; /**< [ 30: 30](RO/H) clk_fast_rgt and clk_fast_lft outputs of the phase detector had concurrently an
1720 illegal reading during the last debug window set by [DBG_WINDOW]. */
1721 uint64_t illegal_pd_late : 1; /**< [ 29: 29](RO/H) clk_fast_rgt output of the phase detector had an illegal reading (1) during the
1722 last debug window set by [DBG_WINDOW]. */
1723 uint64_t illegal_pd_early : 1; /**< [ 28: 28](RO/H) clk_fast_lft output of the phase detector had an illegal reading (0) during the
1724 last debug window set by [DBG_WINDOW]. */
1725 uint64_t reserved_27 : 1;
1726 uint64_t max_dll_setting : 7; /**< [ 26: 20](RO/H) Max reported DLL setting during the last debug window set by [DBG_WINDOW]. */
1727 uint64_t reserved_19 : 1;
1728 uint64_t min_dll_setting : 7; /**< [ 18: 12](RO/H) Min reported DLL setting during the last debug window set by [DBG_WINDOW]. */
1729 uint64_t pd_out : 3; /**< [ 11: 9](RO/H) Synchronized output from CCU phase detector:
1730 \<11\> = clk_fast_mid.
1731 \<10\> = clk_fast_lft.
1732 \<9\> = clk_fast_rgt. */
1733 uint64_t dll_lock : 1; /**< [ 8: 8](RO/H) The dll_lock signal from ROC core-clock DLL, from the positive edge of refclk. */
1734 uint64_t reserved_7 : 1;
1735 uint64_t dll_setting : 7; /**< [ 6: 0](RO/H) The ROC core-clock DLL setting, from the negative edge of refclk. */
1736 #else /* Word 0 - Little Endian */
1737 uint64_t dll_setting : 7; /**< [ 6: 0](RO/H) The ROC core-clock DLL setting, from the negative edge of refclk. */
1738 uint64_t reserved_7 : 1;
1739 uint64_t dll_lock : 1; /**< [ 8: 8](RO/H) The dll_lock signal from ROC core-clock DLL, from the positive edge of refclk. */
1740 uint64_t pd_out : 3; /**< [ 11: 9](RO/H) Synchronized output from CCU phase detector:
1741 \<11\> = clk_fast_mid.
1742 \<10\> = clk_fast_lft.
1743 \<9\> = clk_fast_rgt. */
1744 uint64_t min_dll_setting : 7; /**< [ 18: 12](RO/H) Min reported DLL setting during the last debug window set by [DBG_WINDOW]. */
1745 uint64_t reserved_19 : 1;
1746 uint64_t max_dll_setting : 7; /**< [ 26: 20](RO/H) Max reported DLL setting during the last debug window set by [DBG_WINDOW]. */
1747 uint64_t reserved_27 : 1;
1748 uint64_t illegal_pd_early : 1; /**< [ 28: 28](RO/H) clk_fast_lft output of the phase detector had an illegal reading (0) during the
1749 last debug window set by [DBG_WINDOW]. */
1750 uint64_t illegal_pd_late : 1; /**< [ 29: 29](RO/H) clk_fast_rgt output of the phase detector had an illegal reading (1) during the
1751 last debug window set by [DBG_WINDOW]. */
1752 uint64_t illegal_pd_reversed : 1; /**< [ 30: 30](RO/H) clk_fast_rgt and clk_fast_lft outputs of the phase detector had concurrently an
1753 illegal reading during the last debug window set by [DBG_WINDOW]. */
1754 uint64_t dbg_window_done : 1; /**< [ 31: 31](RO/H) Indicates if the debug window set by [DBG_WINDOW] is completed. */
1755 uint64_t dbg_window : 3; /**< [ 34: 32](R/W/H) Defines a debug window, during which the DLL settings and the phase detector
1756 outputs will be monitored. The min and the max DLL setting during that window is
1757 going to be reported as well as any illegal phase detector outputs. Every write
1758 to the [DBG_WINDOW] resets [ILLEGAL_PD_REVERSED], [ILLEGAL_PD_LATE],
1759 [ILLEGAL_PD_EARLY], [MAX_DLL_SETTING] and [MIN_DLL_SETTING]. The debug window
1760 will correspond to the following number of rclk cycles based on the [DBG_WINDOW]
1761 value.
1762 0x0 = Indefinetly.
1763 0x1 = 2 ^ 8 core clock cycles.
1764 0x2 = 2 ^ 12 core clock cycles.
1765 0x3 = 2 ^ 16 core clock cycles.
1766 0x4 = 2 ^ 20 core clock cycles.
1767 0x5 = 2 ^ 24 core clock cycles.
1768 0x6 = 2 ^ 28 core clock cycles.
1769 0x7 = 2 ^ 32 core clock cycles. */
1770 uint64_t reserved_35_63 : 29;
1771 #endif /* Word 0 - End */
1772 } s;
1773 /* struct bdk_iobnx_dll_s cn; */
1774 };
1775 typedef union bdk_iobnx_dll bdk_iobnx_dll_t;
1776
1777 static inline uint64_t BDK_IOBNX_DLL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_IOBNX_DLL(unsigned long a)1778 static inline uint64_t BDK_IOBNX_DLL(unsigned long a)
1779 {
1780 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
1781 return 0x87e0f0003040ll + 0x1000000ll * ((a) & 0x1);
1782 __bdk_csr_fatal("IOBNX_DLL", 1, a, 0, 0, 0);
1783 }
1784
1785 #define typedef_BDK_IOBNX_DLL(a) bdk_iobnx_dll_t
1786 #define bustype_BDK_IOBNX_DLL(a) BDK_CSR_TYPE_RSL
1787 #define basename_BDK_IOBNX_DLL(a) "IOBNX_DLL"
1788 #define device_bar_BDK_IOBNX_DLL(a) 0x0 /* PF_BAR0 */
1789 #define busnum_BDK_IOBNX_DLL(a) (a)
1790 #define arguments_BDK_IOBNX_DLL(a) (a),-1,-1,-1
1791
1792 /**
1793 * Register (RSL) iobn#_dom#_bus#_streams
1794 *
1795 * IOBN Domain Bus Permit Registers
1796 * This register sets the permissions for a NCBI transaction (which are DMA
1797 * transactions or MSI-X writes), for requests for NCB device virtual-functions
1798 * and bridges.
1799 *
1800 * Index {b} corresponds to the stream's domain (stream_id\<21:16\>).
1801 *
1802 * Index {c} corresponds to the stream's bus number (stream_id\<15:8\>).
1803 *
1804 * For each combination of index {b} and {c}, each index {a} (the IOB number) must be
1805 * programmed to the same value.
1806 *
1807 * Streams which hit index {c}=0x0 are also affected by IOBN()_DOM()_DEV()_STREAMS.
1808 * Streams which hit index {b}=PCC_DEV_CON_E::MRML\<21:16\>,
1809 * {c}=PCC_DEV_CON_E::MRML\<15:8\> are also affected by IOBN()_RSL()_STREAMS.
1810 * Both of those alternative registers provide better granularity, so those indices
1811 * into this register should be left permissive (value of 0x0).
1812 */
1813 union bdk_iobnx_domx_busx_streams
1814 {
1815 uint64_t u;
1816 struct bdk_iobnx_domx_busx_streams_s
1817 {
1818 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1819 uint64_t reserved_2_63 : 62;
1820 uint64_t strm_nsec : 1; /**< [ 1: 1](SR/W) Stream nonsecure.
1821
1822 0 = The device's stream ID is marked secure headed into the SMMU. If the
1823 device is making a non-physical request, the SMMU will use secure world
1824 lookup. The SMMU may, if properly configured, generate an outgoing physical
1825 address that is secure.
1826
1827 1 = The device's stream ID is marked nonsecure headed into the SMMU. If the
1828 device is making a non-physical request, the SMMU will use nonsecure world
1829 lookup. The SMMU outgoing physical address will be nonsecure.
1830
1831 [STRM_NSEC] is ignored if the device is making a physical request (as these
1832 transactions bypass the SMMU translation process).
1833
1834 Typically firmware sets [PHYS_NSEC] and [STRM_NSEC] the same. */
1835 uint64_t phys_nsec : 1; /**< [ 0: 0](SR/W) Physical nonsecure.
1836 0 = When the device makes a physical request, IOB will use the device's
1837 requested secure bit to determine if the request to DRAM/LLC is secure or not.
1838 1 = When the device makes a physical request, IOB will squash the
1839 device's secure request and issue the request to DRAM/LLC as nonsecure.
1840
1841 Ignored if a device makes a non-physical request. (As non-physical requests
1842 cause the SMMU to generate the SMMU-outgoing secure bit based on the SMMU
1843 translation process, including [STRM_NSEC].)
1844
1845 Typically firmware sets [PHYS_NSEC] and [STRM_NSEC] the same. */
1846 #else /* Word 0 - Little Endian */
1847 uint64_t phys_nsec : 1; /**< [ 0: 0](SR/W) Physical nonsecure.
1848 0 = When the device makes a physical request, IOB will use the device's
1849 requested secure bit to determine if the request to DRAM/LLC is secure or not.
1850 1 = When the device makes a physical request, IOB will squash the
1851 device's secure request and issue the request to DRAM/LLC as nonsecure.
1852
1853 Ignored if a device makes a non-physical request. (As non-physical requests
1854 cause the SMMU to generate the SMMU-outgoing secure bit based on the SMMU
1855 translation process, including [STRM_NSEC].)
1856
1857 Typically firmware sets [PHYS_NSEC] and [STRM_NSEC] the same. */
1858 uint64_t strm_nsec : 1; /**< [ 1: 1](SR/W) Stream nonsecure.
1859
1860 0 = The device's stream ID is marked secure headed into the SMMU. If the
1861 device is making a non-physical request, the SMMU will use secure world
1862 lookup. The SMMU may, if properly configured, generate an outgoing physical
1863 address that is secure.
1864
1865 1 = The device's stream ID is marked nonsecure headed into the SMMU. If the
1866 device is making a non-physical request, the SMMU will use nonsecure world
1867 lookup. The SMMU outgoing physical address will be nonsecure.
1868
1869 [STRM_NSEC] is ignored if the device is making a physical request (as these
1870 transactions bypass the SMMU translation process).
1871
1872 Typically firmware sets [PHYS_NSEC] and [STRM_NSEC] the same. */
1873 uint64_t reserved_2_63 : 62;
1874 #endif /* Word 0 - End */
1875 } s;
1876 /* struct bdk_iobnx_domx_busx_streams_s cn; */
1877 };
1878 typedef union bdk_iobnx_domx_busx_streams bdk_iobnx_domx_busx_streams_t;
1879
1880 static inline uint64_t BDK_IOBNX_DOMX_BUSX_STREAMS(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_IOBNX_DOMX_BUSX_STREAMS(unsigned long a,unsigned long b,unsigned long c)1881 static inline uint64_t BDK_IOBNX_DOMX_BUSX_STREAMS(unsigned long a, unsigned long b, unsigned long c)
1882 {
1883 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b<=6) && (c<=255)))
1884 return 0x87e0f0040000ll + 0x1000000ll * ((a) & 0x1) + 0x800ll * ((b) & 0x7) + 8ll * ((c) & 0xff);
1885 __bdk_csr_fatal("IOBNX_DOMX_BUSX_STREAMS", 3, a, b, c, 0);
1886 }
1887
1888 #define typedef_BDK_IOBNX_DOMX_BUSX_STREAMS(a,b,c) bdk_iobnx_domx_busx_streams_t
1889 #define bustype_BDK_IOBNX_DOMX_BUSX_STREAMS(a,b,c) BDK_CSR_TYPE_RSL
1890 #define basename_BDK_IOBNX_DOMX_BUSX_STREAMS(a,b,c) "IOBNX_DOMX_BUSX_STREAMS"
1891 #define device_bar_BDK_IOBNX_DOMX_BUSX_STREAMS(a,b,c) 0x0 /* PF_BAR0 */
1892 #define busnum_BDK_IOBNX_DOMX_BUSX_STREAMS(a,b,c) (a)
1893 #define arguments_BDK_IOBNX_DOMX_BUSX_STREAMS(a,b,c) (a),(b),(c),-1
1894
1895 /**
1896 * Register (RSL) iobn#_dom#_dev#_streams
1897 *
1898 * IOBN Device Bus Permit Registers
1899 * This register sets the permissions for a NCBI transaction (which are DMA
1900 * transactions or MSI-X writes), for requests for NCB device physicical-functions,
1901 * i.e. those where:
1902 *
1903 * _ stream_id\<15:8\> = 0x0.
1904 *
1905 * Index {a} corresponds to the stream's domain number (stream_id\<21:16\>).
1906 *
1907 * Index {b} corresponds to the non-ARI ECAM device number (stream_id\<7:3\>).
1908 *
1909 * For each combination of index {b} and {c}, each index {a} (the IOB number) must be
1910 * programmed to the same value.
1911 */
1912 union bdk_iobnx_domx_devx_streams
1913 {
1914 uint64_t u;
1915 struct bdk_iobnx_domx_devx_streams_s
1916 {
1917 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1918 uint64_t reserved_2_63 : 62;
1919 uint64_t strm_nsec : 1; /**< [ 1: 1](SR/W) Stream nonsecure.
1920
1921 0 = The device's stream ID is marked secure headed into the SMMU. If the
1922 device is making a non-physical request, the SMMU will use secure world
1923 lookup. The SMMU may, if properly configured, generate an outgoing physical
1924 address that is secure.
1925
1926 1 = The device's stream ID is marked nonsecure headed into the SMMU. If the
1927 device is making a non-physical request, the SMMU will use nonsecure world
1928 lookup. The SMMU outgoing physical address will be nonsecure.
1929
1930 [STRM_NSEC] is ignored if the device is making a physical request (as these
1931 transactions bypass the SMMU translation process).
1932
1933 Typically firmware sets [PHYS_NSEC] and [STRM_NSEC] the same. */
1934 uint64_t phys_nsec : 1; /**< [ 0: 0](SR/W) Physical nonsecure.
1935 0 = When the device makes a physical request, IOB will use the device's
1936 requested secure bit to determine if the request to DRAM/LLC is secure or not.
1937 1 = When the device makes a physical request, IOB will squash the
1938 device's secure request and issue the request to DRAM/LLC as nonsecure.
1939
1940 Ignored if a device makes a non-physical request. (As non-physical requests
1941 cause the SMMU to generate the SMMU-outgoing secure bit based on the SMMU
1942 translation process, including [STRM_NSEC].)
1943
1944 Typically firmware sets [PHYS_NSEC] and [STRM_NSEC] the same. */
1945 #else /* Word 0 - Little Endian */
1946 uint64_t phys_nsec : 1; /**< [ 0: 0](SR/W) Physical nonsecure.
1947 0 = When the device makes a physical request, IOB will use the device's
1948 requested secure bit to determine if the request to DRAM/LLC is secure or not.
1949 1 = When the device makes a physical request, IOB will squash the
1950 device's secure request and issue the request to DRAM/LLC as nonsecure.
1951
1952 Ignored if a device makes a non-physical request. (As non-physical requests
1953 cause the SMMU to generate the SMMU-outgoing secure bit based on the SMMU
1954 translation process, including [STRM_NSEC].)
1955
1956 Typically firmware sets [PHYS_NSEC] and [STRM_NSEC] the same. */
1957 uint64_t strm_nsec : 1; /**< [ 1: 1](SR/W) Stream nonsecure.
1958
1959 0 = The device's stream ID is marked secure headed into the SMMU. If the
1960 device is making a non-physical request, the SMMU will use secure world
1961 lookup. The SMMU may, if properly configured, generate an outgoing physical
1962 address that is secure.
1963
1964 1 = The device's stream ID is marked nonsecure headed into the SMMU. If the
1965 device is making a non-physical request, the SMMU will use nonsecure world
1966 lookup. The SMMU outgoing physical address will be nonsecure.
1967
1968 [STRM_NSEC] is ignored if the device is making a physical request (as these
1969 transactions bypass the SMMU translation process).
1970
1971 Typically firmware sets [PHYS_NSEC] and [STRM_NSEC] the same. */
1972 uint64_t reserved_2_63 : 62;
1973 #endif /* Word 0 - End */
1974 } s;
1975 /* struct bdk_iobnx_domx_devx_streams_s cn; */
1976 };
1977 typedef union bdk_iobnx_domx_devx_streams bdk_iobnx_domx_devx_streams_t;
1978
1979 static inline uint64_t BDK_IOBNX_DOMX_DEVX_STREAMS(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_IOBNX_DOMX_DEVX_STREAMS(unsigned long a,unsigned long b,unsigned long c)1980 static inline uint64_t BDK_IOBNX_DOMX_DEVX_STREAMS(unsigned long a, unsigned long b, unsigned long c)
1981 {
1982 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b<=6) && (c<=31)))
1983 return 0x87e0f0010000ll + 0x1000000ll * ((a) & 0x1) + 0x100ll * ((b) & 0x7) + 8ll * ((c) & 0x1f);
1984 __bdk_csr_fatal("IOBNX_DOMX_DEVX_STREAMS", 3, a, b, c, 0);
1985 }
1986
1987 #define typedef_BDK_IOBNX_DOMX_DEVX_STREAMS(a,b,c) bdk_iobnx_domx_devx_streams_t
1988 #define bustype_BDK_IOBNX_DOMX_DEVX_STREAMS(a,b,c) BDK_CSR_TYPE_RSL
1989 #define basename_BDK_IOBNX_DOMX_DEVX_STREAMS(a,b,c) "IOBNX_DOMX_DEVX_STREAMS"
1990 #define device_bar_BDK_IOBNX_DOMX_DEVX_STREAMS(a,b,c) 0x0 /* PF_BAR0 */
1991 #define busnum_BDK_IOBNX_DOMX_DEVX_STREAMS(a,b,c) (a)
1992 #define arguments_BDK_IOBNX_DOMX_DEVX_STREAMS(a,b,c) (a),(b),(c),-1
1993
1994 /**
1995 * Register (RSL) iobn#_gbl_dll
1996 *
1997 * INTERNAL: IOBN Global Core-Clock DLL Status Register
1998 *
1999 * Status of the global core-clock DLL.
2000 */
2001 union bdk_iobnx_gbl_dll
2002 {
2003 uint64_t u;
2004 struct bdk_iobnx_gbl_dll_s
2005 {
2006 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2007 uint64_t reserved_20_63 : 44;
2008 uint64_t pdr_rclk_refclk : 1; /**< [ 19: 19](RO/H) Synchronized pdr_rclk_refclk from global core-clock DLL cmb0 phase detectors. */
2009 uint64_t pdl_rclk_refclk : 1; /**< [ 18: 18](RO/H) Synchronized pdl_rclk_refclk from global core-clock DLL cmb0 phase detectors. */
2010 uint64_t pd_pos_rclk_refclk : 1; /**< [ 17: 17](RO/H) Synchronized pd_pos_rclk_refclk from global core-clock DLL cmb0 phase detectors. */
2011 uint64_t dll_fsm_state_a : 3; /**< [ 16: 14](RO/H) State for the global core-clock DLL, from the positive edge of refclk.
2012 0x0 = TMD_IDLE.
2013 0x1 = TMD_STATE1.
2014 0x2 = TMD_STATE2.
2015 0x3 = TMD_STATE3.
2016 0x4 = TMD_STATE4.
2017 0x5 = TMD_LOCKED. */
2018 uint64_t dll_lock : 1; /**< [ 13: 13](RO/H) The dll_lock signal from global core-clock DLL, from the positive edge of refclk. */
2019 uint64_t dll_clk_invert_out : 1; /**< [ 12: 12](RO/H) The clk_invert setting from the global core-clock DLL, from the negative edge of refclk. */
2020 uint64_t dll_setting : 12; /**< [ 11: 0](RO/H) The global core-clock DLL setting, from the negative edge of refclk. */
2021 #else /* Word 0 - Little Endian */
2022 uint64_t dll_setting : 12; /**< [ 11: 0](RO/H) The global core-clock DLL setting, from the negative edge of refclk. */
2023 uint64_t dll_clk_invert_out : 1; /**< [ 12: 12](RO/H) The clk_invert setting from the global core-clock DLL, from the negative edge of refclk. */
2024 uint64_t dll_lock : 1; /**< [ 13: 13](RO/H) The dll_lock signal from global core-clock DLL, from the positive edge of refclk. */
2025 uint64_t dll_fsm_state_a : 3; /**< [ 16: 14](RO/H) State for the global core-clock DLL, from the positive edge of refclk.
2026 0x0 = TMD_IDLE.
2027 0x1 = TMD_STATE1.
2028 0x2 = TMD_STATE2.
2029 0x3 = TMD_STATE3.
2030 0x4 = TMD_STATE4.
2031 0x5 = TMD_LOCKED. */
2032 uint64_t pd_pos_rclk_refclk : 1; /**< [ 17: 17](RO/H) Synchronized pd_pos_rclk_refclk from global core-clock DLL cmb0 phase detectors. */
2033 uint64_t pdl_rclk_refclk : 1; /**< [ 18: 18](RO/H) Synchronized pdl_rclk_refclk from global core-clock DLL cmb0 phase detectors. */
2034 uint64_t pdr_rclk_refclk : 1; /**< [ 19: 19](RO/H) Synchronized pdr_rclk_refclk from global core-clock DLL cmb0 phase detectors. */
2035 uint64_t reserved_20_63 : 44;
2036 #endif /* Word 0 - End */
2037 } s;
2038 /* struct bdk_iobnx_gbl_dll_s cn; */
2039 };
2040 typedef union bdk_iobnx_gbl_dll bdk_iobnx_gbl_dll_t;
2041
2042 static inline uint64_t BDK_IOBNX_GBL_DLL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_IOBNX_GBL_DLL(unsigned long a)2043 static inline uint64_t BDK_IOBNX_GBL_DLL(unsigned long a)
2044 {
2045 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
2046 return 0x87e0f000a000ll + 0x1000000ll * ((a) & 0x0);
2047 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
2048 return 0x87e0f000a000ll + 0x1000000ll * ((a) & 0x1);
2049 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
2050 return 0x87e0f000a000ll + 0x1000000ll * ((a) & 0x1);
2051 __bdk_csr_fatal("IOBNX_GBL_DLL", 1, a, 0, 0, 0);
2052 }
2053
2054 #define typedef_BDK_IOBNX_GBL_DLL(a) bdk_iobnx_gbl_dll_t
2055 #define bustype_BDK_IOBNX_GBL_DLL(a) BDK_CSR_TYPE_RSL
2056 #define basename_BDK_IOBNX_GBL_DLL(a) "IOBNX_GBL_DLL"
2057 #define device_bar_BDK_IOBNX_GBL_DLL(a) 0x0 /* PF_BAR0 */
2058 #define busnum_BDK_IOBNX_GBL_DLL(a) (a)
2059 #define arguments_BDK_IOBNX_GBL_DLL(a) (a),-1,-1,-1
2060
2061 /**
2062 * Register (RSL) iobn#_int1
2063 *
2064 * IOBN Interrupt Summary Register
2065 * This register contains the different interrupt-summary bits of the IOBN.
2066 */
2067 union bdk_iobnx_int1
2068 {
2069 uint64_t u;
2070 struct bdk_iobnx_int1_s
2071 {
2072 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2073 uint64_t reserved_1_63 : 63;
2074 uint64_t gibm_f : 1; /**< [ 0: 0](R/W1C/H) GIBM on NCB0 received a STDN with fault. */
2075 #else /* Word 0 - Little Endian */
2076 uint64_t gibm_f : 1; /**< [ 0: 0](R/W1C/H) GIBM on NCB0 received a STDN with fault. */
2077 uint64_t reserved_1_63 : 63;
2078 #endif /* Word 0 - End */
2079 } s;
2080 /* struct bdk_iobnx_int1_s cn; */
2081 };
2082 typedef union bdk_iobnx_int1 bdk_iobnx_int1_t;
2083
2084 static inline uint64_t BDK_IOBNX_INT1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_IOBNX_INT1(unsigned long a)2085 static inline uint64_t BDK_IOBNX_INT1(unsigned long a)
2086 {
2087 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
2088 return 0x87e0f000a000ll + 0x1000000ll * ((a) & 0x1);
2089 __bdk_csr_fatal("IOBNX_INT1", 1, a, 0, 0, 0);
2090 }
2091
2092 #define typedef_BDK_IOBNX_INT1(a) bdk_iobnx_int1_t
2093 #define bustype_BDK_IOBNX_INT1(a) BDK_CSR_TYPE_RSL
2094 #define basename_BDK_IOBNX_INT1(a) "IOBNX_INT1"
2095 #define device_bar_BDK_IOBNX_INT1(a) 0x0 /* PF_BAR0 */
2096 #define busnum_BDK_IOBNX_INT1(a) (a)
2097 #define arguments_BDK_IOBNX_INT1(a) (a),-1,-1,-1
2098
2099 /**
2100 * Register (RSL) iobn#_int1_ena_w1c
2101 *
2102 * IOBN Interrupt Enable Clear Register
2103 * This register clears interrupt enable bits.
2104 */
2105 union bdk_iobnx_int1_ena_w1c
2106 {
2107 uint64_t u;
2108 struct bdk_iobnx_int1_ena_w1c_s
2109 {
2110 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2111 uint64_t reserved_1_63 : 63;
2112 uint64_t gibm_f : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for IOBN(0..1)_INT1[GIBM_F]. */
2113 #else /* Word 0 - Little Endian */
2114 uint64_t gibm_f : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for IOBN(0..1)_INT1[GIBM_F]. */
2115 uint64_t reserved_1_63 : 63;
2116 #endif /* Word 0 - End */
2117 } s;
2118 /* struct bdk_iobnx_int1_ena_w1c_s cn; */
2119 };
2120 typedef union bdk_iobnx_int1_ena_w1c bdk_iobnx_int1_ena_w1c_t;
2121
2122 static inline uint64_t BDK_IOBNX_INT1_ENA_W1C(unsigned long a) __attribute__ ((pure, always_inline));
BDK_IOBNX_INT1_ENA_W1C(unsigned long a)2123 static inline uint64_t BDK_IOBNX_INT1_ENA_W1C(unsigned long a)
2124 {
2125 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
2126 return 0x87e0f000a010ll + 0x1000000ll * ((a) & 0x1);
2127 __bdk_csr_fatal("IOBNX_INT1_ENA_W1C", 1, a, 0, 0, 0);
2128 }
2129
2130 #define typedef_BDK_IOBNX_INT1_ENA_W1C(a) bdk_iobnx_int1_ena_w1c_t
2131 #define bustype_BDK_IOBNX_INT1_ENA_W1C(a) BDK_CSR_TYPE_RSL
2132 #define basename_BDK_IOBNX_INT1_ENA_W1C(a) "IOBNX_INT1_ENA_W1C"
2133 #define device_bar_BDK_IOBNX_INT1_ENA_W1C(a) 0x0 /* PF_BAR0 */
2134 #define busnum_BDK_IOBNX_INT1_ENA_W1C(a) (a)
2135 #define arguments_BDK_IOBNX_INT1_ENA_W1C(a) (a),-1,-1,-1
2136
2137 /**
2138 * Register (RSL) iobn#_int1_ena_w1s
2139 *
2140 * IOBN Interrupt Enable Set Register
2141 * This register sets interrupt enable bits.
2142 */
2143 union bdk_iobnx_int1_ena_w1s
2144 {
2145 uint64_t u;
2146 struct bdk_iobnx_int1_ena_w1s_s
2147 {
2148 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2149 uint64_t reserved_1_63 : 63;
2150 uint64_t gibm_f : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for IOBN(0..1)_INT1[GIBM_F]. */
2151 #else /* Word 0 - Little Endian */
2152 uint64_t gibm_f : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for IOBN(0..1)_INT1[GIBM_F]. */
2153 uint64_t reserved_1_63 : 63;
2154 #endif /* Word 0 - End */
2155 } s;
2156 /* struct bdk_iobnx_int1_ena_w1s_s cn; */
2157 };
2158 typedef union bdk_iobnx_int1_ena_w1s bdk_iobnx_int1_ena_w1s_t;
2159
2160 static inline uint64_t BDK_IOBNX_INT1_ENA_W1S(unsigned long a) __attribute__ ((pure, always_inline));
BDK_IOBNX_INT1_ENA_W1S(unsigned long a)2161 static inline uint64_t BDK_IOBNX_INT1_ENA_W1S(unsigned long a)
2162 {
2163 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
2164 return 0x87e0f000a018ll + 0x1000000ll * ((a) & 0x1);
2165 __bdk_csr_fatal("IOBNX_INT1_ENA_W1S", 1, a, 0, 0, 0);
2166 }
2167
2168 #define typedef_BDK_IOBNX_INT1_ENA_W1S(a) bdk_iobnx_int1_ena_w1s_t
2169 #define bustype_BDK_IOBNX_INT1_ENA_W1S(a) BDK_CSR_TYPE_RSL
2170 #define basename_BDK_IOBNX_INT1_ENA_W1S(a) "IOBNX_INT1_ENA_W1S"
2171 #define device_bar_BDK_IOBNX_INT1_ENA_W1S(a) 0x0 /* PF_BAR0 */
2172 #define busnum_BDK_IOBNX_INT1_ENA_W1S(a) (a)
2173 #define arguments_BDK_IOBNX_INT1_ENA_W1S(a) (a),-1,-1,-1
2174
2175 /**
2176 * Register (RSL) iobn#_int1_w1s
2177 *
2178 * IOBN Interrupt Set Register
2179 * This register sets interrupt bits.
2180 */
2181 union bdk_iobnx_int1_w1s
2182 {
2183 uint64_t u;
2184 struct bdk_iobnx_int1_w1s_s
2185 {
2186 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2187 uint64_t reserved_1_63 : 63;
2188 uint64_t gibm_f : 1; /**< [ 0: 0](R/W1S/H) Reads or sets IOBN(0..1)_INT1[GIBM_F]. */
2189 #else /* Word 0 - Little Endian */
2190 uint64_t gibm_f : 1; /**< [ 0: 0](R/W1S/H) Reads or sets IOBN(0..1)_INT1[GIBM_F]. */
2191 uint64_t reserved_1_63 : 63;
2192 #endif /* Word 0 - End */
2193 } s;
2194 /* struct bdk_iobnx_int1_w1s_s cn; */
2195 };
2196 typedef union bdk_iobnx_int1_w1s bdk_iobnx_int1_w1s_t;
2197
2198 static inline uint64_t BDK_IOBNX_INT1_W1S(unsigned long a) __attribute__ ((pure, always_inline));
BDK_IOBNX_INT1_W1S(unsigned long a)2199 static inline uint64_t BDK_IOBNX_INT1_W1S(unsigned long a)
2200 {
2201 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
2202 return 0x87e0f000a008ll + 0x1000000ll * ((a) & 0x1);
2203 __bdk_csr_fatal("IOBNX_INT1_W1S", 1, a, 0, 0, 0);
2204 }
2205
2206 #define typedef_BDK_IOBNX_INT1_W1S(a) bdk_iobnx_int1_w1s_t
2207 #define bustype_BDK_IOBNX_INT1_W1S(a) BDK_CSR_TYPE_RSL
2208 #define basename_BDK_IOBNX_INT1_W1S(a) "IOBNX_INT1_W1S"
2209 #define device_bar_BDK_IOBNX_INT1_W1S(a) 0x0 /* PF_BAR0 */
2210 #define busnum_BDK_IOBNX_INT1_W1S(a) (a)
2211 #define arguments_BDK_IOBNX_INT1_W1S(a) (a),-1,-1,-1
2212
2213 /**
2214 * Register (RSL) iobn#_int_ena_w1c
2215 *
2216 * IOBN Interrupt Enable Clear Register
2217 * This register clears interrupt enable bits.
2218 */
2219 union bdk_iobnx_int_ena_w1c
2220 {
2221 uint64_t u;
2222 struct bdk_iobnx_int_ena_w1c_s
2223 {
2224 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2225 uint64_t pem_sie : 1; /**< [ 63: 63](R/W1C/H) Reads or clears enable for IOBN(0..1)_INT_SUM[PEM_SIE]. */
2226 uint64_t ied0_dbe : 31; /**< [ 62: 32](R/W1C/H) Reads or clears enable for IOBN(0..1)_INT_SUM[IED0_DBE].
2227 Internal:
2228 gmr_ixofifo_dbe_sclk,
2229 icc0_xmc_fif_dbe,
2230 icc1_xmc_fif_dbe,
2231 icc_xmc_fifo_ecc_dbe,
2232 sli_preq_0_dbe_sclk,
2233 sli_req_0_dbe_sclk,
2234 sli_preq_1_dbe_sclk,
2235 sli_req_1_dbe_sclk,
2236 sli_preq_2_dbe_sclk,
2237 sli_req_2_dbe_sclk,
2238 ixo_smmu_mem0_dbe_sclk,
2239 iop_breq_fifo0_dbe,
2240 iop_breq_fifo1_dbe ,
2241 iop_breq_fifo2_dbe,
2242 iop_breq_fifo3_dbe ,
2243 iop_ffifo_dbe_sclk,
2244 rsd_mem0_dbe,
2245 rsd_mem1_dbe,
2246 ics_cmd_fifo_dbe_sclk,
2247 ixo_xmd_mem1_dbe_sclk,
2248 ixo_xmd_mem0_dbe_sclk,
2249 iobn_iorn_ffifo0__dbe_sclk,
2250 iobn_iorn_ffifo1__dbe_sclk,
2251 irp1_flid_mem_dbe,
2252 irp0_flid_mem_dbe,
2253 ixo_icc_fifo0_dbe_in_sclk,
2254 ixo_icc_fifo1_dbe_in_sclk,
2255 ixo_ics_mem_dbe_in_sclk. */
2256 uint64_t reserved_0_31 : 32;
2257 #else /* Word 0 - Little Endian */
2258 uint64_t reserved_0_31 : 32;
2259 uint64_t ied0_dbe : 31; /**< [ 62: 32](R/W1C/H) Reads or clears enable for IOBN(0..1)_INT_SUM[IED0_DBE].
2260 Internal:
2261 gmr_ixofifo_dbe_sclk,
2262 icc0_xmc_fif_dbe,
2263 icc1_xmc_fif_dbe,
2264 icc_xmc_fifo_ecc_dbe,
2265 sli_preq_0_dbe_sclk,
2266 sli_req_0_dbe_sclk,
2267 sli_preq_1_dbe_sclk,
2268 sli_req_1_dbe_sclk,
2269 sli_preq_2_dbe_sclk,
2270 sli_req_2_dbe_sclk,
2271 ixo_smmu_mem0_dbe_sclk,
2272 iop_breq_fifo0_dbe,
2273 iop_breq_fifo1_dbe ,
2274 iop_breq_fifo2_dbe,
2275 iop_breq_fifo3_dbe ,
2276 iop_ffifo_dbe_sclk,
2277 rsd_mem0_dbe,
2278 rsd_mem1_dbe,
2279 ics_cmd_fifo_dbe_sclk,
2280 ixo_xmd_mem1_dbe_sclk,
2281 ixo_xmd_mem0_dbe_sclk,
2282 iobn_iorn_ffifo0__dbe_sclk,
2283 iobn_iorn_ffifo1__dbe_sclk,
2284 irp1_flid_mem_dbe,
2285 irp0_flid_mem_dbe,
2286 ixo_icc_fifo0_dbe_in_sclk,
2287 ixo_icc_fifo1_dbe_in_sclk,
2288 ixo_ics_mem_dbe_in_sclk. */
2289 uint64_t pem_sie : 1; /**< [ 63: 63](R/W1C/H) Reads or clears enable for IOBN(0..1)_INT_SUM[PEM_SIE]. */
2290 #endif /* Word 0 - End */
2291 } s;
2292 struct bdk_iobnx_int_ena_w1c_cn88xxp1
2293 {
2294 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2295 uint64_t reserved_60_63 : 4;
2296 uint64_t ied0_dbe : 28; /**< [ 59: 32](R/W1C/H) Reads or clears enable for IOBN(0..1)_INT_SUM[IED0_DBE].
2297 Internal:
2298 gmr_ixofifo_dbe_sclk,
2299 icc0_xmc_fif_dbe,
2300 icc1_xmc_fif_dbe,
2301 icc_xmc_fifo_ecc_dbe,
2302 sli_preq_0_dbe_sclk,
2303 sli_req_0_dbe_sclk,
2304 sli_preq_1_dbe_sclk,
2305 sli_req_1_dbe_sclk,
2306 sli_preq_2_dbe_sclk,
2307 sli_req_2_dbe_sclk,
2308 ixo_smmu_mem0_dbe_sclk,
2309 iop_breq_fifo0_dbe,
2310 iop_breq_fifo1_dbe ,
2311 iop_breq_fifo2_dbe,
2312 iop_breq_fifo3_dbe ,
2313 iop_ffifo_dbe_sclk,
2314 rsd_mem0_dbe,
2315 rsd_mem1_dbe,
2316 ics_cmd_fifo_dbe_sclk,
2317 ixo_xmd_mem1_dbe_sclk,
2318 ixo_xmd_mem0_dbe_sclk,
2319 iobn_iorn_ffifo0__dbe_sclk,
2320 iobn_iorn_ffifo1__dbe_sclk,
2321 irp1_flid_mem_dbe,
2322 irp0_flid_mem_dbe,
2323 ixo_icc_fifo0_dbe_in_sclk,
2324 ixo_icc_fifo1_dbe_in_sclk,
2325 ixo_ics_mem_dbe_in_sclk. */
2326 uint64_t reserved_28_31 : 4;
2327 uint64_t ied0_sbe : 28; /**< [ 27: 0](R/W1C/H) Reads or clears enable for IOBN(0..1)_INT_SUM[IED0_SBE].
2328 Internal:
2329 gmr_ixofifo_sbe_sclk,
2330 icc0_xmc_fif_sbe,
2331 icc1_xmc_fif_sbe,
2332 icc_xmc_fifo_ecc_sbe,
2333 sli_preq_0_sbe_sclk,
2334 sli_req_0_sbe_sclk,
2335 sli_preq_1_sbe_sclk,
2336 sli_req_1_sbe_sclk,
2337 sli_preq_2_sbe_sclk,
2338 sli_req_2_sbe_sclk,
2339 ixo_smmu_mem0_sbe_sclk,
2340 iop_breq_fifo0_sbe,
2341 iop_breq_fifo1_sbe ,
2342 iop_breq_fifo2_sbe,
2343 iop_breq_fifo3_sbe ,
2344 iop_ffifo_sbe_sclk,
2345 rsd_mem0_sbe,
2346 rsd_mem1_sbe,
2347 ics_cmd_fifo_sbe_sclk,
2348 ixo_xmd_mem1_sbe_sclk,
2349 ixo_xmd_mem0_sbe_sclk,
2350 iobn_iorn_ffifo0__sbe_sclk,
2351 iobn_iorn_ffifo1__sbe_sclk,
2352 irp1_flid_mem_sbe,
2353 irp0_flid_mem_sbe,
2354 ixo_icc_fifo0_sbe_in_sclk,
2355 ixo_icc_fifo1_sbe_in_sclk,
2356 ixo_ics_mem_sbe_in_sclk. */
2357 #else /* Word 0 - Little Endian */
2358 uint64_t ied0_sbe : 28; /**< [ 27: 0](R/W1C/H) Reads or clears enable for IOBN(0..1)_INT_SUM[IED0_SBE].
2359 Internal:
2360 gmr_ixofifo_sbe_sclk,
2361 icc0_xmc_fif_sbe,
2362 icc1_xmc_fif_sbe,
2363 icc_xmc_fifo_ecc_sbe,
2364 sli_preq_0_sbe_sclk,
2365 sli_req_0_sbe_sclk,
2366 sli_preq_1_sbe_sclk,
2367 sli_req_1_sbe_sclk,
2368 sli_preq_2_sbe_sclk,
2369 sli_req_2_sbe_sclk,
2370 ixo_smmu_mem0_sbe_sclk,
2371 iop_breq_fifo0_sbe,
2372 iop_breq_fifo1_sbe ,
2373 iop_breq_fifo2_sbe,
2374 iop_breq_fifo3_sbe ,
2375 iop_ffifo_sbe_sclk,
2376 rsd_mem0_sbe,
2377 rsd_mem1_sbe,
2378 ics_cmd_fifo_sbe_sclk,
2379 ixo_xmd_mem1_sbe_sclk,
2380 ixo_xmd_mem0_sbe_sclk,
2381 iobn_iorn_ffifo0__sbe_sclk,
2382 iobn_iorn_ffifo1__sbe_sclk,
2383 irp1_flid_mem_sbe,
2384 irp0_flid_mem_sbe,
2385 ixo_icc_fifo0_sbe_in_sclk,
2386 ixo_icc_fifo1_sbe_in_sclk,
2387 ixo_ics_mem_sbe_in_sclk. */
2388 uint64_t reserved_28_31 : 4;
2389 uint64_t ied0_dbe : 28; /**< [ 59: 32](R/W1C/H) Reads or clears enable for IOBN(0..1)_INT_SUM[IED0_DBE].
2390 Internal:
2391 gmr_ixofifo_dbe_sclk,
2392 icc0_xmc_fif_dbe,
2393 icc1_xmc_fif_dbe,
2394 icc_xmc_fifo_ecc_dbe,
2395 sli_preq_0_dbe_sclk,
2396 sli_req_0_dbe_sclk,
2397 sli_preq_1_dbe_sclk,
2398 sli_req_1_dbe_sclk,
2399 sli_preq_2_dbe_sclk,
2400 sli_req_2_dbe_sclk,
2401 ixo_smmu_mem0_dbe_sclk,
2402 iop_breq_fifo0_dbe,
2403 iop_breq_fifo1_dbe ,
2404 iop_breq_fifo2_dbe,
2405 iop_breq_fifo3_dbe ,
2406 iop_ffifo_dbe_sclk,
2407 rsd_mem0_dbe,
2408 rsd_mem1_dbe,
2409 ics_cmd_fifo_dbe_sclk,
2410 ixo_xmd_mem1_dbe_sclk,
2411 ixo_xmd_mem0_dbe_sclk,
2412 iobn_iorn_ffifo0__dbe_sclk,
2413 iobn_iorn_ffifo1__dbe_sclk,
2414 irp1_flid_mem_dbe,
2415 irp0_flid_mem_dbe,
2416 ixo_icc_fifo0_dbe_in_sclk,
2417 ixo_icc_fifo1_dbe_in_sclk,
2418 ixo_ics_mem_dbe_in_sclk. */
2419 uint64_t reserved_60_63 : 4;
2420 #endif /* Word 0 - End */
2421 } cn88xxp1;
2422 struct bdk_iobnx_int_ena_w1c_cn9
2423 {
2424 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2425 uint64_t reserved_4_63 : 60;
2426 uint64_t ncbo_ncb2_psn : 1; /**< [ 3: 3](R/W1C/H) Reads or clears enable for IOBN(0..1)_INT_SUM[NCBO_NCB2_PSN]. */
2427 uint64_t ncbo_ncb1_psn : 1; /**< [ 2: 2](R/W1C/H) Reads or clears enable for IOBN(0..1)_INT_SUM[NCBO_NCB1_PSN]. */
2428 uint64_t ncbo_ncb0_psn : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for IOBN(0..1)_INT_SUM[NCBO_NCB0_PSN]. */
2429 uint64_t ncbo_to : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for IOBN(0..1)_INT_SUM[NCBO_TO]. */
2430 #else /* Word 0 - Little Endian */
2431 uint64_t ncbo_to : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for IOBN(0..1)_INT_SUM[NCBO_TO]. */
2432 uint64_t ncbo_ncb0_psn : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for IOBN(0..1)_INT_SUM[NCBO_NCB0_PSN]. */
2433 uint64_t ncbo_ncb1_psn : 1; /**< [ 2: 2](R/W1C/H) Reads or clears enable for IOBN(0..1)_INT_SUM[NCBO_NCB1_PSN]. */
2434 uint64_t ncbo_ncb2_psn : 1; /**< [ 3: 3](R/W1C/H) Reads or clears enable for IOBN(0..1)_INT_SUM[NCBO_NCB2_PSN]. */
2435 uint64_t reserved_4_63 : 60;
2436 #endif /* Word 0 - End */
2437 } cn9;
2438 struct bdk_iobnx_int_ena_w1c_cn81xx
2439 {
2440 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2441 uint64_t pem_sie : 1; /**< [ 63: 63](R/W1C/H) Reads or clears enable for IOBN(0)_INT_SUM[PEM_SIE]. */
2442 uint64_t reserved_61_62 : 2;
2443 uint64_t ied0_dbe : 29; /**< [ 60: 32](R/W1C/H) Reads or clears enable for IOBN(0)_INT_SUM[IED0_DBE].
2444 Internal:
2445 iob_mem_data_xmd_sbe_sclk,
2446 gmr_ixofifo_dbe_sclk,
2447 icc0_xmc_fif_dbe,
2448 icc1_xmc_fif_dbe,
2449 icc_xmc_fifo_ecc_dbe,
2450 sli_preq_0_dbe_sclk,
2451 sli_req_0_dbe_sclk,
2452 sli_preq_1_dbe_sclk,
2453 sli_req_1_dbe_sclk,
2454 sli_preq_2_dbe_sclk,
2455 sli_req_2_dbe_sclk,
2456 ixo_smmu_mem0_dbe_sclk,
2457 iop_breq_fifo0_dbe,
2458 iop_breq_fifo1_dbe ,
2459 iop_breq_fifo2_dbe,
2460 iop_breq_fifo3_dbe ,
2461 iop_ffifo_dbe_sclk,
2462 rsd_mem0_dbe,
2463 rsd_mem1_dbe,
2464 ics_cmd_fifo_dbe_sclk,
2465 ixo_xmd_mem1_dbe_sclk,
2466 ixo_xmd_mem0_dbe_sclk,
2467 iobn_iorn_ffifo0__dbe_sclk,
2468 iobn_iorn_ffifo1__dbe_sclk,
2469 irp1_flid_mem_dbe,
2470 irp0_flid_mem_dbe,
2471 ixo_icc_fifo0_dbe_in_sclk,
2472 ixo_icc_fifo1_dbe_in_sclk,
2473 ixo_ics_mem_dbe_in_sclk. */
2474 uint64_t reserved_29_31 : 3;
2475 uint64_t ied0_sbe : 29; /**< [ 28: 0](R/W1C/H) Reads or clears enable for IOBN(0)_INT_SUM[IED0_SBE].
2476 Internal:
2477 iob_mem_data_xmd_sbe_sclk,
2478 gmr_ixofifo_sbe_sclk,
2479 icc0_xmc_fif_sbe,
2480 icc1_xmc_fif_sbe,
2481 icc_xmc_fifo_ecc_sbe,
2482 sli_preq_0_sbe_sclk,
2483 sli_req_0_sbe_sclk,
2484 sli_preq_1_sbe_sclk,
2485 sli_req_1_sbe_sclk,
2486 sli_preq_2_sbe_sclk,
2487 sli_req_2_sbe_sclk,
2488 ixo_smmu_mem0_sbe_sclk,
2489 iop_breq_fifo0_sbe,
2490 iop_breq_fifo1_sbe ,
2491 iop_breq_fifo2_sbe,
2492 iop_breq_fifo3_sbe ,
2493 iop_ffifo_sbe_sclk,
2494 rsd_mem0_sbe,
2495 rsd_mem1_sbe,
2496 ics_cmd_fifo_sbe_sclk,
2497 ixo_xmd_mem1_sbe_sclk,
2498 ixo_xmd_mem0_sbe_sclk,
2499 iobn_iorn_ffifo0__sbe_sclk,
2500 iobn_iorn_ffifo1__sbe_sclk,
2501 irp1_flid_mem_sbe,
2502 irp0_flid_mem_sbe,
2503 ixo_icc_fifo0_sbe_in_sclk,
2504 ixo_icc_fifo1_sbe_in_sclk,
2505 ixo_ics_mem_sbe_in_sclk. */
2506 #else /* Word 0 - Little Endian */
2507 uint64_t ied0_sbe : 29; /**< [ 28: 0](R/W1C/H) Reads or clears enable for IOBN(0)_INT_SUM[IED0_SBE].
2508 Internal:
2509 iob_mem_data_xmd_sbe_sclk,
2510 gmr_ixofifo_sbe_sclk,
2511 icc0_xmc_fif_sbe,
2512 icc1_xmc_fif_sbe,
2513 icc_xmc_fifo_ecc_sbe,
2514 sli_preq_0_sbe_sclk,
2515 sli_req_0_sbe_sclk,
2516 sli_preq_1_sbe_sclk,
2517 sli_req_1_sbe_sclk,
2518 sli_preq_2_sbe_sclk,
2519 sli_req_2_sbe_sclk,
2520 ixo_smmu_mem0_sbe_sclk,
2521 iop_breq_fifo0_sbe,
2522 iop_breq_fifo1_sbe ,
2523 iop_breq_fifo2_sbe,
2524 iop_breq_fifo3_sbe ,
2525 iop_ffifo_sbe_sclk,
2526 rsd_mem0_sbe,
2527 rsd_mem1_sbe,
2528 ics_cmd_fifo_sbe_sclk,
2529 ixo_xmd_mem1_sbe_sclk,
2530 ixo_xmd_mem0_sbe_sclk,
2531 iobn_iorn_ffifo0__sbe_sclk,
2532 iobn_iorn_ffifo1__sbe_sclk,
2533 irp1_flid_mem_sbe,
2534 irp0_flid_mem_sbe,
2535 ixo_icc_fifo0_sbe_in_sclk,
2536 ixo_icc_fifo1_sbe_in_sclk,
2537 ixo_ics_mem_sbe_in_sclk. */
2538 uint64_t reserved_29_31 : 3;
2539 uint64_t ied0_dbe : 29; /**< [ 60: 32](R/W1C/H) Reads or clears enable for IOBN(0)_INT_SUM[IED0_DBE].
2540 Internal:
2541 iob_mem_data_xmd_sbe_sclk,
2542 gmr_ixofifo_dbe_sclk,
2543 icc0_xmc_fif_dbe,
2544 icc1_xmc_fif_dbe,
2545 icc_xmc_fifo_ecc_dbe,
2546 sli_preq_0_dbe_sclk,
2547 sli_req_0_dbe_sclk,
2548 sli_preq_1_dbe_sclk,
2549 sli_req_1_dbe_sclk,
2550 sli_preq_2_dbe_sclk,
2551 sli_req_2_dbe_sclk,
2552 ixo_smmu_mem0_dbe_sclk,
2553 iop_breq_fifo0_dbe,
2554 iop_breq_fifo1_dbe ,
2555 iop_breq_fifo2_dbe,
2556 iop_breq_fifo3_dbe ,
2557 iop_ffifo_dbe_sclk,
2558 rsd_mem0_dbe,
2559 rsd_mem1_dbe,
2560 ics_cmd_fifo_dbe_sclk,
2561 ixo_xmd_mem1_dbe_sclk,
2562 ixo_xmd_mem0_dbe_sclk,
2563 iobn_iorn_ffifo0__dbe_sclk,
2564 iobn_iorn_ffifo1__dbe_sclk,
2565 irp1_flid_mem_dbe,
2566 irp0_flid_mem_dbe,
2567 ixo_icc_fifo0_dbe_in_sclk,
2568 ixo_icc_fifo1_dbe_in_sclk,
2569 ixo_ics_mem_dbe_in_sclk. */
2570 uint64_t reserved_61_62 : 2;
2571 uint64_t pem_sie : 1; /**< [ 63: 63](R/W1C/H) Reads or clears enable for IOBN(0)_INT_SUM[PEM_SIE]. */
2572 #endif /* Word 0 - End */
2573 } cn81xx;
2574 struct bdk_iobnx_int_ena_w1c_cn83xx
2575 {
2576 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2577 uint64_t pem_sie : 1; /**< [ 63: 63](R/W1C/H) Reads or clears enable for IOBN(0..1)_INT_SUM[PEM_SIE]. */
2578 uint64_t ied0_dbe : 31; /**< [ 62: 32](R/W1C/H) Reads or clears enable for IOBN(0..1)_INT_SUM[IED0_DBE].
2579 Internal:
2580 iob_mem_data_xmd_sbe_sclk,
2581 gmr_ixofifo_dbe_sclk,
2582 icc0_xmc_fif_dbe,
2583 icc1_xmc_fif_dbe,
2584 icc_xmc_fifo_ecc_dbe,
2585 sli_preq_0_dbe_sclk,
2586 sli_req_0_dbe_sclk,
2587 sli_preq_1_dbe_sclk,
2588 sli_req_1_dbe_sclk,
2589 sli_preq_2_dbe_sclk,
2590 sli_req_2_dbe_sclk,
2591 sli_preq_3_dbe_sclk,
2592 sli_req_3_dbe_sclk,
2593 ixo_smmu_mem0_dbe_sclk,
2594 iop_breq_fifo0_dbe,
2595 iop_breq_fifo1_dbe ,
2596 iop_breq_fifo2_dbe,
2597 iop_breq_fifo3_dbe ,
2598 iop_ffifo_dbe_sclk,
2599 rsd_mem0_dbe,
2600 rsd_mem1_dbe,
2601 ics_cmd_fifo_dbe_sclk,
2602 ixo_xmd_mem1_dbe_sclk,
2603 ixo_xmd_mem0_dbe_sclk,
2604 iobn_iorn_ffifo0__dbe_sclk,
2605 iobn_iorn_ffifo1__dbe_sclk,
2606 irp1_flid_mem_dbe,
2607 irp0_flid_mem_dbe,
2608 ixo_icc_fifo0_dbe_in_sclk,
2609 ixo_icc_fifo1_dbe_in_sclk,
2610 ixo_ics_mem_dbe_in_sclk. */
2611 uint64_t reserved_31 : 1;
2612 uint64_t ied0_sbe : 31; /**< [ 30: 0](R/W1C/H) Reads or clears enable for IOBN(0..1)_INT_SUM[IED0_SBE].
2613 Internal:
2614 iob_mem_data_xmd_sbe_sclk,
2615 gmr_ixofifo_sbe_sclk,
2616 icc0_xmc_fif_sbe,
2617 icc1_xmc_fif_sbe,
2618 icc_xmc_fifo_ecc_sbe,
2619 sli_preq_0_sbe_sclk,
2620 sli_req_0_sbe_sclk,
2621 sli_preq_1_sbe_sclk,
2622 sli_req_1_sbe_sclk,
2623 sli_preq_2_sbe_sclk,
2624 sli_req_2_sbe_sclk,
2625 sli_preq_3_sbe_sclk,
2626 sli_req_3_sbe_sclk,
2627 ixo_smmu_mem0_sbe_sclk,
2628 iop_breq_fifo0_sbe,
2629 iop_breq_fifo1_sbe ,
2630 iop_breq_fifo2_sbe,
2631 iop_breq_fifo3_sbe ,
2632 iop_ffifo_sbe_sclk,
2633 rsd_mem0_sbe,
2634 rsd_mem1_sbe,
2635 ics_cmd_fifo_sbe_sclk,
2636 ixo_xmd_mem1_sbe_sclk,
2637 ixo_xmd_mem0_sbe_sclk,
2638 iobn_iorn_ffifo0__sbe_sclk,
2639 iobn_iorn_ffifo1__sbe_sclk,
2640 irp1_flid_mem_sbe,
2641 irp0_flid_mem_sbe,
2642 ixo_icc_fifo0_sbe_in_sclk,
2643 ixo_icc_fifo1_sbe_in_sclk,
2644 ixo_ics_mem_sbe_in_sclk. */
2645 #else /* Word 0 - Little Endian */
2646 uint64_t ied0_sbe : 31; /**< [ 30: 0](R/W1C/H) Reads or clears enable for IOBN(0..1)_INT_SUM[IED0_SBE].
2647 Internal:
2648 iob_mem_data_xmd_sbe_sclk,
2649 gmr_ixofifo_sbe_sclk,
2650 icc0_xmc_fif_sbe,
2651 icc1_xmc_fif_sbe,
2652 icc_xmc_fifo_ecc_sbe,
2653 sli_preq_0_sbe_sclk,
2654 sli_req_0_sbe_sclk,
2655 sli_preq_1_sbe_sclk,
2656 sli_req_1_sbe_sclk,
2657 sli_preq_2_sbe_sclk,
2658 sli_req_2_sbe_sclk,
2659 sli_preq_3_sbe_sclk,
2660 sli_req_3_sbe_sclk,
2661 ixo_smmu_mem0_sbe_sclk,
2662 iop_breq_fifo0_sbe,
2663 iop_breq_fifo1_sbe ,
2664 iop_breq_fifo2_sbe,
2665 iop_breq_fifo3_sbe ,
2666 iop_ffifo_sbe_sclk,
2667 rsd_mem0_sbe,
2668 rsd_mem1_sbe,
2669 ics_cmd_fifo_sbe_sclk,
2670 ixo_xmd_mem1_sbe_sclk,
2671 ixo_xmd_mem0_sbe_sclk,
2672 iobn_iorn_ffifo0__sbe_sclk,
2673 iobn_iorn_ffifo1__sbe_sclk,
2674 irp1_flid_mem_sbe,
2675 irp0_flid_mem_sbe,
2676 ixo_icc_fifo0_sbe_in_sclk,
2677 ixo_icc_fifo1_sbe_in_sclk,
2678 ixo_ics_mem_sbe_in_sclk. */
2679 uint64_t reserved_31 : 1;
2680 uint64_t ied0_dbe : 31; /**< [ 62: 32](R/W1C/H) Reads or clears enable for IOBN(0..1)_INT_SUM[IED0_DBE].
2681 Internal:
2682 iob_mem_data_xmd_sbe_sclk,
2683 gmr_ixofifo_dbe_sclk,
2684 icc0_xmc_fif_dbe,
2685 icc1_xmc_fif_dbe,
2686 icc_xmc_fifo_ecc_dbe,
2687 sli_preq_0_dbe_sclk,
2688 sli_req_0_dbe_sclk,
2689 sli_preq_1_dbe_sclk,
2690 sli_req_1_dbe_sclk,
2691 sli_preq_2_dbe_sclk,
2692 sli_req_2_dbe_sclk,
2693 sli_preq_3_dbe_sclk,
2694 sli_req_3_dbe_sclk,
2695 ixo_smmu_mem0_dbe_sclk,
2696 iop_breq_fifo0_dbe,
2697 iop_breq_fifo1_dbe ,
2698 iop_breq_fifo2_dbe,
2699 iop_breq_fifo3_dbe ,
2700 iop_ffifo_dbe_sclk,
2701 rsd_mem0_dbe,
2702 rsd_mem1_dbe,
2703 ics_cmd_fifo_dbe_sclk,
2704 ixo_xmd_mem1_dbe_sclk,
2705 ixo_xmd_mem0_dbe_sclk,
2706 iobn_iorn_ffifo0__dbe_sclk,
2707 iobn_iorn_ffifo1__dbe_sclk,
2708 irp1_flid_mem_dbe,
2709 irp0_flid_mem_dbe,
2710 ixo_icc_fifo0_dbe_in_sclk,
2711 ixo_icc_fifo1_dbe_in_sclk,
2712 ixo_ics_mem_dbe_in_sclk. */
2713 uint64_t pem_sie : 1; /**< [ 63: 63](R/W1C/H) Reads or clears enable for IOBN(0..1)_INT_SUM[PEM_SIE]. */
2714 #endif /* Word 0 - End */
2715 } cn83xx;
2716 struct bdk_iobnx_int_ena_w1c_cn88xxp2
2717 {
2718 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2719 uint64_t pem_sie : 1; /**< [ 63: 63](R/W1C/H) Reads or clears enable for IOBN(0..1)_INT_SUM[PEM_SIE]. */
2720 uint64_t reserved_61_62 : 2;
2721 uint64_t ied0_dbe : 29; /**< [ 60: 32](R/W1C/H) Reads or clears enable for IOBN(0..1)_INT_SUM[IED0_DBE].
2722 Internal:
2723 iob_mem_data_xmd_sbe_sclk,
2724 gmr_ixofifo_dbe_sclk,
2725 icc0_xmc_fif_dbe,
2726 icc1_xmc_fif_dbe,
2727 icc_xmc_fifo_ecc_dbe,
2728 sli_preq_0_dbe_sclk,
2729 sli_req_0_dbe_sclk,
2730 sli_preq_1_dbe_sclk,
2731 sli_req_1_dbe_sclk,
2732 sli_preq_2_dbe_sclk,
2733 sli_req_2_dbe_sclk,
2734 ixo_smmu_mem0_dbe_sclk,
2735 iop_breq_fifo0_dbe,
2736 iop_breq_fifo1_dbe ,
2737 iop_breq_fifo2_dbe,
2738 iop_breq_fifo3_dbe ,
2739 iop_ffifo_dbe_sclk,
2740 rsd_mem0_dbe,
2741 rsd_mem1_dbe,
2742 ics_cmd_fifo_dbe_sclk,
2743 ixo_xmd_mem1_dbe_sclk,
2744 ixo_xmd_mem0_dbe_sclk,
2745 iobn_iorn_ffifo0__dbe_sclk,
2746 iobn_iorn_ffifo1__dbe_sclk,
2747 irp1_flid_mem_dbe,
2748 irp0_flid_mem_dbe,
2749 ixo_icc_fifo0_dbe_in_sclk,
2750 ixo_icc_fifo1_dbe_in_sclk,
2751 ixo_ics_mem_dbe_in_sclk. */
2752 uint64_t reserved_29_31 : 3;
2753 uint64_t ied0_sbe : 29; /**< [ 28: 0](R/W1C/H) Reads or clears enable for IOBN(0..1)_INT_SUM[IED0_SBE].
2754 Internal:
2755 iob_mem_data_xmd_sbe_sclk,
2756 gmr_ixofifo_sbe_sclk,
2757 icc0_xmc_fif_sbe,
2758 icc1_xmc_fif_sbe,
2759 icc_xmc_fifo_ecc_sbe,
2760 sli_preq_0_sbe_sclk,
2761 sli_req_0_sbe_sclk,
2762 sli_preq_1_sbe_sclk,
2763 sli_req_1_sbe_sclk,
2764 sli_preq_2_sbe_sclk,
2765 sli_req_2_sbe_sclk,
2766 ixo_smmu_mem0_sbe_sclk,
2767 iop_breq_fifo0_sbe,
2768 iop_breq_fifo1_sbe ,
2769 iop_breq_fifo2_sbe,
2770 iop_breq_fifo3_sbe ,
2771 iop_ffifo_sbe_sclk,
2772 rsd_mem0_sbe,
2773 rsd_mem1_sbe,
2774 ics_cmd_fifo_sbe_sclk,
2775 ixo_xmd_mem1_sbe_sclk,
2776 ixo_xmd_mem0_sbe_sclk,
2777 iobn_iorn_ffifo0__sbe_sclk,
2778 iobn_iorn_ffifo1__sbe_sclk,
2779 irp1_flid_mem_sbe,
2780 irp0_flid_mem_sbe,
2781 ixo_icc_fifo0_sbe_in_sclk,
2782 ixo_icc_fifo1_sbe_in_sclk,
2783 ixo_ics_mem_sbe_in_sclk. */
2784 #else /* Word 0 - Little Endian */
2785 uint64_t ied0_sbe : 29; /**< [ 28: 0](R/W1C/H) Reads or clears enable for IOBN(0..1)_INT_SUM[IED0_SBE].
2786 Internal:
2787 iob_mem_data_xmd_sbe_sclk,
2788 gmr_ixofifo_sbe_sclk,
2789 icc0_xmc_fif_sbe,
2790 icc1_xmc_fif_sbe,
2791 icc_xmc_fifo_ecc_sbe,
2792 sli_preq_0_sbe_sclk,
2793 sli_req_0_sbe_sclk,
2794 sli_preq_1_sbe_sclk,
2795 sli_req_1_sbe_sclk,
2796 sli_preq_2_sbe_sclk,
2797 sli_req_2_sbe_sclk,
2798 ixo_smmu_mem0_sbe_sclk,
2799 iop_breq_fifo0_sbe,
2800 iop_breq_fifo1_sbe ,
2801 iop_breq_fifo2_sbe,
2802 iop_breq_fifo3_sbe ,
2803 iop_ffifo_sbe_sclk,
2804 rsd_mem0_sbe,
2805 rsd_mem1_sbe,
2806 ics_cmd_fifo_sbe_sclk,
2807 ixo_xmd_mem1_sbe_sclk,
2808 ixo_xmd_mem0_sbe_sclk,
2809 iobn_iorn_ffifo0__sbe_sclk,
2810 iobn_iorn_ffifo1__sbe_sclk,
2811 irp1_flid_mem_sbe,
2812 irp0_flid_mem_sbe,
2813 ixo_icc_fifo0_sbe_in_sclk,
2814 ixo_icc_fifo1_sbe_in_sclk,
2815 ixo_ics_mem_sbe_in_sclk. */
2816 uint64_t reserved_29_31 : 3;
2817 uint64_t ied0_dbe : 29; /**< [ 60: 32](R/W1C/H) Reads or clears enable for IOBN(0..1)_INT_SUM[IED0_DBE].
2818 Internal:
2819 iob_mem_data_xmd_sbe_sclk,
2820 gmr_ixofifo_dbe_sclk,
2821 icc0_xmc_fif_dbe,
2822 icc1_xmc_fif_dbe,
2823 icc_xmc_fifo_ecc_dbe,
2824 sli_preq_0_dbe_sclk,
2825 sli_req_0_dbe_sclk,
2826 sli_preq_1_dbe_sclk,
2827 sli_req_1_dbe_sclk,
2828 sli_preq_2_dbe_sclk,
2829 sli_req_2_dbe_sclk,
2830 ixo_smmu_mem0_dbe_sclk,
2831 iop_breq_fifo0_dbe,
2832 iop_breq_fifo1_dbe ,
2833 iop_breq_fifo2_dbe,
2834 iop_breq_fifo3_dbe ,
2835 iop_ffifo_dbe_sclk,
2836 rsd_mem0_dbe,
2837 rsd_mem1_dbe,
2838 ics_cmd_fifo_dbe_sclk,
2839 ixo_xmd_mem1_dbe_sclk,
2840 ixo_xmd_mem0_dbe_sclk,
2841 iobn_iorn_ffifo0__dbe_sclk,
2842 iobn_iorn_ffifo1__dbe_sclk,
2843 irp1_flid_mem_dbe,
2844 irp0_flid_mem_dbe,
2845 ixo_icc_fifo0_dbe_in_sclk,
2846 ixo_icc_fifo1_dbe_in_sclk,
2847 ixo_ics_mem_dbe_in_sclk. */
2848 uint64_t reserved_61_62 : 2;
2849 uint64_t pem_sie : 1; /**< [ 63: 63](R/W1C/H) Reads or clears enable for IOBN(0..1)_INT_SUM[PEM_SIE]. */
2850 #endif /* Word 0 - End */
2851 } cn88xxp2;
2852 };
2853 typedef union bdk_iobnx_int_ena_w1c bdk_iobnx_int_ena_w1c_t;
2854
2855 static inline uint64_t BDK_IOBNX_INT_ENA_W1C(unsigned long a) __attribute__ ((pure, always_inline));
BDK_IOBNX_INT_ENA_W1C(unsigned long a)2856 static inline uint64_t BDK_IOBNX_INT_ENA_W1C(unsigned long a)
2857 {
2858 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
2859 return 0x87e0f0008000ll + 0x1000000ll * ((a) & 0x0);
2860 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
2861 return 0x87e0f0008000ll + 0x1000000ll * ((a) & 0x1);
2862 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
2863 return 0x87e0f0008000ll + 0x1000000ll * ((a) & 0x1);
2864 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
2865 return 0x87e0f0008000ll + 0x1000000ll * ((a) & 0x1);
2866 __bdk_csr_fatal("IOBNX_INT_ENA_W1C", 1, a, 0, 0, 0);
2867 }
2868
2869 #define typedef_BDK_IOBNX_INT_ENA_W1C(a) bdk_iobnx_int_ena_w1c_t
2870 #define bustype_BDK_IOBNX_INT_ENA_W1C(a) BDK_CSR_TYPE_RSL
2871 #define basename_BDK_IOBNX_INT_ENA_W1C(a) "IOBNX_INT_ENA_W1C"
2872 #define device_bar_BDK_IOBNX_INT_ENA_W1C(a) 0x0 /* PF_BAR0 */
2873 #define busnum_BDK_IOBNX_INT_ENA_W1C(a) (a)
2874 #define arguments_BDK_IOBNX_INT_ENA_W1C(a) (a),-1,-1,-1
2875
2876 /**
2877 * Register (RSL) iobn#_int_ena_w1s
2878 *
2879 * IOBN Interrupt Enable Set Register
2880 * This register sets interrupt enable bits.
2881 */
2882 union bdk_iobnx_int_ena_w1s
2883 {
2884 uint64_t u;
2885 struct bdk_iobnx_int_ena_w1s_s
2886 {
2887 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2888 uint64_t pem_sie : 1; /**< [ 63: 63](R/W1S/H) Reads or sets enable for IOBN(0..1)_INT_SUM[PEM_SIE]. */
2889 uint64_t ied0_dbe : 31; /**< [ 62: 32](R/W1S/H) Reads or sets enable for IOBN(0..1)_INT_SUM[IED0_DBE].
2890 Internal:
2891 gmr_ixofifo_dbe_sclk,
2892 icc0_xmc_fif_dbe,
2893 icc1_xmc_fif_dbe,
2894 icc_xmc_fifo_ecc_dbe,
2895 sli_preq_0_dbe_sclk,
2896 sli_req_0_dbe_sclk,
2897 sli_preq_1_dbe_sclk,
2898 sli_req_1_dbe_sclk,
2899 sli_preq_2_dbe_sclk,
2900 sli_req_2_dbe_sclk,
2901 ixo_smmu_mem0_dbe_sclk,
2902 iop_breq_fifo0_dbe,
2903 iop_breq_fifo1_dbe ,
2904 iop_breq_fifo2_dbe,
2905 iop_breq_fifo3_dbe ,
2906 iop_ffifo_dbe_sclk,
2907 rsd_mem0_dbe,
2908 rsd_mem1_dbe,
2909 ics_cmd_fifo_dbe_sclk,
2910 ixo_xmd_mem1_dbe_sclk,
2911 ixo_xmd_mem0_dbe_sclk,
2912 iobn_iorn_ffifo0__dbe_sclk,
2913 iobn_iorn_ffifo1__dbe_sclk,
2914 irp1_flid_mem_dbe,
2915 irp0_flid_mem_dbe,
2916 ixo_icc_fifo0_dbe_in_sclk,
2917 ixo_icc_fifo1_dbe_in_sclk,
2918 ixo_ics_mem_dbe_in_sclk. */
2919 uint64_t reserved_0_31 : 32;
2920 #else /* Word 0 - Little Endian */
2921 uint64_t reserved_0_31 : 32;
2922 uint64_t ied0_dbe : 31; /**< [ 62: 32](R/W1S/H) Reads or sets enable for IOBN(0..1)_INT_SUM[IED0_DBE].
2923 Internal:
2924 gmr_ixofifo_dbe_sclk,
2925 icc0_xmc_fif_dbe,
2926 icc1_xmc_fif_dbe,
2927 icc_xmc_fifo_ecc_dbe,
2928 sli_preq_0_dbe_sclk,
2929 sli_req_0_dbe_sclk,
2930 sli_preq_1_dbe_sclk,
2931 sli_req_1_dbe_sclk,
2932 sli_preq_2_dbe_sclk,
2933 sli_req_2_dbe_sclk,
2934 ixo_smmu_mem0_dbe_sclk,
2935 iop_breq_fifo0_dbe,
2936 iop_breq_fifo1_dbe ,
2937 iop_breq_fifo2_dbe,
2938 iop_breq_fifo3_dbe ,
2939 iop_ffifo_dbe_sclk,
2940 rsd_mem0_dbe,
2941 rsd_mem1_dbe,
2942 ics_cmd_fifo_dbe_sclk,
2943 ixo_xmd_mem1_dbe_sclk,
2944 ixo_xmd_mem0_dbe_sclk,
2945 iobn_iorn_ffifo0__dbe_sclk,
2946 iobn_iorn_ffifo1__dbe_sclk,
2947 irp1_flid_mem_dbe,
2948 irp0_flid_mem_dbe,
2949 ixo_icc_fifo0_dbe_in_sclk,
2950 ixo_icc_fifo1_dbe_in_sclk,
2951 ixo_ics_mem_dbe_in_sclk. */
2952 uint64_t pem_sie : 1; /**< [ 63: 63](R/W1S/H) Reads or sets enable for IOBN(0..1)_INT_SUM[PEM_SIE]. */
2953 #endif /* Word 0 - End */
2954 } s;
2955 struct bdk_iobnx_int_ena_w1s_cn88xxp1
2956 {
2957 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2958 uint64_t reserved_60_63 : 4;
2959 uint64_t ied0_dbe : 28; /**< [ 59: 32](R/W1S/H) Reads or sets enable for IOBN(0..1)_INT_SUM[IED0_DBE].
2960 Internal:
2961 gmr_ixofifo_dbe_sclk,
2962 icc0_xmc_fif_dbe,
2963 icc1_xmc_fif_dbe,
2964 icc_xmc_fifo_ecc_dbe,
2965 sli_preq_0_dbe_sclk,
2966 sli_req_0_dbe_sclk,
2967 sli_preq_1_dbe_sclk,
2968 sli_req_1_dbe_sclk,
2969 sli_preq_2_dbe_sclk,
2970 sli_req_2_dbe_sclk,
2971 ixo_smmu_mem0_dbe_sclk,
2972 iop_breq_fifo0_dbe,
2973 iop_breq_fifo1_dbe ,
2974 iop_breq_fifo2_dbe,
2975 iop_breq_fifo3_dbe ,
2976 iop_ffifo_dbe_sclk,
2977 rsd_mem0_dbe,
2978 rsd_mem1_dbe,
2979 ics_cmd_fifo_dbe_sclk,
2980 ixo_xmd_mem1_dbe_sclk,
2981 ixo_xmd_mem0_dbe_sclk,
2982 iobn_iorn_ffifo0__dbe_sclk,
2983 iobn_iorn_ffifo1__dbe_sclk,
2984 irp1_flid_mem_dbe,
2985 irp0_flid_mem_dbe,
2986 ixo_icc_fifo0_dbe_in_sclk,
2987 ixo_icc_fifo1_dbe_in_sclk,
2988 ixo_ics_mem_dbe_in_sclk. */
2989 uint64_t reserved_28_31 : 4;
2990 uint64_t ied0_sbe : 28; /**< [ 27: 0](R/W1S/H) Reads or sets enable for IOBN(0..1)_INT_SUM[IED0_SBE].
2991 Internal:
2992 gmr_ixofifo_sbe_sclk,
2993 icc0_xmc_fif_sbe,
2994 icc1_xmc_fif_sbe,
2995 icc_xmc_fifo_ecc_sbe,
2996 sli_preq_0_sbe_sclk,
2997 sli_req_0_sbe_sclk,
2998 sli_preq_1_sbe_sclk,
2999 sli_req_1_sbe_sclk,
3000 sli_preq_2_sbe_sclk,
3001 sli_req_2_sbe_sclk,
3002 ixo_smmu_mem0_sbe_sclk,
3003 iop_breq_fifo0_sbe,
3004 iop_breq_fifo1_sbe ,
3005 iop_breq_fifo2_sbe,
3006 iop_breq_fifo3_sbe ,
3007 iop_ffifo_sbe_sclk,
3008 rsd_mem0_sbe,
3009 rsd_mem1_sbe,
3010 ics_cmd_fifo_sbe_sclk,
3011 ixo_xmd_mem1_sbe_sclk,
3012 ixo_xmd_mem0_sbe_sclk,
3013 iobn_iorn_ffifo0__sbe_sclk,
3014 iobn_iorn_ffifo1__sbe_sclk,
3015 irp1_flid_mem_sbe,
3016 irp0_flid_mem_sbe,
3017 ixo_icc_fifo0_sbe_in_sclk,
3018 ixo_icc_fifo1_sbe_in_sclk,
3019 ixo_ics_mem_sbe_in_sclk. */
3020 #else /* Word 0 - Little Endian */
3021 uint64_t ied0_sbe : 28; /**< [ 27: 0](R/W1S/H) Reads or sets enable for IOBN(0..1)_INT_SUM[IED0_SBE].
3022 Internal:
3023 gmr_ixofifo_sbe_sclk,
3024 icc0_xmc_fif_sbe,
3025 icc1_xmc_fif_sbe,
3026 icc_xmc_fifo_ecc_sbe,
3027 sli_preq_0_sbe_sclk,
3028 sli_req_0_sbe_sclk,
3029 sli_preq_1_sbe_sclk,
3030 sli_req_1_sbe_sclk,
3031 sli_preq_2_sbe_sclk,
3032 sli_req_2_sbe_sclk,
3033 ixo_smmu_mem0_sbe_sclk,
3034 iop_breq_fifo0_sbe,
3035 iop_breq_fifo1_sbe ,
3036 iop_breq_fifo2_sbe,
3037 iop_breq_fifo3_sbe ,
3038 iop_ffifo_sbe_sclk,
3039 rsd_mem0_sbe,
3040 rsd_mem1_sbe,
3041 ics_cmd_fifo_sbe_sclk,
3042 ixo_xmd_mem1_sbe_sclk,
3043 ixo_xmd_mem0_sbe_sclk,
3044 iobn_iorn_ffifo0__sbe_sclk,
3045 iobn_iorn_ffifo1__sbe_sclk,
3046 irp1_flid_mem_sbe,
3047 irp0_flid_mem_sbe,
3048 ixo_icc_fifo0_sbe_in_sclk,
3049 ixo_icc_fifo1_sbe_in_sclk,
3050 ixo_ics_mem_sbe_in_sclk. */
3051 uint64_t reserved_28_31 : 4;
3052 uint64_t ied0_dbe : 28; /**< [ 59: 32](R/W1S/H) Reads or sets enable for IOBN(0..1)_INT_SUM[IED0_DBE].
3053 Internal:
3054 gmr_ixofifo_dbe_sclk,
3055 icc0_xmc_fif_dbe,
3056 icc1_xmc_fif_dbe,
3057 icc_xmc_fifo_ecc_dbe,
3058 sli_preq_0_dbe_sclk,
3059 sli_req_0_dbe_sclk,
3060 sli_preq_1_dbe_sclk,
3061 sli_req_1_dbe_sclk,
3062 sli_preq_2_dbe_sclk,
3063 sli_req_2_dbe_sclk,
3064 ixo_smmu_mem0_dbe_sclk,
3065 iop_breq_fifo0_dbe,
3066 iop_breq_fifo1_dbe ,
3067 iop_breq_fifo2_dbe,
3068 iop_breq_fifo3_dbe ,
3069 iop_ffifo_dbe_sclk,
3070 rsd_mem0_dbe,
3071 rsd_mem1_dbe,
3072 ics_cmd_fifo_dbe_sclk,
3073 ixo_xmd_mem1_dbe_sclk,
3074 ixo_xmd_mem0_dbe_sclk,
3075 iobn_iorn_ffifo0__dbe_sclk,
3076 iobn_iorn_ffifo1__dbe_sclk,
3077 irp1_flid_mem_dbe,
3078 irp0_flid_mem_dbe,
3079 ixo_icc_fifo0_dbe_in_sclk,
3080 ixo_icc_fifo1_dbe_in_sclk,
3081 ixo_ics_mem_dbe_in_sclk. */
3082 uint64_t reserved_60_63 : 4;
3083 #endif /* Word 0 - End */
3084 } cn88xxp1;
3085 struct bdk_iobnx_int_ena_w1s_cn9
3086 {
3087 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3088 uint64_t reserved_4_63 : 60;
3089 uint64_t ncbo_ncb2_psn : 1; /**< [ 3: 3](R/W1S/H) Reads or sets enable for IOBN(0..1)_INT_SUM[NCBO_NCB2_PSN]. */
3090 uint64_t ncbo_ncb1_psn : 1; /**< [ 2: 2](R/W1S/H) Reads or sets enable for IOBN(0..1)_INT_SUM[NCBO_NCB1_PSN]. */
3091 uint64_t ncbo_ncb0_psn : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for IOBN(0..1)_INT_SUM[NCBO_NCB0_PSN]. */
3092 uint64_t ncbo_to : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for IOBN(0..1)_INT_SUM[NCBO_TO]. */
3093 #else /* Word 0 - Little Endian */
3094 uint64_t ncbo_to : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for IOBN(0..1)_INT_SUM[NCBO_TO]. */
3095 uint64_t ncbo_ncb0_psn : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for IOBN(0..1)_INT_SUM[NCBO_NCB0_PSN]. */
3096 uint64_t ncbo_ncb1_psn : 1; /**< [ 2: 2](R/W1S/H) Reads or sets enable for IOBN(0..1)_INT_SUM[NCBO_NCB1_PSN]. */
3097 uint64_t ncbo_ncb2_psn : 1; /**< [ 3: 3](R/W1S/H) Reads or sets enable for IOBN(0..1)_INT_SUM[NCBO_NCB2_PSN]. */
3098 uint64_t reserved_4_63 : 60;
3099 #endif /* Word 0 - End */
3100 } cn9;
3101 struct bdk_iobnx_int_ena_w1s_cn81xx
3102 {
3103 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3104 uint64_t pem_sie : 1; /**< [ 63: 63](R/W1S/H) Reads or sets enable for IOBN(0)_INT_SUM[PEM_SIE]. */
3105 uint64_t reserved_61_62 : 2;
3106 uint64_t ied0_dbe : 29; /**< [ 60: 32](R/W1S/H) Reads or sets enable for IOBN(0)_INT_SUM[IED0_DBE].
3107 Internal:
3108 iob_mem_data_xmd_sbe_sclk,
3109 gmr_ixofifo_dbe_sclk,
3110 icc0_xmc_fif_dbe,
3111 icc1_xmc_fif_dbe,
3112 icc_xmc_fifo_ecc_dbe,
3113 sli_preq_0_dbe_sclk,
3114 sli_req_0_dbe_sclk,
3115 sli_preq_1_dbe_sclk,
3116 sli_req_1_dbe_sclk,
3117 sli_preq_2_dbe_sclk,
3118 sli_req_2_dbe_sclk,
3119 ixo_smmu_mem0_dbe_sclk,
3120 iop_breq_fifo0_dbe,
3121 iop_breq_fifo1_dbe ,
3122 iop_breq_fifo2_dbe,
3123 iop_breq_fifo3_dbe ,
3124 iop_ffifo_dbe_sclk,
3125 rsd_mem0_dbe,
3126 rsd_mem1_dbe,
3127 ics_cmd_fifo_dbe_sclk,
3128 ixo_xmd_mem1_dbe_sclk,
3129 ixo_xmd_mem0_dbe_sclk,
3130 iobn_iorn_ffifo0__dbe_sclk,
3131 iobn_iorn_ffifo1__dbe_sclk,
3132 irp1_flid_mem_dbe,
3133 irp0_flid_mem_dbe,
3134 ixo_icc_fifo0_dbe_in_sclk,
3135 ixo_icc_fifo1_dbe_in_sclk,
3136 ixo_ics_mem_dbe_in_sclk. */
3137 uint64_t reserved_29_31 : 3;
3138 uint64_t ied0_sbe : 29; /**< [ 28: 0](R/W1S/H) Reads or sets enable for IOBN(0)_INT_SUM[IED0_SBE].
3139 Internal:
3140 iob_mem_data_xmd_sbe_sclk,
3141 gmr_ixofifo_sbe_sclk,
3142 icc0_xmc_fif_sbe,
3143 icc1_xmc_fif_sbe,
3144 icc_xmc_fifo_ecc_sbe,
3145 sli_preq_0_sbe_sclk,
3146 sli_req_0_sbe_sclk,
3147 sli_preq_1_sbe_sclk,
3148 sli_req_1_sbe_sclk,
3149 sli_preq_2_sbe_sclk,
3150 sli_req_2_sbe_sclk,
3151 ixo_smmu_mem0_sbe_sclk,
3152 iop_breq_fifo0_sbe,
3153 iop_breq_fifo1_sbe ,
3154 iop_breq_fifo2_sbe,
3155 iop_breq_fifo3_sbe ,
3156 iop_ffifo_sbe_sclk,
3157 rsd_mem0_sbe,
3158 rsd_mem1_sbe,
3159 ics_cmd_fifo_sbe_sclk,
3160 ixo_xmd_mem1_sbe_sclk,
3161 ixo_xmd_mem0_sbe_sclk,
3162 iobn_iorn_ffifo0__sbe_sclk,
3163 iobn_iorn_ffifo1__sbe_sclk,
3164 irp1_flid_mem_sbe,
3165 irp0_flid_mem_sbe,
3166 ixo_icc_fifo0_sbe_in_sclk,
3167 ixo_icc_fifo1_sbe_in_sclk,
3168 ixo_ics_mem_sbe_in_sclk. */
3169 #else /* Word 0 - Little Endian */
3170 uint64_t ied0_sbe : 29; /**< [ 28: 0](R/W1S/H) Reads or sets enable for IOBN(0)_INT_SUM[IED0_SBE].
3171 Internal:
3172 iob_mem_data_xmd_sbe_sclk,
3173 gmr_ixofifo_sbe_sclk,
3174 icc0_xmc_fif_sbe,
3175 icc1_xmc_fif_sbe,
3176 icc_xmc_fifo_ecc_sbe,
3177 sli_preq_0_sbe_sclk,
3178 sli_req_0_sbe_sclk,
3179 sli_preq_1_sbe_sclk,
3180 sli_req_1_sbe_sclk,
3181 sli_preq_2_sbe_sclk,
3182 sli_req_2_sbe_sclk,
3183 ixo_smmu_mem0_sbe_sclk,
3184 iop_breq_fifo0_sbe,
3185 iop_breq_fifo1_sbe ,
3186 iop_breq_fifo2_sbe,
3187 iop_breq_fifo3_sbe ,
3188 iop_ffifo_sbe_sclk,
3189 rsd_mem0_sbe,
3190 rsd_mem1_sbe,
3191 ics_cmd_fifo_sbe_sclk,
3192 ixo_xmd_mem1_sbe_sclk,
3193 ixo_xmd_mem0_sbe_sclk,
3194 iobn_iorn_ffifo0__sbe_sclk,
3195 iobn_iorn_ffifo1__sbe_sclk,
3196 irp1_flid_mem_sbe,
3197 irp0_flid_mem_sbe,
3198 ixo_icc_fifo0_sbe_in_sclk,
3199 ixo_icc_fifo1_sbe_in_sclk,
3200 ixo_ics_mem_sbe_in_sclk. */
3201 uint64_t reserved_29_31 : 3;
3202 uint64_t ied0_dbe : 29; /**< [ 60: 32](R/W1S/H) Reads or sets enable for IOBN(0)_INT_SUM[IED0_DBE].
3203 Internal:
3204 iob_mem_data_xmd_sbe_sclk,
3205 gmr_ixofifo_dbe_sclk,
3206 icc0_xmc_fif_dbe,
3207 icc1_xmc_fif_dbe,
3208 icc_xmc_fifo_ecc_dbe,
3209 sli_preq_0_dbe_sclk,
3210 sli_req_0_dbe_sclk,
3211 sli_preq_1_dbe_sclk,
3212 sli_req_1_dbe_sclk,
3213 sli_preq_2_dbe_sclk,
3214 sli_req_2_dbe_sclk,
3215 ixo_smmu_mem0_dbe_sclk,
3216 iop_breq_fifo0_dbe,
3217 iop_breq_fifo1_dbe ,
3218 iop_breq_fifo2_dbe,
3219 iop_breq_fifo3_dbe ,
3220 iop_ffifo_dbe_sclk,
3221 rsd_mem0_dbe,
3222 rsd_mem1_dbe,
3223 ics_cmd_fifo_dbe_sclk,
3224 ixo_xmd_mem1_dbe_sclk,
3225 ixo_xmd_mem0_dbe_sclk,
3226 iobn_iorn_ffifo0__dbe_sclk,
3227 iobn_iorn_ffifo1__dbe_sclk,
3228 irp1_flid_mem_dbe,
3229 irp0_flid_mem_dbe,
3230 ixo_icc_fifo0_dbe_in_sclk,
3231 ixo_icc_fifo1_dbe_in_sclk,
3232 ixo_ics_mem_dbe_in_sclk. */
3233 uint64_t reserved_61_62 : 2;
3234 uint64_t pem_sie : 1; /**< [ 63: 63](R/W1S/H) Reads or sets enable for IOBN(0)_INT_SUM[PEM_SIE]. */
3235 #endif /* Word 0 - End */
3236 } cn81xx;
3237 struct bdk_iobnx_int_ena_w1s_cn83xx
3238 {
3239 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3240 uint64_t pem_sie : 1; /**< [ 63: 63](R/W1S/H) Reads or sets enable for IOBN(0..1)_INT_SUM[PEM_SIE]. */
3241 uint64_t ied0_dbe : 31; /**< [ 62: 32](R/W1S/H) Reads or sets enable for IOBN(0..1)_INT_SUM[IED0_DBE].
3242 Internal:
3243 iob_mem_data_xmd_sbe_sclk,
3244 gmr_ixofifo_dbe_sclk,
3245 icc0_xmc_fif_dbe,
3246 icc1_xmc_fif_dbe,
3247 icc_xmc_fifo_ecc_dbe,
3248 sli_preq_0_dbe_sclk,
3249 sli_req_0_dbe_sclk,
3250 sli_preq_1_dbe_sclk,
3251 sli_req_1_dbe_sclk,
3252 sli_preq_2_dbe_sclk,
3253 sli_req_2_dbe_sclk,
3254 sli_preq_3_dbe_sclk,
3255 sli_req_3_dbe_sclk,
3256 ixo_smmu_mem0_dbe_sclk,
3257 iop_breq_fifo0_dbe,
3258 iop_breq_fifo1_dbe ,
3259 iop_breq_fifo2_dbe,
3260 iop_breq_fifo3_dbe ,
3261 iop_ffifo_dbe_sclk,
3262 rsd_mem0_dbe,
3263 rsd_mem1_dbe,
3264 ics_cmd_fifo_dbe_sclk,
3265 ixo_xmd_mem1_dbe_sclk,
3266 ixo_xmd_mem0_dbe_sclk,
3267 iobn_iorn_ffifo0__dbe_sclk,
3268 iobn_iorn_ffifo1__dbe_sclk,
3269 irp1_flid_mem_dbe,
3270 irp0_flid_mem_dbe,
3271 ixo_icc_fifo0_dbe_in_sclk,
3272 ixo_icc_fifo1_dbe_in_sclk,
3273 ixo_ics_mem_dbe_in_sclk. */
3274 uint64_t reserved_31 : 1;
3275 uint64_t ied0_sbe : 31; /**< [ 30: 0](R/W1S/H) Reads or sets enable for IOBN(0..1)_INT_SUM[IED0_SBE].
3276 Internal:
3277 iob_mem_data_xmd_sbe_sclk,
3278 gmr_ixofifo_sbe_sclk,
3279 icc0_xmc_fif_sbe,
3280 icc1_xmc_fif_sbe,
3281 icc_xmc_fifo_ecc_sbe,
3282 sli_preq_0_sbe_sclk,
3283 sli_req_0_sbe_sclk,
3284 sli_preq_1_sbe_sclk,
3285 sli_req_1_sbe_sclk,
3286 sli_preq_2_sbe_sclk,
3287 sli_req_2_sbe_sclk,
3288 sli_preq_3_sbe_sclk,
3289 sli_req_3_sbe_sclk,
3290 ixo_smmu_mem0_sbe_sclk,
3291 iop_breq_fifo0_sbe,
3292 iop_breq_fifo1_sbe ,
3293 iop_breq_fifo2_sbe,
3294 iop_breq_fifo3_sbe ,
3295 iop_ffifo_sbe_sclk,
3296 rsd_mem0_sbe,
3297 rsd_mem1_sbe,
3298 ics_cmd_fifo_sbe_sclk,
3299 ixo_xmd_mem1_sbe_sclk,
3300 ixo_xmd_mem0_sbe_sclk,
3301 iobn_iorn_ffifo0__sbe_sclk,
3302 iobn_iorn_ffifo1__sbe_sclk,
3303 irp1_flid_mem_sbe,
3304 irp0_flid_mem_sbe,
3305 ixo_icc_fifo0_sbe_in_sclk,
3306 ixo_icc_fifo1_sbe_in_sclk,
3307 ixo_ics_mem_sbe_in_sclk. */
3308 #else /* Word 0 - Little Endian */
3309 uint64_t ied0_sbe : 31; /**< [ 30: 0](R/W1S/H) Reads or sets enable for IOBN(0..1)_INT_SUM[IED0_SBE].
3310 Internal:
3311 iob_mem_data_xmd_sbe_sclk,
3312 gmr_ixofifo_sbe_sclk,
3313 icc0_xmc_fif_sbe,
3314 icc1_xmc_fif_sbe,
3315 icc_xmc_fifo_ecc_sbe,
3316 sli_preq_0_sbe_sclk,
3317 sli_req_0_sbe_sclk,
3318 sli_preq_1_sbe_sclk,
3319 sli_req_1_sbe_sclk,
3320 sli_preq_2_sbe_sclk,
3321 sli_req_2_sbe_sclk,
3322 sli_preq_3_sbe_sclk,
3323 sli_req_3_sbe_sclk,
3324 ixo_smmu_mem0_sbe_sclk,
3325 iop_breq_fifo0_sbe,
3326 iop_breq_fifo1_sbe ,
3327 iop_breq_fifo2_sbe,
3328 iop_breq_fifo3_sbe ,
3329 iop_ffifo_sbe_sclk,
3330 rsd_mem0_sbe,
3331 rsd_mem1_sbe,
3332 ics_cmd_fifo_sbe_sclk,
3333 ixo_xmd_mem1_sbe_sclk,
3334 ixo_xmd_mem0_sbe_sclk,
3335 iobn_iorn_ffifo0__sbe_sclk,
3336 iobn_iorn_ffifo1__sbe_sclk,
3337 irp1_flid_mem_sbe,
3338 irp0_flid_mem_sbe,
3339 ixo_icc_fifo0_sbe_in_sclk,
3340 ixo_icc_fifo1_sbe_in_sclk,
3341 ixo_ics_mem_sbe_in_sclk. */
3342 uint64_t reserved_31 : 1;
3343 uint64_t ied0_dbe : 31; /**< [ 62: 32](R/W1S/H) Reads or sets enable for IOBN(0..1)_INT_SUM[IED0_DBE].
3344 Internal:
3345 iob_mem_data_xmd_sbe_sclk,
3346 gmr_ixofifo_dbe_sclk,
3347 icc0_xmc_fif_dbe,
3348 icc1_xmc_fif_dbe,
3349 icc_xmc_fifo_ecc_dbe,
3350 sli_preq_0_dbe_sclk,
3351 sli_req_0_dbe_sclk,
3352 sli_preq_1_dbe_sclk,
3353 sli_req_1_dbe_sclk,
3354 sli_preq_2_dbe_sclk,
3355 sli_req_2_dbe_sclk,
3356 sli_preq_3_dbe_sclk,
3357 sli_req_3_dbe_sclk,
3358 ixo_smmu_mem0_dbe_sclk,
3359 iop_breq_fifo0_dbe,
3360 iop_breq_fifo1_dbe ,
3361 iop_breq_fifo2_dbe,
3362 iop_breq_fifo3_dbe ,
3363 iop_ffifo_dbe_sclk,
3364 rsd_mem0_dbe,
3365 rsd_mem1_dbe,
3366 ics_cmd_fifo_dbe_sclk,
3367 ixo_xmd_mem1_dbe_sclk,
3368 ixo_xmd_mem0_dbe_sclk,
3369 iobn_iorn_ffifo0__dbe_sclk,
3370 iobn_iorn_ffifo1__dbe_sclk,
3371 irp1_flid_mem_dbe,
3372 irp0_flid_mem_dbe,
3373 ixo_icc_fifo0_dbe_in_sclk,
3374 ixo_icc_fifo1_dbe_in_sclk,
3375 ixo_ics_mem_dbe_in_sclk. */
3376 uint64_t pem_sie : 1; /**< [ 63: 63](R/W1S/H) Reads or sets enable for IOBN(0..1)_INT_SUM[PEM_SIE]. */
3377 #endif /* Word 0 - End */
3378 } cn83xx;
3379 struct bdk_iobnx_int_ena_w1s_cn88xxp2
3380 {
3381 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3382 uint64_t pem_sie : 1; /**< [ 63: 63](R/W1S/H) Reads or sets enable for IOBN(0..1)_INT_SUM[PEM_SIE]. */
3383 uint64_t reserved_61_62 : 2;
3384 uint64_t ied0_dbe : 29; /**< [ 60: 32](R/W1S/H) Reads or sets enable for IOBN(0..1)_INT_SUM[IED0_DBE].
3385 Internal:
3386 iob_mem_data_xmd_sbe_sclk,
3387 gmr_ixofifo_dbe_sclk,
3388 icc0_xmc_fif_dbe,
3389 icc1_xmc_fif_dbe,
3390 icc_xmc_fifo_ecc_dbe,
3391 sli_preq_0_dbe_sclk,
3392 sli_req_0_dbe_sclk,
3393 sli_preq_1_dbe_sclk,
3394 sli_req_1_dbe_sclk,
3395 sli_preq_2_dbe_sclk,
3396 sli_req_2_dbe_sclk,
3397 ixo_smmu_mem0_dbe_sclk,
3398 iop_breq_fifo0_dbe,
3399 iop_breq_fifo1_dbe ,
3400 iop_breq_fifo2_dbe,
3401 iop_breq_fifo3_dbe ,
3402 iop_ffifo_dbe_sclk,
3403 rsd_mem0_dbe,
3404 rsd_mem1_dbe,
3405 ics_cmd_fifo_dbe_sclk,
3406 ixo_xmd_mem1_dbe_sclk,
3407 ixo_xmd_mem0_dbe_sclk,
3408 iobn_iorn_ffifo0__dbe_sclk,
3409 iobn_iorn_ffifo1__dbe_sclk,
3410 irp1_flid_mem_dbe,
3411 irp0_flid_mem_dbe,
3412 ixo_icc_fifo0_dbe_in_sclk,
3413 ixo_icc_fifo1_dbe_in_sclk,
3414 ixo_ics_mem_dbe_in_sclk. */
3415 uint64_t reserved_29_31 : 3;
3416 uint64_t ied0_sbe : 29; /**< [ 28: 0](R/W1S/H) Reads or sets enable for IOBN(0..1)_INT_SUM[IED0_SBE].
3417 Internal:
3418 iob_mem_data_xmd_sbe_sclk,
3419 gmr_ixofifo_sbe_sclk,
3420 icc0_xmc_fif_sbe,
3421 icc1_xmc_fif_sbe,
3422 icc_xmc_fifo_ecc_sbe,
3423 sli_preq_0_sbe_sclk,
3424 sli_req_0_sbe_sclk,
3425 sli_preq_1_sbe_sclk,
3426 sli_req_1_sbe_sclk,
3427 sli_preq_2_sbe_sclk,
3428 sli_req_2_sbe_sclk,
3429 ixo_smmu_mem0_sbe_sclk,
3430 iop_breq_fifo0_sbe,
3431 iop_breq_fifo1_sbe ,
3432 iop_breq_fifo2_sbe,
3433 iop_breq_fifo3_sbe ,
3434 iop_ffifo_sbe_sclk,
3435 rsd_mem0_sbe,
3436 rsd_mem1_sbe,
3437 ics_cmd_fifo_sbe_sclk,
3438 ixo_xmd_mem1_sbe_sclk,
3439 ixo_xmd_mem0_sbe_sclk,
3440 iobn_iorn_ffifo0__sbe_sclk,
3441 iobn_iorn_ffifo1__sbe_sclk,
3442 irp1_flid_mem_sbe,
3443 irp0_flid_mem_sbe,
3444 ixo_icc_fifo0_sbe_in_sclk,
3445 ixo_icc_fifo1_sbe_in_sclk,
3446 ixo_ics_mem_sbe_in_sclk. */
3447 #else /* Word 0 - Little Endian */
3448 uint64_t ied0_sbe : 29; /**< [ 28: 0](R/W1S/H) Reads or sets enable for IOBN(0..1)_INT_SUM[IED0_SBE].
3449 Internal:
3450 iob_mem_data_xmd_sbe_sclk,
3451 gmr_ixofifo_sbe_sclk,
3452 icc0_xmc_fif_sbe,
3453 icc1_xmc_fif_sbe,
3454 icc_xmc_fifo_ecc_sbe,
3455 sli_preq_0_sbe_sclk,
3456 sli_req_0_sbe_sclk,
3457 sli_preq_1_sbe_sclk,
3458 sli_req_1_sbe_sclk,
3459 sli_preq_2_sbe_sclk,
3460 sli_req_2_sbe_sclk,
3461 ixo_smmu_mem0_sbe_sclk,
3462 iop_breq_fifo0_sbe,
3463 iop_breq_fifo1_sbe ,
3464 iop_breq_fifo2_sbe,
3465 iop_breq_fifo3_sbe ,
3466 iop_ffifo_sbe_sclk,
3467 rsd_mem0_sbe,
3468 rsd_mem1_sbe,
3469 ics_cmd_fifo_sbe_sclk,
3470 ixo_xmd_mem1_sbe_sclk,
3471 ixo_xmd_mem0_sbe_sclk,
3472 iobn_iorn_ffifo0__sbe_sclk,
3473 iobn_iorn_ffifo1__sbe_sclk,
3474 irp1_flid_mem_sbe,
3475 irp0_flid_mem_sbe,
3476 ixo_icc_fifo0_sbe_in_sclk,
3477 ixo_icc_fifo1_sbe_in_sclk,
3478 ixo_ics_mem_sbe_in_sclk. */
3479 uint64_t reserved_29_31 : 3;
3480 uint64_t ied0_dbe : 29; /**< [ 60: 32](R/W1S/H) Reads or sets enable for IOBN(0..1)_INT_SUM[IED0_DBE].
3481 Internal:
3482 iob_mem_data_xmd_sbe_sclk,
3483 gmr_ixofifo_dbe_sclk,
3484 icc0_xmc_fif_dbe,
3485 icc1_xmc_fif_dbe,
3486 icc_xmc_fifo_ecc_dbe,
3487 sli_preq_0_dbe_sclk,
3488 sli_req_0_dbe_sclk,
3489 sli_preq_1_dbe_sclk,
3490 sli_req_1_dbe_sclk,
3491 sli_preq_2_dbe_sclk,
3492 sli_req_2_dbe_sclk,
3493 ixo_smmu_mem0_dbe_sclk,
3494 iop_breq_fifo0_dbe,
3495 iop_breq_fifo1_dbe ,
3496 iop_breq_fifo2_dbe,
3497 iop_breq_fifo3_dbe ,
3498 iop_ffifo_dbe_sclk,
3499 rsd_mem0_dbe,
3500 rsd_mem1_dbe,
3501 ics_cmd_fifo_dbe_sclk,
3502 ixo_xmd_mem1_dbe_sclk,
3503 ixo_xmd_mem0_dbe_sclk,
3504 iobn_iorn_ffifo0__dbe_sclk,
3505 iobn_iorn_ffifo1__dbe_sclk,
3506 irp1_flid_mem_dbe,
3507 irp0_flid_mem_dbe,
3508 ixo_icc_fifo0_dbe_in_sclk,
3509 ixo_icc_fifo1_dbe_in_sclk,
3510 ixo_ics_mem_dbe_in_sclk. */
3511 uint64_t reserved_61_62 : 2;
3512 uint64_t pem_sie : 1; /**< [ 63: 63](R/W1S/H) Reads or sets enable for IOBN(0..1)_INT_SUM[PEM_SIE]. */
3513 #endif /* Word 0 - End */
3514 } cn88xxp2;
3515 };
3516 typedef union bdk_iobnx_int_ena_w1s bdk_iobnx_int_ena_w1s_t;
3517
3518 static inline uint64_t BDK_IOBNX_INT_ENA_W1S(unsigned long a) __attribute__ ((pure, always_inline));
BDK_IOBNX_INT_ENA_W1S(unsigned long a)3519 static inline uint64_t BDK_IOBNX_INT_ENA_W1S(unsigned long a)
3520 {
3521 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
3522 return 0x87e0f0009000ll + 0x1000000ll * ((a) & 0x0);
3523 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
3524 return 0x87e0f0009000ll + 0x1000000ll * ((a) & 0x1);
3525 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
3526 return 0x87e0f0009000ll + 0x1000000ll * ((a) & 0x1);
3527 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
3528 return 0x87e0f0009000ll + 0x1000000ll * ((a) & 0x1);
3529 __bdk_csr_fatal("IOBNX_INT_ENA_W1S", 1, a, 0, 0, 0);
3530 }
3531
3532 #define typedef_BDK_IOBNX_INT_ENA_W1S(a) bdk_iobnx_int_ena_w1s_t
3533 #define bustype_BDK_IOBNX_INT_ENA_W1S(a) BDK_CSR_TYPE_RSL
3534 #define basename_BDK_IOBNX_INT_ENA_W1S(a) "IOBNX_INT_ENA_W1S"
3535 #define device_bar_BDK_IOBNX_INT_ENA_W1S(a) 0x0 /* PF_BAR0 */
3536 #define busnum_BDK_IOBNX_INT_ENA_W1S(a) (a)
3537 #define arguments_BDK_IOBNX_INT_ENA_W1S(a) (a),-1,-1,-1
3538
3539 /**
3540 * Register (RSL) iobn#_int_sum
3541 *
3542 * IOBN Interrupt Summary Register
3543 * This register contains the different interrupt-summary bits of the IOBN.
3544 */
3545 union bdk_iobnx_int_sum
3546 {
3547 uint64_t u;
3548 struct bdk_iobnx_int_sum_s
3549 {
3550 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3551 uint64_t pem_sie : 1; /**< [ 63: 63](R/W1C/H) PEM sent in an invalid stream ID, the transaction was returned with fault. Advisory
3552 notification only. */
3553 uint64_t ied0_dbe : 31; /**< [ 62: 32](R/W1C/H) IED0 double-bit error. When set, an IED0 double-bit error has occurred.
3554 Internal:
3555 gmr_ixofifo_dbe_sclk,
3556 icc0_xmc_fif_dbe,
3557 icc1_xmc_fif_dbe,
3558 icc_xmc_fifo_ecc_dbe,
3559 sli_preq_0_dbe_sclk,
3560 sli_req_0_dbe_sclk,
3561 sli_preq_1_dbe_sclk,
3562 sli_req_1_dbe_sclk,
3563 sli_preq_2_dbe_sclk,
3564 sli_req_2_dbe_sclk,
3565 ixo_smmu_mem0_dbe_sclk,
3566 iop_breq_fifo0_dbe,
3567 iop_breq_fifo1_dbe ,
3568 iop_breq_fifo2_dbe,
3569 iop_breq_fifo3_dbe ,
3570 iop_ffifo_dbe_sclk,
3571 rsd_mem0_dbe,
3572 rsd_mem1_dbe,
3573 ics_cmd_fifo_dbe_sclk,
3574 ixo_xmd_mem1_dbe_sclk,
3575 ixo_xmd_mem0_dbe_sclk,
3576 iobn_iorn_ffifo0__dbe_sclk,
3577 iobn_iorn_ffifo1__dbe_sclk,
3578 irp1_flid_mem_dbe,
3579 irp0_flid_mem_dbe,
3580 ixo_icc_fifo0_dbe_in_sclk,
3581 ixo_icc_fifo1_dbe_in_sclk,
3582 ixo_ics_mem_dbe_in_sclk. */
3583 uint64_t reserved_0_31 : 32;
3584 #else /* Word 0 - Little Endian */
3585 uint64_t reserved_0_31 : 32;
3586 uint64_t ied0_dbe : 31; /**< [ 62: 32](R/W1C/H) IED0 double-bit error. When set, an IED0 double-bit error has occurred.
3587 Internal:
3588 gmr_ixofifo_dbe_sclk,
3589 icc0_xmc_fif_dbe,
3590 icc1_xmc_fif_dbe,
3591 icc_xmc_fifo_ecc_dbe,
3592 sli_preq_0_dbe_sclk,
3593 sli_req_0_dbe_sclk,
3594 sli_preq_1_dbe_sclk,
3595 sli_req_1_dbe_sclk,
3596 sli_preq_2_dbe_sclk,
3597 sli_req_2_dbe_sclk,
3598 ixo_smmu_mem0_dbe_sclk,
3599 iop_breq_fifo0_dbe,
3600 iop_breq_fifo1_dbe ,
3601 iop_breq_fifo2_dbe,
3602 iop_breq_fifo3_dbe ,
3603 iop_ffifo_dbe_sclk,
3604 rsd_mem0_dbe,
3605 rsd_mem1_dbe,
3606 ics_cmd_fifo_dbe_sclk,
3607 ixo_xmd_mem1_dbe_sclk,
3608 ixo_xmd_mem0_dbe_sclk,
3609 iobn_iorn_ffifo0__dbe_sclk,
3610 iobn_iorn_ffifo1__dbe_sclk,
3611 irp1_flid_mem_dbe,
3612 irp0_flid_mem_dbe,
3613 ixo_icc_fifo0_dbe_in_sclk,
3614 ixo_icc_fifo1_dbe_in_sclk,
3615 ixo_ics_mem_dbe_in_sclk. */
3616 uint64_t pem_sie : 1; /**< [ 63: 63](R/W1C/H) PEM sent in an invalid stream ID, the transaction was returned with fault. Advisory
3617 notification only. */
3618 #endif /* Word 0 - End */
3619 } s;
3620 struct bdk_iobnx_int_sum_cn88xxp1
3621 {
3622 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3623 uint64_t reserved_60_63 : 4;
3624 uint64_t ied0_dbe : 28; /**< [ 59: 32](R/W1C/H) IED0 double-bit error. When set, an IED0 double-bit error has occurred.
3625 Internal:
3626 gmr_ixofifo_dbe_sclk,
3627 icc0_xmc_fif_dbe,
3628 icc1_xmc_fif_dbe,
3629 icc_xmc_fifo_ecc_dbe,
3630 sli_preq_0_dbe_sclk,
3631 sli_req_0_dbe_sclk,
3632 sli_preq_1_dbe_sclk,
3633 sli_req_1_dbe_sclk,
3634 sli_preq_2_dbe_sclk,
3635 sli_req_2_dbe_sclk,
3636 ixo_smmu_mem0_dbe_sclk,
3637 iop_breq_fifo0_dbe,
3638 iop_breq_fifo1_dbe ,
3639 iop_breq_fifo2_dbe,
3640 iop_breq_fifo3_dbe ,
3641 iop_ffifo_dbe_sclk,
3642 rsd_mem0_dbe,
3643 rsd_mem1_dbe,
3644 ics_cmd_fifo_dbe_sclk,
3645 ixo_xmd_mem1_dbe_sclk,
3646 ixo_xmd_mem0_dbe_sclk,
3647 iobn_iorn_ffifo0__dbe_sclk,
3648 iobn_iorn_ffifo1__dbe_sclk,
3649 irp1_flid_mem_dbe,
3650 irp0_flid_mem_dbe,
3651 ixo_icc_fifo0_dbe_in_sclk,
3652 ixo_icc_fifo1_dbe_in_sclk,
3653 ixo_ics_mem_dbe_in_sclk. */
3654 uint64_t reserved_28_31 : 4;
3655 uint64_t ied0_sbe : 28; /**< [ 27: 0](R/W1C/H) IED0 single-bit error. When set, an IED0 single-bit error has occurred.
3656 Internal:
3657 gmr_ixofifo_sbe_sclk,
3658 icc0_xmc_fif_sbe,
3659 icc1_xmc_fif_sbe,
3660 icc_xmc_fifo_ecc_sbe,
3661 sli_preq_0_sbe_sclk,
3662 sli_req_0_sbe_sclk,
3663 sli_preq_1_sbe_sclk,
3664 sli_req_1_sbe_sclk,
3665 sli_preq_2_sbe_sclk,
3666 sli_req_2_sbe_sclk,
3667 ixo_smmu_mem0_sbe_sclk,
3668 iop_breq_fifo0_sbe,
3669 iop_breq_fifo1_sbe ,
3670 iop_breq_fifo2_sbe,
3671 iop_breq_fifo3_sbe ,
3672 iop_ffifo_sbe_sclk,
3673 rsd_mem0_sbe,
3674 rsd_mem1_sbe,
3675 ics_cmd_fifo_sbe_sclk,
3676 ixo_xmd_mem1_sbe_sclk,
3677 ixo_xmd_mem0_sbe_sclk,
3678 iobn_iorn_ffifo0__sbe_sclk,
3679 iobn_iorn_ffifo1__sbe_sclk,
3680 irp1_flid_mem_sbe,
3681 irp0_flid_mem_sbe,
3682 ixo_icc_fifo0_sbe_in_sclk,
3683 ixo_icc_fifo1_sbe_in_sclk,
3684 ixo_ics_mem_sbe_in_sclk. */
3685 #else /* Word 0 - Little Endian */
3686 uint64_t ied0_sbe : 28; /**< [ 27: 0](R/W1C/H) IED0 single-bit error. When set, an IED0 single-bit error has occurred.
3687 Internal:
3688 gmr_ixofifo_sbe_sclk,
3689 icc0_xmc_fif_sbe,
3690 icc1_xmc_fif_sbe,
3691 icc_xmc_fifo_ecc_sbe,
3692 sli_preq_0_sbe_sclk,
3693 sli_req_0_sbe_sclk,
3694 sli_preq_1_sbe_sclk,
3695 sli_req_1_sbe_sclk,
3696 sli_preq_2_sbe_sclk,
3697 sli_req_2_sbe_sclk,
3698 ixo_smmu_mem0_sbe_sclk,
3699 iop_breq_fifo0_sbe,
3700 iop_breq_fifo1_sbe ,
3701 iop_breq_fifo2_sbe,
3702 iop_breq_fifo3_sbe ,
3703 iop_ffifo_sbe_sclk,
3704 rsd_mem0_sbe,
3705 rsd_mem1_sbe,
3706 ics_cmd_fifo_sbe_sclk,
3707 ixo_xmd_mem1_sbe_sclk,
3708 ixo_xmd_mem0_sbe_sclk,
3709 iobn_iorn_ffifo0__sbe_sclk,
3710 iobn_iorn_ffifo1__sbe_sclk,
3711 irp1_flid_mem_sbe,
3712 irp0_flid_mem_sbe,
3713 ixo_icc_fifo0_sbe_in_sclk,
3714 ixo_icc_fifo1_sbe_in_sclk,
3715 ixo_ics_mem_sbe_in_sclk. */
3716 uint64_t reserved_28_31 : 4;
3717 uint64_t ied0_dbe : 28; /**< [ 59: 32](R/W1C/H) IED0 double-bit error. When set, an IED0 double-bit error has occurred.
3718 Internal:
3719 gmr_ixofifo_dbe_sclk,
3720 icc0_xmc_fif_dbe,
3721 icc1_xmc_fif_dbe,
3722 icc_xmc_fifo_ecc_dbe,
3723 sli_preq_0_dbe_sclk,
3724 sli_req_0_dbe_sclk,
3725 sli_preq_1_dbe_sclk,
3726 sli_req_1_dbe_sclk,
3727 sli_preq_2_dbe_sclk,
3728 sli_req_2_dbe_sclk,
3729 ixo_smmu_mem0_dbe_sclk,
3730 iop_breq_fifo0_dbe,
3731 iop_breq_fifo1_dbe ,
3732 iop_breq_fifo2_dbe,
3733 iop_breq_fifo3_dbe ,
3734 iop_ffifo_dbe_sclk,
3735 rsd_mem0_dbe,
3736 rsd_mem1_dbe,
3737 ics_cmd_fifo_dbe_sclk,
3738 ixo_xmd_mem1_dbe_sclk,
3739 ixo_xmd_mem0_dbe_sclk,
3740 iobn_iorn_ffifo0__dbe_sclk,
3741 iobn_iorn_ffifo1__dbe_sclk,
3742 irp1_flid_mem_dbe,
3743 irp0_flid_mem_dbe,
3744 ixo_icc_fifo0_dbe_in_sclk,
3745 ixo_icc_fifo1_dbe_in_sclk,
3746 ixo_ics_mem_dbe_in_sclk. */
3747 uint64_t reserved_60_63 : 4;
3748 #endif /* Word 0 - End */
3749 } cn88xxp1;
3750 struct bdk_iobnx_int_sum_cn9
3751 {
3752 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3753 uint64_t reserved_4_63 : 60;
3754 uint64_t ncbo_ncb2_psn : 1; /**< [ 3: 3](R/W1C/H) NCBO bus2 store data with poison. IOBN()_NCBO()_PSN_STATUS saves the first error information. */
3755 uint64_t ncbo_ncb1_psn : 1; /**< [ 2: 2](R/W1C/H) NCB1 bus0 store data with poison. IOBN()_NCBO()_PSN_STATUS saves the first error information. */
3756 uint64_t ncbo_ncb0_psn : 1; /**< [ 1: 1](R/W1C/H) NCBO bus0 store data with poison. IOBN()_NCBO()_PSN_STATUS saves the first error information. */
3757 uint64_t ncbo_to : 1; /**< [ 0: 0](R/W1C/H) NPR to a NCB-DEVICE has timed out. See IOBN()_NCBO_TO[SUB_TIME]. */
3758 #else /* Word 0 - Little Endian */
3759 uint64_t ncbo_to : 1; /**< [ 0: 0](R/W1C/H) NPR to a NCB-DEVICE has timed out. See IOBN()_NCBO_TO[SUB_TIME]. */
3760 uint64_t ncbo_ncb0_psn : 1; /**< [ 1: 1](R/W1C/H) NCBO bus0 store data with poison. IOBN()_NCBO()_PSN_STATUS saves the first error information. */
3761 uint64_t ncbo_ncb1_psn : 1; /**< [ 2: 2](R/W1C/H) NCB1 bus0 store data with poison. IOBN()_NCBO()_PSN_STATUS saves the first error information. */
3762 uint64_t ncbo_ncb2_psn : 1; /**< [ 3: 3](R/W1C/H) NCBO bus2 store data with poison. IOBN()_NCBO()_PSN_STATUS saves the first error information. */
3763 uint64_t reserved_4_63 : 60;
3764 #endif /* Word 0 - End */
3765 } cn9;
3766 struct bdk_iobnx_int_sum_cn81xx
3767 {
3768 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3769 uint64_t pem_sie : 1; /**< [ 63: 63](R/W1C/H) PEM sent in an invalid stream ID, the transaction was returned with fault. Advisory
3770 notification only. */
3771 uint64_t reserved_61_62 : 2;
3772 uint64_t ied0_dbe : 29; /**< [ 60: 32](R/W1C/H) IED0 double-bit error. When set, an IED0 double-bit error has occurred.
3773 Internal:
3774 iob_mem_data_xmd_sbe_sclk,
3775 gmr_ixofifo_dbe_sclk,
3776 icc0_xmc_fif_dbe,
3777 icc1_xmc_fif_dbe,
3778 icc_xmc_fifo_ecc_dbe,
3779 sli_preq_0_dbe_sclk,
3780 sli_req_0_dbe_sclk,
3781 sli_preq_1_dbe_sclk,
3782 sli_req_1_dbe_sclk,
3783 sli_preq_2_dbe_sclk,
3784 sli_req_2_dbe_sclk,
3785 ixo_smmu_mem0_dbe_sclk,
3786 iop_breq_fifo0_dbe,
3787 iop_breq_fifo1_dbe ,
3788 iop_breq_fifo2_dbe,
3789 iop_breq_fifo3_dbe ,
3790 iop_ffifo_dbe_sclk,
3791 rsd_mem0_dbe,
3792 rsd_mem1_dbe,
3793 ics_cmd_fifo_dbe_sclk,
3794 ixo_xmd_mem1_dbe_sclk,
3795 ixo_xmd_mem0_dbe_sclk,
3796 iobn_iorn_ffifo0__dbe_sclk,
3797 iobn_iorn_ffifo1__dbe_sclk,
3798 irp1_flid_mem_dbe,
3799 irp0_flid_mem_dbe,
3800 ixo_icc_fifo0_dbe_in_sclk,
3801 ixo_icc_fifo1_dbe_in_sclk,
3802 ixo_ics_mem_dbe_in_sclk. */
3803 uint64_t reserved_29_31 : 3;
3804 uint64_t ied0_sbe : 29; /**< [ 28: 0](R/W1C/H) IED0 single-bit error. When set, an IED0 single-bit error has occurred.
3805 Internal:
3806 iob_mem_data_xmd_sbe_sclk,
3807 gmr_ixofifo_sbe_sclk,
3808 icc0_xmc_fif_sbe,
3809 icc1_xmc_fif_sbe,
3810 icc_xmc_fifo_ecc_sbe,
3811 sli_preq_0_sbe_sclk,
3812 sli_req_0_sbe_sclk,
3813 sli_preq_1_sbe_sclk,
3814 sli_req_1_sbe_sclk,
3815 sli_preq_2_sbe_sclk,
3816 sli_req_2_sbe_sclk,
3817 ixo_smmu_mem0_sbe_sclk,
3818 iop_breq_fifo0_sbe,
3819 iop_breq_fifo1_sbe ,
3820 iop_breq_fifo2_sbe,
3821 iop_breq_fifo3_sbe ,
3822 iop_ffifo_sbe_sclk,
3823 rsd_mem0_sbe,
3824 rsd_mem1_sbe,
3825 ics_cmd_fifo_sbe_sclk,
3826 ixo_xmd_mem1_sbe_sclk,
3827 ixo_xmd_mem0_sbe_sclk,
3828 iobn_iorn_ffifo0__sbe_sclk,
3829 iobn_iorn_ffifo1__sbe_sclk,
3830 irp1_flid_mem_sbe,
3831 irp0_flid_mem_sbe,
3832 ixo_icc_fifo0_sbe_in_sclk,
3833 ixo_icc_fifo1_sbe_in_sclk,
3834 ixo_ics_mem_sbe_in_sclk. */
3835 #else /* Word 0 - Little Endian */
3836 uint64_t ied0_sbe : 29; /**< [ 28: 0](R/W1C/H) IED0 single-bit error. When set, an IED0 single-bit error has occurred.
3837 Internal:
3838 iob_mem_data_xmd_sbe_sclk,
3839 gmr_ixofifo_sbe_sclk,
3840 icc0_xmc_fif_sbe,
3841 icc1_xmc_fif_sbe,
3842 icc_xmc_fifo_ecc_sbe,
3843 sli_preq_0_sbe_sclk,
3844 sli_req_0_sbe_sclk,
3845 sli_preq_1_sbe_sclk,
3846 sli_req_1_sbe_sclk,
3847 sli_preq_2_sbe_sclk,
3848 sli_req_2_sbe_sclk,
3849 ixo_smmu_mem0_sbe_sclk,
3850 iop_breq_fifo0_sbe,
3851 iop_breq_fifo1_sbe ,
3852 iop_breq_fifo2_sbe,
3853 iop_breq_fifo3_sbe ,
3854 iop_ffifo_sbe_sclk,
3855 rsd_mem0_sbe,
3856 rsd_mem1_sbe,
3857 ics_cmd_fifo_sbe_sclk,
3858 ixo_xmd_mem1_sbe_sclk,
3859 ixo_xmd_mem0_sbe_sclk,
3860 iobn_iorn_ffifo0__sbe_sclk,
3861 iobn_iorn_ffifo1__sbe_sclk,
3862 irp1_flid_mem_sbe,
3863 irp0_flid_mem_sbe,
3864 ixo_icc_fifo0_sbe_in_sclk,
3865 ixo_icc_fifo1_sbe_in_sclk,
3866 ixo_ics_mem_sbe_in_sclk. */
3867 uint64_t reserved_29_31 : 3;
3868 uint64_t ied0_dbe : 29; /**< [ 60: 32](R/W1C/H) IED0 double-bit error. When set, an IED0 double-bit error has occurred.
3869 Internal:
3870 iob_mem_data_xmd_sbe_sclk,
3871 gmr_ixofifo_dbe_sclk,
3872 icc0_xmc_fif_dbe,
3873 icc1_xmc_fif_dbe,
3874 icc_xmc_fifo_ecc_dbe,
3875 sli_preq_0_dbe_sclk,
3876 sli_req_0_dbe_sclk,
3877 sli_preq_1_dbe_sclk,
3878 sli_req_1_dbe_sclk,
3879 sli_preq_2_dbe_sclk,
3880 sli_req_2_dbe_sclk,
3881 ixo_smmu_mem0_dbe_sclk,
3882 iop_breq_fifo0_dbe,
3883 iop_breq_fifo1_dbe ,
3884 iop_breq_fifo2_dbe,
3885 iop_breq_fifo3_dbe ,
3886 iop_ffifo_dbe_sclk,
3887 rsd_mem0_dbe,
3888 rsd_mem1_dbe,
3889 ics_cmd_fifo_dbe_sclk,
3890 ixo_xmd_mem1_dbe_sclk,
3891 ixo_xmd_mem0_dbe_sclk,
3892 iobn_iorn_ffifo0__dbe_sclk,
3893 iobn_iorn_ffifo1__dbe_sclk,
3894 irp1_flid_mem_dbe,
3895 irp0_flid_mem_dbe,
3896 ixo_icc_fifo0_dbe_in_sclk,
3897 ixo_icc_fifo1_dbe_in_sclk,
3898 ixo_ics_mem_dbe_in_sclk. */
3899 uint64_t reserved_61_62 : 2;
3900 uint64_t pem_sie : 1; /**< [ 63: 63](R/W1C/H) PEM sent in an invalid stream ID, the transaction was returned with fault. Advisory
3901 notification only. */
3902 #endif /* Word 0 - End */
3903 } cn81xx;
3904 struct bdk_iobnx_int_sum_cn83xx
3905 {
3906 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3907 uint64_t pem_sie : 1; /**< [ 63: 63](R/W1C/H) PEM sent in an invalid stream ID, the transaction was returned with fault. Advisory
3908 notification only. */
3909 uint64_t ied0_dbe : 31; /**< [ 62: 32](R/W1C/H) IED0 double-bit error. When set, an IED0 double-bit error has occurred.
3910 Internal:
3911 iob_mem_data_xmd_sbe_sclk,
3912 gmr_ixofifo_dbe_sclk,
3913 icc0_xmc_fif_dbe,
3914 icc1_xmc_fif_dbe,
3915 icc_xmc_fifo_ecc_dbe,
3916 sli_preq_0_dbe_sclk,
3917 sli_req_0_dbe_sclk,
3918 sli_preq_1_dbe_sclk,
3919 sli_req_1_dbe_sclk,
3920 sli_preq_2_dbe_sclk,
3921 sli_req_2_dbe_sclk,
3922 sli_preq_3_dbe_sclk,
3923 sli_req_3_dbe_sclk,
3924 ixo_smmu_mem0_dbe_sclk,
3925 iop_breq_fifo0_dbe,
3926 iop_breq_fifo1_dbe ,
3927 iop_breq_fifo2_dbe,
3928 iop_breq_fifo3_dbe ,
3929 iop_ffifo_dbe_sclk,
3930 rsd_mem0_dbe,
3931 rsd_mem1_dbe,
3932 ics_cmd_fifo_dbe_sclk,
3933 ixo_xmd_mem1_dbe_sclk,
3934 ixo_xmd_mem0_dbe_sclk,
3935 iobn_iorn_ffifo0__dbe_sclk,
3936 iobn_iorn_ffifo1__dbe_sclk,
3937 irp1_flid_mem_dbe,
3938 irp0_flid_mem_dbe,
3939 ixo_icc_fifo0_dbe_in_sclk,
3940 ixo_icc_fifo1_dbe_in_sclk,
3941 ixo_ics_mem_dbe_in_sclk. */
3942 uint64_t reserved_31 : 1;
3943 uint64_t ied0_sbe : 31; /**< [ 30: 0](R/W1C/H) IED0 single-bit error. When set, an IED0 single-bit error has occurred.
3944 Internal:
3945 iob_mem_data_xmd_sbe_sclk,
3946 gmr_ixofifo_sbe_sclk,
3947 icc0_xmc_fif_sbe,
3948 icc1_xmc_fif_sbe,
3949 icc_xmc_fifo_ecc_sbe,
3950 sli_preq_0_sbe_sclk,
3951 sli_req_0_sbe_sclk,
3952 sli_preq_1_sbe_sclk,
3953 sli_req_1_sbe_sclk,
3954 sli_preq_2_sbe_sclk,
3955 sli_req_2_sbe_sclk,
3956 sli_preq_3_sbe_sclk,
3957 sli_req_3_sbe_sclk,
3958 ixo_smmu_mem0_sbe_sclk,
3959 iop_breq_fifo0_sbe,
3960 iop_breq_fifo1_sbe ,
3961 iop_breq_fifo2_sbe,
3962 iop_breq_fifo3_sbe ,
3963 iop_ffifo_sbe_sclk,
3964 rsd_mem0_sbe,
3965 rsd_mem1_sbe,
3966 ics_cmd_fifo_sbe_sclk,
3967 ixo_xmd_mem1_sbe_sclk,
3968 ixo_xmd_mem0_sbe_sclk,
3969 iobn_iorn_ffifo0__sbe_sclk,
3970 iobn_iorn_ffifo1__sbe_sclk,
3971 irp1_flid_mem_sbe,
3972 irp0_flid_mem_sbe,
3973 ixo_icc_fifo0_sbe_in_sclk,
3974 ixo_icc_fifo1_sbe_in_sclk,
3975 ixo_ics_mem_sbe_in_sclk. */
3976 #else /* Word 0 - Little Endian */
3977 uint64_t ied0_sbe : 31; /**< [ 30: 0](R/W1C/H) IED0 single-bit error. When set, an IED0 single-bit error has occurred.
3978 Internal:
3979 iob_mem_data_xmd_sbe_sclk,
3980 gmr_ixofifo_sbe_sclk,
3981 icc0_xmc_fif_sbe,
3982 icc1_xmc_fif_sbe,
3983 icc_xmc_fifo_ecc_sbe,
3984 sli_preq_0_sbe_sclk,
3985 sli_req_0_sbe_sclk,
3986 sli_preq_1_sbe_sclk,
3987 sli_req_1_sbe_sclk,
3988 sli_preq_2_sbe_sclk,
3989 sli_req_2_sbe_sclk,
3990 sli_preq_3_sbe_sclk,
3991 sli_req_3_sbe_sclk,
3992 ixo_smmu_mem0_sbe_sclk,
3993 iop_breq_fifo0_sbe,
3994 iop_breq_fifo1_sbe ,
3995 iop_breq_fifo2_sbe,
3996 iop_breq_fifo3_sbe ,
3997 iop_ffifo_sbe_sclk,
3998 rsd_mem0_sbe,
3999 rsd_mem1_sbe,
4000 ics_cmd_fifo_sbe_sclk,
4001 ixo_xmd_mem1_sbe_sclk,
4002 ixo_xmd_mem0_sbe_sclk,
4003 iobn_iorn_ffifo0__sbe_sclk,
4004 iobn_iorn_ffifo1__sbe_sclk,
4005 irp1_flid_mem_sbe,
4006 irp0_flid_mem_sbe,
4007 ixo_icc_fifo0_sbe_in_sclk,
4008 ixo_icc_fifo1_sbe_in_sclk,
4009 ixo_ics_mem_sbe_in_sclk. */
4010 uint64_t reserved_31 : 1;
4011 uint64_t ied0_dbe : 31; /**< [ 62: 32](R/W1C/H) IED0 double-bit error. When set, an IED0 double-bit error has occurred.
4012 Internal:
4013 iob_mem_data_xmd_sbe_sclk,
4014 gmr_ixofifo_dbe_sclk,
4015 icc0_xmc_fif_dbe,
4016 icc1_xmc_fif_dbe,
4017 icc_xmc_fifo_ecc_dbe,
4018 sli_preq_0_dbe_sclk,
4019 sli_req_0_dbe_sclk,
4020 sli_preq_1_dbe_sclk,
4021 sli_req_1_dbe_sclk,
4022 sli_preq_2_dbe_sclk,
4023 sli_req_2_dbe_sclk,
4024 sli_preq_3_dbe_sclk,
4025 sli_req_3_dbe_sclk,
4026 ixo_smmu_mem0_dbe_sclk,
4027 iop_breq_fifo0_dbe,
4028 iop_breq_fifo1_dbe ,
4029 iop_breq_fifo2_dbe,
4030 iop_breq_fifo3_dbe ,
4031 iop_ffifo_dbe_sclk,
4032 rsd_mem0_dbe,
4033 rsd_mem1_dbe,
4034 ics_cmd_fifo_dbe_sclk,
4035 ixo_xmd_mem1_dbe_sclk,
4036 ixo_xmd_mem0_dbe_sclk,
4037 iobn_iorn_ffifo0__dbe_sclk,
4038 iobn_iorn_ffifo1__dbe_sclk,
4039 irp1_flid_mem_dbe,
4040 irp0_flid_mem_dbe,
4041 ixo_icc_fifo0_dbe_in_sclk,
4042 ixo_icc_fifo1_dbe_in_sclk,
4043 ixo_ics_mem_dbe_in_sclk. */
4044 uint64_t pem_sie : 1; /**< [ 63: 63](R/W1C/H) PEM sent in an invalid stream ID, the transaction was returned with fault. Advisory
4045 notification only. */
4046 #endif /* Word 0 - End */
4047 } cn83xx;
4048 struct bdk_iobnx_int_sum_cn88xxp2
4049 {
4050 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4051 uint64_t pem_sie : 1; /**< [ 63: 63](R/W1C/H) PEM sent in an invalid stream ID. */
4052 uint64_t reserved_61_62 : 2;
4053 uint64_t ied0_dbe : 29; /**< [ 60: 32](R/W1C/H) IED0 double-bit error. When set, an IED0 double-bit error has occurred.
4054 Internal:
4055 iob_mem_data_xmd_sbe_sclk,
4056 gmr_ixofifo_dbe_sclk,
4057 icc0_xmc_fif_dbe,
4058 icc1_xmc_fif_dbe,
4059 icc_xmc_fifo_ecc_dbe,
4060 sli_preq_0_dbe_sclk,
4061 sli_req_0_dbe_sclk,
4062 sli_preq_1_dbe_sclk,
4063 sli_req_1_dbe_sclk,
4064 sli_preq_2_dbe_sclk,
4065 sli_req_2_dbe_sclk,
4066 ixo_smmu_mem0_dbe_sclk,
4067 iop_breq_fifo0_dbe,
4068 iop_breq_fifo1_dbe ,
4069 iop_breq_fifo2_dbe,
4070 iop_breq_fifo3_dbe ,
4071 iop_ffifo_dbe_sclk,
4072 rsd_mem0_dbe,
4073 rsd_mem1_dbe,
4074 ics_cmd_fifo_dbe_sclk,
4075 ixo_xmd_mem1_dbe_sclk,
4076 ixo_xmd_mem0_dbe_sclk,
4077 iobn_iorn_ffifo0__dbe_sclk,
4078 iobn_iorn_ffifo1__dbe_sclk,
4079 irp1_flid_mem_dbe,
4080 irp0_flid_mem_dbe,
4081 ixo_icc_fifo0_dbe_in_sclk,
4082 ixo_icc_fifo1_dbe_in_sclk,
4083 ixo_ics_mem_dbe_in_sclk. */
4084 uint64_t reserved_29_31 : 3;
4085 uint64_t ied0_sbe : 29; /**< [ 28: 0](R/W1C/H) IED0 single-bit error. When set, an IED0 single-bit error has occurred.
4086 Internal:
4087 iob_mem_data_xmd_sbe_sclk,
4088 gmr_ixofifo_sbe_sclk,
4089 icc0_xmc_fif_sbe,
4090 icc1_xmc_fif_sbe,
4091 icc_xmc_fifo_ecc_sbe,
4092 sli_preq_0_sbe_sclk,
4093 sli_req_0_sbe_sclk,
4094 sli_preq_1_sbe_sclk,
4095 sli_req_1_sbe_sclk,
4096 sli_preq_2_sbe_sclk,
4097 sli_req_2_sbe_sclk,
4098 ixo_smmu_mem0_sbe_sclk,
4099 iop_breq_fifo0_sbe,
4100 iop_breq_fifo1_sbe ,
4101 iop_breq_fifo2_sbe,
4102 iop_breq_fifo3_sbe ,
4103 iop_ffifo_sbe_sclk,
4104 rsd_mem0_sbe,
4105 rsd_mem1_sbe,
4106 ics_cmd_fifo_sbe_sclk,
4107 ixo_xmd_mem1_sbe_sclk,
4108 ixo_xmd_mem0_sbe_sclk,
4109 iobn_iorn_ffifo0__sbe_sclk,
4110 iobn_iorn_ffifo1__sbe_sclk,
4111 irp1_flid_mem_sbe,
4112 irp0_flid_mem_sbe,
4113 ixo_icc_fifo0_sbe_in_sclk,
4114 ixo_icc_fifo1_sbe_in_sclk,
4115 ixo_ics_mem_sbe_in_sclk. */
4116 #else /* Word 0 - Little Endian */
4117 uint64_t ied0_sbe : 29; /**< [ 28: 0](R/W1C/H) IED0 single-bit error. When set, an IED0 single-bit error has occurred.
4118 Internal:
4119 iob_mem_data_xmd_sbe_sclk,
4120 gmr_ixofifo_sbe_sclk,
4121 icc0_xmc_fif_sbe,
4122 icc1_xmc_fif_sbe,
4123 icc_xmc_fifo_ecc_sbe,
4124 sli_preq_0_sbe_sclk,
4125 sli_req_0_sbe_sclk,
4126 sli_preq_1_sbe_sclk,
4127 sli_req_1_sbe_sclk,
4128 sli_preq_2_sbe_sclk,
4129 sli_req_2_sbe_sclk,
4130 ixo_smmu_mem0_sbe_sclk,
4131 iop_breq_fifo0_sbe,
4132 iop_breq_fifo1_sbe ,
4133 iop_breq_fifo2_sbe,
4134 iop_breq_fifo3_sbe ,
4135 iop_ffifo_sbe_sclk,
4136 rsd_mem0_sbe,
4137 rsd_mem1_sbe,
4138 ics_cmd_fifo_sbe_sclk,
4139 ixo_xmd_mem1_sbe_sclk,
4140 ixo_xmd_mem0_sbe_sclk,
4141 iobn_iorn_ffifo0__sbe_sclk,
4142 iobn_iorn_ffifo1__sbe_sclk,
4143 irp1_flid_mem_sbe,
4144 irp0_flid_mem_sbe,
4145 ixo_icc_fifo0_sbe_in_sclk,
4146 ixo_icc_fifo1_sbe_in_sclk,
4147 ixo_ics_mem_sbe_in_sclk. */
4148 uint64_t reserved_29_31 : 3;
4149 uint64_t ied0_dbe : 29; /**< [ 60: 32](R/W1C/H) IED0 double-bit error. When set, an IED0 double-bit error has occurred.
4150 Internal:
4151 iob_mem_data_xmd_sbe_sclk,
4152 gmr_ixofifo_dbe_sclk,
4153 icc0_xmc_fif_dbe,
4154 icc1_xmc_fif_dbe,
4155 icc_xmc_fifo_ecc_dbe,
4156 sli_preq_0_dbe_sclk,
4157 sli_req_0_dbe_sclk,
4158 sli_preq_1_dbe_sclk,
4159 sli_req_1_dbe_sclk,
4160 sli_preq_2_dbe_sclk,
4161 sli_req_2_dbe_sclk,
4162 ixo_smmu_mem0_dbe_sclk,
4163 iop_breq_fifo0_dbe,
4164 iop_breq_fifo1_dbe ,
4165 iop_breq_fifo2_dbe,
4166 iop_breq_fifo3_dbe ,
4167 iop_ffifo_dbe_sclk,
4168 rsd_mem0_dbe,
4169 rsd_mem1_dbe,
4170 ics_cmd_fifo_dbe_sclk,
4171 ixo_xmd_mem1_dbe_sclk,
4172 ixo_xmd_mem0_dbe_sclk,
4173 iobn_iorn_ffifo0__dbe_sclk,
4174 iobn_iorn_ffifo1__dbe_sclk,
4175 irp1_flid_mem_dbe,
4176 irp0_flid_mem_dbe,
4177 ixo_icc_fifo0_dbe_in_sclk,
4178 ixo_icc_fifo1_dbe_in_sclk,
4179 ixo_ics_mem_dbe_in_sclk. */
4180 uint64_t reserved_61_62 : 2;
4181 uint64_t pem_sie : 1; /**< [ 63: 63](R/W1C/H) PEM sent in an invalid stream ID. */
4182 #endif /* Word 0 - End */
4183 } cn88xxp2;
4184 };
4185 typedef union bdk_iobnx_int_sum bdk_iobnx_int_sum_t;
4186
4187 static inline uint64_t BDK_IOBNX_INT_SUM(unsigned long a) __attribute__ ((pure, always_inline));
BDK_IOBNX_INT_SUM(unsigned long a)4188 static inline uint64_t BDK_IOBNX_INT_SUM(unsigned long a)
4189 {
4190 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
4191 return 0x87e0f0006000ll + 0x1000000ll * ((a) & 0x0);
4192 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
4193 return 0x87e0f0006000ll + 0x1000000ll * ((a) & 0x1);
4194 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
4195 return 0x87e0f0006000ll + 0x1000000ll * ((a) & 0x1);
4196 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
4197 return 0x87e0f0006000ll + 0x1000000ll * ((a) & 0x1);
4198 __bdk_csr_fatal("IOBNX_INT_SUM", 1, a, 0, 0, 0);
4199 }
4200
4201 #define typedef_BDK_IOBNX_INT_SUM(a) bdk_iobnx_int_sum_t
4202 #define bustype_BDK_IOBNX_INT_SUM(a) BDK_CSR_TYPE_RSL
4203 #define basename_BDK_IOBNX_INT_SUM(a) "IOBNX_INT_SUM"
4204 #define device_bar_BDK_IOBNX_INT_SUM(a) 0x0 /* PF_BAR0 */
4205 #define busnum_BDK_IOBNX_INT_SUM(a) (a)
4206 #define arguments_BDK_IOBNX_INT_SUM(a) (a),-1,-1,-1
4207
4208 /**
4209 * Register (RSL) iobn#_int_sum_w1s
4210 *
4211 * IOBN Interrupt Set Register
4212 * This register sets interrupt bits.
4213 */
4214 union bdk_iobnx_int_sum_w1s
4215 {
4216 uint64_t u;
4217 struct bdk_iobnx_int_sum_w1s_s
4218 {
4219 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4220 uint64_t pem_sie : 1; /**< [ 63: 63](R/W1S/H) Reads or sets IOBN(0..1)_INT_SUM[PEM_SIE]. */
4221 uint64_t ied0_dbe : 31; /**< [ 62: 32](R/W1S/H) Reads or sets IOBN(0..1)_INT_SUM[IED0_DBE].
4222 Internal:
4223 gmr_ixofifo_dbe_sclk,
4224 icc0_xmc_fif_dbe,
4225 icc1_xmc_fif_dbe,
4226 icc_xmc_fifo_ecc_dbe,
4227 sli_preq_0_dbe_sclk,
4228 sli_req_0_dbe_sclk,
4229 sli_preq_1_dbe_sclk,
4230 sli_req_1_dbe_sclk,
4231 sli_preq_2_dbe_sclk,
4232 sli_req_2_dbe_sclk,
4233 ixo_smmu_mem0_dbe_sclk,
4234 iop_breq_fifo0_dbe,
4235 iop_breq_fifo1_dbe ,
4236 iop_breq_fifo2_dbe,
4237 iop_breq_fifo3_dbe ,
4238 iop_ffifo_dbe_sclk,
4239 rsd_mem0_dbe,
4240 rsd_mem1_dbe,
4241 ics_cmd_fifo_dbe_sclk,
4242 ixo_xmd_mem1_dbe_sclk,
4243 ixo_xmd_mem0_dbe_sclk,
4244 iobn_iorn_ffifo0__dbe_sclk,
4245 iobn_iorn_ffifo1__dbe_sclk,
4246 irp1_flid_mem_dbe,
4247 irp0_flid_mem_dbe,
4248 ixo_icc_fifo0_dbe_in_sclk,
4249 ixo_icc_fifo1_dbe_in_sclk,
4250 ixo_ics_mem_dbe_in_sclk. */
4251 uint64_t reserved_0_31 : 32;
4252 #else /* Word 0 - Little Endian */
4253 uint64_t reserved_0_31 : 32;
4254 uint64_t ied0_dbe : 31; /**< [ 62: 32](R/W1S/H) Reads or sets IOBN(0..1)_INT_SUM[IED0_DBE].
4255 Internal:
4256 gmr_ixofifo_dbe_sclk,
4257 icc0_xmc_fif_dbe,
4258 icc1_xmc_fif_dbe,
4259 icc_xmc_fifo_ecc_dbe,
4260 sli_preq_0_dbe_sclk,
4261 sli_req_0_dbe_sclk,
4262 sli_preq_1_dbe_sclk,
4263 sli_req_1_dbe_sclk,
4264 sli_preq_2_dbe_sclk,
4265 sli_req_2_dbe_sclk,
4266 ixo_smmu_mem0_dbe_sclk,
4267 iop_breq_fifo0_dbe,
4268 iop_breq_fifo1_dbe ,
4269 iop_breq_fifo2_dbe,
4270 iop_breq_fifo3_dbe ,
4271 iop_ffifo_dbe_sclk,
4272 rsd_mem0_dbe,
4273 rsd_mem1_dbe,
4274 ics_cmd_fifo_dbe_sclk,
4275 ixo_xmd_mem1_dbe_sclk,
4276 ixo_xmd_mem0_dbe_sclk,
4277 iobn_iorn_ffifo0__dbe_sclk,
4278 iobn_iorn_ffifo1__dbe_sclk,
4279 irp1_flid_mem_dbe,
4280 irp0_flid_mem_dbe,
4281 ixo_icc_fifo0_dbe_in_sclk,
4282 ixo_icc_fifo1_dbe_in_sclk,
4283 ixo_ics_mem_dbe_in_sclk. */
4284 uint64_t pem_sie : 1; /**< [ 63: 63](R/W1S/H) Reads or sets IOBN(0..1)_INT_SUM[PEM_SIE]. */
4285 #endif /* Word 0 - End */
4286 } s;
4287 struct bdk_iobnx_int_sum_w1s_cn88xxp1
4288 {
4289 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4290 uint64_t reserved_60_63 : 4;
4291 uint64_t ied0_dbe : 28; /**< [ 59: 32](R/W1S/H) Reads or sets IOBN(0..1)_INT_SUM[IED0_DBE].
4292 Internal:
4293 gmr_ixofifo_dbe_sclk,
4294 icc0_xmc_fif_dbe,
4295 icc1_xmc_fif_dbe,
4296 icc_xmc_fifo_ecc_dbe,
4297 sli_preq_0_dbe_sclk,
4298 sli_req_0_dbe_sclk,
4299 sli_preq_1_dbe_sclk,
4300 sli_req_1_dbe_sclk,
4301 sli_preq_2_dbe_sclk,
4302 sli_req_2_dbe_sclk,
4303 ixo_smmu_mem0_dbe_sclk,
4304 iop_breq_fifo0_dbe,
4305 iop_breq_fifo1_dbe ,
4306 iop_breq_fifo2_dbe,
4307 iop_breq_fifo3_dbe ,
4308 iop_ffifo_dbe_sclk,
4309 rsd_mem0_dbe,
4310 rsd_mem1_dbe,
4311 ics_cmd_fifo_dbe_sclk,
4312 ixo_xmd_mem1_dbe_sclk,
4313 ixo_xmd_mem0_dbe_sclk,
4314 iobn_iorn_ffifo0__dbe_sclk,
4315 iobn_iorn_ffifo1__dbe_sclk,
4316 irp1_flid_mem_dbe,
4317 irp0_flid_mem_dbe,
4318 ixo_icc_fifo0_dbe_in_sclk,
4319 ixo_icc_fifo1_dbe_in_sclk,
4320 ixo_ics_mem_dbe_in_sclk. */
4321 uint64_t reserved_28_31 : 4;
4322 uint64_t ied0_sbe : 28; /**< [ 27: 0](R/W1S/H) Reads or sets IOBN(0..1)_INT_SUM[IED0_SBE].
4323 Internal:
4324 gmr_ixofifo_sbe_sclk,
4325 icc0_xmc_fif_sbe,
4326 icc1_xmc_fif_sbe,
4327 icc_xmc_fifo_ecc_sbe,
4328 sli_preq_0_sbe_sclk,
4329 sli_req_0_sbe_sclk,
4330 sli_preq_1_sbe_sclk,
4331 sli_req_1_sbe_sclk,
4332 sli_preq_2_sbe_sclk,
4333 sli_req_2_sbe_sclk,
4334 ixo_smmu_mem0_sbe_sclk,
4335 iop_breq_fifo0_sbe,
4336 iop_breq_fifo1_sbe ,
4337 iop_breq_fifo2_sbe,
4338 iop_breq_fifo3_sbe ,
4339 iop_ffifo_sbe_sclk,
4340 rsd_mem0_sbe,
4341 rsd_mem1_sbe,
4342 ics_cmd_fifo_sbe_sclk,
4343 ixo_xmd_mem1_sbe_sclk,
4344 ixo_xmd_mem0_sbe_sclk,
4345 iobn_iorn_ffifo0__sbe_sclk,
4346 iobn_iorn_ffifo1__sbe_sclk,
4347 irp1_flid_mem_sbe,
4348 irp0_flid_mem_sbe,
4349 ixo_icc_fifo0_sbe_in_sclk,
4350 ixo_icc_fifo1_sbe_in_sclk,
4351 ixo_ics_mem_sbe_in_sclk. */
4352 #else /* Word 0 - Little Endian */
4353 uint64_t ied0_sbe : 28; /**< [ 27: 0](R/W1S/H) Reads or sets IOBN(0..1)_INT_SUM[IED0_SBE].
4354 Internal:
4355 gmr_ixofifo_sbe_sclk,
4356 icc0_xmc_fif_sbe,
4357 icc1_xmc_fif_sbe,
4358 icc_xmc_fifo_ecc_sbe,
4359 sli_preq_0_sbe_sclk,
4360 sli_req_0_sbe_sclk,
4361 sli_preq_1_sbe_sclk,
4362 sli_req_1_sbe_sclk,
4363 sli_preq_2_sbe_sclk,
4364 sli_req_2_sbe_sclk,
4365 ixo_smmu_mem0_sbe_sclk,
4366 iop_breq_fifo0_sbe,
4367 iop_breq_fifo1_sbe ,
4368 iop_breq_fifo2_sbe,
4369 iop_breq_fifo3_sbe ,
4370 iop_ffifo_sbe_sclk,
4371 rsd_mem0_sbe,
4372 rsd_mem1_sbe,
4373 ics_cmd_fifo_sbe_sclk,
4374 ixo_xmd_mem1_sbe_sclk,
4375 ixo_xmd_mem0_sbe_sclk,
4376 iobn_iorn_ffifo0__sbe_sclk,
4377 iobn_iorn_ffifo1__sbe_sclk,
4378 irp1_flid_mem_sbe,
4379 irp0_flid_mem_sbe,
4380 ixo_icc_fifo0_sbe_in_sclk,
4381 ixo_icc_fifo1_sbe_in_sclk,
4382 ixo_ics_mem_sbe_in_sclk. */
4383 uint64_t reserved_28_31 : 4;
4384 uint64_t ied0_dbe : 28; /**< [ 59: 32](R/W1S/H) Reads or sets IOBN(0..1)_INT_SUM[IED0_DBE].
4385 Internal:
4386 gmr_ixofifo_dbe_sclk,
4387 icc0_xmc_fif_dbe,
4388 icc1_xmc_fif_dbe,
4389 icc_xmc_fifo_ecc_dbe,
4390 sli_preq_0_dbe_sclk,
4391 sli_req_0_dbe_sclk,
4392 sli_preq_1_dbe_sclk,
4393 sli_req_1_dbe_sclk,
4394 sli_preq_2_dbe_sclk,
4395 sli_req_2_dbe_sclk,
4396 ixo_smmu_mem0_dbe_sclk,
4397 iop_breq_fifo0_dbe,
4398 iop_breq_fifo1_dbe ,
4399 iop_breq_fifo2_dbe,
4400 iop_breq_fifo3_dbe ,
4401 iop_ffifo_dbe_sclk,
4402 rsd_mem0_dbe,
4403 rsd_mem1_dbe,
4404 ics_cmd_fifo_dbe_sclk,
4405 ixo_xmd_mem1_dbe_sclk,
4406 ixo_xmd_mem0_dbe_sclk,
4407 iobn_iorn_ffifo0__dbe_sclk,
4408 iobn_iorn_ffifo1__dbe_sclk,
4409 irp1_flid_mem_dbe,
4410 irp0_flid_mem_dbe,
4411 ixo_icc_fifo0_dbe_in_sclk,
4412 ixo_icc_fifo1_dbe_in_sclk,
4413 ixo_ics_mem_dbe_in_sclk. */
4414 uint64_t reserved_60_63 : 4;
4415 #endif /* Word 0 - End */
4416 } cn88xxp1;
4417 struct bdk_iobnx_int_sum_w1s_cn9
4418 {
4419 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4420 uint64_t reserved_4_63 : 60;
4421 uint64_t ncbo_ncb2_psn : 1; /**< [ 3: 3](R/W1S/H) Reads or sets IOBN(0..1)_INT_SUM[NCBO_NCB2_PSN]. */
4422 uint64_t ncbo_ncb1_psn : 1; /**< [ 2: 2](R/W1S/H) Reads or sets IOBN(0..1)_INT_SUM[NCBO_NCB1_PSN]. */
4423 uint64_t ncbo_ncb0_psn : 1; /**< [ 1: 1](R/W1S/H) Reads or sets IOBN(0..1)_INT_SUM[NCBO_NCB0_PSN]. */
4424 uint64_t ncbo_to : 1; /**< [ 0: 0](R/W1S/H) Reads or sets IOBN(0..1)_INT_SUM[NCBO_TO]. */
4425 #else /* Word 0 - Little Endian */
4426 uint64_t ncbo_to : 1; /**< [ 0: 0](R/W1S/H) Reads or sets IOBN(0..1)_INT_SUM[NCBO_TO]. */
4427 uint64_t ncbo_ncb0_psn : 1; /**< [ 1: 1](R/W1S/H) Reads or sets IOBN(0..1)_INT_SUM[NCBO_NCB0_PSN]. */
4428 uint64_t ncbo_ncb1_psn : 1; /**< [ 2: 2](R/W1S/H) Reads or sets IOBN(0..1)_INT_SUM[NCBO_NCB1_PSN]. */
4429 uint64_t ncbo_ncb2_psn : 1; /**< [ 3: 3](R/W1S/H) Reads or sets IOBN(0..1)_INT_SUM[NCBO_NCB2_PSN]. */
4430 uint64_t reserved_4_63 : 60;
4431 #endif /* Word 0 - End */
4432 } cn9;
4433 struct bdk_iobnx_int_sum_w1s_cn81xx
4434 {
4435 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4436 uint64_t pem_sie : 1; /**< [ 63: 63](R/W1S/H) Reads or sets IOBN(0)_INT_SUM[PEM_SIE]. */
4437 uint64_t reserved_61_62 : 2;
4438 uint64_t ied0_dbe : 29; /**< [ 60: 32](R/W1S/H) Reads or sets IOBN(0)_INT_SUM[IED0_DBE].
4439 Internal:
4440 iob_mem_data_xmd_sbe_sclk,
4441 gmr_ixofifo_dbe_sclk,
4442 icc0_xmc_fif_dbe,
4443 icc1_xmc_fif_dbe,
4444 icc_xmc_fifo_ecc_dbe,
4445 sli_preq_0_dbe_sclk,
4446 sli_req_0_dbe_sclk,
4447 sli_preq_1_dbe_sclk,
4448 sli_req_1_dbe_sclk,
4449 sli_preq_2_dbe_sclk,
4450 sli_req_2_dbe_sclk,
4451 ixo_smmu_mem0_dbe_sclk,
4452 iop_breq_fifo0_dbe,
4453 iop_breq_fifo1_dbe ,
4454 iop_breq_fifo2_dbe,
4455 iop_breq_fifo3_dbe ,
4456 iop_ffifo_dbe_sclk,
4457 rsd_mem0_dbe,
4458 rsd_mem1_dbe,
4459 ics_cmd_fifo_dbe_sclk,
4460 ixo_xmd_mem1_dbe_sclk,
4461 ixo_xmd_mem0_dbe_sclk,
4462 iobn_iorn_ffifo0__dbe_sclk,
4463 iobn_iorn_ffifo1__dbe_sclk,
4464 irp1_flid_mem_dbe,
4465 irp0_flid_mem_dbe,
4466 ixo_icc_fifo0_dbe_in_sclk,
4467 ixo_icc_fifo1_dbe_in_sclk,
4468 ixo_ics_mem_dbe_in_sclk. */
4469 uint64_t reserved_29_31 : 3;
4470 uint64_t ied0_sbe : 29; /**< [ 28: 0](R/W1S/H) Reads or sets IOBN(0)_INT_SUM[IED0_SBE].
4471 Internal:
4472 iob_mem_data_xmd_sbe_sclk,
4473 gmr_ixofifo_sbe_sclk,
4474 icc0_xmc_fif_sbe,
4475 icc1_xmc_fif_sbe,
4476 icc_xmc_fifo_ecc_sbe,
4477 sli_preq_0_sbe_sclk,
4478 sli_req_0_sbe_sclk,
4479 sli_preq_1_sbe_sclk,
4480 sli_req_1_sbe_sclk,
4481 sli_preq_2_sbe_sclk,
4482 sli_req_2_sbe_sclk,
4483 ixo_smmu_mem0_sbe_sclk,
4484 iop_breq_fifo0_sbe,
4485 iop_breq_fifo1_sbe ,
4486 iop_breq_fifo2_sbe,
4487 iop_breq_fifo3_sbe ,
4488 iop_ffifo_sbe_sclk,
4489 rsd_mem0_sbe,
4490 rsd_mem1_sbe,
4491 ics_cmd_fifo_sbe_sclk,
4492 ixo_xmd_mem1_sbe_sclk,
4493 ixo_xmd_mem0_sbe_sclk,
4494 iobn_iorn_ffifo0__sbe_sclk,
4495 iobn_iorn_ffifo1__sbe_sclk,
4496 irp1_flid_mem_sbe,
4497 irp0_flid_mem_sbe,
4498 ixo_icc_fifo0_sbe_in_sclk,
4499 ixo_icc_fifo1_sbe_in_sclk,
4500 ixo_ics_mem_sbe_in_sclk. */
4501 #else /* Word 0 - Little Endian */
4502 uint64_t ied0_sbe : 29; /**< [ 28: 0](R/W1S/H) Reads or sets IOBN(0)_INT_SUM[IED0_SBE].
4503 Internal:
4504 iob_mem_data_xmd_sbe_sclk,
4505 gmr_ixofifo_sbe_sclk,
4506 icc0_xmc_fif_sbe,
4507 icc1_xmc_fif_sbe,
4508 icc_xmc_fifo_ecc_sbe,
4509 sli_preq_0_sbe_sclk,
4510 sli_req_0_sbe_sclk,
4511 sli_preq_1_sbe_sclk,
4512 sli_req_1_sbe_sclk,
4513 sli_preq_2_sbe_sclk,
4514 sli_req_2_sbe_sclk,
4515 ixo_smmu_mem0_sbe_sclk,
4516 iop_breq_fifo0_sbe,
4517 iop_breq_fifo1_sbe ,
4518 iop_breq_fifo2_sbe,
4519 iop_breq_fifo3_sbe ,
4520 iop_ffifo_sbe_sclk,
4521 rsd_mem0_sbe,
4522 rsd_mem1_sbe,
4523 ics_cmd_fifo_sbe_sclk,
4524 ixo_xmd_mem1_sbe_sclk,
4525 ixo_xmd_mem0_sbe_sclk,
4526 iobn_iorn_ffifo0__sbe_sclk,
4527 iobn_iorn_ffifo1__sbe_sclk,
4528 irp1_flid_mem_sbe,
4529 irp0_flid_mem_sbe,
4530 ixo_icc_fifo0_sbe_in_sclk,
4531 ixo_icc_fifo1_sbe_in_sclk,
4532 ixo_ics_mem_sbe_in_sclk. */
4533 uint64_t reserved_29_31 : 3;
4534 uint64_t ied0_dbe : 29; /**< [ 60: 32](R/W1S/H) Reads or sets IOBN(0)_INT_SUM[IED0_DBE].
4535 Internal:
4536 iob_mem_data_xmd_sbe_sclk,
4537 gmr_ixofifo_dbe_sclk,
4538 icc0_xmc_fif_dbe,
4539 icc1_xmc_fif_dbe,
4540 icc_xmc_fifo_ecc_dbe,
4541 sli_preq_0_dbe_sclk,
4542 sli_req_0_dbe_sclk,
4543 sli_preq_1_dbe_sclk,
4544 sli_req_1_dbe_sclk,
4545 sli_preq_2_dbe_sclk,
4546 sli_req_2_dbe_sclk,
4547 ixo_smmu_mem0_dbe_sclk,
4548 iop_breq_fifo0_dbe,
4549 iop_breq_fifo1_dbe ,
4550 iop_breq_fifo2_dbe,
4551 iop_breq_fifo3_dbe ,
4552 iop_ffifo_dbe_sclk,
4553 rsd_mem0_dbe,
4554 rsd_mem1_dbe,
4555 ics_cmd_fifo_dbe_sclk,
4556 ixo_xmd_mem1_dbe_sclk,
4557 ixo_xmd_mem0_dbe_sclk,
4558 iobn_iorn_ffifo0__dbe_sclk,
4559 iobn_iorn_ffifo1__dbe_sclk,
4560 irp1_flid_mem_dbe,
4561 irp0_flid_mem_dbe,
4562 ixo_icc_fifo0_dbe_in_sclk,
4563 ixo_icc_fifo1_dbe_in_sclk,
4564 ixo_ics_mem_dbe_in_sclk. */
4565 uint64_t reserved_61_62 : 2;
4566 uint64_t pem_sie : 1; /**< [ 63: 63](R/W1S/H) Reads or sets IOBN(0)_INT_SUM[PEM_SIE]. */
4567 #endif /* Word 0 - End */
4568 } cn81xx;
4569 struct bdk_iobnx_int_sum_w1s_cn83xx
4570 {
4571 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4572 uint64_t pem_sie : 1; /**< [ 63: 63](R/W1S/H) Reads or sets IOBN(0..1)_INT_SUM[PEM_SIE]. */
4573 uint64_t ied0_dbe : 31; /**< [ 62: 32](R/W1S/H) Reads or sets IOBN(0..1)_INT_SUM[IED0_DBE].
4574 Internal:
4575 iob_mem_data_xmd_sbe_sclk,
4576 gmr_ixofifo_dbe_sclk,
4577 icc0_xmc_fif_dbe,
4578 icc1_xmc_fif_dbe,
4579 icc_xmc_fifo_ecc_dbe,
4580 sli_preq_0_dbe_sclk,
4581 sli_req_0_dbe_sclk,
4582 sli_preq_1_dbe_sclk,
4583 sli_req_1_dbe_sclk,
4584 sli_preq_2_dbe_sclk,
4585 sli_req_2_dbe_sclk,
4586 sli_preq_3_dbe_sclk,
4587 sli_req_3_dbe_sclk,
4588 ixo_smmu_mem0_dbe_sclk,
4589 iop_breq_fifo0_dbe,
4590 iop_breq_fifo1_dbe ,
4591 iop_breq_fifo2_dbe,
4592 iop_breq_fifo3_dbe ,
4593 iop_ffifo_dbe_sclk,
4594 rsd_mem0_dbe,
4595 rsd_mem1_dbe,
4596 ics_cmd_fifo_dbe_sclk,
4597 ixo_xmd_mem1_dbe_sclk,
4598 ixo_xmd_mem0_dbe_sclk,
4599 iobn_iorn_ffifo0__dbe_sclk,
4600 iobn_iorn_ffifo1__dbe_sclk,
4601 irp1_flid_mem_dbe,
4602 irp0_flid_mem_dbe,
4603 ixo_icc_fifo0_dbe_in_sclk,
4604 ixo_icc_fifo1_dbe_in_sclk,
4605 ixo_ics_mem_dbe_in_sclk. */
4606 uint64_t reserved_31 : 1;
4607 uint64_t ied0_sbe : 31; /**< [ 30: 0](R/W1S/H) Reads or sets IOBN(0..1)_INT_SUM[IED0_SBE].
4608 Internal:
4609 iob_mem_data_xmd_sbe_sclk,
4610 gmr_ixofifo_sbe_sclk,
4611 icc0_xmc_fif_sbe,
4612 icc1_xmc_fif_sbe,
4613 icc_xmc_fifo_ecc_sbe,
4614 sli_preq_0_sbe_sclk,
4615 sli_req_0_sbe_sclk,
4616 sli_preq_1_sbe_sclk,
4617 sli_req_1_sbe_sclk,
4618 sli_preq_2_sbe_sclk,
4619 sli_req_2_sbe_sclk,
4620 sli_preq_3_sbe_sclk,
4621 sli_req_3_sbe_sclk,
4622 ixo_smmu_mem0_sbe_sclk,
4623 iop_breq_fifo0_sbe,
4624 iop_breq_fifo1_sbe ,
4625 iop_breq_fifo2_sbe,
4626 iop_breq_fifo3_sbe ,
4627 iop_ffifo_sbe_sclk,
4628 rsd_mem0_sbe,
4629 rsd_mem1_sbe,
4630 ics_cmd_fifo_sbe_sclk,
4631 ixo_xmd_mem1_sbe_sclk,
4632 ixo_xmd_mem0_sbe_sclk,
4633 iobn_iorn_ffifo0__sbe_sclk,
4634 iobn_iorn_ffifo1__sbe_sclk,
4635 irp1_flid_mem_sbe,
4636 irp0_flid_mem_sbe,
4637 ixo_icc_fifo0_sbe_in_sclk,
4638 ixo_icc_fifo1_sbe_in_sclk,
4639 ixo_ics_mem_sbe_in_sclk. */
4640 #else /* Word 0 - Little Endian */
4641 uint64_t ied0_sbe : 31; /**< [ 30: 0](R/W1S/H) Reads or sets IOBN(0..1)_INT_SUM[IED0_SBE].
4642 Internal:
4643 iob_mem_data_xmd_sbe_sclk,
4644 gmr_ixofifo_sbe_sclk,
4645 icc0_xmc_fif_sbe,
4646 icc1_xmc_fif_sbe,
4647 icc_xmc_fifo_ecc_sbe,
4648 sli_preq_0_sbe_sclk,
4649 sli_req_0_sbe_sclk,
4650 sli_preq_1_sbe_sclk,
4651 sli_req_1_sbe_sclk,
4652 sli_preq_2_sbe_sclk,
4653 sli_req_2_sbe_sclk,
4654 sli_preq_3_sbe_sclk,
4655 sli_req_3_sbe_sclk,
4656 ixo_smmu_mem0_sbe_sclk,
4657 iop_breq_fifo0_sbe,
4658 iop_breq_fifo1_sbe ,
4659 iop_breq_fifo2_sbe,
4660 iop_breq_fifo3_sbe ,
4661 iop_ffifo_sbe_sclk,
4662 rsd_mem0_sbe,
4663 rsd_mem1_sbe,
4664 ics_cmd_fifo_sbe_sclk,
4665 ixo_xmd_mem1_sbe_sclk,
4666 ixo_xmd_mem0_sbe_sclk,
4667 iobn_iorn_ffifo0__sbe_sclk,
4668 iobn_iorn_ffifo1__sbe_sclk,
4669 irp1_flid_mem_sbe,
4670 irp0_flid_mem_sbe,
4671 ixo_icc_fifo0_sbe_in_sclk,
4672 ixo_icc_fifo1_sbe_in_sclk,
4673 ixo_ics_mem_sbe_in_sclk. */
4674 uint64_t reserved_31 : 1;
4675 uint64_t ied0_dbe : 31; /**< [ 62: 32](R/W1S/H) Reads or sets IOBN(0..1)_INT_SUM[IED0_DBE].
4676 Internal:
4677 iob_mem_data_xmd_sbe_sclk,
4678 gmr_ixofifo_dbe_sclk,
4679 icc0_xmc_fif_dbe,
4680 icc1_xmc_fif_dbe,
4681 icc_xmc_fifo_ecc_dbe,
4682 sli_preq_0_dbe_sclk,
4683 sli_req_0_dbe_sclk,
4684 sli_preq_1_dbe_sclk,
4685 sli_req_1_dbe_sclk,
4686 sli_preq_2_dbe_sclk,
4687 sli_req_2_dbe_sclk,
4688 sli_preq_3_dbe_sclk,
4689 sli_req_3_dbe_sclk,
4690 ixo_smmu_mem0_dbe_sclk,
4691 iop_breq_fifo0_dbe,
4692 iop_breq_fifo1_dbe ,
4693 iop_breq_fifo2_dbe,
4694 iop_breq_fifo3_dbe ,
4695 iop_ffifo_dbe_sclk,
4696 rsd_mem0_dbe,
4697 rsd_mem1_dbe,
4698 ics_cmd_fifo_dbe_sclk,
4699 ixo_xmd_mem1_dbe_sclk,
4700 ixo_xmd_mem0_dbe_sclk,
4701 iobn_iorn_ffifo0__dbe_sclk,
4702 iobn_iorn_ffifo1__dbe_sclk,
4703 irp1_flid_mem_dbe,
4704 irp0_flid_mem_dbe,
4705 ixo_icc_fifo0_dbe_in_sclk,
4706 ixo_icc_fifo1_dbe_in_sclk,
4707 ixo_ics_mem_dbe_in_sclk. */
4708 uint64_t pem_sie : 1; /**< [ 63: 63](R/W1S/H) Reads or sets IOBN(0..1)_INT_SUM[PEM_SIE]. */
4709 #endif /* Word 0 - End */
4710 } cn83xx;
4711 struct bdk_iobnx_int_sum_w1s_cn88xxp2
4712 {
4713 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4714 uint64_t pem_sie : 1; /**< [ 63: 63](R/W1S/H) Reads or sets IOBN(0..1)_INT_SUM[PEM_SIE]. */
4715 uint64_t reserved_61_62 : 2;
4716 uint64_t ied0_dbe : 29; /**< [ 60: 32](R/W1S/H) Reads or sets IOBN(0..1)_INT_SUM[IED0_DBE].
4717 Internal:
4718 iob_mem_data_xmd_sbe_sclk,
4719 gmr_ixofifo_dbe_sclk,
4720 icc0_xmc_fif_dbe,
4721 icc1_xmc_fif_dbe,
4722 icc_xmc_fifo_ecc_dbe,
4723 sli_preq_0_dbe_sclk,
4724 sli_req_0_dbe_sclk,
4725 sli_preq_1_dbe_sclk,
4726 sli_req_1_dbe_sclk,
4727 sli_preq_2_dbe_sclk,
4728 sli_req_2_dbe_sclk,
4729 ixo_smmu_mem0_dbe_sclk,
4730 iop_breq_fifo0_dbe,
4731 iop_breq_fifo1_dbe ,
4732 iop_breq_fifo2_dbe,
4733 iop_breq_fifo3_dbe ,
4734 iop_ffifo_dbe_sclk,
4735 rsd_mem0_dbe,
4736 rsd_mem1_dbe,
4737 ics_cmd_fifo_dbe_sclk,
4738 ixo_xmd_mem1_dbe_sclk,
4739 ixo_xmd_mem0_dbe_sclk,
4740 iobn_iorn_ffifo0__dbe_sclk,
4741 iobn_iorn_ffifo1__dbe_sclk,
4742 irp1_flid_mem_dbe,
4743 irp0_flid_mem_dbe,
4744 ixo_icc_fifo0_dbe_in_sclk,
4745 ixo_icc_fifo1_dbe_in_sclk,
4746 ixo_ics_mem_dbe_in_sclk. */
4747 uint64_t reserved_29_31 : 3;
4748 uint64_t ied0_sbe : 29; /**< [ 28: 0](R/W1S/H) Reads or sets IOBN(0..1)_INT_SUM[IED0_SBE].
4749 Internal:
4750 iob_mem_data_xmd_sbe_sclk,
4751 gmr_ixofifo_sbe_sclk,
4752 icc0_xmc_fif_sbe,
4753 icc1_xmc_fif_sbe,
4754 icc_xmc_fifo_ecc_sbe,
4755 sli_preq_0_sbe_sclk,
4756 sli_req_0_sbe_sclk,
4757 sli_preq_1_sbe_sclk,
4758 sli_req_1_sbe_sclk,
4759 sli_preq_2_sbe_sclk,
4760 sli_req_2_sbe_sclk,
4761 ixo_smmu_mem0_sbe_sclk,
4762 iop_breq_fifo0_sbe,
4763 iop_breq_fifo1_sbe ,
4764 iop_breq_fifo2_sbe,
4765 iop_breq_fifo3_sbe ,
4766 iop_ffifo_sbe_sclk,
4767 rsd_mem0_sbe,
4768 rsd_mem1_sbe,
4769 ics_cmd_fifo_sbe_sclk,
4770 ixo_xmd_mem1_sbe_sclk,
4771 ixo_xmd_mem0_sbe_sclk,
4772 iobn_iorn_ffifo0__sbe_sclk,
4773 iobn_iorn_ffifo1__sbe_sclk,
4774 irp1_flid_mem_sbe,
4775 irp0_flid_mem_sbe,
4776 ixo_icc_fifo0_sbe_in_sclk,
4777 ixo_icc_fifo1_sbe_in_sclk,
4778 ixo_ics_mem_sbe_in_sclk. */
4779 #else /* Word 0 - Little Endian */
4780 uint64_t ied0_sbe : 29; /**< [ 28: 0](R/W1S/H) Reads or sets IOBN(0..1)_INT_SUM[IED0_SBE].
4781 Internal:
4782 iob_mem_data_xmd_sbe_sclk,
4783 gmr_ixofifo_sbe_sclk,
4784 icc0_xmc_fif_sbe,
4785 icc1_xmc_fif_sbe,
4786 icc_xmc_fifo_ecc_sbe,
4787 sli_preq_0_sbe_sclk,
4788 sli_req_0_sbe_sclk,
4789 sli_preq_1_sbe_sclk,
4790 sli_req_1_sbe_sclk,
4791 sli_preq_2_sbe_sclk,
4792 sli_req_2_sbe_sclk,
4793 ixo_smmu_mem0_sbe_sclk,
4794 iop_breq_fifo0_sbe,
4795 iop_breq_fifo1_sbe ,
4796 iop_breq_fifo2_sbe,
4797 iop_breq_fifo3_sbe ,
4798 iop_ffifo_sbe_sclk,
4799 rsd_mem0_sbe,
4800 rsd_mem1_sbe,
4801 ics_cmd_fifo_sbe_sclk,
4802 ixo_xmd_mem1_sbe_sclk,
4803 ixo_xmd_mem0_sbe_sclk,
4804 iobn_iorn_ffifo0__sbe_sclk,
4805 iobn_iorn_ffifo1__sbe_sclk,
4806 irp1_flid_mem_sbe,
4807 irp0_flid_mem_sbe,
4808 ixo_icc_fifo0_sbe_in_sclk,
4809 ixo_icc_fifo1_sbe_in_sclk,
4810 ixo_ics_mem_sbe_in_sclk. */
4811 uint64_t reserved_29_31 : 3;
4812 uint64_t ied0_dbe : 29; /**< [ 60: 32](R/W1S/H) Reads or sets IOBN(0..1)_INT_SUM[IED0_DBE].
4813 Internal:
4814 iob_mem_data_xmd_sbe_sclk,
4815 gmr_ixofifo_dbe_sclk,
4816 icc0_xmc_fif_dbe,
4817 icc1_xmc_fif_dbe,
4818 icc_xmc_fifo_ecc_dbe,
4819 sli_preq_0_dbe_sclk,
4820 sli_req_0_dbe_sclk,
4821 sli_preq_1_dbe_sclk,
4822 sli_req_1_dbe_sclk,
4823 sli_preq_2_dbe_sclk,
4824 sli_req_2_dbe_sclk,
4825 ixo_smmu_mem0_dbe_sclk,
4826 iop_breq_fifo0_dbe,
4827 iop_breq_fifo1_dbe ,
4828 iop_breq_fifo2_dbe,
4829 iop_breq_fifo3_dbe ,
4830 iop_ffifo_dbe_sclk,
4831 rsd_mem0_dbe,
4832 rsd_mem1_dbe,
4833 ics_cmd_fifo_dbe_sclk,
4834 ixo_xmd_mem1_dbe_sclk,
4835 ixo_xmd_mem0_dbe_sclk,
4836 iobn_iorn_ffifo0__dbe_sclk,
4837 iobn_iorn_ffifo1__dbe_sclk,
4838 irp1_flid_mem_dbe,
4839 irp0_flid_mem_dbe,
4840 ixo_icc_fifo0_dbe_in_sclk,
4841 ixo_icc_fifo1_dbe_in_sclk,
4842 ixo_ics_mem_dbe_in_sclk. */
4843 uint64_t reserved_61_62 : 2;
4844 uint64_t pem_sie : 1; /**< [ 63: 63](R/W1S/H) Reads or sets IOBN(0..1)_INT_SUM[PEM_SIE]. */
4845 #endif /* Word 0 - End */
4846 } cn88xxp2;
4847 };
4848 typedef union bdk_iobnx_int_sum_w1s bdk_iobnx_int_sum_w1s_t;
4849
4850 static inline uint64_t BDK_IOBNX_INT_SUM_W1S(unsigned long a) __attribute__ ((pure, always_inline));
BDK_IOBNX_INT_SUM_W1S(unsigned long a)4851 static inline uint64_t BDK_IOBNX_INT_SUM_W1S(unsigned long a)
4852 {
4853 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
4854 return 0x87e0f0007000ll + 0x1000000ll * ((a) & 0x0);
4855 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
4856 return 0x87e0f0007000ll + 0x1000000ll * ((a) & 0x1);
4857 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
4858 return 0x87e0f0007000ll + 0x1000000ll * ((a) & 0x1);
4859 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
4860 return 0x87e0f0007000ll + 0x1000000ll * ((a) & 0x1);
4861 __bdk_csr_fatal("IOBNX_INT_SUM_W1S", 1, a, 0, 0, 0);
4862 }
4863
4864 #define typedef_BDK_IOBNX_INT_SUM_W1S(a) bdk_iobnx_int_sum_w1s_t
4865 #define bustype_BDK_IOBNX_INT_SUM_W1S(a) BDK_CSR_TYPE_RSL
4866 #define basename_BDK_IOBNX_INT_SUM_W1S(a) "IOBNX_INT_SUM_W1S"
4867 #define device_bar_BDK_IOBNX_INT_SUM_W1S(a) 0x0 /* PF_BAR0 */
4868 #define busnum_BDK_IOBNX_INT_SUM_W1S(a) (a)
4869 #define arguments_BDK_IOBNX_INT_SUM_W1S(a) (a),-1,-1,-1
4870
4871 /**
4872 * Register (RSL) iobn#_mctlr_reg
4873 *
4874 * IOBN Memory SControl Register
4875 * Contains the sclk memory control for memories.
4876 */
4877 union bdk_iobnx_mctlr_reg
4878 {
4879 uint64_t u;
4880 struct bdk_iobnx_mctlr_reg_s
4881 {
4882 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4883 uint64_t reserved_49_63 : 15;
4884 uint64_t dis : 17; /**< [ 48: 32](R/W) Memory ECC disable.
4885 Internal:
4886 \<47:32\> = iobn_gmr_ixofifo_csr_cor_dis,
4887 sli_req_2_cor_dis and sli_preq_2_cor_dis,
4888 sli_req_1_cor_dis and sli_preq_1_cor_dis,
4889 sli_req_0_cor_dis and sli_preq_0_cor_dis,
4890 iob__iob_xmd_csr_cor_dis_rclk,
4891 ixo_smmu_mem0_csr_cor_dis,
4892 ixo_smmu_mem1_csr_cor_dis,
4893 ixo_ics_mem_csr_cor_dis,
4894 ixo_icc_fifo0_csr_cor_dis,
4895 ixo_icc_fifo1_csr_cor_dis,
4896 ixo_xmd_mem0_csr_cor_dis,
4897 ixo_xmd_mem1_csr_cor_dis,
4898 iobn_iorn_ffifo0__csr_cor_dis,
4899 iobn_iorn_ffifo1__csr_cor_dis,
4900 iop_ffifo_csr_cor_dis,
4901 ics_cmd_fifo_csr_cor_dis */
4902 uint64_t reserved_30_31 : 2;
4903 uint64_t flip : 30; /**< [ 29: 0](R/W) Memory ECC flip.
4904 Internal:
4905 \<27:0\> = iobn_gmr_ixofifo_csr_flip_synd,
4906 sli_req_2_flip_synd and sli_preq_2_flip_synd,
4907 sli_req_1_flip_synd and sli_preq_1_flip_synd,
4908 sli_req_0_flip_synd and sli_preq_0_flip_synd,
4909 iobn_rsd_mem0_csr_flip_synd_rclk,
4910 iobn_rsd_mem1_csr_flip_synd_rclk,
4911 ixo_smmu_mem0_csr_flip_synd,
4912 ixo_smmu_mem1_csr_flip_synd,
4913 ixo_ics_mem_csr_flip_synd,
4914 iop_ffifo_csr_flip_synd,
4915 iop_breq_fifo0_csr_flip_synd,
4916 iop_breq_fifo1_csr_flip_synd,
4917 iop_breq_fifo2_csr_flip_synd,
4918 iop_breq_fifo3_csr_flip_synd */
4919 #else /* Word 0 - Little Endian */
4920 uint64_t flip : 30; /**< [ 29: 0](R/W) Memory ECC flip.
4921 Internal:
4922 \<27:0\> = iobn_gmr_ixofifo_csr_flip_synd,
4923 sli_req_2_flip_synd and sli_preq_2_flip_synd,
4924 sli_req_1_flip_synd and sli_preq_1_flip_synd,
4925 sli_req_0_flip_synd and sli_preq_0_flip_synd,
4926 iobn_rsd_mem0_csr_flip_synd_rclk,
4927 iobn_rsd_mem1_csr_flip_synd_rclk,
4928 ixo_smmu_mem0_csr_flip_synd,
4929 ixo_smmu_mem1_csr_flip_synd,
4930 ixo_ics_mem_csr_flip_synd,
4931 iop_ffifo_csr_flip_synd,
4932 iop_breq_fifo0_csr_flip_synd,
4933 iop_breq_fifo1_csr_flip_synd,
4934 iop_breq_fifo2_csr_flip_synd,
4935 iop_breq_fifo3_csr_flip_synd */
4936 uint64_t reserved_30_31 : 2;
4937 uint64_t dis : 17; /**< [ 48: 32](R/W) Memory ECC disable.
4938 Internal:
4939 \<47:32\> = iobn_gmr_ixofifo_csr_cor_dis,
4940 sli_req_2_cor_dis and sli_preq_2_cor_dis,
4941 sli_req_1_cor_dis and sli_preq_1_cor_dis,
4942 sli_req_0_cor_dis and sli_preq_0_cor_dis,
4943 iob__iob_xmd_csr_cor_dis_rclk,
4944 ixo_smmu_mem0_csr_cor_dis,
4945 ixo_smmu_mem1_csr_cor_dis,
4946 ixo_ics_mem_csr_cor_dis,
4947 ixo_icc_fifo0_csr_cor_dis,
4948 ixo_icc_fifo1_csr_cor_dis,
4949 ixo_xmd_mem0_csr_cor_dis,
4950 ixo_xmd_mem1_csr_cor_dis,
4951 iobn_iorn_ffifo0__csr_cor_dis,
4952 iobn_iorn_ffifo1__csr_cor_dis,
4953 iop_ffifo_csr_cor_dis,
4954 ics_cmd_fifo_csr_cor_dis */
4955 uint64_t reserved_49_63 : 15;
4956 #endif /* Word 0 - End */
4957 } s;
4958 struct bdk_iobnx_mctlr_reg_cn81xx
4959 {
4960 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4961 uint64_t reserved_48_63 : 16;
4962 uint64_t dis : 16; /**< [ 47: 32](R/W) Memory ECC disable.
4963 Internal:
4964 \<47:32\> = iobn_gmr_ixofifo_csr_cor_dis,
4965 sli_req_2_cor_dis and sli_preq_2_cor_dis,
4966 sli_req_1_cor_dis and sli_preq_1_cor_dis,
4967 sli_req_0_cor_dis and sli_preq_0_cor_dis,
4968 iob__iob_xmd_csr_cor_dis_rclk,
4969 ixo_smmu_mem0_csr_cor_dis,
4970 ixo_smmu_mem1_csr_cor_dis,
4971 ixo_ics_mem_csr_cor_dis,
4972 ixo_icc_fifo0_csr_cor_dis,
4973 ixo_icc_fifo1_csr_cor_dis,
4974 ixo_xmd_mem0_csr_cor_dis,
4975 ixo_xmd_mem1_csr_cor_dis,
4976 iobn_iorn_ffifo0__csr_cor_dis,
4977 iobn_iorn_ffifo1__csr_cor_dis,
4978 iop_ffifo_csr_cor_dis,
4979 ics_cmd_fifo_csr_cor_dis */
4980 uint64_t reserved_28_31 : 4;
4981 uint64_t flip : 28; /**< [ 27: 0](R/W) Memory ECC flip.
4982 Internal:
4983 \<27:0\> = iobn_gmr_ixofifo_csr_flip_synd,
4984 sli_req_2_flip_synd and sli_preq_2_flip_synd,
4985 sli_req_1_flip_synd and sli_preq_1_flip_synd,
4986 sli_req_0_flip_synd and sli_preq_0_flip_synd,
4987 iobn_rsd_mem0_csr_flip_synd_rclk,
4988 iobn_rsd_mem1_csr_flip_synd_rclk,
4989 ixo_smmu_mem0_csr_flip_synd,
4990 ixo_smmu_mem1_csr_flip_synd,
4991 ixo_ics_mem_csr_flip_synd,
4992 iop_ffifo_csr_flip_synd,
4993 iop_breq_fifo0_csr_flip_synd,
4994 iop_breq_fifo1_csr_flip_synd,
4995 iop_breq_fifo2_csr_flip_synd,
4996 iop_breq_fifo3_csr_flip_synd */
4997 #else /* Word 0 - Little Endian */
4998 uint64_t flip : 28; /**< [ 27: 0](R/W) Memory ECC flip.
4999 Internal:
5000 \<27:0\> = iobn_gmr_ixofifo_csr_flip_synd,
5001 sli_req_2_flip_synd and sli_preq_2_flip_synd,
5002 sli_req_1_flip_synd and sli_preq_1_flip_synd,
5003 sli_req_0_flip_synd and sli_preq_0_flip_synd,
5004 iobn_rsd_mem0_csr_flip_synd_rclk,
5005 iobn_rsd_mem1_csr_flip_synd_rclk,
5006 ixo_smmu_mem0_csr_flip_synd,
5007 ixo_smmu_mem1_csr_flip_synd,
5008 ixo_ics_mem_csr_flip_synd,
5009 iop_ffifo_csr_flip_synd,
5010 iop_breq_fifo0_csr_flip_synd,
5011 iop_breq_fifo1_csr_flip_synd,
5012 iop_breq_fifo2_csr_flip_synd,
5013 iop_breq_fifo3_csr_flip_synd */
5014 uint64_t reserved_28_31 : 4;
5015 uint64_t dis : 16; /**< [ 47: 32](R/W) Memory ECC disable.
5016 Internal:
5017 \<47:32\> = iobn_gmr_ixofifo_csr_cor_dis,
5018 sli_req_2_cor_dis and sli_preq_2_cor_dis,
5019 sli_req_1_cor_dis and sli_preq_1_cor_dis,
5020 sli_req_0_cor_dis and sli_preq_0_cor_dis,
5021 iob__iob_xmd_csr_cor_dis_rclk,
5022 ixo_smmu_mem0_csr_cor_dis,
5023 ixo_smmu_mem1_csr_cor_dis,
5024 ixo_ics_mem_csr_cor_dis,
5025 ixo_icc_fifo0_csr_cor_dis,
5026 ixo_icc_fifo1_csr_cor_dis,
5027 ixo_xmd_mem0_csr_cor_dis,
5028 ixo_xmd_mem1_csr_cor_dis,
5029 iobn_iorn_ffifo0__csr_cor_dis,
5030 iobn_iorn_ffifo1__csr_cor_dis,
5031 iop_ffifo_csr_cor_dis,
5032 ics_cmd_fifo_csr_cor_dis */
5033 uint64_t reserved_48_63 : 16;
5034 #endif /* Word 0 - End */
5035 } cn81xx;
5036 /* struct bdk_iobnx_mctlr_reg_cn81xx cn88xx; */
5037 struct bdk_iobnx_mctlr_reg_cn83xx
5038 {
5039 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5040 uint64_t reserved_49_63 : 15;
5041 uint64_t dis : 17; /**< [ 48: 32](R/W) Memory ECC disable.
5042 Internal:
5043 \<48:32\> = iobn_gmr_ixofifo_csr_cor_dis,
5044 sli_req_3_cor_dis and sli_preq_3_cor_dis,
5045 sli_req_2_cor_dis and sli_preq_2_cor_dis,
5046 sli_req_1_cor_dis and sli_preq_1_cor_dis,
5047 sli_req_0_cor_dis and sli_preq_0_cor_dis,
5048 iob__iob_xmd_csr_cor_dis_rclk,
5049 ixo_smmu_mem0_csr_cor_dis,
5050 ixo_smmu_mem1_csr_cor_dis,
5051 ixo_ics_mem_csr_cor_dis,
5052 ixo_icc_fifo0_csr_cor_dis,
5053 ixo_icc_fifo1_csr_cor_dis,
5054 ixo_xmd_mem0_csr_cor_dis,
5055 ixo_xmd_mem1_csr_cor_dis,
5056 iobn_iorn_ffifo0__csr_cor_dis,
5057 iobn_iorn_ffifo1__csr_cor_dis,
5058 iop_ffifo_csr_cor_dis,
5059 ics_cmd_fifo_csr_cor_dis */
5060 uint64_t reserved_30_31 : 2;
5061 uint64_t flip : 30; /**< [ 29: 0](R/W) Memory ECC flip.
5062 Internal:
5063 \<29:0\> = iobn_gmr_ixofifo_csr_flip_synd,
5064 sli_req_3_flip_synd and sli_preq_3_flip_synd,
5065 sli_req_2_flip_synd and sli_preq_2_flip_synd,
5066 sli_req_1_flip_synd and sli_preq_1_flip_synd,
5067 sli_req_0_flip_synd and sli_preq_0_flip_synd,
5068 iobn_rsd_mem0_csr_flip_synd_rclk,
5069 iobn_rsd_mem1_csr_flip_synd_rclk,
5070 ixo_smmu_mem0_csr_flip_synd,
5071 ixo_smmu_mem1_csr_flip_synd,
5072 ixo_ics_mem_csr_flip_synd,
5073 iop_ffifo_csr_flip_synd,
5074 iop_breq_fifo0_csr_flip_synd,
5075 iop_breq_fifo1_csr_flip_synd,
5076 iop_breq_fifo2_csr_flip_synd,
5077 iop_breq_fifo3_csr_flip_synd */
5078 #else /* Word 0 - Little Endian */
5079 uint64_t flip : 30; /**< [ 29: 0](R/W) Memory ECC flip.
5080 Internal:
5081 \<29:0\> = iobn_gmr_ixofifo_csr_flip_synd,
5082 sli_req_3_flip_synd and sli_preq_3_flip_synd,
5083 sli_req_2_flip_synd and sli_preq_2_flip_synd,
5084 sli_req_1_flip_synd and sli_preq_1_flip_synd,
5085 sli_req_0_flip_synd and sli_preq_0_flip_synd,
5086 iobn_rsd_mem0_csr_flip_synd_rclk,
5087 iobn_rsd_mem1_csr_flip_synd_rclk,
5088 ixo_smmu_mem0_csr_flip_synd,
5089 ixo_smmu_mem1_csr_flip_synd,
5090 ixo_ics_mem_csr_flip_synd,
5091 iop_ffifo_csr_flip_synd,
5092 iop_breq_fifo0_csr_flip_synd,
5093 iop_breq_fifo1_csr_flip_synd,
5094 iop_breq_fifo2_csr_flip_synd,
5095 iop_breq_fifo3_csr_flip_synd */
5096 uint64_t reserved_30_31 : 2;
5097 uint64_t dis : 17; /**< [ 48: 32](R/W) Memory ECC disable.
5098 Internal:
5099 \<48:32\> = iobn_gmr_ixofifo_csr_cor_dis,
5100 sli_req_3_cor_dis and sli_preq_3_cor_dis,
5101 sli_req_2_cor_dis and sli_preq_2_cor_dis,
5102 sli_req_1_cor_dis and sli_preq_1_cor_dis,
5103 sli_req_0_cor_dis and sli_preq_0_cor_dis,
5104 iob__iob_xmd_csr_cor_dis_rclk,
5105 ixo_smmu_mem0_csr_cor_dis,
5106 ixo_smmu_mem1_csr_cor_dis,
5107 ixo_ics_mem_csr_cor_dis,
5108 ixo_icc_fifo0_csr_cor_dis,
5109 ixo_icc_fifo1_csr_cor_dis,
5110 ixo_xmd_mem0_csr_cor_dis,
5111 ixo_xmd_mem1_csr_cor_dis,
5112 iobn_iorn_ffifo0__csr_cor_dis,
5113 iobn_iorn_ffifo1__csr_cor_dis,
5114 iop_ffifo_csr_cor_dis,
5115 ics_cmd_fifo_csr_cor_dis */
5116 uint64_t reserved_49_63 : 15;
5117 #endif /* Word 0 - End */
5118 } cn83xx;
5119 };
5120 typedef union bdk_iobnx_mctlr_reg bdk_iobnx_mctlr_reg_t;
5121
5122 static inline uint64_t BDK_IOBNX_MCTLR_REG(unsigned long a) __attribute__ ((pure, always_inline));
BDK_IOBNX_MCTLR_REG(unsigned long a)5123 static inline uint64_t BDK_IOBNX_MCTLR_REG(unsigned long a)
5124 {
5125 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
5126 return 0x87e0f0005108ll + 0x1000000ll * ((a) & 0x0);
5127 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
5128 return 0x87e0f0005108ll + 0x1000000ll * ((a) & 0x1);
5129 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
5130 return 0x87e0f0005108ll + 0x1000000ll * ((a) & 0x1);
5131 __bdk_csr_fatal("IOBNX_MCTLR_REG", 1, a, 0, 0, 0);
5132 }
5133
5134 #define typedef_BDK_IOBNX_MCTLR_REG(a) bdk_iobnx_mctlr_reg_t
5135 #define bustype_BDK_IOBNX_MCTLR_REG(a) BDK_CSR_TYPE_RSL
5136 #define basename_BDK_IOBNX_MCTLR_REG(a) "IOBNX_MCTLR_REG"
5137 #define device_bar_BDK_IOBNX_MCTLR_REG(a) 0x0 /* PF_BAR0 */
5138 #define busnum_BDK_IOBNX_MCTLR_REG(a) (a)
5139 #define arguments_BDK_IOBNX_MCTLR_REG(a) (a),-1,-1,-1
5140
5141 /**
5142 * Register (RSL) iobn#_mctls_reg
5143 *
5144 * IOBN Memory SControl Register
5145 * Contains the sclk memory control for memories.
5146 */
5147 union bdk_iobnx_mctls_reg
5148 {
5149 uint64_t u;
5150 struct bdk_iobnx_mctls_reg_s
5151 {
5152 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5153 uint64_t reserved_43_63 : 21;
5154 uint64_t dis : 11; /**< [ 42: 32](R/W) Memory ECC disable.
5155 Internal:
5156 \<42:32\> = iobn_rsd_mem0_csr_cor_dis,
5157 iobn_rsd_mem1_csr_cor_dis,
5158 irp0_flid_mem_csr_cor_dis,
5159 irp1_flid_mem_csr_cor_dis,
5160 iop_breq_fifo0_csr_cor_dis,
5161 iop_breq_fifo1_csr_cor_dis,
5162 iop_breq_fifo2_csr_cor_dis,
5163 iop_breq_fifo3_csr_cor_dis,
5164 icc_xmc_fifo_ecc_csr_cor_dis,
5165 icc0_xmc_fifo_csr_cor_dis,
5166 icc1_xmc_fifo_csr_cor_dis */
5167 uint64_t reserved_26_31 : 6;
5168 uint64_t flip : 26; /**< [ 25: 0](R/W) Memory ECC flip.
5169 Internal:
5170 \<25:0\> = iob__iob_xmd_csr_flip_synd_sclk,
5171 ixo_icc_fifo0_csr_flip_synd,
5172 ixo_icc_fifo1_csr_flip_synd,
5173 ixo_xmd_mem0_csr_flip_synd,
5174 ixo_xmd_mem1_csr_flip_synd,
5175 irp0_flid_mem_csr_flip_synd,
5176 irp1_flid_mem_csr_flip_synd,
5177 iobn_iorn_ffifo0__csr_flip_synd,
5178 iobn_iorn_ffifo1__csr_flip_synd,
5179 icc_xmc_fifo_ecc_csr_flip_synd,
5180 ics_cmd_fifo_csr_flip_synd,
5181 icc0_xmc_fifo_csr_flip_synd,
5182 icc1_xmc_fifo_csr_flip_synd */
5183 #else /* Word 0 - Little Endian */
5184 uint64_t flip : 26; /**< [ 25: 0](R/W) Memory ECC flip.
5185 Internal:
5186 \<25:0\> = iob__iob_xmd_csr_flip_synd_sclk,
5187 ixo_icc_fifo0_csr_flip_synd,
5188 ixo_icc_fifo1_csr_flip_synd,
5189 ixo_xmd_mem0_csr_flip_synd,
5190 ixo_xmd_mem1_csr_flip_synd,
5191 irp0_flid_mem_csr_flip_synd,
5192 irp1_flid_mem_csr_flip_synd,
5193 iobn_iorn_ffifo0__csr_flip_synd,
5194 iobn_iorn_ffifo1__csr_flip_synd,
5195 icc_xmc_fifo_ecc_csr_flip_synd,
5196 ics_cmd_fifo_csr_flip_synd,
5197 icc0_xmc_fifo_csr_flip_synd,
5198 icc1_xmc_fifo_csr_flip_synd */
5199 uint64_t reserved_26_31 : 6;
5200 uint64_t dis : 11; /**< [ 42: 32](R/W) Memory ECC disable.
5201 Internal:
5202 \<42:32\> = iobn_rsd_mem0_csr_cor_dis,
5203 iobn_rsd_mem1_csr_cor_dis,
5204 irp0_flid_mem_csr_cor_dis,
5205 irp1_flid_mem_csr_cor_dis,
5206 iop_breq_fifo0_csr_cor_dis,
5207 iop_breq_fifo1_csr_cor_dis,
5208 iop_breq_fifo2_csr_cor_dis,
5209 iop_breq_fifo3_csr_cor_dis,
5210 icc_xmc_fifo_ecc_csr_cor_dis,
5211 icc0_xmc_fifo_csr_cor_dis,
5212 icc1_xmc_fifo_csr_cor_dis */
5213 uint64_t reserved_43_63 : 21;
5214 #endif /* Word 0 - End */
5215 } s;
5216 /* struct bdk_iobnx_mctls_reg_s cn; */
5217 };
5218 typedef union bdk_iobnx_mctls_reg bdk_iobnx_mctls_reg_t;
5219
5220 static inline uint64_t BDK_IOBNX_MCTLS_REG(unsigned long a) __attribute__ ((pure, always_inline));
BDK_IOBNX_MCTLS_REG(unsigned long a)5221 static inline uint64_t BDK_IOBNX_MCTLS_REG(unsigned long a)
5222 {
5223 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
5224 return 0x87e0f0005100ll + 0x1000000ll * ((a) & 0x0);
5225 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
5226 return 0x87e0f0005100ll + 0x1000000ll * ((a) & 0x1);
5227 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
5228 return 0x87e0f0005100ll + 0x1000000ll * ((a) & 0x1);
5229 __bdk_csr_fatal("IOBNX_MCTLS_REG", 1, a, 0, 0, 0);
5230 }
5231
5232 #define typedef_BDK_IOBNX_MCTLS_REG(a) bdk_iobnx_mctls_reg_t
5233 #define bustype_BDK_IOBNX_MCTLS_REG(a) BDK_CSR_TYPE_RSL
5234 #define basename_BDK_IOBNX_MCTLS_REG(a) "IOBNX_MCTLS_REG"
5235 #define device_bar_BDK_IOBNX_MCTLS_REG(a) 0x0 /* PF_BAR0 */
5236 #define busnum_BDK_IOBNX_MCTLS_REG(a) (a)
5237 #define arguments_BDK_IOBNX_MCTLS_REG(a) (a),-1,-1,-1
5238
5239 /**
5240 * Register (RSL) iobn#_msix_pba#
5241 *
5242 * IOBN MSI-X Pending Bit Array Registers
5243 * This register is the MSI-X PBA table; the bit number is indexed by the IOBN_INT_VEC_E enumeration.
5244 */
5245 union bdk_iobnx_msix_pbax
5246 {
5247 uint64_t u;
5248 struct bdk_iobnx_msix_pbax_s
5249 {
5250 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5251 uint64_t pend : 64; /**< [ 63: 0](RO) Pending message for the associated IOBN()_MSIX_VEC()_CTL, enumerated by IOBN_INT_VEC_E.
5252 Bits that have no associated IOBN_INT_VEC_E are zero. */
5253 #else /* Word 0 - Little Endian */
5254 uint64_t pend : 64; /**< [ 63: 0](RO) Pending message for the associated IOBN()_MSIX_VEC()_CTL, enumerated by IOBN_INT_VEC_E.
5255 Bits that have no associated IOBN_INT_VEC_E are zero. */
5256 #endif /* Word 0 - End */
5257 } s;
5258 /* struct bdk_iobnx_msix_pbax_s cn; */
5259 };
5260 typedef union bdk_iobnx_msix_pbax bdk_iobnx_msix_pbax_t;
5261
5262 static inline uint64_t BDK_IOBNX_MSIX_PBAX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_IOBNX_MSIX_PBAX(unsigned long a,unsigned long b)5263 static inline uint64_t BDK_IOBNX_MSIX_PBAX(unsigned long a, unsigned long b)
5264 {
5265 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b==0)))
5266 return 0x87e0f0ff0000ll + 0x1000000ll * ((a) & 0x0) + 8ll * ((b) & 0x0);
5267 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b==0)))
5268 return 0x87e0f0ff0000ll + 0x1000000ll * ((a) & 0x1) + 8ll * ((b) & 0x0);
5269 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b==0)))
5270 return 0x87e0f0ff0000ll + 0x1000000ll * ((a) & 0x1) + 8ll * ((b) & 0x0);
5271 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b==0)))
5272 return 0x87e0f0ff0000ll + 0x1000000ll * ((a) & 0x1) + 8ll * ((b) & 0x0);
5273 __bdk_csr_fatal("IOBNX_MSIX_PBAX", 2, a, b, 0, 0);
5274 }
5275
5276 #define typedef_BDK_IOBNX_MSIX_PBAX(a,b) bdk_iobnx_msix_pbax_t
5277 #define bustype_BDK_IOBNX_MSIX_PBAX(a,b) BDK_CSR_TYPE_RSL
5278 #define basename_BDK_IOBNX_MSIX_PBAX(a,b) "IOBNX_MSIX_PBAX"
5279 #define device_bar_BDK_IOBNX_MSIX_PBAX(a,b) 0x4 /* PF_BAR4 */
5280 #define busnum_BDK_IOBNX_MSIX_PBAX(a,b) (a)
5281 #define arguments_BDK_IOBNX_MSIX_PBAX(a,b) (a),(b),-1,-1
5282
5283 /**
5284 * Register (RSL) iobn#_msix_vec#_addr
5285 *
5286 * IOBN MSI-X Vector-Table Address Register
5287 * This register is the MSI-X vector table, indexed by the IOBN_INT_VEC_E enumeration.
5288 */
5289 union bdk_iobnx_msix_vecx_addr
5290 {
5291 uint64_t u;
5292 struct bdk_iobnx_msix_vecx_addr_s
5293 {
5294 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5295 uint64_t reserved_53_63 : 11;
5296 uint64_t addr : 51; /**< [ 52: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
5297 uint64_t reserved_1 : 1;
5298 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
5299 0 = This vector may be read or written by either secure or nonsecure states.
5300 1 = This vector's IOBN_MSIX_VEC()_ADDR, IOBN_MSIX_VEC()_CTL, and corresponding
5301 bit of IOBN_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
5302 by the nonsecure world.
5303
5304 If PCCPF_IOBN_VSEC_SCTL[MSIX_SEC] (for documentation, see PCCPF_XXX_VSEC_SCTL[MSIX_SEC])
5305 is set, all vectors are secure and function as if [SECVEC] was set. */
5306 #else /* Word 0 - Little Endian */
5307 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
5308 0 = This vector may be read or written by either secure or nonsecure states.
5309 1 = This vector's IOBN_MSIX_VEC()_ADDR, IOBN_MSIX_VEC()_CTL, and corresponding
5310 bit of IOBN_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
5311 by the nonsecure world.
5312
5313 If PCCPF_IOBN_VSEC_SCTL[MSIX_SEC] (for documentation, see PCCPF_XXX_VSEC_SCTL[MSIX_SEC])
5314 is set, all vectors are secure and function as if [SECVEC] was set. */
5315 uint64_t reserved_1 : 1;
5316 uint64_t addr : 51; /**< [ 52: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
5317 uint64_t reserved_53_63 : 11;
5318 #endif /* Word 0 - End */
5319 } s;
5320 struct bdk_iobnx_msix_vecx_addr_cn8
5321 {
5322 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5323 uint64_t reserved_49_63 : 15;
5324 uint64_t addr : 47; /**< [ 48: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
5325 uint64_t reserved_1 : 1;
5326 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
5327 0 = This vector may be read or written by either secure or nonsecure states.
5328 1 = This vector's IOBN_MSIX_VEC()_ADDR, IOBN_MSIX_VEC()_CTL, and corresponding
5329 bit of IOBN_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
5330 by the nonsecure world.
5331
5332 If PCCPF_IOBN_VSEC_SCTL[MSIX_SEC] (for documentation, see PCCPF_XXX_VSEC_SCTL[MSIX_SEC])
5333 is set, all vectors are secure and function as if [SECVEC] was set. */
5334 #else /* Word 0 - Little Endian */
5335 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
5336 0 = This vector may be read or written by either secure or nonsecure states.
5337 1 = This vector's IOBN_MSIX_VEC()_ADDR, IOBN_MSIX_VEC()_CTL, and corresponding
5338 bit of IOBN_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
5339 by the nonsecure world.
5340
5341 If PCCPF_IOBN_VSEC_SCTL[MSIX_SEC] (for documentation, see PCCPF_XXX_VSEC_SCTL[MSIX_SEC])
5342 is set, all vectors are secure and function as if [SECVEC] was set. */
5343 uint64_t reserved_1 : 1;
5344 uint64_t addr : 47; /**< [ 48: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
5345 uint64_t reserved_49_63 : 15;
5346 #endif /* Word 0 - End */
5347 } cn8;
5348 struct bdk_iobnx_msix_vecx_addr_cn9
5349 {
5350 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5351 uint64_t reserved_53_63 : 11;
5352 uint64_t addr : 51; /**< [ 52: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
5353 uint64_t reserved_1 : 1;
5354 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
5355 0 = This vector may be read or written by either secure or nonsecure states.
5356 1 = This vector's IOBN()_MSIX_VEC()_ADDR, IOBN()_MSIX_VEC()_CTL, and
5357 corresponding bit of IOBN()_MSIX_PBA() are RAZ/WI and does not cause a fault
5358 when accessed by the nonsecure world.
5359
5360 If PCCPF_IOBN_VSEC_SCTL[MSIX_SEC] (for documentation, see PCCPF_XXX_VSEC_SCTL[MSIX_SEC])
5361 is set, all vectors are secure and function as if [SECVEC] was set. */
5362 #else /* Word 0 - Little Endian */
5363 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
5364 0 = This vector may be read or written by either secure or nonsecure states.
5365 1 = This vector's IOBN()_MSIX_VEC()_ADDR, IOBN()_MSIX_VEC()_CTL, and
5366 corresponding bit of IOBN()_MSIX_PBA() are RAZ/WI and does not cause a fault
5367 when accessed by the nonsecure world.
5368
5369 If PCCPF_IOBN_VSEC_SCTL[MSIX_SEC] (for documentation, see PCCPF_XXX_VSEC_SCTL[MSIX_SEC])
5370 is set, all vectors are secure and function as if [SECVEC] was set. */
5371 uint64_t reserved_1 : 1;
5372 uint64_t addr : 51; /**< [ 52: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
5373 uint64_t reserved_53_63 : 11;
5374 #endif /* Word 0 - End */
5375 } cn9;
5376 };
5377 typedef union bdk_iobnx_msix_vecx_addr bdk_iobnx_msix_vecx_addr_t;
5378
5379 static inline uint64_t BDK_IOBNX_MSIX_VECX_ADDR(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_IOBNX_MSIX_VECX_ADDR(unsigned long a,unsigned long b)5380 static inline uint64_t BDK_IOBNX_MSIX_VECX_ADDR(unsigned long a, unsigned long b)
5381 {
5382 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b==0)))
5383 return 0x87e0f0f00000ll + 0x1000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x0);
5384 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b==0)))
5385 return 0x87e0f0f00000ll + 0x1000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x0);
5386 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b==0)))
5387 return 0x87e0f0f00000ll + 0x1000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x0);
5388 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b<=1)))
5389 return 0x87e0f0f00000ll + 0x1000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x1);
5390 __bdk_csr_fatal("IOBNX_MSIX_VECX_ADDR", 2, a, b, 0, 0);
5391 }
5392
5393 #define typedef_BDK_IOBNX_MSIX_VECX_ADDR(a,b) bdk_iobnx_msix_vecx_addr_t
5394 #define bustype_BDK_IOBNX_MSIX_VECX_ADDR(a,b) BDK_CSR_TYPE_RSL
5395 #define basename_BDK_IOBNX_MSIX_VECX_ADDR(a,b) "IOBNX_MSIX_VECX_ADDR"
5396 #define device_bar_BDK_IOBNX_MSIX_VECX_ADDR(a,b) 0x4 /* PF_BAR4 */
5397 #define busnum_BDK_IOBNX_MSIX_VECX_ADDR(a,b) (a)
5398 #define arguments_BDK_IOBNX_MSIX_VECX_ADDR(a,b) (a),(b),-1,-1
5399
5400 /**
5401 * Register (RSL) iobn#_msix_vec#_ctl
5402 *
5403 * IOBN MSI-X Vector-Table Control and Data Register
5404 * This register is the MSI-X vector table, indexed by the IOBN_INT_VEC_E enumeration.
5405 */
5406 union bdk_iobnx_msix_vecx_ctl
5407 {
5408 uint64_t u;
5409 struct bdk_iobnx_msix_vecx_ctl_s
5410 {
5411 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5412 uint64_t reserved_33_63 : 31;
5413 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts are sent to this vector. */
5414 uint64_t data : 32; /**< [ 31: 0](R/W) Data to use for MSI-X delivery of this vector. */
5415 #else /* Word 0 - Little Endian */
5416 uint64_t data : 32; /**< [ 31: 0](R/W) Data to use for MSI-X delivery of this vector. */
5417 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts are sent to this vector. */
5418 uint64_t reserved_33_63 : 31;
5419 #endif /* Word 0 - End */
5420 } s;
5421 struct bdk_iobnx_msix_vecx_ctl_cn8
5422 {
5423 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5424 uint64_t reserved_33_63 : 31;
5425 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts are sent to this vector. */
5426 uint64_t reserved_20_31 : 12;
5427 uint64_t data : 20; /**< [ 19: 0](R/W) Data to use for MSI-X delivery of this vector. */
5428 #else /* Word 0 - Little Endian */
5429 uint64_t data : 20; /**< [ 19: 0](R/W) Data to use for MSI-X delivery of this vector. */
5430 uint64_t reserved_20_31 : 12;
5431 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts are sent to this vector. */
5432 uint64_t reserved_33_63 : 31;
5433 #endif /* Word 0 - End */
5434 } cn8;
5435 /* struct bdk_iobnx_msix_vecx_ctl_s cn9; */
5436 };
5437 typedef union bdk_iobnx_msix_vecx_ctl bdk_iobnx_msix_vecx_ctl_t;
5438
5439 static inline uint64_t BDK_IOBNX_MSIX_VECX_CTL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_IOBNX_MSIX_VECX_CTL(unsigned long a,unsigned long b)5440 static inline uint64_t BDK_IOBNX_MSIX_VECX_CTL(unsigned long a, unsigned long b)
5441 {
5442 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b==0)))
5443 return 0x87e0f0f00008ll + 0x1000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x0);
5444 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b==0)))
5445 return 0x87e0f0f00008ll + 0x1000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x0);
5446 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b==0)))
5447 return 0x87e0f0f00008ll + 0x1000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x0);
5448 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b<=1)))
5449 return 0x87e0f0f00008ll + 0x1000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x1);
5450 __bdk_csr_fatal("IOBNX_MSIX_VECX_CTL", 2, a, b, 0, 0);
5451 }
5452
5453 #define typedef_BDK_IOBNX_MSIX_VECX_CTL(a,b) bdk_iobnx_msix_vecx_ctl_t
5454 #define bustype_BDK_IOBNX_MSIX_VECX_CTL(a,b) BDK_CSR_TYPE_RSL
5455 #define basename_BDK_IOBNX_MSIX_VECX_CTL(a,b) "IOBNX_MSIX_VECX_CTL"
5456 #define device_bar_BDK_IOBNX_MSIX_VECX_CTL(a,b) 0x4 /* PF_BAR4 */
5457 #define busnum_BDK_IOBNX_MSIX_VECX_CTL(a,b) (a)
5458 #define arguments_BDK_IOBNX_MSIX_VECX_CTL(a,b) (a),(b),-1,-1
5459
5460 /**
5461 * Register (RSL) iobn#_ncb#_acc
5462 *
5463 * IOBN NCB Access Registers
5464 * This register sets attributes of NCBDIDs address bits \<43:36\>.
5465 */
5466 union bdk_iobnx_ncbx_acc
5467 {
5468 uint64_t u;
5469 struct bdk_iobnx_ncbx_acc_s
5470 {
5471 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5472 uint64_t reserved_1_63 : 63;
5473 uint64_t all_cmds : 1; /**< [ 0: 0](R/W) Device supports all commends.
5474 0 = Only naturally aligned loads and stores that are 64-bit or smaller are
5475 permitted to the NCB device. This setting is used for non-PEM devices.
5476 1 = Allow all size accesses, plus atomics and LMTSTs. This setting is used for
5477 PEM.
5478
5479 Reset value of this field varies for different devices.
5480 Using non-reset values is for diagnostic use only.
5481
5482 Internal:
5483 FIXME resets to be added. */
5484 #else /* Word 0 - Little Endian */
5485 uint64_t all_cmds : 1; /**< [ 0: 0](R/W) Device supports all commends.
5486 0 = Only naturally aligned loads and stores that are 64-bit or smaller are
5487 permitted to the NCB device. This setting is used for non-PEM devices.
5488 1 = Allow all size accesses, plus atomics and LMTSTs. This setting is used for
5489 PEM.
5490
5491 Reset value of this field varies for different devices.
5492 Using non-reset values is for diagnostic use only.
5493
5494 Internal:
5495 FIXME resets to be added. */
5496 uint64_t reserved_1_63 : 63;
5497 #endif /* Word 0 - End */
5498 } s;
5499 /* struct bdk_iobnx_ncbx_acc_s cn; */
5500 };
5501 typedef union bdk_iobnx_ncbx_acc bdk_iobnx_ncbx_acc_t;
5502
5503 static inline uint64_t BDK_IOBNX_NCBX_ACC(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_IOBNX_NCBX_ACC(unsigned long a,unsigned long b)5504 static inline uint64_t BDK_IOBNX_NCBX_ACC(unsigned long a, unsigned long b)
5505 {
5506 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b<=255)))
5507 return 0x87e0f0080000ll + 0x1000000ll * ((a) & 0x1) + 8ll * ((b) & 0xff);
5508 __bdk_csr_fatal("IOBNX_NCBX_ACC", 2, a, b, 0, 0);
5509 }
5510
5511 #define typedef_BDK_IOBNX_NCBX_ACC(a,b) bdk_iobnx_ncbx_acc_t
5512 #define bustype_BDK_IOBNX_NCBX_ACC(a,b) BDK_CSR_TYPE_RSL
5513 #define basename_BDK_IOBNX_NCBX_ACC(a,b) "IOBNX_NCBX_ACC"
5514 #define device_bar_BDK_IOBNX_NCBX_ACC(a,b) 0x0 /* PF_BAR0 */
5515 #define busnum_BDK_IOBNX_NCBX_ACC(a,b) (a)
5516 #define arguments_BDK_IOBNX_NCBX_ACC(a,b) (a),(b),-1,-1
5517
5518 /**
5519 * Register (RSL) iobn#_ncb#_arb#_bp_test
5520 *
5521 * IOBN Back Pressure Register
5522 */
5523 union bdk_iobnx_ncbx_arbx_bp_test
5524 {
5525 uint64_t u;
5526 struct bdk_iobnx_ncbx_arbx_bp_test_s
5527 {
5528 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5529 uint64_t bp_cfg : 64; /**< [ 63: 0](R/W) Backpressure weight. For diagnostic use only.
5530 Internal:
5531 There are 2 backpressure configuration bits per enable, with the two bits
5532 defined as 0x0=100% of the time, 0x1=75% of the time, 0x2=50% of the time,
5533 0x3=25% of the time.
5534 \<etc\> up to max number of supported ports per arbiter
5535 \<7:6\> = Config 3.
5536 \<25:4\> = Config 2.
5537 \<3:2\> = Config 1.
5538 \<1:0\> = Config 0. */
5539 #else /* Word 0 - Little Endian */
5540 uint64_t bp_cfg : 64; /**< [ 63: 0](R/W) Backpressure weight. For diagnostic use only.
5541 Internal:
5542 There are 2 backpressure configuration bits per enable, with the two bits
5543 defined as 0x0=100% of the time, 0x1=75% of the time, 0x2=50% of the time,
5544 0x3=25% of the time.
5545 \<etc\> up to max number of supported ports per arbiter
5546 \<7:6\> = Config 3.
5547 \<25:4\> = Config 2.
5548 \<3:2\> = Config 1.
5549 \<1:0\> = Config 0. */
5550 #endif /* Word 0 - End */
5551 } s;
5552 /* struct bdk_iobnx_ncbx_arbx_bp_test_s cn; */
5553 };
5554 typedef union bdk_iobnx_ncbx_arbx_bp_test bdk_iobnx_ncbx_arbx_bp_test_t;
5555
5556 static inline uint64_t BDK_IOBNX_NCBX_ARBX_BP_TEST(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_IOBNX_NCBX_ARBX_BP_TEST(unsigned long a,unsigned long b,unsigned long c)5557 static inline uint64_t BDK_IOBNX_NCBX_ARBX_BP_TEST(unsigned long a, unsigned long b, unsigned long c)
5558 {
5559 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b<=2) && (c<=31)))
5560 return 0x87e0f00f8000ll + 0x1000000ll * ((a) & 0x1) + 0x400ll * ((b) & 0x3) + 8ll * ((c) & 0x1f);
5561 __bdk_csr_fatal("IOBNX_NCBX_ARBX_BP_TEST", 3, a, b, c, 0);
5562 }
5563
5564 #define typedef_BDK_IOBNX_NCBX_ARBX_BP_TEST(a,b,c) bdk_iobnx_ncbx_arbx_bp_test_t
5565 #define bustype_BDK_IOBNX_NCBX_ARBX_BP_TEST(a,b,c) BDK_CSR_TYPE_RSL
5566 #define basename_BDK_IOBNX_NCBX_ARBX_BP_TEST(a,b,c) "IOBNX_NCBX_ARBX_BP_TEST"
5567 #define device_bar_BDK_IOBNX_NCBX_ARBX_BP_TEST(a,b,c) 0x0 /* PF_BAR0 */
5568 #define busnum_BDK_IOBNX_NCBX_ARBX_BP_TEST(a,b,c) (a)
5569 #define arguments_BDK_IOBNX_NCBX_ARBX_BP_TEST(a,b,c) (a),(b),(c),-1
5570
5571 /**
5572 * Register (RSL) iobn#_ncb#_arb#_crds
5573 *
5574 * IOBN NREQ Priority Register
5575 */
5576 union bdk_iobnx_ncbx_arbx_crds
5577 {
5578 uint64_t u;
5579 struct bdk_iobnx_ncbx_arbx_crds_s
5580 {
5581 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5582 uint64_t reserved_16_63 : 48;
5583 uint64_t max : 8; /**< [ 15: 8](R/W) Maximum number of FLIDs available to the requestor.
5584 Decreasing this number will limit the maximum burst performance of this device. */
5585 uint64_t min : 8; /**< [ 7: 0](R/W) Minimum number of FLIDs available to the requestor. From the total available
5586 credits this many will be set aside for this NREQID to use.
5587 Increasing this number will insure this device has dedicated bandwidth over
5588 other devices. Must be 0x1 or larger for GIC. Recommend 0x1 or larger for
5589 all devices that are used. */
5590 #else /* Word 0 - Little Endian */
5591 uint64_t min : 8; /**< [ 7: 0](R/W) Minimum number of FLIDs available to the requestor. From the total available
5592 credits this many will be set aside for this NREQID to use.
5593 Increasing this number will insure this device has dedicated bandwidth over
5594 other devices. Must be 0x1 or larger for GIC. Recommend 0x1 or larger for
5595 all devices that are used. */
5596 uint64_t max : 8; /**< [ 15: 8](R/W) Maximum number of FLIDs available to the requestor.
5597 Decreasing this number will limit the maximum burst performance of this device. */
5598 uint64_t reserved_16_63 : 48;
5599 #endif /* Word 0 - End */
5600 } s;
5601 /* struct bdk_iobnx_ncbx_arbx_crds_s cn; */
5602 };
5603 typedef union bdk_iobnx_ncbx_arbx_crds bdk_iobnx_ncbx_arbx_crds_t;
5604
5605 static inline uint64_t BDK_IOBNX_NCBX_ARBX_CRDS(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_IOBNX_NCBX_ARBX_CRDS(unsigned long a,unsigned long b,unsigned long c)5606 static inline uint64_t BDK_IOBNX_NCBX_ARBX_CRDS(unsigned long a, unsigned long b, unsigned long c)
5607 {
5608 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b<=2) && (c<=31)))
5609 return 0x87e0f00f0000ll + 0x1000000ll * ((a) & 0x1) + 0x400ll * ((b) & 0x3) + 8ll * ((c) & 0x1f);
5610 __bdk_csr_fatal("IOBNX_NCBX_ARBX_CRDS", 3, a, b, c, 0);
5611 }
5612
5613 #define typedef_BDK_IOBNX_NCBX_ARBX_CRDS(a,b,c) bdk_iobnx_ncbx_arbx_crds_t
5614 #define bustype_BDK_IOBNX_NCBX_ARBX_CRDS(a,b,c) BDK_CSR_TYPE_RSL
5615 #define basename_BDK_IOBNX_NCBX_ARBX_CRDS(a,b,c) "IOBNX_NCBX_ARBX_CRDS"
5616 #define device_bar_BDK_IOBNX_NCBX_ARBX_CRDS(a,b,c) 0x0 /* PF_BAR0 */
5617 #define busnum_BDK_IOBNX_NCBX_ARBX_CRDS(a,b,c) (a)
5618 #define arguments_BDK_IOBNX_NCBX_ARBX_CRDS(a,b,c) (a),(b),(c),-1
5619
5620 /**
5621 * Register (RSL) iobn#_ncb#_arb#_rw#_lat_pc
5622 *
5623 * IOBN NCB Latency Performance Counter Registers
5624 */
5625 union bdk_iobnx_ncbx_arbx_rwx_lat_pc
5626 {
5627 uint64_t u;
5628 struct bdk_iobnx_ncbx_arbx_rwx_lat_pc_s
5629 {
5630 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5631 uint64_t count : 64; /**< [ 63: 0](R/W/H) Latency performance counter.
5632
5633 _ RW(0) increments every cycle by the number of read transactions that have been
5634 granted from the given NCB, but have not had there credit returned to the NGNT.
5635
5636 _ RW(0) increments every cycle by the number of write transactions that have been
5637 granted from the given NCB, but have not had there credit returned to the NGNT.
5638
5639 This counter should be divided by IOBN()_NCB()_ARB()_RW()_REQ_PC to determine each NCB
5640 bus's average read and write latency. */
5641 #else /* Word 0 - Little Endian */
5642 uint64_t count : 64; /**< [ 63: 0](R/W/H) Latency performance counter.
5643
5644 _ RW(0) increments every cycle by the number of read transactions that have been
5645 granted from the given NCB, but have not had there credit returned to the NGNT.
5646
5647 _ RW(0) increments every cycle by the number of write transactions that have been
5648 granted from the given NCB, but have not had there credit returned to the NGNT.
5649
5650 This counter should be divided by IOBN()_NCB()_ARB()_RW()_REQ_PC to determine each NCB
5651 bus's average read and write latency. */
5652 #endif /* Word 0 - End */
5653 } s;
5654 /* struct bdk_iobnx_ncbx_arbx_rwx_lat_pc_s cn; */
5655 };
5656 typedef union bdk_iobnx_ncbx_arbx_rwx_lat_pc bdk_iobnx_ncbx_arbx_rwx_lat_pc_t;
5657
5658 static inline uint64_t BDK_IOBNX_NCBX_ARBX_RWX_LAT_PC(unsigned long a, unsigned long b, unsigned long c, unsigned long d) __attribute__ ((pure, always_inline));
BDK_IOBNX_NCBX_ARBX_RWX_LAT_PC(unsigned long a,unsigned long b,unsigned long c,unsigned long d)5659 static inline uint64_t BDK_IOBNX_NCBX_ARBX_RWX_LAT_PC(unsigned long a, unsigned long b, unsigned long c, unsigned long d)
5660 {
5661 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b<=2) && (c<=31) && (d<=1)))
5662 return 0x87e0f00f4000ll + 0x1000000ll * ((a) & 0x1) + 0x400ll * ((b) & 0x3) + 0x20ll * ((c) & 0x1f) + 8ll * ((d) & 0x1);
5663 __bdk_csr_fatal("IOBNX_NCBX_ARBX_RWX_LAT_PC", 4, a, b, c, d);
5664 }
5665
5666 #define typedef_BDK_IOBNX_NCBX_ARBX_RWX_LAT_PC(a,b,c,d) bdk_iobnx_ncbx_arbx_rwx_lat_pc_t
5667 #define bustype_BDK_IOBNX_NCBX_ARBX_RWX_LAT_PC(a,b,c,d) BDK_CSR_TYPE_RSL
5668 #define basename_BDK_IOBNX_NCBX_ARBX_RWX_LAT_PC(a,b,c,d) "IOBNX_NCBX_ARBX_RWX_LAT_PC"
5669 #define device_bar_BDK_IOBNX_NCBX_ARBX_RWX_LAT_PC(a,b,c,d) 0x0 /* PF_BAR0 */
5670 #define busnum_BDK_IOBNX_NCBX_ARBX_RWX_LAT_PC(a,b,c,d) (a)
5671 #define arguments_BDK_IOBNX_NCBX_ARBX_RWX_LAT_PC(a,b,c,d) (a),(b),(c),(d)
5672
5673 /**
5674 * Register (RSL) iobn#_ncb#_arb#_rw#_req_pc
5675 *
5676 * IOBN NCB Request Performance Counter Registers
5677 */
5678 union bdk_iobnx_ncbx_arbx_rwx_req_pc
5679 {
5680 uint64_t u;
5681 struct bdk_iobnx_ncbx_arbx_rwx_req_pc_s
5682 {
5683 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5684 uint64_t count : 64; /**< [ 63: 0](R/W/H) Request performance counter.
5685
5686 _ RW(0) increments on read transaction being granted by NGNT.
5687
5688 _ RW(1) increments on write transaction being granted by NGNT. */
5689 #else /* Word 0 - Little Endian */
5690 uint64_t count : 64; /**< [ 63: 0](R/W/H) Request performance counter.
5691
5692 _ RW(0) increments on read transaction being granted by NGNT.
5693
5694 _ RW(1) increments on write transaction being granted by NGNT. */
5695 #endif /* Word 0 - End */
5696 } s;
5697 /* struct bdk_iobnx_ncbx_arbx_rwx_req_pc_s cn; */
5698 };
5699 typedef union bdk_iobnx_ncbx_arbx_rwx_req_pc bdk_iobnx_ncbx_arbx_rwx_req_pc_t;
5700
5701 static inline uint64_t BDK_IOBNX_NCBX_ARBX_RWX_REQ_PC(unsigned long a, unsigned long b, unsigned long c, unsigned long d) __attribute__ ((pure, always_inline));
BDK_IOBNX_NCBX_ARBX_RWX_REQ_PC(unsigned long a,unsigned long b,unsigned long c,unsigned long d)5702 static inline uint64_t BDK_IOBNX_NCBX_ARBX_RWX_REQ_PC(unsigned long a, unsigned long b, unsigned long c, unsigned long d)
5703 {
5704 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b<=2) && (c<=31) && (d<=1)))
5705 return 0x87e0f00f2000ll + 0x1000000ll * ((a) & 0x1) + 0x400ll * ((b) & 0x3) + 0x20ll * ((c) & 0x1f) + 8ll * ((d) & 0x1);
5706 __bdk_csr_fatal("IOBNX_NCBX_ARBX_RWX_REQ_PC", 4, a, b, c, d);
5707 }
5708
5709 #define typedef_BDK_IOBNX_NCBX_ARBX_RWX_REQ_PC(a,b,c,d) bdk_iobnx_ncbx_arbx_rwx_req_pc_t
5710 #define bustype_BDK_IOBNX_NCBX_ARBX_RWX_REQ_PC(a,b,c,d) BDK_CSR_TYPE_RSL
5711 #define basename_BDK_IOBNX_NCBX_ARBX_RWX_REQ_PC(a,b,c,d) "IOBNX_NCBX_ARBX_RWX_REQ_PC"
5712 #define device_bar_BDK_IOBNX_NCBX_ARBX_RWX_REQ_PC(a,b,c,d) 0x0 /* PF_BAR0 */
5713 #define busnum_BDK_IOBNX_NCBX_ARBX_RWX_REQ_PC(a,b,c,d) (a)
5714 #define arguments_BDK_IOBNX_NCBX_ARBX_RWX_REQ_PC(a,b,c,d) (a),(b),(c),(d)
5715
5716 /**
5717 * Register (RSL) iobn#_ncb#_const
5718 *
5719 * IOBN NCB Constant Registers
5720 * This register returns discovery information indexed by each NCB ID (physical address
5721 * bits \<43:36\>). Each index {a} (IOB) returns identical information for a given index {b}.
5722 */
5723 union bdk_iobnx_ncbx_const
5724 {
5725 uint64_t u;
5726 struct bdk_iobnx_ncbx_const_s
5727 {
5728 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5729 uint64_t reserved_24_63 : 40;
5730 uint64_t farbid : 8; /**< [ 23: 16](RO) Flat ARBID for the given NCB ID. */
5731 uint64_t arbid : 8; /**< [ 15: 8](RO) NCB bus ARBID for the given NCB ID. */
5732 uint64_t ncb : 4; /**< [ 7: 4](RO) Physical bus number for the given NCB ID. */
5733 uint64_t iob : 3; /**< [ 3: 1](RO) IOB number for the given NCB ID. */
5734 uint64_t valid : 1; /**< [ 0: 0](RO) Set if this NCB ID is a valid ID. */
5735 #else /* Word 0 - Little Endian */
5736 uint64_t valid : 1; /**< [ 0: 0](RO) Set if this NCB ID is a valid ID. */
5737 uint64_t iob : 3; /**< [ 3: 1](RO) IOB number for the given NCB ID. */
5738 uint64_t ncb : 4; /**< [ 7: 4](RO) Physical bus number for the given NCB ID. */
5739 uint64_t arbid : 8; /**< [ 15: 8](RO) NCB bus ARBID for the given NCB ID. */
5740 uint64_t farbid : 8; /**< [ 23: 16](RO) Flat ARBID for the given NCB ID. */
5741 uint64_t reserved_24_63 : 40;
5742 #endif /* Word 0 - End */
5743 } s;
5744 /* struct bdk_iobnx_ncbx_const_s cn; */
5745 };
5746 typedef union bdk_iobnx_ncbx_const bdk_iobnx_ncbx_const_t;
5747
5748 static inline uint64_t BDK_IOBNX_NCBX_CONST(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_IOBNX_NCBX_CONST(unsigned long a,unsigned long b)5749 static inline uint64_t BDK_IOBNX_NCBX_CONST(unsigned long a, unsigned long b)
5750 {
5751 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b<=255)))
5752 return 0x87e0f0001000ll + 0x1000000ll * ((a) & 0x1) + 8ll * ((b) & 0xff);
5753 __bdk_csr_fatal("IOBNX_NCBX_CONST", 2, a, b, 0, 0);
5754 }
5755
5756 #define typedef_BDK_IOBNX_NCBX_CONST(a,b) bdk_iobnx_ncbx_const_t
5757 #define bustype_BDK_IOBNX_NCBX_CONST(a,b) BDK_CSR_TYPE_RSL
5758 #define basename_BDK_IOBNX_NCBX_CONST(a,b) "IOBNX_NCBX_CONST"
5759 #define device_bar_BDK_IOBNX_NCBX_CONST(a,b) 0x0 /* PF_BAR0 */
5760 #define busnum_BDK_IOBNX_NCBX_CONST(a,b) (a)
5761 #define arguments_BDK_IOBNX_NCBX_CONST(a,b) (a),(b),-1,-1
5762
5763 /**
5764 * Register (RSL) iobn#_ncb#_credits
5765 *
5766 * IOBN NCB Credits Register
5767 * This register controls the number of loads and stores each NCB can have to the L2.
5768 */
5769 union bdk_iobnx_ncbx_credits
5770 {
5771 uint64_t u;
5772 struct bdk_iobnx_ncbx_credits_s
5773 {
5774 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5775 uint64_t reserved_23_63 : 41;
5776 uint64_t ncb_wr_buf_crd : 7; /**< [ 22: 16](R/W) NCB write buffer credit. Each NCB can have 64 write buffers in flight to the L2; this is
5777 the number by which to decrease the 64. */
5778 uint64_t reserved_15 : 1;
5779 uint64_t ncb0_wr_crd : 7; /**< [ 14: 8](R/W) NCB write credit. Each NCB can have 64 writes in flight to the L2; this is the number by
5780 which to
5781 decrease the 64. */
5782 uint64_t reserved_7 : 1;
5783 uint64_t ncb0_rd_crd : 7; /**< [ 6: 0](R/W) NCB read credit. Each NCB can have 64 reads in flight to the L2; this is the number to
5784 decrease the 64 by. */
5785 #else /* Word 0 - Little Endian */
5786 uint64_t ncb0_rd_crd : 7; /**< [ 6: 0](R/W) NCB read credit. Each NCB can have 64 reads in flight to the L2; this is the number to
5787 decrease the 64 by. */
5788 uint64_t reserved_7 : 1;
5789 uint64_t ncb0_wr_crd : 7; /**< [ 14: 8](R/W) NCB write credit. Each NCB can have 64 writes in flight to the L2; this is the number by
5790 which to
5791 decrease the 64. */
5792 uint64_t reserved_15 : 1;
5793 uint64_t ncb_wr_buf_crd : 7; /**< [ 22: 16](R/W) NCB write buffer credit. Each NCB can have 64 write buffers in flight to the L2; this is
5794 the number by which to decrease the 64. */
5795 uint64_t reserved_23_63 : 41;
5796 #endif /* Word 0 - End */
5797 } s;
5798 /* struct bdk_iobnx_ncbx_credits_s cn; */
5799 };
5800 typedef union bdk_iobnx_ncbx_credits bdk_iobnx_ncbx_credits_t;
5801
5802 static inline uint64_t BDK_IOBNX_NCBX_CREDITS(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_IOBNX_NCBX_CREDITS(unsigned long a,unsigned long b)5803 static inline uint64_t BDK_IOBNX_NCBX_CREDITS(unsigned long a, unsigned long b)
5804 {
5805 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b==0)))
5806 return 0x87e0f0001000ll + 0x1000000ll * ((a) & 0x0) + 0x100ll * ((b) & 0x0);
5807 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b<=1)))
5808 return 0x87e0f0001000ll + 0x1000000ll * ((a) & 0x1) + 0x100ll * ((b) & 0x1);
5809 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=1)))
5810 return 0x87e0f0001000ll + 0x1000000ll * ((a) & 0x1) + 0x100ll * ((b) & 0x1);
5811 __bdk_csr_fatal("IOBNX_NCBX_CREDITS", 2, a, b, 0, 0);
5812 }
5813
5814 #define typedef_BDK_IOBNX_NCBX_CREDITS(a,b) bdk_iobnx_ncbx_credits_t
5815 #define bustype_BDK_IOBNX_NCBX_CREDITS(a,b) BDK_CSR_TYPE_RSL
5816 #define basename_BDK_IOBNX_NCBX_CREDITS(a,b) "IOBNX_NCBX_CREDITS"
5817 #define device_bar_BDK_IOBNX_NCBX_CREDITS(a,b) 0x0 /* PF_BAR0 */
5818 #define busnum_BDK_IOBNX_NCBX_CREDITS(a,b) (a)
5819 #define arguments_BDK_IOBNX_NCBX_CREDITS(a,b) (a),(b),-1,-1
5820
5821 /**
5822 * Register (RSL) iobn#_ncb#_ctl
5823 *
5824 * IOBN NCB Control Registers
5825 */
5826 union bdk_iobnx_ncbx_ctl
5827 {
5828 uint64_t u;
5829 struct bdk_iobnx_ncbx_ctl_s
5830 {
5831 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5832 uint64_t reserved_10_63 : 54;
5833 uint64_t stp : 2; /**< [ 9: 8](R/W) When a complete cache block is written a STP will be converted to:
5834 0 = STF.
5835 1 = STY.
5836 2 = STT.
5837 3 = Reserved. */
5838 uint64_t reserved_0_7 : 8;
5839 #else /* Word 0 - Little Endian */
5840 uint64_t reserved_0_7 : 8;
5841 uint64_t stp : 2; /**< [ 9: 8](R/W) When a complete cache block is written a STP will be converted to:
5842 0 = STF.
5843 1 = STY.
5844 2 = STT.
5845 3 = Reserved. */
5846 uint64_t reserved_10_63 : 54;
5847 #endif /* Word 0 - End */
5848 } s;
5849 struct bdk_iobnx_ncbx_ctl_cn8
5850 {
5851 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5852 uint64_t reserved_10_63 : 54;
5853 uint64_t stp : 2; /**< [ 9: 8](R/W) When a complete cache block is written a STP will be converted to:
5854 0 = STF.
5855 1 = STY.
5856 2 = STT.
5857 3 = Reserved. */
5858 uint64_t reserved_2_7 : 6;
5859 uint64_t rstp : 2; /**< [ 1: 0](R/W) When a complete cache block is written a RSTP will be converted to:
5860 0 = STY.
5861 1 = STT.
5862 2 = STF.
5863 3 = Reserved. */
5864 #else /* Word 0 - Little Endian */
5865 uint64_t rstp : 2; /**< [ 1: 0](R/W) When a complete cache block is written a RSTP will be converted to:
5866 0 = STY.
5867 1 = STT.
5868 2 = STF.
5869 3 = Reserved. */
5870 uint64_t reserved_2_7 : 6;
5871 uint64_t stp : 2; /**< [ 9: 8](R/W) When a complete cache block is written a STP will be converted to:
5872 0 = STF.
5873 1 = STY.
5874 2 = STT.
5875 3 = Reserved. */
5876 uint64_t reserved_10_63 : 54;
5877 #endif /* Word 0 - End */
5878 } cn8;
5879 struct bdk_iobnx_ncbx_ctl_cn9
5880 {
5881 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5882 uint64_t reserved_2_63 : 62;
5883 uint64_t dis : 1; /**< [ 1: 1](R/W/H) Disable the opportunistic low latency mode for all ports. For diagnostic use only. */
5884 uint64_t cal : 1; /**< [ 0: 0](R/W/H) Calibration active. Write one to field to start calibration. Cleared when
5885 calibration is complete. For diagnostic use only. */
5886 #else /* Word 0 - Little Endian */
5887 uint64_t cal : 1; /**< [ 0: 0](R/W/H) Calibration active. Write one to field to start calibration. Cleared when
5888 calibration is complete. For diagnostic use only. */
5889 uint64_t dis : 1; /**< [ 1: 1](R/W/H) Disable the opportunistic low latency mode for all ports. For diagnostic use only. */
5890 uint64_t reserved_2_63 : 62;
5891 #endif /* Word 0 - End */
5892 } cn9;
5893 };
5894 typedef union bdk_iobnx_ncbx_ctl bdk_iobnx_ncbx_ctl_t;
5895
5896 static inline uint64_t BDK_IOBNX_NCBX_CTL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_IOBNX_NCBX_CTL(unsigned long a,unsigned long b)5897 static inline uint64_t BDK_IOBNX_NCBX_CTL(unsigned long a, unsigned long b)
5898 {
5899 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b==0)))
5900 return 0x87e0f0004000ll + 0x1000000ll * ((a) & 0x0) + 0x100ll * ((b) & 0x0);
5901 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b<=1)))
5902 return 0x87e0f0004000ll + 0x1000000ll * ((a) & 0x1) + 0x100ll * ((b) & 0x1);
5903 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=1)))
5904 return 0x87e0f0004000ll + 0x1000000ll * ((a) & 0x1) + 0x100ll * ((b) & 0x1);
5905 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b<=2)))
5906 return 0x87e0f00f6000ll + 0x1000000ll * ((a) & 0x1) + 0x400ll * ((b) & 0x3);
5907 __bdk_csr_fatal("IOBNX_NCBX_CTL", 2, a, b, 0, 0);
5908 }
5909
5910 #define typedef_BDK_IOBNX_NCBX_CTL(a,b) bdk_iobnx_ncbx_ctl_t
5911 #define bustype_BDK_IOBNX_NCBX_CTL(a,b) BDK_CSR_TYPE_RSL
5912 #define basename_BDK_IOBNX_NCBX_CTL(a,b) "IOBNX_NCBX_CTL"
5913 #define device_bar_BDK_IOBNX_NCBX_CTL(a,b) 0x0 /* PF_BAR0 */
5914 #define busnum_BDK_IOBNX_NCBX_CTL(a,b) (a)
5915 #define arguments_BDK_IOBNX_NCBX_CTL(a,b) (a),(b),-1,-1
5916
5917 /**
5918 * Register (RSL) iobn#_ncb#_mrml_permit_shadow
5919 *
5920 * INTERNAL: IOBN NCB Access Registers
5921 *
5922 * This register provides a way to read back IOB's IOB captures writes to MRML's
5923 * MRML_NCB()_PERMIT. For diagnostic use only.
5924 */
5925 union bdk_iobnx_ncbx_mrml_permit_shadow
5926 {
5927 uint64_t u;
5928 struct bdk_iobnx_ncbx_mrml_permit_shadow_s
5929 {
5930 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5931 uint64_t reserved_8_63 : 56;
5932 uint64_t kill : 1; /**< [ 7: 7](SRO/H) Kill the device. Once written with one, stays
5933 set until warm chip reset. If set, no access
5934 allowed by any initiator. */
5935 uint64_t reserved_2_6 : 5;
5936 uint64_t nsec_dis : 1; /**< [ 1: 1](SRO/H) Nonsecure disable. As with [SEC_DIS], but for accesses initiated by non-secure devices */
5937 uint64_t sec_dis : 1; /**< [ 0: 0](SRO/H) Secure disable. */
5938 #else /* Word 0 - Little Endian */
5939 uint64_t sec_dis : 1; /**< [ 0: 0](SRO/H) Secure disable. */
5940 uint64_t nsec_dis : 1; /**< [ 1: 1](SRO/H) Nonsecure disable. As with [SEC_DIS], but for accesses initiated by non-secure devices */
5941 uint64_t reserved_2_6 : 5;
5942 uint64_t kill : 1; /**< [ 7: 7](SRO/H) Kill the device. Once written with one, stays
5943 set until warm chip reset. If set, no access
5944 allowed by any initiator. */
5945 uint64_t reserved_8_63 : 56;
5946 #endif /* Word 0 - End */
5947 } s;
5948 /* struct bdk_iobnx_ncbx_mrml_permit_shadow_s cn; */
5949 };
5950 typedef union bdk_iobnx_ncbx_mrml_permit_shadow bdk_iobnx_ncbx_mrml_permit_shadow_t;
5951
5952 static inline uint64_t BDK_IOBNX_NCBX_MRML_PERMIT_SHADOW(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_IOBNX_NCBX_MRML_PERMIT_SHADOW(unsigned long a,unsigned long b)5953 static inline uint64_t BDK_IOBNX_NCBX_MRML_PERMIT_SHADOW(unsigned long a, unsigned long b)
5954 {
5955 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b<=255)))
5956 return 0x87e0f0090000ll + 0x1000000ll * ((a) & 0x1) + 8ll * ((b) & 0xff);
5957 __bdk_csr_fatal("IOBNX_NCBX_MRML_PERMIT_SHADOW", 2, a, b, 0, 0);
5958 }
5959
5960 #define typedef_BDK_IOBNX_NCBX_MRML_PERMIT_SHADOW(a,b) bdk_iobnx_ncbx_mrml_permit_shadow_t
5961 #define bustype_BDK_IOBNX_NCBX_MRML_PERMIT_SHADOW(a,b) BDK_CSR_TYPE_RSL
5962 #define basename_BDK_IOBNX_NCBX_MRML_PERMIT_SHADOW(a,b) "IOBNX_NCBX_MRML_PERMIT_SHADOW"
5963 #define device_bar_BDK_IOBNX_NCBX_MRML_PERMIT_SHADOW(a,b) 0x0 /* PF_BAR0 */
5964 #define busnum_BDK_IOBNX_NCBX_MRML_PERMIT_SHADOW(a,b) (a)
5965 #define arguments_BDK_IOBNX_NCBX_MRML_PERMIT_SHADOW(a,b) (a),(b),-1,-1
5966
5967 /**
5968 * Register (RSL) iobn#_ncb#_rw#_lat_pc
5969 *
5970 * IOBN NCB Latency Performance Counter Registers
5971 */
5972 union bdk_iobnx_ncbx_rwx_lat_pc
5973 {
5974 uint64_t u;
5975 struct bdk_iobnx_ncbx_rwx_lat_pc_s
5976 {
5977 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5978 uint64_t count : 64; /**< [ 63: 0](R/W/H) Latency performance counter.
5979
5980 _ RW(0) increments every cycle by the number of read transactions that have
5981 entered IOB from the given NCB, but have not returned read data to the device.
5982
5983 _ RW(1) increments every cycle by the number of write transactions that have
5984 entered IOB from the given NCB, but have not returned write commits to the
5985 device.
5986
5987 This counter should be divided by IOBN()_NCB()_RW()_REQ_PC to determine each NCB
5988 bus's average read and write latency. */
5989 #else /* Word 0 - Little Endian */
5990 uint64_t count : 64; /**< [ 63: 0](R/W/H) Latency performance counter.
5991
5992 _ RW(0) increments every cycle by the number of read transactions that have
5993 entered IOB from the given NCB, but have not returned read data to the device.
5994
5995 _ RW(1) increments every cycle by the number of write transactions that have
5996 entered IOB from the given NCB, but have not returned write commits to the
5997 device.
5998
5999 This counter should be divided by IOBN()_NCB()_RW()_REQ_PC to determine each NCB
6000 bus's average read and write latency. */
6001 #endif /* Word 0 - End */
6002 } s;
6003 /* struct bdk_iobnx_ncbx_rwx_lat_pc_s cn; */
6004 };
6005 typedef union bdk_iobnx_ncbx_rwx_lat_pc bdk_iobnx_ncbx_rwx_lat_pc_t;
6006
6007 static inline uint64_t BDK_IOBNX_NCBX_RWX_LAT_PC(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_IOBNX_NCBX_RWX_LAT_PC(unsigned long a,unsigned long b,unsigned long c)6008 static inline uint64_t BDK_IOBNX_NCBX_RWX_LAT_PC(unsigned long a, unsigned long b, unsigned long c)
6009 {
6010 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b==0) && (c<=1)))
6011 return 0x87e0f000d000ll + 0x1000000ll * ((a) & 0x0) + 0x100ll * ((b) & 0x0) + 0x10ll * ((c) & 0x1);
6012 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b<=1) && (c<=1)))
6013 return 0x87e0f000d000ll + 0x1000000ll * ((a) & 0x1) + 0x100ll * ((b) & 0x1) + 0x10ll * ((c) & 0x1);
6014 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b<=2) && (c<=1)))
6015 return 0x87e0f000d000ll + 0x1000000ll * ((a) & 0x1) + 0x100ll * ((b) & 0x3) + 0x10ll * ((c) & 0x1);
6016 __bdk_csr_fatal("IOBNX_NCBX_RWX_LAT_PC", 3, a, b, c, 0);
6017 }
6018
6019 #define typedef_BDK_IOBNX_NCBX_RWX_LAT_PC(a,b,c) bdk_iobnx_ncbx_rwx_lat_pc_t
6020 #define bustype_BDK_IOBNX_NCBX_RWX_LAT_PC(a,b,c) BDK_CSR_TYPE_RSL
6021 #define basename_BDK_IOBNX_NCBX_RWX_LAT_PC(a,b,c) "IOBNX_NCBX_RWX_LAT_PC"
6022 #define device_bar_BDK_IOBNX_NCBX_RWX_LAT_PC(a,b,c) 0x0 /* PF_BAR0 */
6023 #define busnum_BDK_IOBNX_NCBX_RWX_LAT_PC(a,b,c) (a)
6024 #define arguments_BDK_IOBNX_NCBX_RWX_LAT_PC(a,b,c) (a),(b),(c),-1
6025
6026 /**
6027 * Register (RSL) iobn#_ncb#_rw#_req_pc
6028 *
6029 * IOBN NCB Request Performance Counter Registers
6030 */
6031 union bdk_iobnx_ncbx_rwx_req_pc
6032 {
6033 uint64_t u;
6034 struct bdk_iobnx_ncbx_rwx_req_pc_s
6035 {
6036 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6037 uint64_t count : 64; /**< [ 63: 0](R/W/H) Request performance counter.
6038
6039 _ RW(0) increments on read transaction entering IOB on given NCB bus.
6040
6041 _ RW(1) increments on write transaction entering IOB on given NCB bus. */
6042 #else /* Word 0 - Little Endian */
6043 uint64_t count : 64; /**< [ 63: 0](R/W/H) Request performance counter.
6044
6045 _ RW(0) increments on read transaction entering IOB on given NCB bus.
6046
6047 _ RW(1) increments on write transaction entering IOB on given NCB bus. */
6048 #endif /* Word 0 - End */
6049 } s;
6050 /* struct bdk_iobnx_ncbx_rwx_req_pc_s cn; */
6051 };
6052 typedef union bdk_iobnx_ncbx_rwx_req_pc bdk_iobnx_ncbx_rwx_req_pc_t;
6053
6054 static inline uint64_t BDK_IOBNX_NCBX_RWX_REQ_PC(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_IOBNX_NCBX_RWX_REQ_PC(unsigned long a,unsigned long b,unsigned long c)6055 static inline uint64_t BDK_IOBNX_NCBX_RWX_REQ_PC(unsigned long a, unsigned long b, unsigned long c)
6056 {
6057 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b==0) && (c<=1)))
6058 return 0x87e0f000c000ll + 0x1000000ll * ((a) & 0x0) + 0x100ll * ((b) & 0x0) + 0x10ll * ((c) & 0x1);
6059 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b<=1) && (c<=1)))
6060 return 0x87e0f000c000ll + 0x1000000ll * ((a) & 0x1) + 0x100ll * ((b) & 0x1) + 0x10ll * ((c) & 0x1);
6061 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX_PASS2_X) && ((a<=1) && (b<=1) && (c<=1)))
6062 return 0x87e0f000c000ll + 0x1000000ll * ((a) & 0x1) + 0x100ll * ((b) & 0x1) + 0x10ll * ((c) & 0x1);
6063 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b<=2) && (c<=1)))
6064 return 0x87e0f000c000ll + 0x1000000ll * ((a) & 0x1) + 0x100ll * ((b) & 0x3) + 0x10ll * ((c) & 0x1);
6065 __bdk_csr_fatal("IOBNX_NCBX_RWX_REQ_PC", 3, a, b, c, 0);
6066 }
6067
6068 #define typedef_BDK_IOBNX_NCBX_RWX_REQ_PC(a,b,c) bdk_iobnx_ncbx_rwx_req_pc_t
6069 #define bustype_BDK_IOBNX_NCBX_RWX_REQ_PC(a,b,c) BDK_CSR_TYPE_RSL
6070 #define basename_BDK_IOBNX_NCBX_RWX_REQ_PC(a,b,c) "IOBNX_NCBX_RWX_REQ_PC"
6071 #define device_bar_BDK_IOBNX_NCBX_RWX_REQ_PC(a,b,c) 0x0 /* PF_BAR0 */
6072 #define busnum_BDK_IOBNX_NCBX_RWX_REQ_PC(a,b,c) (a)
6073 #define arguments_BDK_IOBNX_NCBX_RWX_REQ_PC(a,b,c) (a),(b),(c),-1
6074
6075 /**
6076 * Register (RSL) iobn#_ncb#_rw#_smmu_lat_pc
6077 *
6078 * IOBN NCB SMMU Latency Performance Counter Registers
6079 */
6080 union bdk_iobnx_ncbx_rwx_smmu_lat_pc
6081 {
6082 uint64_t u;
6083 struct bdk_iobnx_ncbx_rwx_smmu_lat_pc_s
6084 {
6085 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6086 uint64_t count : 64; /**< [ 63: 0](R/W/H) SMMU latency performance counter.
6087
6088 _ RW(0) increments every cycle by the number of read transactions that have
6089 entered IOB from the given NCB, but have not been address translated by the
6090 SMMU.
6091
6092 _ RW(1) increments by the number of write transactions that have entered IOB
6093 from the given NCB, but have not been address translated by the SMMU.
6094
6095 This counter should be divided by IOBN()_NCB()_RW()_REQ_PC to determine each NCB
6096 bus's average read and write SMMU plus IOB front-end latency. */
6097 #else /* Word 0 - Little Endian */
6098 uint64_t count : 64; /**< [ 63: 0](R/W/H) SMMU latency performance counter.
6099
6100 _ RW(0) increments every cycle by the number of read transactions that have
6101 entered IOB from the given NCB, but have not been address translated by the
6102 SMMU.
6103
6104 _ RW(1) increments by the number of write transactions that have entered IOB
6105 from the given NCB, but have not been address translated by the SMMU.
6106
6107 This counter should be divided by IOBN()_NCB()_RW()_REQ_PC to determine each NCB
6108 bus's average read and write SMMU plus IOB front-end latency. */
6109 #endif /* Word 0 - End */
6110 } s;
6111 /* struct bdk_iobnx_ncbx_rwx_smmu_lat_pc_s cn; */
6112 };
6113 typedef union bdk_iobnx_ncbx_rwx_smmu_lat_pc bdk_iobnx_ncbx_rwx_smmu_lat_pc_t;
6114
6115 static inline uint64_t BDK_IOBNX_NCBX_RWX_SMMU_LAT_PC(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_IOBNX_NCBX_RWX_SMMU_LAT_PC(unsigned long a,unsigned long b,unsigned long c)6116 static inline uint64_t BDK_IOBNX_NCBX_RWX_SMMU_LAT_PC(unsigned long a, unsigned long b, unsigned long c)
6117 {
6118 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b==0) && (c<=1)))
6119 return 0x87e0f000e000ll + 0x1000000ll * ((a) & 0x0) + 0x100ll * ((b) & 0x0) + 0x10ll * ((c) & 0x1);
6120 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b<=1) && (c<=1)))
6121 return 0x87e0f000e000ll + 0x1000000ll * ((a) & 0x1) + 0x100ll * ((b) & 0x1) + 0x10ll * ((c) & 0x1);
6122 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b<=2) && (c<=1)))
6123 return 0x87e0f000e000ll + 0x1000000ll * ((a) & 0x1) + 0x100ll * ((b) & 0x3) + 0x10ll * ((c) & 0x1);
6124 __bdk_csr_fatal("IOBNX_NCBX_RWX_SMMU_LAT_PC", 3, a, b, c, 0);
6125 }
6126
6127 #define typedef_BDK_IOBNX_NCBX_RWX_SMMU_LAT_PC(a,b,c) bdk_iobnx_ncbx_rwx_smmu_lat_pc_t
6128 #define bustype_BDK_IOBNX_NCBX_RWX_SMMU_LAT_PC(a,b,c) BDK_CSR_TYPE_RSL
6129 #define basename_BDK_IOBNX_NCBX_RWX_SMMU_LAT_PC(a,b,c) "IOBNX_NCBX_RWX_SMMU_LAT_PC"
6130 #define device_bar_BDK_IOBNX_NCBX_RWX_SMMU_LAT_PC(a,b,c) 0x0 /* PF_BAR0 */
6131 #define busnum_BDK_IOBNX_NCBX_RWX_SMMU_LAT_PC(a,b,c) (a)
6132 #define arguments_BDK_IOBNX_NCBX_RWX_SMMU_LAT_PC(a,b,c) (a),(b),(c),-1
6133
6134 /**
6135 * Register (RSL) iobn#_ncb0_hp
6136 *
6137 * IOBN NCBI0 High Performance Register
6138 */
6139 union bdk_iobnx_ncb0_hp
6140 {
6141 uint64_t u;
6142 struct bdk_iobnx_ncb0_hp_s
6143 {
6144 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6145 uint64_t reserved_4_63 : 60;
6146 uint64_t lp : 1; /**< [ 3: 3](R/W) For IOBN0 the reset value for this is 0x1. For IOBN1 the reset value is 0x0.
6147 When set, NCBI 0 ARB 0 request port 3 will use the low performance path through ARB 0. */
6148 uint64_t hp : 3; /**< [ 2: 0](R/W) When set, NCBI 0 ARB 0 will use the high performance path through the IOBN.
6149 Software typically must have IOB(0)_NCB0_HP[HP] set, and IOB(1)_NCB0_HP[HP] clear. */
6150 #else /* Word 0 - Little Endian */
6151 uint64_t hp : 3; /**< [ 2: 0](R/W) When set, NCBI 0 ARB 0 will use the high performance path through the IOBN.
6152 Software typically must have IOB(0)_NCB0_HP[HP] set, and IOB(1)_NCB0_HP[HP] clear. */
6153 uint64_t lp : 1; /**< [ 3: 3](R/W) For IOBN0 the reset value for this is 0x1. For IOBN1 the reset value is 0x0.
6154 When set, NCBI 0 ARB 0 request port 3 will use the low performance path through ARB 0. */
6155 uint64_t reserved_4_63 : 60;
6156 #endif /* Word 0 - End */
6157 } s;
6158 struct bdk_iobnx_ncb0_hp_cn81xx
6159 {
6160 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6161 uint64_t reserved_4_63 : 60;
6162 uint64_t lp : 1; /**< [ 3: 3](R/W) When set, NCBI 0 ARB 0 request port 3 will use the low performance path through ARB 0. */
6163 uint64_t hp : 3; /**< [ 2: 0](R/W) When set, NCBI 0 ARB 0 for request ports 2..0 will use the high performance path through
6164 the IOBN.
6165 Software typically must have IOB(0)_NCB0_HP[HP] = 0x1. */
6166 #else /* Word 0 - Little Endian */
6167 uint64_t hp : 3; /**< [ 2: 0](R/W) When set, NCBI 0 ARB 0 for request ports 2..0 will use the high performance path through
6168 the IOBN.
6169 Software typically must have IOB(0)_NCB0_HP[HP] = 0x1. */
6170 uint64_t lp : 1; /**< [ 3: 3](R/W) When set, NCBI 0 ARB 0 request port 3 will use the low performance path through ARB 0. */
6171 uint64_t reserved_4_63 : 60;
6172 #endif /* Word 0 - End */
6173 } cn81xx;
6174 struct bdk_iobnx_ncb0_hp_cn88xx
6175 {
6176 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6177 uint64_t reserved_1_63 : 63;
6178 uint64_t hp : 1; /**< [ 0: 0](R/W) When set, NCBI 0 ARB 0 will use the high performance path through the IOBN.
6179 Software typically must have IOB(0)_NCB0_HP[HP] set, and IOB(1)_NCB0_HP[HP] clear. */
6180 #else /* Word 0 - Little Endian */
6181 uint64_t hp : 1; /**< [ 0: 0](R/W) When set, NCBI 0 ARB 0 will use the high performance path through the IOBN.
6182 Software typically must have IOB(0)_NCB0_HP[HP] set, and IOB(1)_NCB0_HP[HP] clear. */
6183 uint64_t reserved_1_63 : 63;
6184 #endif /* Word 0 - End */
6185 } cn88xx;
6186 struct bdk_iobnx_ncb0_hp_cn83xx
6187 {
6188 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6189 uint64_t reserved_4_63 : 60;
6190 uint64_t lp : 1; /**< [ 3: 3](R/W) For IOBN0 the reset value for this is 0x1. For IOBN1 the reset value is 0x0.
6191 When set, NCBI 0 ARB 0 request port 3 will use the low performance path through ARB 0. */
6192 uint64_t hp : 3; /**< [ 2: 0](R/W) For IOBN0 the reset value for this is 0x7. For IOBN1 the reset value is 0x0.
6193 When set, NCBI 0 ARB 0 for request ports 2..0 will use the high performance path through
6194 the IOBN.
6195 Software typically must have IOB(0)_NCB0_HP[HP] = 0x7, and IOB(1)_NCB0_HP[HP] = 0x0. */
6196 #else /* Word 0 - Little Endian */
6197 uint64_t hp : 3; /**< [ 2: 0](R/W) For IOBN0 the reset value for this is 0x7. For IOBN1 the reset value is 0x0.
6198 When set, NCBI 0 ARB 0 for request ports 2..0 will use the high performance path through
6199 the IOBN.
6200 Software typically must have IOB(0)_NCB0_HP[HP] = 0x7, and IOB(1)_NCB0_HP[HP] = 0x0. */
6201 uint64_t lp : 1; /**< [ 3: 3](R/W) For IOBN0 the reset value for this is 0x1. For IOBN1 the reset value is 0x0.
6202 When set, NCBI 0 ARB 0 request port 3 will use the low performance path through ARB 0. */
6203 uint64_t reserved_4_63 : 60;
6204 #endif /* Word 0 - End */
6205 } cn83xx;
6206 };
6207 typedef union bdk_iobnx_ncb0_hp bdk_iobnx_ncb0_hp_t;
6208
6209 static inline uint64_t BDK_IOBNX_NCB0_HP(unsigned long a) __attribute__ ((pure, always_inline));
BDK_IOBNX_NCB0_HP(unsigned long a)6210 static inline uint64_t BDK_IOBNX_NCB0_HP(unsigned long a)
6211 {
6212 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
6213 return 0x87e0f0003008ll + 0x1000000ll * ((a) & 0x0);
6214 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
6215 return 0x87e0f0003008ll + 0x1000000ll * ((a) & 0x1);
6216 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
6217 return 0x87e0f0003008ll + 0x1000000ll * ((a) & 0x1);
6218 __bdk_csr_fatal("IOBNX_NCB0_HP", 1, a, 0, 0, 0);
6219 }
6220
6221 #define typedef_BDK_IOBNX_NCB0_HP(a) bdk_iobnx_ncb0_hp_t
6222 #define bustype_BDK_IOBNX_NCB0_HP(a) BDK_CSR_TYPE_RSL
6223 #define basename_BDK_IOBNX_NCB0_HP(a) "IOBNX_NCB0_HP"
6224 #define device_bar_BDK_IOBNX_NCB0_HP(a) 0x0 /* PF_BAR0 */
6225 #define busnum_BDK_IOBNX_NCB0_HP(a) (a)
6226 #define arguments_BDK_IOBNX_NCB0_HP(a) (a),-1,-1,-1
6227
6228 /**
6229 * Register (RSL) iobn#_ncb0_sdis#
6230 *
6231 * IOBN NCB Secure Disable Register
6232 */
6233 union bdk_iobnx_ncb0_sdisx
6234 {
6235 uint64_t u;
6236 struct bdk_iobnx_ncb0_sdisx_s
6237 {
6238 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6239 uint64_t did : 64; /**< [ 63: 0](SR/W) When set a secure operation is required to access the NCBDID. If a nonsecure
6240 operation occurs it will result in a R/W to ECAM0_NOP_ZF.
6241
6242 Index 0 corresponds to DIDs 63:0, index 1 to DIDs 127:64, index 2 to DISs
6243 191:128, and index 3 to DIDs 255:192.
6244
6245 Each IOB instance should be programmed identically, and should also be identical
6246 to MRML_NCB()_SDEV. */
6247 #else /* Word 0 - Little Endian */
6248 uint64_t did : 64; /**< [ 63: 0](SR/W) When set a secure operation is required to access the NCBDID. If a nonsecure
6249 operation occurs it will result in a R/W to ECAM0_NOP_ZF.
6250
6251 Index 0 corresponds to DIDs 63:0, index 1 to DIDs 127:64, index 2 to DISs
6252 191:128, and index 3 to DIDs 255:192.
6253
6254 Each IOB instance should be programmed identically, and should also be identical
6255 to MRML_NCB()_SDEV. */
6256 #endif /* Word 0 - End */
6257 } s;
6258 /* struct bdk_iobnx_ncb0_sdisx_s cn; */
6259 };
6260 typedef union bdk_iobnx_ncb0_sdisx bdk_iobnx_ncb0_sdisx_t;
6261
6262 static inline uint64_t BDK_IOBNX_NCB0_SDISX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_IOBNX_NCB0_SDISX(unsigned long a,unsigned long b)6263 static inline uint64_t BDK_IOBNX_NCB0_SDISX(unsigned long a, unsigned long b)
6264 {
6265 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b<=3)))
6266 return 0x87e0f0002000ll + 0x1000000ll * ((a) & 0x0) + 0x100ll * ((b) & 0x3);
6267 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b<=3)))
6268 return 0x87e0f0002000ll + 0x1000000ll * ((a) & 0x1) + 0x100ll * ((b) & 0x3);
6269 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
6270 return 0x87e0f0002000ll + 0x1000000ll * ((a) & 0x1) + 0x100ll * ((b) & 0x3);
6271 __bdk_csr_fatal("IOBNX_NCB0_SDISX", 2, a, b, 0, 0);
6272 }
6273
6274 #define typedef_BDK_IOBNX_NCB0_SDISX(a,b) bdk_iobnx_ncb0_sdisx_t
6275 #define bustype_BDK_IOBNX_NCB0_SDISX(a,b) BDK_CSR_TYPE_RSL
6276 #define basename_BDK_IOBNX_NCB0_SDISX(a,b) "IOBNX_NCB0_SDISX"
6277 #define device_bar_BDK_IOBNX_NCB0_SDISX(a,b) 0x0 /* PF_BAR0 */
6278 #define busnum_BDK_IOBNX_NCB0_SDISX(a,b) (a)
6279 #define arguments_BDK_IOBNX_NCB0_SDISX(a,b) (a),(b),-1,-1
6280
6281 /**
6282 * Register (RSL) iobn#_ncb0_skill#
6283 *
6284 * IOBN NCB Secure Kill-Device Registers
6285 */
6286 union bdk_iobnx_ncb0_skillx
6287 {
6288 uint64_t u;
6289 struct bdk_iobnx_ncb0_skillx_s
6290 {
6291 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6292 uint64_t skill : 64; /**< [ 63: 0](SR/W1S) NCB function kill. If set, any operation to this device will be will be directed
6293 to ECAM0_NOP_ZF. Write one to set, once set cannot be cleared until soft reset.
6294
6295 Index 0 corresponds to DIDs 63:0, index 1 to DIDs 127:64, index 2 to DISs
6296 191:128, and index 3 to DIDs 255:192.
6297
6298 Each IOB instance should be programmed identically, and should also be identical
6299 to MRML_NCB()_SKILL. */
6300 #else /* Word 0 - Little Endian */
6301 uint64_t skill : 64; /**< [ 63: 0](SR/W1S) NCB function kill. If set, any operation to this device will be will be directed
6302 to ECAM0_NOP_ZF. Write one to set, once set cannot be cleared until soft reset.
6303
6304 Index 0 corresponds to DIDs 63:0, index 1 to DIDs 127:64, index 2 to DISs
6305 191:128, and index 3 to DIDs 255:192.
6306
6307 Each IOB instance should be programmed identically, and should also be identical
6308 to MRML_NCB()_SKILL. */
6309 #endif /* Word 0 - End */
6310 } s;
6311 /* struct bdk_iobnx_ncb0_skillx_s cn; */
6312 };
6313 typedef union bdk_iobnx_ncb0_skillx bdk_iobnx_ncb0_skillx_t;
6314
6315 static inline uint64_t BDK_IOBNX_NCB0_SKILLX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_IOBNX_NCB0_SKILLX(unsigned long a,unsigned long b)6316 static inline uint64_t BDK_IOBNX_NCB0_SKILLX(unsigned long a, unsigned long b)
6317 {
6318 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b<=3)))
6319 return 0x87e0f000b000ll + 0x1000000ll * ((a) & 0x0) + 0x100ll * ((b) & 0x3);
6320 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b<=3)))
6321 return 0x87e0f000b000ll + 0x1000000ll * ((a) & 0x1) + 0x100ll * ((b) & 0x3);
6322 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX_PASS2_X) && ((a<=1) && (b<=3)))
6323 return 0x87e0f000b000ll + 0x1000000ll * ((a) & 0x1) + 0x100ll * ((b) & 0x3);
6324 __bdk_csr_fatal("IOBNX_NCB0_SKILLX", 2, a, b, 0, 0);
6325 }
6326
6327 #define typedef_BDK_IOBNX_NCB0_SKILLX(a,b) bdk_iobnx_ncb0_skillx_t
6328 #define bustype_BDK_IOBNX_NCB0_SKILLX(a,b) BDK_CSR_TYPE_RSL
6329 #define basename_BDK_IOBNX_NCB0_SKILLX(a,b) "IOBNX_NCB0_SKILLX"
6330 #define device_bar_BDK_IOBNX_NCB0_SKILLX(a,b) 0x0 /* PF_BAR0 */
6331 #define busnum_BDK_IOBNX_NCB0_SKILLX(a,b) (a)
6332 #define arguments_BDK_IOBNX_NCB0_SKILLX(a,b) (a),(b),-1,-1
6333
6334 /**
6335 * Register (RSL) iobn#_ncbo#_psn_status
6336 *
6337 * IOBN NCBO Poison Status Register
6338 */
6339 union bdk_iobnx_ncbox_psn_status
6340 {
6341 uint64_t u;
6342 struct bdk_iobnx_ncbox_psn_status_s
6343 {
6344 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6345 uint64_t reserved_52_63 : 12;
6346 uint64_t address : 52; /**< [ 51: 0](RO/H) Captured address when poison transaction was sent on NCBO. Valid when
6347 corresponding bit is set in IOBN()_INT_SUM .
6348 When corresponding bit in IOBN()_INT_SUM is cleared allows a new poison error to be latched. */
6349 #else /* Word 0 - Little Endian */
6350 uint64_t address : 52; /**< [ 51: 0](RO/H) Captured address when poison transaction was sent on NCBO. Valid when
6351 corresponding bit is set in IOBN()_INT_SUM .
6352 When corresponding bit in IOBN()_INT_SUM is cleared allows a new poison error to be latched. */
6353 uint64_t reserved_52_63 : 12;
6354 #endif /* Word 0 - End */
6355 } s;
6356 /* struct bdk_iobnx_ncbox_psn_status_s cn; */
6357 };
6358 typedef union bdk_iobnx_ncbox_psn_status bdk_iobnx_ncbox_psn_status_t;
6359
6360 static inline uint64_t BDK_IOBNX_NCBOX_PSN_STATUS(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_IOBNX_NCBOX_PSN_STATUS(unsigned long a,unsigned long b)6361 static inline uint64_t BDK_IOBNX_NCBOX_PSN_STATUS(unsigned long a, unsigned long b)
6362 {
6363 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b<=2)))
6364 return 0x87e0f0003060ll + 0x1000000ll * ((a) & 0x1) + 8ll * ((b) & 0x3);
6365 __bdk_csr_fatal("IOBNX_NCBOX_PSN_STATUS", 2, a, b, 0, 0);
6366 }
6367
6368 #define typedef_BDK_IOBNX_NCBOX_PSN_STATUS(a,b) bdk_iobnx_ncbox_psn_status_t
6369 #define bustype_BDK_IOBNX_NCBOX_PSN_STATUS(a,b) BDK_CSR_TYPE_RSL
6370 #define basename_BDK_IOBNX_NCBOX_PSN_STATUS(a,b) "IOBNX_NCBOX_PSN_STATUS"
6371 #define device_bar_BDK_IOBNX_NCBOX_PSN_STATUS(a,b) 0x0 /* PF_BAR0 */
6372 #define busnum_BDK_IOBNX_NCBOX_PSN_STATUS(a,b) (a)
6373 #define arguments_BDK_IOBNX_NCBOX_PSN_STATUS(a,b) (a),(b),-1,-1
6374
6375 /**
6376 * Register (RSL) iobn#_ncbo_ctl
6377 *
6378 * IOBN NCBO control Registers
6379 * This register set controls for NCBO processing.
6380 */
6381 union bdk_iobnx_ncbo_ctl
6382 {
6383 uint64_t u;
6384 struct bdk_iobnx_ncbo_ctl_s
6385 {
6386 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6387 uint64_t reserved_7_63 : 57;
6388 uint64_t clken : 3; /**< [ 6: 4](R/W) Force the NCBO clock enable to be always on. For diagnostic use only.
6389 Each bit is control for a given ncb bus, where bit 4 is for ncb bus 0 and bit 6 is for ncb bus 2. */
6390 uint64_t reserved_3 : 1;
6391 uint64_t bypass_ena : 3; /**< [ 2: 0](R/W) When set allows requests to bypass FIFO and go directly to output of NCBO bus, when FIFO is empty.
6392 Each bit is control for a given ncb bus, where bit 0 is for ncb bus 0 and bit 2 is for ncb bus 2.
6393
6394 Internal:
6395 FIXME rename bypass_dis and default to on (0x0), and then describe as diag only. */
6396 #else /* Word 0 - Little Endian */
6397 uint64_t bypass_ena : 3; /**< [ 2: 0](R/W) When set allows requests to bypass FIFO and go directly to output of NCBO bus, when FIFO is empty.
6398 Each bit is control for a given ncb bus, where bit 0 is for ncb bus 0 and bit 2 is for ncb bus 2.
6399
6400 Internal:
6401 FIXME rename bypass_dis and default to on (0x0), and then describe as diag only. */
6402 uint64_t reserved_3 : 1;
6403 uint64_t clken : 3; /**< [ 6: 4](R/W) Force the NCBO clock enable to be always on. For diagnostic use only.
6404 Each bit is control for a given ncb bus, where bit 4 is for ncb bus 0 and bit 6 is for ncb bus 2. */
6405 uint64_t reserved_7_63 : 57;
6406 #endif /* Word 0 - End */
6407 } s;
6408 /* struct bdk_iobnx_ncbo_ctl_s cn; */
6409 };
6410 typedef union bdk_iobnx_ncbo_ctl bdk_iobnx_ncbo_ctl_t;
6411
6412 static inline uint64_t BDK_IOBNX_NCBO_CTL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_IOBNX_NCBO_CTL(unsigned long a)6413 static inline uint64_t BDK_IOBNX_NCBO_CTL(unsigned long a)
6414 {
6415 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
6416 return 0x87e0f0002200ll + 0x1000000ll * ((a) & 0x1);
6417 __bdk_csr_fatal("IOBNX_NCBO_CTL", 1, a, 0, 0, 0);
6418 }
6419
6420 #define typedef_BDK_IOBNX_NCBO_CTL(a) bdk_iobnx_ncbo_ctl_t
6421 #define bustype_BDK_IOBNX_NCBO_CTL(a) BDK_CSR_TYPE_RSL
6422 #define basename_BDK_IOBNX_NCBO_CTL(a) "IOBNX_NCBO_CTL"
6423 #define device_bar_BDK_IOBNX_NCBO_CTL(a) 0x0 /* PF_BAR0 */
6424 #define busnum_BDK_IOBNX_NCBO_CTL(a) (a)
6425 #define arguments_BDK_IOBNX_NCBO_CTL(a) (a),-1,-1,-1
6426
6427 /**
6428 * Register (RSL) iobn#_ncbo_to
6429 *
6430 * IOBN NCBO Timeout Counter Registers
6431 * This register set the counter value for expected return data on NCBI.
6432 */
6433 union bdk_iobnx_ncbo_to
6434 {
6435 uint64_t u;
6436 struct bdk_iobnx_ncbo_to_s
6437 {
6438 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6439 uint64_t reserved_32_63 : 32;
6440 uint64_t sub_time : 32; /**< [ 31: 0](R/W) Timeout value. When a load operation is sent on NCBO, the timeout counter is
6441 started, and if return data on NCBI does not return within between three to four
6442 times the value of [SUB_TIME] in coprocessor-clocks, a timeout occurs and
6443 IOBN()_INT_SUM[NCBO_TO] is set. 0x0 disables. */
6444 #else /* Word 0 - Little Endian */
6445 uint64_t sub_time : 32; /**< [ 31: 0](R/W) Timeout value. When a load operation is sent on NCBO, the timeout counter is
6446 started, and if return data on NCBI does not return within between three to four
6447 times the value of [SUB_TIME] in coprocessor-clocks, a timeout occurs and
6448 IOBN()_INT_SUM[NCBO_TO] is set. 0x0 disables. */
6449 uint64_t reserved_32_63 : 32;
6450 #endif /* Word 0 - End */
6451 } s;
6452 /* struct bdk_iobnx_ncbo_to_s cn; */
6453 };
6454 typedef union bdk_iobnx_ncbo_to bdk_iobnx_ncbo_to_t;
6455
6456 static inline uint64_t BDK_IOBNX_NCBO_TO(unsigned long a) __attribute__ ((pure, always_inline));
BDK_IOBNX_NCBO_TO(unsigned long a)6457 static inline uint64_t BDK_IOBNX_NCBO_TO(unsigned long a)
6458 {
6459 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
6460 return 0x87e0f0000008ll + 0x1000000ll * ((a) & 0x1);
6461 __bdk_csr_fatal("IOBNX_NCBO_TO", 1, a, 0, 0, 0);
6462 }
6463
6464 #define typedef_BDK_IOBNX_NCBO_TO(a) bdk_iobnx_ncbo_to_t
6465 #define bustype_BDK_IOBNX_NCBO_TO(a) BDK_CSR_TYPE_RSL
6466 #define basename_BDK_IOBNX_NCBO_TO(a) "IOBNX_NCBO_TO"
6467 #define device_bar_BDK_IOBNX_NCBO_TO(a) 0x0 /* PF_BAR0 */
6468 #define busnum_BDK_IOBNX_NCBO_TO(a) (a)
6469 #define arguments_BDK_IOBNX_NCBO_TO(a) (a),-1,-1,-1
6470
6471 /**
6472 * Register (RSL) iobn#_ncbo_to_err
6473 *
6474 * IOBN NCB Timeout Error Register
6475 * This register captures error information for a non-posted request that times out on
6476 * NCBO (when IOBN()_INT_SUM[NCBO_TO] is set).
6477 */
6478 union bdk_iobnx_ncbo_to_err
6479 {
6480 uint64_t u;
6481 struct bdk_iobnx_ncbo_to_err_s
6482 {
6483 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6484 uint64_t reserved_17_63 : 47;
6485 uint64_t cpid : 9; /**< [ 16: 8](RO/H) CPID for NP request that timed out on NCBO. */
6486 uint64_t reserved_5_7 : 3;
6487 uint64_t arbid : 5; /**< [ 4: 0](RO/H) Flat ARBID for NP request that timed out on NCBO. */
6488 #else /* Word 0 - Little Endian */
6489 uint64_t arbid : 5; /**< [ 4: 0](RO/H) Flat ARBID for NP request that timed out on NCBO. */
6490 uint64_t reserved_5_7 : 3;
6491 uint64_t cpid : 9; /**< [ 16: 8](RO/H) CPID for NP request that timed out on NCBO. */
6492 uint64_t reserved_17_63 : 47;
6493 #endif /* Word 0 - End */
6494 } s;
6495 /* struct bdk_iobnx_ncbo_to_err_s cn; */
6496 };
6497 typedef union bdk_iobnx_ncbo_to_err bdk_iobnx_ncbo_to_err_t;
6498
6499 static inline uint64_t BDK_IOBNX_NCBO_TO_ERR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_IOBNX_NCBO_TO_ERR(unsigned long a)6500 static inline uint64_t BDK_IOBNX_NCBO_TO_ERR(unsigned long a)
6501 {
6502 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
6503 return 0x87e0f00a0000ll + 0x1000000ll * ((a) & 0x1);
6504 __bdk_csr_fatal("IOBNX_NCBO_TO_ERR", 1, a, 0, 0, 0);
6505 }
6506
6507 #define typedef_BDK_IOBNX_NCBO_TO_ERR(a) bdk_iobnx_ncbo_to_err_t
6508 #define bustype_BDK_IOBNX_NCBO_TO_ERR(a) BDK_CSR_TYPE_RSL
6509 #define basename_BDK_IOBNX_NCBO_TO_ERR(a) "IOBNX_NCBO_TO_ERR"
6510 #define device_bar_BDK_IOBNX_NCBO_TO_ERR(a) 0x0 /* PF_BAR0 */
6511 #define busnum_BDK_IOBNX_NCBO_TO_ERR(a) (a)
6512 #define arguments_BDK_IOBNX_NCBO_TO_ERR(a) (a),-1,-1,-1
6513
6514 /**
6515 * Register (RSL) iobn#_psn_ctl
6516 *
6517 * Poison Control Register
6518 */
6519 union bdk_iobnx_psn_ctl
6520 {
6521 uint64_t u;
6522 struct bdk_iobnx_psn_ctl_s
6523 {
6524 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6525 uint64_t reserved_1_63 : 63;
6526 uint64_t dispsn : 1; /**< [ 0: 0](R/W) Disable poison code creation and detection in the mesh / NCB ECC
6527 checkers/generators. */
6528 #else /* Word 0 - Little Endian */
6529 uint64_t dispsn : 1; /**< [ 0: 0](R/W) Disable poison code creation and detection in the mesh / NCB ECC
6530 checkers/generators. */
6531 uint64_t reserved_1_63 : 63;
6532 #endif /* Word 0 - End */
6533 } s;
6534 /* struct bdk_iobnx_psn_ctl_s cn; */
6535 };
6536 typedef union bdk_iobnx_psn_ctl bdk_iobnx_psn_ctl_t;
6537
6538 static inline uint64_t BDK_IOBNX_PSN_CTL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_IOBNX_PSN_CTL(unsigned long a)6539 static inline uint64_t BDK_IOBNX_PSN_CTL(unsigned long a)
6540 {
6541 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
6542 return 0x87e0f0003050ll + 0x1000000ll * ((a) & 0x1);
6543 __bdk_csr_fatal("IOBNX_PSN_CTL", 1, a, 0, 0, 0);
6544 }
6545
6546 #define typedef_BDK_IOBNX_PSN_CTL(a) bdk_iobnx_psn_ctl_t
6547 #define bustype_BDK_IOBNX_PSN_CTL(a) BDK_CSR_TYPE_RSL
6548 #define basename_BDK_IOBNX_PSN_CTL(a) "IOBNX_PSN_CTL"
6549 #define device_bar_BDK_IOBNX_PSN_CTL(a) 0x0 /* PF_BAR0 */
6550 #define busnum_BDK_IOBNX_PSN_CTL(a) (a)
6551 #define arguments_BDK_IOBNX_PSN_CTL(a) (a),-1,-1,-1
6552
6553 /**
6554 * Register (RSL) iobn#_roc_dll
6555 *
6556 * INTERNAL: IOBN Global Core-Clock DLL Status Register
6557 *
6558 * Status of the ROC core-clock DLL.
6559 */
6560 union bdk_iobnx_roc_dll
6561 {
6562 uint64_t u;
6563 struct bdk_iobnx_roc_dll_s
6564 {
6565 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6566 uint64_t reserved_60_63 : 4;
6567 uint64_t max_dll_setting : 12; /**< [ 59: 48](RO/H) Max reported DLL setting. */
6568 uint64_t min_dll_setting : 12; /**< [ 47: 36](RO/H) Min reported DLL setting. */
6569 uint64_t reserved_32_35 : 4;
6570 uint64_t pdr_rclk_refclk : 1; /**< [ 31: 31](RO/H) Synchronized pdr_rclk_refclk from ROC core-clock DLL cmb0 phase detectors. */
6571 uint64_t pdl_rclk_refclk : 1; /**< [ 30: 30](RO/H) Synchronized pdl_rclk_refclk from ROC core-clock DLL cmb0 phase detectors. */
6572 uint64_t pd_pos_rclk_refclk : 1; /**< [ 29: 29](RO/H) Synchronized pd_pos_rclk_refclk from ROC core-clock DLL cmb0 phase detectors. */
6573 uint64_t dll_lock : 1; /**< [ 28: 28](RO/H) The dll_lock signal from ROC core-clock DLL, from the positive edge of refclk. */
6574 uint64_t dll_dly_elem_en : 16; /**< [ 27: 12](RO/H) The ROC core-clock delay element enable setting, from the negative edge of refclk. */
6575 uint64_t dll_setting : 12; /**< [ 11: 0](RO/H) The ROC core-clock DLL setting, from the negative edge of refclk. */
6576 #else /* Word 0 - Little Endian */
6577 uint64_t dll_setting : 12; /**< [ 11: 0](RO/H) The ROC core-clock DLL setting, from the negative edge of refclk. */
6578 uint64_t dll_dly_elem_en : 16; /**< [ 27: 12](RO/H) The ROC core-clock delay element enable setting, from the negative edge of refclk. */
6579 uint64_t dll_lock : 1; /**< [ 28: 28](RO/H) The dll_lock signal from ROC core-clock DLL, from the positive edge of refclk. */
6580 uint64_t pd_pos_rclk_refclk : 1; /**< [ 29: 29](RO/H) Synchronized pd_pos_rclk_refclk from ROC core-clock DLL cmb0 phase detectors. */
6581 uint64_t pdl_rclk_refclk : 1; /**< [ 30: 30](RO/H) Synchronized pdl_rclk_refclk from ROC core-clock DLL cmb0 phase detectors. */
6582 uint64_t pdr_rclk_refclk : 1; /**< [ 31: 31](RO/H) Synchronized pdr_rclk_refclk from ROC core-clock DLL cmb0 phase detectors. */
6583 uint64_t reserved_32_35 : 4;
6584 uint64_t min_dll_setting : 12; /**< [ 47: 36](RO/H) Min reported DLL setting. */
6585 uint64_t max_dll_setting : 12; /**< [ 59: 48](RO/H) Max reported DLL setting. */
6586 uint64_t reserved_60_63 : 4;
6587 #endif /* Word 0 - End */
6588 } s;
6589 struct bdk_iobnx_roc_dll_cn88xxp1
6590 {
6591 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6592 uint64_t reserved_32_63 : 32;
6593 uint64_t pdr_rclk_refclk : 1; /**< [ 31: 31](RO/H) Synchronized pdr_rclk_refclk from ROC core-clock DLL cmb0 phase detectors. */
6594 uint64_t pdl_rclk_refclk : 1; /**< [ 30: 30](RO/H) Synchronized pdl_rclk_refclk from ROC core-clock DLL cmb0 phase detectors. */
6595 uint64_t pd_pos_rclk_refclk : 1; /**< [ 29: 29](RO/H) Synchronized pd_pos_rclk_refclk from ROC core-clock DLL cmb0 phase detectors. */
6596 uint64_t dll_lock : 1; /**< [ 28: 28](RO/H) The dll_lock signal from ROC core-clock DLL, from the positive edge of refclk. */
6597 uint64_t dll_dly_elem_en : 16; /**< [ 27: 12](RO/H) The ROC core-clock delay element enable setting, from the negative edge of refclk. */
6598 uint64_t dll_setting : 12; /**< [ 11: 0](RO/H) The ROC core-clock DLL setting, from the negative edge of refclk. */
6599 #else /* Word 0 - Little Endian */
6600 uint64_t dll_setting : 12; /**< [ 11: 0](RO/H) The ROC core-clock DLL setting, from the negative edge of refclk. */
6601 uint64_t dll_dly_elem_en : 16; /**< [ 27: 12](RO/H) The ROC core-clock delay element enable setting, from the negative edge of refclk. */
6602 uint64_t dll_lock : 1; /**< [ 28: 28](RO/H) The dll_lock signal from ROC core-clock DLL, from the positive edge of refclk. */
6603 uint64_t pd_pos_rclk_refclk : 1; /**< [ 29: 29](RO/H) Synchronized pd_pos_rclk_refclk from ROC core-clock DLL cmb0 phase detectors. */
6604 uint64_t pdl_rclk_refclk : 1; /**< [ 30: 30](RO/H) Synchronized pdl_rclk_refclk from ROC core-clock DLL cmb0 phase detectors. */
6605 uint64_t pdr_rclk_refclk : 1; /**< [ 31: 31](RO/H) Synchronized pdr_rclk_refclk from ROC core-clock DLL cmb0 phase detectors. */
6606 uint64_t reserved_32_63 : 32;
6607 #endif /* Word 0 - End */
6608 } cn88xxp1;
6609 /* struct bdk_iobnx_roc_dll_s cn81xx; */
6610 /* struct bdk_iobnx_roc_dll_s cn83xx; */
6611 /* struct bdk_iobnx_roc_dll_s cn88xxp2; */
6612 };
6613 typedef union bdk_iobnx_roc_dll bdk_iobnx_roc_dll_t;
6614
6615 static inline uint64_t BDK_IOBNX_ROC_DLL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_IOBNX_ROC_DLL(unsigned long a)6616 static inline uint64_t BDK_IOBNX_ROC_DLL(unsigned long a)
6617 {
6618 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
6619 return 0x87e0f000a008ll + 0x1000000ll * ((a) & 0x0);
6620 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
6621 return 0x87e0f000a008ll + 0x1000000ll * ((a) & 0x1);
6622 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
6623 return 0x87e0f000a008ll + 0x1000000ll * ((a) & 0x1);
6624 __bdk_csr_fatal("IOBNX_ROC_DLL", 1, a, 0, 0, 0);
6625 }
6626
6627 #define typedef_BDK_IOBNX_ROC_DLL(a) bdk_iobnx_roc_dll_t
6628 #define bustype_BDK_IOBNX_ROC_DLL(a) BDK_CSR_TYPE_RSL
6629 #define basename_BDK_IOBNX_ROC_DLL(a) "IOBNX_ROC_DLL"
6630 #define device_bar_BDK_IOBNX_ROC_DLL(a) 0x0 /* PF_BAR0 */
6631 #define busnum_BDK_IOBNX_ROC_DLL(a) (a)
6632 #define arguments_BDK_IOBNX_ROC_DLL(a) (a),-1,-1,-1
6633
6634 /**
6635 * Register (RSL) iobn#_rsl#_streams
6636 *
6637 * IOBN RSL Stream Permission Registers
6638 * This register sets the permissions for a NCBI transaction (which are DMA
6639 * transactions or MSI-X writes), for requests from a RSL device, i.e.
6640 * those where:
6641 *
6642 * _ stream_id\<21:8\> = PCC_DEV_CON_E::MRML\<21:8\>
6643 *
6644 * Index {b} corresponds to the PCC function number for the RSL device
6645 * (stream_id\<7:0\>).
6646 *
6647 * For each given index {b} (the RSL function number), each index {a} (the IOB number)
6648 * must be programmed to the same value.
6649 */
6650 union bdk_iobnx_rslx_streams
6651 {
6652 uint64_t u;
6653 struct bdk_iobnx_rslx_streams_s
6654 {
6655 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6656 uint64_t reserved_2_63 : 62;
6657 uint64_t strm_nsec : 1; /**< [ 1: 1](SR/W) Stream nonsecure.
6658
6659 0 = The device's stream ID is marked secure headed into the SMMU. If the
6660 device is making a non-physical request, the SMMU will use secure world
6661 lookup. The SMMU may, if properly configured, generate an outgoing physical
6662 address that is secure.
6663
6664 1 = The device's stream ID is marked nonsecure headed into the SMMU. If the
6665 device is making a non-physical request, the SMMU will use nonsecure world
6666 lookup. The SMMU outgoing physical address will be nonsecure.
6667
6668 [STRM_NSEC] is ignored if the device is making a physical request (as these
6669 transactions bypass the SMMU translation process).
6670
6671 Typically firmware sets [PHYS_NSEC] and [STRM_NSEC] the same. */
6672 uint64_t phys_nsec : 1; /**< [ 0: 0](SR/W) Physical nonsecure.
6673 0 = When the device makes a physical request, IOB will use the device's
6674 requested secure bit to determine if the request to DRAM/LLC is secure or not.
6675 1 = When the device makes a physical request, IOB will squash the
6676 device's secure request and issue the request to DRAM/LLC as nonsecure.
6677
6678 Ignored if a device makes a non-physical request. (As non-physical requests
6679 cause the SMMU to generate the SMMU-outgoing secure bit based on the SMMU
6680 translation process, including [STRM_NSEC].)
6681
6682 Typically firmware sets [PHYS_NSEC] and [STRM_NSEC] the same. */
6683 #else /* Word 0 - Little Endian */
6684 uint64_t phys_nsec : 1; /**< [ 0: 0](SR/W) Physical nonsecure.
6685 0 = When the device makes a physical request, IOB will use the device's
6686 requested secure bit to determine if the request to DRAM/LLC is secure or not.
6687 1 = When the device makes a physical request, IOB will squash the
6688 device's secure request and issue the request to DRAM/LLC as nonsecure.
6689
6690 Ignored if a device makes a non-physical request. (As non-physical requests
6691 cause the SMMU to generate the SMMU-outgoing secure bit based on the SMMU
6692 translation process, including [STRM_NSEC].)
6693
6694 Typically firmware sets [PHYS_NSEC] and [STRM_NSEC] the same. */
6695 uint64_t strm_nsec : 1; /**< [ 1: 1](SR/W) Stream nonsecure.
6696
6697 0 = The device's stream ID is marked secure headed into the SMMU. If the
6698 device is making a non-physical request, the SMMU will use secure world
6699 lookup. The SMMU may, if properly configured, generate an outgoing physical
6700 address that is secure.
6701
6702 1 = The device's stream ID is marked nonsecure headed into the SMMU. If the
6703 device is making a non-physical request, the SMMU will use nonsecure world
6704 lookup. The SMMU outgoing physical address will be nonsecure.
6705
6706 [STRM_NSEC] is ignored if the device is making a physical request (as these
6707 transactions bypass the SMMU translation process).
6708
6709 Typically firmware sets [PHYS_NSEC] and [STRM_NSEC] the same. */
6710 uint64_t reserved_2_63 : 62;
6711 #endif /* Word 0 - End */
6712 } s;
6713 /* struct bdk_iobnx_rslx_streams_s cn; */
6714 };
6715 typedef union bdk_iobnx_rslx_streams bdk_iobnx_rslx_streams_t;
6716
6717 static inline uint64_t BDK_IOBNX_RSLX_STREAMS(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_IOBNX_RSLX_STREAMS(unsigned long a,unsigned long b)6718 static inline uint64_t BDK_IOBNX_RSLX_STREAMS(unsigned long a, unsigned long b)
6719 {
6720 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b<=255)))
6721 return 0x87e0f0002800ll + 0x1000000ll * ((a) & 0x1) + 8ll * ((b) & 0xff);
6722 __bdk_csr_fatal("IOBNX_RSLX_STREAMS", 2, a, b, 0, 0);
6723 }
6724
6725 #define typedef_BDK_IOBNX_RSLX_STREAMS(a,b) bdk_iobnx_rslx_streams_t
6726 #define bustype_BDK_IOBNX_RSLX_STREAMS(a,b) BDK_CSR_TYPE_RSL
6727 #define basename_BDK_IOBNX_RSLX_STREAMS(a,b) "IOBNX_RSLX_STREAMS"
6728 #define device_bar_BDK_IOBNX_RSLX_STREAMS(a,b) 0x0 /* PF_BAR0 */
6729 #define busnum_BDK_IOBNX_RSLX_STREAMS(a,b) (a)
6730 #define arguments_BDK_IOBNX_RSLX_STREAMS(a,b) (a),(b),-1,-1
6731
6732 /**
6733 * Register (RSL) iobn#_rvu_block#_const
6734 *
6735 * IOBN RVU BLOCK Constant Registers
6736 * This register returns discovery information for each RVU BLOCK, where RVU BLOCK is
6737 * enumerated by RVU_BLOCK_ADDR_E, in rvu.csr
6738 * Each IOB returns identical information.
6739 */
6740 union bdk_iobnx_rvu_blockx_const
6741 {
6742 uint64_t u;
6743 struct bdk_iobnx_rvu_blockx_const_s
6744 {
6745 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6746 uint64_t reserved_24_63 : 40;
6747 uint64_t farbid : 8; /**< [ 23: 16](RO) Flat ARBID for the given NCB ID. */
6748 uint64_t arbid : 8; /**< [ 15: 8](RO) ARBID for the given RVU BLOCK. */
6749 uint64_t ncb : 4; /**< [ 7: 4](RO) Physical bus number for the given RVU BLOCK. */
6750 uint64_t iob : 3; /**< [ 3: 1](RO) IOB number for the given RVU BLOCK. */
6751 uint64_t valid : 1; /**< [ 0: 0](RO) Set if this RVU BLOCK is a valid ID. */
6752 #else /* Word 0 - Little Endian */
6753 uint64_t valid : 1; /**< [ 0: 0](RO) Set if this RVU BLOCK is a valid ID. */
6754 uint64_t iob : 3; /**< [ 3: 1](RO) IOB number for the given RVU BLOCK. */
6755 uint64_t ncb : 4; /**< [ 7: 4](RO) Physical bus number for the given RVU BLOCK. */
6756 uint64_t arbid : 8; /**< [ 15: 8](RO) ARBID for the given RVU BLOCK. */
6757 uint64_t farbid : 8; /**< [ 23: 16](RO) Flat ARBID for the given NCB ID. */
6758 uint64_t reserved_24_63 : 40;
6759 #endif /* Word 0 - End */
6760 } s;
6761 /* struct bdk_iobnx_rvu_blockx_const_s cn; */
6762 };
6763 typedef union bdk_iobnx_rvu_blockx_const bdk_iobnx_rvu_blockx_const_t;
6764
6765 static inline uint64_t BDK_IOBNX_RVU_BLOCKX_CONST(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_IOBNX_RVU_BLOCKX_CONST(unsigned long a,unsigned long b)6766 static inline uint64_t BDK_IOBNX_RVU_BLOCKX_CONST(unsigned long a, unsigned long b)
6767 {
6768 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b<=31)))
6769 return 0x87e0f0001800ll + 0x1000000ll * ((a) & 0x1) + 8ll * ((b) & 0x1f);
6770 __bdk_csr_fatal("IOBNX_RVU_BLOCKX_CONST", 2, a, b, 0, 0);
6771 }
6772
6773 #define typedef_BDK_IOBNX_RVU_BLOCKX_CONST(a,b) bdk_iobnx_rvu_blockx_const_t
6774 #define bustype_BDK_IOBNX_RVU_BLOCKX_CONST(a,b) BDK_CSR_TYPE_RSL
6775 #define basename_BDK_IOBNX_RVU_BLOCKX_CONST(a,b) "IOBNX_RVU_BLOCKX_CONST"
6776 #define device_bar_BDK_IOBNX_RVU_BLOCKX_CONST(a,b) 0x0 /* PF_BAR0 */
6777 #define busnum_BDK_IOBNX_RVU_BLOCKX_CONST(a,b) (a)
6778 #define arguments_BDK_IOBNX_RVU_BLOCKX_CONST(a,b) (a),(b),-1,-1
6779
6780 /**
6781 * Register (RSL) iobn#_scratch
6782 *
6783 * INTERNAL: IOBN Scratch Register
6784 */
6785 union bdk_iobnx_scratch
6786 {
6787 uint64_t u;
6788 struct bdk_iobnx_scratch_s
6789 {
6790 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6791 uint64_t data : 64; /**< [ 63: 0](R/W) Test register for CSR access. */
6792 #else /* Word 0 - Little Endian */
6793 uint64_t data : 64; /**< [ 63: 0](R/W) Test register for CSR access. */
6794 #endif /* Word 0 - End */
6795 } s;
6796 /* struct bdk_iobnx_scratch_s cn; */
6797 };
6798 typedef union bdk_iobnx_scratch bdk_iobnx_scratch_t;
6799
6800 static inline uint64_t BDK_IOBNX_SCRATCH(unsigned long a) __attribute__ ((pure, always_inline));
BDK_IOBNX_SCRATCH(unsigned long a)6801 static inline uint64_t BDK_IOBNX_SCRATCH(unsigned long a)
6802 {
6803 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
6804 return 0x87e0f0003020ll + 0x1000000ll * ((a) & 0x0);
6805 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
6806 return 0x87e0f0003020ll + 0x1000000ll * ((a) & 0x1);
6807 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
6808 return 0x87e0f0003020ll + 0x1000000ll * ((a) & 0x1);
6809 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
6810 return 0x87e0f0003020ll + 0x1000000ll * ((a) & 0x1);
6811 __bdk_csr_fatal("IOBNX_SCRATCH", 1, a, 0, 0, 0);
6812 }
6813
6814 #define typedef_BDK_IOBNX_SCRATCH(a) bdk_iobnx_scratch_t
6815 #define bustype_BDK_IOBNX_SCRATCH(a) BDK_CSR_TYPE_RSL
6816 #define basename_BDK_IOBNX_SCRATCH(a) "IOBNX_SCRATCH"
6817 #define device_bar_BDK_IOBNX_SCRATCH(a) 0x0 /* PF_BAR0 */
6818 #define busnum_BDK_IOBNX_SCRATCH(a) (a)
6819 #define arguments_BDK_IOBNX_SCRATCH(a) (a),-1,-1,-1
6820
6821 /**
6822 * Register (RSL) iobn#_slitag#_control
6823 *
6824 * IOBN Control Register
6825 * This register contains various control bits for IOBN functionality.
6826 */
6827 union bdk_iobnx_slitagx_control
6828 {
6829 uint64_t u;
6830 struct bdk_iobnx_slitagx_control_s
6831 {
6832 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6833 uint64_t reserved_9_63 : 55;
6834 uint64_t bits_dis : 1; /**< [ 8: 8](RAZ) Reserved. */
6835 uint64_t reserved_4_7 : 4;
6836 uint64_t ld_ld_ord : 1; /**< [ 3: 3](R/W) Enforce load-following-load ordering for SLI operations. A load operation must
6837 wait for all previous load operations' FILLs before issuing.
6838
6839 Atomic transactions (which for PCI are non-posted so not part of normal store
6840 ordering) are also considered loads for the purpose of this bit. */
6841 uint64_t ld_st_ord : 1; /**< [ 2: 2](R/W) Enforce load-following-store ordering for SLI operations. A load operation must
6842 wait for all previous store operations' STDNs before issuing.
6843
6844 Atomic transactions (which for PCI are non-posted so not part of normal store
6845 ordering) are also considered loads for the purpose of this bit. */
6846 uint64_t st_ld_ord : 1; /**< [ 1: 1](R/W) Enforce store-following-load ordering for SLI operations. A store operation must
6847 wait for all previous load operations' FILLs before issuing.
6848
6849 Atomic transactions (which for PCI are non-posted so not part of normal store
6850 ordering) are also considered loads for the purpose of this bit. */
6851 uint64_t st_st_ord : 1; /**< [ 0: 0](R/W) Enforce store-following-store ordering for SLI operations. A store operation must
6852 wait for all previous store operations' STDNs before issuing. */
6853 #else /* Word 0 - Little Endian */
6854 uint64_t st_st_ord : 1; /**< [ 0: 0](R/W) Enforce store-following-store ordering for SLI operations. A store operation must
6855 wait for all previous store operations' STDNs before issuing. */
6856 uint64_t st_ld_ord : 1; /**< [ 1: 1](R/W) Enforce store-following-load ordering for SLI operations. A store operation must
6857 wait for all previous load operations' FILLs before issuing.
6858
6859 Atomic transactions (which for PCI are non-posted so not part of normal store
6860 ordering) are also considered loads for the purpose of this bit. */
6861 uint64_t ld_st_ord : 1; /**< [ 2: 2](R/W) Enforce load-following-store ordering for SLI operations. A load operation must
6862 wait for all previous store operations' STDNs before issuing.
6863
6864 Atomic transactions (which for PCI are non-posted so not part of normal store
6865 ordering) are also considered loads for the purpose of this bit. */
6866 uint64_t ld_ld_ord : 1; /**< [ 3: 3](R/W) Enforce load-following-load ordering for SLI operations. A load operation must
6867 wait for all previous load operations' FILLs before issuing.
6868
6869 Atomic transactions (which for PCI are non-posted so not part of normal store
6870 ordering) are also considered loads for the purpose of this bit. */
6871 uint64_t reserved_4_7 : 4;
6872 uint64_t bits_dis : 1; /**< [ 8: 8](RAZ) Reserved. */
6873 uint64_t reserved_9_63 : 55;
6874 #endif /* Word 0 - End */
6875 } s;
6876 /* struct bdk_iobnx_slitagx_control_s cn88xxp1; */
6877 struct bdk_iobnx_slitagx_control_cn81xx
6878 {
6879 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6880 uint64_t reserved_9_63 : 55;
6881 uint64_t bits_dis : 1; /**< [ 8: 8](R/W) When set, disables stream validity checking. For diagnostic use only. */
6882 uint64_t reserved_4_7 : 4;
6883 uint64_t ld_ld_ord : 1; /**< [ 3: 3](R/W) Enforce load-following-load ordering for SLI operations. A load operation must
6884 wait for all previous load operations' FILLs before issuing.
6885
6886 Atomic transactions (which for PCI are non-posted so not part of normal store
6887 ordering) are also considered loads for the purpose of this bit. */
6888 uint64_t ld_st_ord : 1; /**< [ 2: 2](R/W) Enforce load-following-store ordering for SLI operations. A load operation must
6889 wait for all previous store operations' STDNs before issuing.
6890
6891 Atomic transactions (which for PCI are non-posted so not part of normal store
6892 ordering) are also considered loads for the purpose of this bit. */
6893 uint64_t st_ld_ord : 1; /**< [ 1: 1](R/W) Enforce store-following-load ordering for SLI operations. A store operation must
6894 wait for all previous load operations' FILLs before issuing.
6895
6896 Atomic transactions (which for PCI are non-posted so not part of normal store
6897 ordering) are also considered loads for the purpose of this bit. */
6898 uint64_t st_st_ord : 1; /**< [ 0: 0](R/W) Enforce store-following-store ordering for SLI operations. A store operation must
6899 wait for all previous store operations' STDNs before issuing. */
6900 #else /* Word 0 - Little Endian */
6901 uint64_t st_st_ord : 1; /**< [ 0: 0](R/W) Enforce store-following-store ordering for SLI operations. A store operation must
6902 wait for all previous store operations' STDNs before issuing. */
6903 uint64_t st_ld_ord : 1; /**< [ 1: 1](R/W) Enforce store-following-load ordering for SLI operations. A store operation must
6904 wait for all previous load operations' FILLs before issuing.
6905
6906 Atomic transactions (which for PCI are non-posted so not part of normal store
6907 ordering) are also considered loads for the purpose of this bit. */
6908 uint64_t ld_st_ord : 1; /**< [ 2: 2](R/W) Enforce load-following-store ordering for SLI operations. A load operation must
6909 wait for all previous store operations' STDNs before issuing.
6910
6911 Atomic transactions (which for PCI are non-posted so not part of normal store
6912 ordering) are also considered loads for the purpose of this bit. */
6913 uint64_t ld_ld_ord : 1; /**< [ 3: 3](R/W) Enforce load-following-load ordering for SLI operations. A load operation must
6914 wait for all previous load operations' FILLs before issuing.
6915
6916 Atomic transactions (which for PCI are non-posted so not part of normal store
6917 ordering) are also considered loads for the purpose of this bit. */
6918 uint64_t reserved_4_7 : 4;
6919 uint64_t bits_dis : 1; /**< [ 8: 8](R/W) When set, disables stream validity checking. For diagnostic use only. */
6920 uint64_t reserved_9_63 : 55;
6921 #endif /* Word 0 - End */
6922 } cn81xx;
6923 struct bdk_iobnx_slitagx_control_cn83xx
6924 {
6925 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6926 uint64_t reserved_9_63 : 55;
6927 uint64_t bits_dis : 1; /**< [ 8: 8](SR/W) Bitstream disable.
6928 0 = Check inbound stream IDs from a PEM are between the secondary and
6929 subordinate bus numbers corresponding to that PEM (used when PEM is in host
6930 mode), or from the stream ID PCC_DEV_CON_E::PCIERC() (used when PEM is in
6931 endpoint mode). This prevents SR-IOV security issues.
6932 1 = Do not check inbound stream IDs. See PEM()_CTL_STREAM[EPSBBASE]. */
6933 uint64_t reserved_4_7 : 4;
6934 uint64_t ld_ld_ord : 1; /**< [ 3: 3](R/W) Enforce load-following-load ordering for SLI operations. A load operation must
6935 wait for all previous load operations' FILLs before issuing.
6936
6937 Atomic transactions (which for PCI are non-posted so not part of normal store
6938 ordering) are also considered loads for the purpose of this bit. */
6939 uint64_t ld_st_ord : 1; /**< [ 2: 2](R/W) Enforce load-following-store ordering for SLI operations. A load operation must
6940 wait for all previous store operations' STDNs before issuing.
6941
6942 Atomic transactions (which for PCI are non-posted so not part of normal store
6943 ordering) are also considered loads for the purpose of this bit. */
6944 uint64_t st_ld_ord : 1; /**< [ 1: 1](R/W) Enforce store-following-load ordering for SLI operations. A store operation must
6945 wait for all previous load operations' FILLs before issuing.
6946
6947 Atomic transactions (which for PCI are non-posted so not part of normal store
6948 ordering) are also considered loads for the purpose of this bit. */
6949 uint64_t st_st_ord : 1; /**< [ 0: 0](R/W) Enforce store-following-store ordering for SLI operations. A store operation must
6950 wait for all previous store operations' STDNs before issuing. */
6951 #else /* Word 0 - Little Endian */
6952 uint64_t st_st_ord : 1; /**< [ 0: 0](R/W) Enforce store-following-store ordering for SLI operations. A store operation must
6953 wait for all previous store operations' STDNs before issuing. */
6954 uint64_t st_ld_ord : 1; /**< [ 1: 1](R/W) Enforce store-following-load ordering for SLI operations. A store operation must
6955 wait for all previous load operations' FILLs before issuing.
6956
6957 Atomic transactions (which for PCI are non-posted so not part of normal store
6958 ordering) are also considered loads for the purpose of this bit. */
6959 uint64_t ld_st_ord : 1; /**< [ 2: 2](R/W) Enforce load-following-store ordering for SLI operations. A load operation must
6960 wait for all previous store operations' STDNs before issuing.
6961
6962 Atomic transactions (which for PCI are non-posted so not part of normal store
6963 ordering) are also considered loads for the purpose of this bit. */
6964 uint64_t ld_ld_ord : 1; /**< [ 3: 3](R/W) Enforce load-following-load ordering for SLI operations. A load operation must
6965 wait for all previous load operations' FILLs before issuing.
6966
6967 Atomic transactions (which for PCI are non-posted so not part of normal store
6968 ordering) are also considered loads for the purpose of this bit. */
6969 uint64_t reserved_4_7 : 4;
6970 uint64_t bits_dis : 1; /**< [ 8: 8](SR/W) Bitstream disable.
6971 0 = Check inbound stream IDs from a PEM are between the secondary and
6972 subordinate bus numbers corresponding to that PEM (used when PEM is in host
6973 mode), or from the stream ID PCC_DEV_CON_E::PCIERC() (used when PEM is in
6974 endpoint mode). This prevents SR-IOV security issues.
6975 1 = Do not check inbound stream IDs. See PEM()_CTL_STREAM[EPSBBASE]. */
6976 uint64_t reserved_9_63 : 55;
6977 #endif /* Word 0 - End */
6978 } cn83xx;
6979 /* struct bdk_iobnx_slitagx_control_cn81xx cn88xxp2; */
6980 };
6981 typedef union bdk_iobnx_slitagx_control bdk_iobnx_slitagx_control_t;
6982
6983 static inline uint64_t BDK_IOBNX_SLITAGX_CONTROL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_IOBNX_SLITAGX_CONTROL(unsigned long a,unsigned long b)6984 static inline uint64_t BDK_IOBNX_SLITAGX_CONTROL(unsigned long a, unsigned long b)
6985 {
6986 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b<=2)))
6987 return 0x87e0f0000000ll + 0x1000000ll * ((a) & 0x0) + 0x100ll * ((b) & 0x3);
6988 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b<=3)))
6989 return 0x87e0f0000000ll + 0x1000000ll * ((a) & 0x1) + 0x100ll * ((b) & 0x3);
6990 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=2)))
6991 return 0x87e0f0000000ll + 0x1000000ll * ((a) & 0x1) + 0x100ll * ((b) & 0x3);
6992 __bdk_csr_fatal("IOBNX_SLITAGX_CONTROL", 2, a, b, 0, 0);
6993 }
6994
6995 #define typedef_BDK_IOBNX_SLITAGX_CONTROL(a,b) bdk_iobnx_slitagx_control_t
6996 #define bustype_BDK_IOBNX_SLITAGX_CONTROL(a,b) BDK_CSR_TYPE_RSL
6997 #define basename_BDK_IOBNX_SLITAGX_CONTROL(a,b) "IOBNX_SLITAGX_CONTROL"
6998 #define device_bar_BDK_IOBNX_SLITAGX_CONTROL(a,b) 0x0 /* PF_BAR0 */
6999 #define busnum_BDK_IOBNX_SLITAGX_CONTROL(a,b) (a)
7000 #define arguments_BDK_IOBNX_SLITAGX_CONTROL(a,b) (a),(b),-1,-1
7001
7002 /**
7003 * Register (RSL) iobn#_test
7004 *
7005 * INTERNAL: IOBN Test Register
7006 */
7007 union bdk_iobnx_test
7008 {
7009 uint64_t u;
7010 struct bdk_iobnx_test_s
7011 {
7012 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7013 uint64_t reserved_1_63 : 63;
7014 uint64_t gibarb_testmode : 1; /**< [ 0: 0](R/W) When set, the IOBN GIB arbiters will only grant one requestor at a time. */
7015 #else /* Word 0 - Little Endian */
7016 uint64_t gibarb_testmode : 1; /**< [ 0: 0](R/W) When set, the IOBN GIB arbiters will only grant one requestor at a time. */
7017 uint64_t reserved_1_63 : 63;
7018 #endif /* Word 0 - End */
7019 } s;
7020 struct bdk_iobnx_test_cn81xx
7021 {
7022 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7023 uint64_t reserved_1_63 : 63;
7024 uint64_t gibarb_testmode : 1; /**< [ 0: 0](RO) When set, the IOBN GIB arbiters will only grant one requestor at a time. */
7025 #else /* Word 0 - Little Endian */
7026 uint64_t gibarb_testmode : 1; /**< [ 0: 0](RO) When set, the IOBN GIB arbiters will only grant one requestor at a time. */
7027 uint64_t reserved_1_63 : 63;
7028 #endif /* Word 0 - End */
7029 } cn81xx;
7030 /* struct bdk_iobnx_test_s cn88xx; */
7031 /* struct bdk_iobnx_test_cn81xx cn83xx; */
7032 };
7033 typedef union bdk_iobnx_test bdk_iobnx_test_t;
7034
7035 static inline uint64_t BDK_IOBNX_TEST(unsigned long a) __attribute__ ((pure, always_inline));
BDK_IOBNX_TEST(unsigned long a)7036 static inline uint64_t BDK_IOBNX_TEST(unsigned long a)
7037 {
7038 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
7039 return 0x87e0f0003010ll + 0x1000000ll * ((a) & 0x0);
7040 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
7041 return 0x87e0f0003010ll + 0x1000000ll * ((a) & 0x1);
7042 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
7043 return 0x87e0f0003010ll + 0x1000000ll * ((a) & 0x1);
7044 __bdk_csr_fatal("IOBNX_TEST", 1, a, 0, 0, 0);
7045 }
7046
7047 #define typedef_BDK_IOBNX_TEST(a) bdk_iobnx_test_t
7048 #define bustype_BDK_IOBNX_TEST(a) BDK_CSR_TYPE_RSL
7049 #define basename_BDK_IOBNX_TEST(a) "IOBNX_TEST"
7050 #define device_bar_BDK_IOBNX_TEST(a) 0x0 /* PF_BAR0 */
7051 #define busnum_BDK_IOBNX_TEST(a) (a)
7052 #define arguments_BDK_IOBNX_TEST(a) (a),-1,-1,-1
7053
7054 #endif /* __BDK_CSRS_IOBN_H__ */
7055