1 #ifndef __BDK_CSRS_SLI_H__
2 #define __BDK_CSRS_SLI_H__
3 /* This file is auto-generated. Do not edit */
4
5 /***********************license start***************
6 * Copyright (c) 2003-2017 Cavium Inc. ([email protected]). All rights
7 * reserved.
8 *
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26
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31
32 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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42 ***********************license end**************************************/
43
44
45 /**
46 * @file
47 *
48 * Configuration and status register (CSR) address and type definitions for
49 * Cavium SLI.
50 *
51 * This file is auto generated. Do not edit.
52 *
53 */
54
55 /**
56 * Enumeration sdp_in_rams_e
57 *
58 * SDP Input RAMs Field Enumeration
59 * Enumerates the relative bit positions within SDP(0)_ECC(1)_CTL[CDIS].
60 */
61 #define BDK_SDP_IN_RAMS_E_CNTS (3)
62 #define BDK_SDP_IN_RAMS_E_DB (4)
63 #define BDK_SDP_IN_RAMS_E_DBELL (0xd)
64 #define BDK_SDP_IN_RAMS_E_DIR (5)
65 #define BDK_SDP_IN_RAMS_E_DMARSP0 (0)
66 #define BDK_SDP_IN_RAMS_E_DMARSP1 (1)
67 #define BDK_SDP_IN_RAMS_E_GTHR0 (8)
68 #define BDK_SDP_IN_RAMS_E_GTHR1 (9)
69 #define BDK_SDP_IN_RAMS_E_IHFD0 (6)
70 #define BDK_SDP_IN_RAMS_E_IHFD1 (7)
71 #define BDK_SDP_IN_RAMS_E_IND (0xb)
72 #define BDK_SDP_IN_RAMS_E_INFO (0xa)
73 #define BDK_SDP_IN_RAMS_E_LEVELS (0xc)
74 #define BDK_SDP_IN_RAMS_E_MBOX (0x10)
75 #define BDK_SDP_IN_RAMS_E_PERF (2)
76 #define BDK_SDP_IN_RAMS_E_PKTRSP (0xf)
77 #define BDK_SDP_IN_RAMS_E_X2P (0xe)
78
79 /**
80 * Enumeration sdp_out_rams_e
81 *
82 * SDP Output RAMs Field Enumeration
83 * Enumerates the relative bit positions within SDP(0)_ECC(0)_CTL[CDIS].
84 */
85 #define BDK_SDP_OUT_RAMS_E_BISIZE (0)
86 #define BDK_SDP_OUT_RAMS_E_BPF0 (0xd)
87 #define BDK_SDP_OUT_RAMS_E_BPF1 (0xe)
88 #define BDK_SDP_OUT_RAMS_E_CNTS (2)
89 #define BDK_SDP_OUT_RAMS_E_DB (4)
90 #define BDK_SDP_OUT_RAMS_E_DBELL (3)
91 #define BDK_SDP_OUT_RAMS_E_DPLF_DIR (6)
92 #define BDK_SDP_OUT_RAMS_E_DPLF_IND (9)
93 #define BDK_SDP_OUT_RAMS_E_IB (7)
94 #define BDK_SDP_OUT_RAMS_E_INFO (0xa)
95 #define BDK_SDP_OUT_RAMS_E_IPLF_DIR (5)
96 #define BDK_SDP_OUT_RAMS_E_IPLF_IND (8)
97 #define BDK_SDP_OUT_RAMS_E_LEVELS (0xb)
98 #define BDK_SDP_OUT_RAMS_E_MSIX_ADDR (0x11)
99 #define BDK_SDP_OUT_RAMS_E_MSIX_DATA (0x12)
100 #define BDK_SDP_OUT_RAMS_E_P2X (0xc)
101 #define BDK_SDP_OUT_RAMS_E_PERF (1)
102 #define BDK_SDP_OUT_RAMS_E_TRACK0 (0xf)
103 #define BDK_SDP_OUT_RAMS_E_TRACK1 (0x10)
104
105 /**
106 * Enumeration sli_bar_e
107 *
108 * SLI Base Address Register Enumeration
109 * Enumerates the base address registers.
110 */
111 #define BDK_SLI_BAR_E_SLIX_PF_BAR0_CN81XX(a) (0x874000000000ll + 0x1000000000ll * (a))
112 #define BDK_SLI_BAR_E_SLIX_PF_BAR0_CN81XX_SIZE 0x2000000ull
113 #define BDK_SLI_BAR_E_SLIX_PF_BAR0_CN88XX(a) (0x874000000000ll + 0x1000000000ll * (a))
114 #define BDK_SLI_BAR_E_SLIX_PF_BAR0_CN88XX_SIZE 0x2000000ull
115 #define BDK_SLI_BAR_E_SLIX_PF_BAR0_CN83XX(a) (0x874000000000ll + 0x1000000000ll * (a))
116 #define BDK_SLI_BAR_E_SLIX_PF_BAR0_CN83XX_SIZE 0x800000000ull
117 #define BDK_SLI_BAR_E_SLIX_PF_BAR4_CN81XX(a) (0x874010000000ll + 0x1000000000ll * (a))
118 #define BDK_SLI_BAR_E_SLIX_PF_BAR4_CN81XX_SIZE 0x100000ull
119 #define BDK_SLI_BAR_E_SLIX_PF_BAR4_CN88XX(a) (0x874010000000ll + 0x1000000000ll * (a))
120 #define BDK_SLI_BAR_E_SLIX_PF_BAR4_CN88XX_SIZE 0x100000ull
121 #define BDK_SLI_BAR_E_SLIX_PF_BAR4_CN83XX(a) (0x874c00000000ll + 0x1000000000ll * (a))
122 #define BDK_SLI_BAR_E_SLIX_PF_BAR4_CN83XX_SIZE 0x100000ull
123
124 /**
125 * Enumeration sli_endianswap_e
126 *
127 * SLI/SDP Endian Swap Mode Enumeration
128 * Enumerates the endian swap modes that SLI and SDP support.
129 */
130 #define BDK_SLI_ENDIANSWAP_E_BYTE_SWAP_32B (2)
131 #define BDK_SLI_ENDIANSWAP_E_BYTE_SWAP_64B (1)
132 #define BDK_SLI_ENDIANSWAP_E_LW_SWAP_64B (3)
133 #define BDK_SLI_ENDIANSWAP_E_PASS_THRU (0)
134
135 /**
136 * Enumeration sli_int_vec_e
137 *
138 * SLI MSI-X Vector Enumeration
139 * Enumerates the MSI-X interrupt vectors.
140 */
141 #define BDK_SLI_INT_VEC_E_MACX(a) (1 + (a))
142 #define BDK_SLI_INT_VEC_E_MBE (0)
143 #define BDK_SLI_INT_VEC_E_SDP_ECCX_LINT(a) (0xe + (a))
144 #define BDK_SLI_INT_VEC_E_SDP_EPFX_FLR_VF_LINT(a) (0 + (a))
145 #define BDK_SLI_INT_VEC_E_SDP_EPFX_IRERR_LINT(a) (0xa + (a))
146 #define BDK_SLI_INT_VEC_E_SDP_EPFX_ORERR_LINT(a) (0xc + (a))
147 #define BDK_SLI_INT_VEC_E_SLI_EPFX_DMA_VF_LINT(a) (8 + (a))
148 #define BDK_SLI_INT_VEC_E_SLI_EPFX_MISC_LINT(a) (2 + (a))
149 #define BDK_SLI_INT_VEC_E_SLI_EPFX_PP_VF_LINT(a) (6 + (a))
150 #define BDK_SLI_INT_VEC_E_SLI_MBE (0x10)
151
152 /**
153 * Enumeration sli_rams_e
154 *
155 * SLI RAM Field Enumeration
156 * Enumerates the relative bit positions within SLI()_MEM_CTL[CDIS].
157 */
158 #define BDK_SLI_RAMS_E_CPL0_FIF (3)
159 #define BDK_SLI_RAMS_E_CPL1_FIF (2)
160 #define BDK_SLI_RAMS_E_CPL2_FIF (1)
161 #define BDK_SLI_RAMS_E_CPL3_FIF (0)
162 #define BDK_SLI_RAMS_E_DSI_FIF (0x1e)
163 #define BDK_SLI_RAMS_E_NOD_FIF (0x1d)
164 #define BDK_SLI_RAMS_E_P2NP0C_FIF (0xf)
165 #define BDK_SLI_RAMS_E_P2NP0N_FIF (0xe)
166 #define BDK_SLI_RAMS_E_P2NP0P_FIF (0xd)
167 #define BDK_SLI_RAMS_E_P2NP1C_FIF (0xc)
168 #define BDK_SLI_RAMS_E_P2NP1N_FIF (0xb)
169 #define BDK_SLI_RAMS_E_P2NP1P_FIF (0xa)
170 #define BDK_SLI_RAMS_E_P2NP2C_FIF (9)
171 #define BDK_SLI_RAMS_E_P2NP2N_FIF (8)
172 #define BDK_SLI_RAMS_E_P2NP2P_FIF (7)
173 #define BDK_SLI_RAMS_E_P2NP3C_FIF (6)
174 #define BDK_SLI_RAMS_E_P2NP3N_FIF (5)
175 #define BDK_SLI_RAMS_E_P2NP3P_FIF (4)
176 #define BDK_SLI_RAMS_E_REG_FIF (0x1c)
177 #define BDK_SLI_RAMS_E_SNCF0_FIF (0x1b)
178 #define BDK_SLI_RAMS_E_SNCF1_FIF (0x18)
179 #define BDK_SLI_RAMS_E_SNCF2_FIF (0x15)
180 #define BDK_SLI_RAMS_E_SNCF3_FIF (0x12)
181 #define BDK_SLI_RAMS_E_SNDFH0_FIF (0x1a)
182 #define BDK_SLI_RAMS_E_SNDFH1_FIF (0x17)
183 #define BDK_SLI_RAMS_E_SNDFH2_FIF (0x14)
184 #define BDK_SLI_RAMS_E_SNDFH3_FIF (0x11)
185 #define BDK_SLI_RAMS_E_SNDFL0_FIF (0x19)
186 #define BDK_SLI_RAMS_E_SNDFL1_FIF (0x16)
187 #define BDK_SLI_RAMS_E_SNDFL2_FIF (0x13)
188 #define BDK_SLI_RAMS_E_SNDFL3_FIF (0x10)
189
190 /**
191 * Structure sli_s2m_op_s
192 *
193 * SLI to MAC Operation Structure
194 * Core initiated load and store operations that are initiating MAC transactions form an address
195 * with this structure. 8-bit, 16-bit, 32-bit and 64-bit reads and writes, in addition to atomics
196 * are supported to this region.
197 */
198 union bdk_sli_s2m_op_s
199 {
200 uint64_t u;
201 struct bdk_sli_s2m_op_s_s
202 {
203 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
204 uint64_t reserved_48_63 : 16;
205 uint64_t io : 1; /**< [ 47: 47] Indicates IO space. */
206 uint64_t reserved_46 : 1;
207 uint64_t node : 2; /**< [ 45: 44] CCPI node number. */
208 uint64_t did_hi : 4; /**< [ 43: 40] SLI device ID high bits. Specifies which SLI:
209 0x8 = SLI0.
210 0x9 = SLI1.
211
212 else = Reserved. */
213 uint64_t region : 8; /**< [ 39: 32] SLI region. Indexes into SLI()_S2M_REG()_ACC. */
214 uint64_t addr : 32; /**< [ 31: 0] Register address within the device. */
215 #else /* Word 0 - Little Endian */
216 uint64_t addr : 32; /**< [ 31: 0] Register address within the device. */
217 uint64_t region : 8; /**< [ 39: 32] SLI region. Indexes into SLI()_S2M_REG()_ACC. */
218 uint64_t did_hi : 4; /**< [ 43: 40] SLI device ID high bits. Specifies which SLI:
219 0x8 = SLI0.
220 0x9 = SLI1.
221
222 else = Reserved. */
223 uint64_t node : 2; /**< [ 45: 44] CCPI node number. */
224 uint64_t reserved_46 : 1;
225 uint64_t io : 1; /**< [ 47: 47] Indicates IO space. */
226 uint64_t reserved_48_63 : 16;
227 #endif /* Word 0 - End */
228 } s;
229 /* struct bdk_sli_s2m_op_s_s cn81xx; */
230 /* struct bdk_sli_s2m_op_s_s cn88xx; */
231 struct bdk_sli_s2m_op_s_cn83xx
232 {
233 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
234 uint64_t reserved_48_63 : 16;
235 uint64_t io : 1; /**< [ 47: 47] Indicates IO space. */
236 uint64_t reserved_46 : 1;
237 uint64_t node : 2; /**< [ 45: 44] CCPI node number. Must be zero for CN83XX. */
238 uint64_t did_hi : 4; /**< [ 43: 40] SLI device ID high bits. Must be 0x8 for CN83XX. */
239 uint64_t region : 8; /**< [ 39: 32] SLI region. Indexes into SLI()_S2M_REG()_ACC. */
240 uint64_t addr : 32; /**< [ 31: 0] Register address within the device. */
241 #else /* Word 0 - Little Endian */
242 uint64_t addr : 32; /**< [ 31: 0] Register address within the device. */
243 uint64_t region : 8; /**< [ 39: 32] SLI region. Indexes into SLI()_S2M_REG()_ACC. */
244 uint64_t did_hi : 4; /**< [ 43: 40] SLI device ID high bits. Must be 0x8 for CN83XX. */
245 uint64_t node : 2; /**< [ 45: 44] CCPI node number. Must be zero for CN83XX. */
246 uint64_t reserved_46 : 1;
247 uint64_t io : 1; /**< [ 47: 47] Indicates IO space. */
248 uint64_t reserved_48_63 : 16;
249 #endif /* Word 0 - End */
250 } cn83xx;
251 };
252
253 /**
254 * Structure sli_sdp_addr_s
255 *
256 * INTERNAL: SLI/SDP Address Structure
257 *
258 * Address decoding for SLI/SDP CSR address space
259 */
260 union bdk_sli_sdp_addr_s
261 {
262 uint64_t u;
263 struct bdk_sli_sdp_addr_s_s
264 {
265 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
266 uint64_t reserved_48_63 : 16;
267 uint64_t bit47_46 : 2; /**< [ 47: 46] NA */
268 uint64_t nn : 2; /**< [ 45: 44] NA */
269 uint64_t did : 8; /**< [ 43: 36] SLI DID */
270 uint64_t region : 2; /**< [ 35: 34] NA */
271 uint64_t r33_32 : 2; /**< [ 33: 32] NA */
272 uint64_t ncbonly : 1; /**< [ 31: 31] Set to 1 for registers that can only be accessed by AP cores */
273 uint64_t r30_26 : 5; /**< [ 30: 26] */
274 uint64_t epf : 3; /**< [ 25: 23] EPF targeted by AP cores */
275 uint64_t ring : 6; /**< [ 22: 17] SDP Packet Ring */
276 uint64_t space : 2; /**< [ 16: 15] SDP and SLI decode space:
277 0x2 = SDP ring space.
278 0x0 = SDP common space.
279 0x1 = SLI common space. */
280 uint64_t offset : 11; /**< [ 14: 4] Register offset */
281 uint64_t bit3_0 : 4; /**< [ 3: 0] NA */
282 #else /* Word 0 - Little Endian */
283 uint64_t bit3_0 : 4; /**< [ 3: 0] NA */
284 uint64_t offset : 11; /**< [ 14: 4] Register offset */
285 uint64_t space : 2; /**< [ 16: 15] SDP and SLI decode space:
286 0x2 = SDP ring space.
287 0x0 = SDP common space.
288 0x1 = SLI common space. */
289 uint64_t ring : 6; /**< [ 22: 17] SDP Packet Ring */
290 uint64_t epf : 3; /**< [ 25: 23] EPF targeted by AP cores */
291 uint64_t r30_26 : 5; /**< [ 30: 26] */
292 uint64_t ncbonly : 1; /**< [ 31: 31] Set to 1 for registers that can only be accessed by AP cores */
293 uint64_t r33_32 : 2; /**< [ 33: 32] NA */
294 uint64_t region : 2; /**< [ 35: 34] NA */
295 uint64_t did : 8; /**< [ 43: 36] SLI DID */
296 uint64_t nn : 2; /**< [ 45: 44] NA */
297 uint64_t bit47_46 : 2; /**< [ 47: 46] NA */
298 uint64_t reserved_48_63 : 16;
299 #endif /* Word 0 - End */
300 } s;
301 /* struct bdk_sli_sdp_addr_s_s cn; */
302 };
303
304 /**
305 * Register (NCB) sdp#_bist#_status
306 *
307 * SDP BIST Status Register
308 * This register contains results from BIST runs of MAC's memories: 0 = pass (or BIST in
309 * progress/never run), 1 = fail.
310 */
311 union bdk_sdpx_bistx_status
312 {
313 uint64_t u;
314 struct bdk_sdpx_bistx_status_s
315 {
316 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
317 uint64_t reserved_32_63 : 32;
318 uint64_t bstatus : 32; /**< [ 31: 0](RO/H) BIST status. One bit per memory.
319 SDP()_BIST(0)_STATUS enumerated by SDP_OUT_RAMS_E and SDP()_BIST(1)_STATUS
320 enumerated by SDP_IN_RAMS_E. */
321 #else /* Word 0 - Little Endian */
322 uint64_t bstatus : 32; /**< [ 31: 0](RO/H) BIST status. One bit per memory.
323 SDP()_BIST(0)_STATUS enumerated by SDP_OUT_RAMS_E and SDP()_BIST(1)_STATUS
324 enumerated by SDP_IN_RAMS_E. */
325 uint64_t reserved_32_63 : 32;
326 #endif /* Word 0 - End */
327 } s;
328 /* struct bdk_sdpx_bistx_status_s cn; */
329 };
330 typedef union bdk_sdpx_bistx_status bdk_sdpx_bistx_status_t;
331
332 static inline uint64_t BDK_SDPX_BISTX_STATUS(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SDPX_BISTX_STATUS(unsigned long a,unsigned long b)333 static inline uint64_t BDK_SDPX_BISTX_STATUS(unsigned long a, unsigned long b)
334 {
335 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
336 return 0x874000880120ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x1);
337 __bdk_csr_fatal("SDPX_BISTX_STATUS", 2, a, b, 0, 0);
338 }
339
340 #define typedef_BDK_SDPX_BISTX_STATUS(a,b) bdk_sdpx_bistx_status_t
341 #define bustype_BDK_SDPX_BISTX_STATUS(a,b) BDK_CSR_TYPE_NCB
342 #define basename_BDK_SDPX_BISTX_STATUS(a,b) "SDPX_BISTX_STATUS"
343 #define device_bar_BDK_SDPX_BISTX_STATUS(a,b) 0x0 /* PF_BAR0 */
344 #define busnum_BDK_SDPX_BISTX_STATUS(a,b) (a)
345 #define arguments_BDK_SDPX_BISTX_STATUS(a,b) (a),(b),-1,-1
346
347 /**
348 * Register (NCB) sdp#_ecc#_ctl
349 *
350 * SDP ECC Control Register
351 * This register controls the ECC of the SDP memories.
352 */
353 union bdk_sdpx_eccx_ctl
354 {
355 uint64_t u;
356 struct bdk_sdpx_eccx_ctl_s
357 {
358 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
359 uint64_t reserved_32_63 : 32;
360 uint64_t cdis : 32; /**< [ 31: 0](R/W) Disables ECC correction on each RAM.
361 SDP()_ECC(0)_CTL enumerated by SDP_OUT_RAMS_E and SDP()_ECC(1)_CTL
362 enumerated by SDP_IN_RAMS_E. */
363 #else /* Word 0 - Little Endian */
364 uint64_t cdis : 32; /**< [ 31: 0](R/W) Disables ECC correction on each RAM.
365 SDP()_ECC(0)_CTL enumerated by SDP_OUT_RAMS_E and SDP()_ECC(1)_CTL
366 enumerated by SDP_IN_RAMS_E. */
367 uint64_t reserved_32_63 : 32;
368 #endif /* Word 0 - End */
369 } s;
370 /* struct bdk_sdpx_eccx_ctl_s cn; */
371 };
372 typedef union bdk_sdpx_eccx_ctl bdk_sdpx_eccx_ctl_t;
373
374 static inline uint64_t BDK_SDPX_ECCX_CTL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SDPX_ECCX_CTL(unsigned long a,unsigned long b)375 static inline uint64_t BDK_SDPX_ECCX_CTL(unsigned long a, unsigned long b)
376 {
377 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
378 return 0x8740008800a0ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x1);
379 __bdk_csr_fatal("SDPX_ECCX_CTL", 2, a, b, 0, 0);
380 }
381
382 #define typedef_BDK_SDPX_ECCX_CTL(a,b) bdk_sdpx_eccx_ctl_t
383 #define bustype_BDK_SDPX_ECCX_CTL(a,b) BDK_CSR_TYPE_NCB
384 #define basename_BDK_SDPX_ECCX_CTL(a,b) "SDPX_ECCX_CTL"
385 #define device_bar_BDK_SDPX_ECCX_CTL(a,b) 0x0 /* PF_BAR0 */
386 #define busnum_BDK_SDPX_ECCX_CTL(a,b) (a)
387 #define arguments_BDK_SDPX_ECCX_CTL(a,b) (a),(b),-1,-1
388
389 /**
390 * Register (NCB) sdp#_ecc#_flip
391 *
392 * SDP ECC Control Register
393 * This register controls the ECC of the SDP memories.
394 */
395 union bdk_sdpx_eccx_flip
396 {
397 uint64_t u;
398 struct bdk_sdpx_eccx_flip_s
399 {
400 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
401 uint64_t flip1 : 32; /**< [ 63: 32](R/W) Flips syndrome bit 1 on writes.
402 SDP()_ECC(0)_FLIP enumerated by SDP_OUT_RAMS_E and SDP()_ECC(1)_FLIP
403 enumerated by SDP_IN_RAMS_E. */
404 uint64_t flip0 : 32; /**< [ 31: 0](R/W) Flips syndrome bit 0 on writes.
405 SDP()_ECC(0)_FLIP enumerated by SDP_OUT_RAMS_E and SDP()_ECC(1)_FLIP
406 enumerated by SDP_IN_RAMS_E. */
407 #else /* Word 0 - Little Endian */
408 uint64_t flip0 : 32; /**< [ 31: 0](R/W) Flips syndrome bit 0 on writes.
409 SDP()_ECC(0)_FLIP enumerated by SDP_OUT_RAMS_E and SDP()_ECC(1)_FLIP
410 enumerated by SDP_IN_RAMS_E. */
411 uint64_t flip1 : 32; /**< [ 63: 32](R/W) Flips syndrome bit 1 on writes.
412 SDP()_ECC(0)_FLIP enumerated by SDP_OUT_RAMS_E and SDP()_ECC(1)_FLIP
413 enumerated by SDP_IN_RAMS_E. */
414 #endif /* Word 0 - End */
415 } s;
416 /* struct bdk_sdpx_eccx_flip_s cn; */
417 };
418 typedef union bdk_sdpx_eccx_flip bdk_sdpx_eccx_flip_t;
419
420 static inline uint64_t BDK_SDPX_ECCX_FLIP(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SDPX_ECCX_FLIP(unsigned long a,unsigned long b)421 static inline uint64_t BDK_SDPX_ECCX_FLIP(unsigned long a, unsigned long b)
422 {
423 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
424 return 0x874000880100ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x1);
425 __bdk_csr_fatal("SDPX_ECCX_FLIP", 2, a, b, 0, 0);
426 }
427
428 #define typedef_BDK_SDPX_ECCX_FLIP(a,b) bdk_sdpx_eccx_flip_t
429 #define bustype_BDK_SDPX_ECCX_FLIP(a,b) BDK_CSR_TYPE_NCB
430 #define basename_BDK_SDPX_ECCX_FLIP(a,b) "SDPX_ECCX_FLIP"
431 #define device_bar_BDK_SDPX_ECCX_FLIP(a,b) 0x0 /* PF_BAR0 */
432 #define busnum_BDK_SDPX_ECCX_FLIP(a,b) (a)
433 #define arguments_BDK_SDPX_ECCX_FLIP(a,b) (a),(b),-1,-1
434
435 /**
436 * Register (NCB) sdp#_ecc#_lint
437 *
438 * SDP ECC Interrupt Status Register
439 * This register contains the ECC interrupt-summary bits of the SDP.
440 */
441 union bdk_sdpx_eccx_lint
442 {
443 uint64_t u;
444 struct bdk_sdpx_eccx_lint_s
445 {
446 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
447 uint64_t dbe : 32; /**< [ 63: 32](R/W1C/H) Double-bit error detected in internal RAM. One bit per memory.
448 SDP()_ECC(0)_LINT enumerated by SDP_OUT_RAMS_E and SDP()_ECC(1)_LINT
449 enumerated by SDP_IN_RAMS_E. */
450 uint64_t sbe : 32; /**< [ 31: 0](R/W1C/H) Single-bit error detected in internal RAM. One bit per memory.
451 SDP()_ECC(0)_LINT enumerated by SDP_OUT_RAMS_E and SDP()_ECC(1)_LINT
452 enumerated by SDP_IN_RAMS_E. */
453 #else /* Word 0 - Little Endian */
454 uint64_t sbe : 32; /**< [ 31: 0](R/W1C/H) Single-bit error detected in internal RAM. One bit per memory.
455 SDP()_ECC(0)_LINT enumerated by SDP_OUT_RAMS_E and SDP()_ECC(1)_LINT
456 enumerated by SDP_IN_RAMS_E. */
457 uint64_t dbe : 32; /**< [ 63: 32](R/W1C/H) Double-bit error detected in internal RAM. One bit per memory.
458 SDP()_ECC(0)_LINT enumerated by SDP_OUT_RAMS_E and SDP()_ECC(1)_LINT
459 enumerated by SDP_IN_RAMS_E. */
460 #endif /* Word 0 - End */
461 } s;
462 /* struct bdk_sdpx_eccx_lint_s cn; */
463 };
464 typedef union bdk_sdpx_eccx_lint bdk_sdpx_eccx_lint_t;
465
466 static inline uint64_t BDK_SDPX_ECCX_LINT(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SDPX_ECCX_LINT(unsigned long a,unsigned long b)467 static inline uint64_t BDK_SDPX_ECCX_LINT(unsigned long a, unsigned long b)
468 {
469 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
470 return 0x874000880020ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x1);
471 __bdk_csr_fatal("SDPX_ECCX_LINT", 2, a, b, 0, 0);
472 }
473
474 #define typedef_BDK_SDPX_ECCX_LINT(a,b) bdk_sdpx_eccx_lint_t
475 #define bustype_BDK_SDPX_ECCX_LINT(a,b) BDK_CSR_TYPE_NCB
476 #define basename_BDK_SDPX_ECCX_LINT(a,b) "SDPX_ECCX_LINT"
477 #define device_bar_BDK_SDPX_ECCX_LINT(a,b) 0x0 /* PF_BAR0 */
478 #define busnum_BDK_SDPX_ECCX_LINT(a,b) (a)
479 #define arguments_BDK_SDPX_ECCX_LINT(a,b) (a),(b),-1,-1
480
481 /**
482 * Register (NCB) sdp#_ecc#_lint_ena_w1c
483 *
484 * SDP ECC Interrupt Enable Clear Register
485 * This register clears interrupt enable bits.
486 */
487 union bdk_sdpx_eccx_lint_ena_w1c
488 {
489 uint64_t u;
490 struct bdk_sdpx_eccx_lint_ena_w1c_s
491 {
492 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
493 uint64_t dbe : 32; /**< [ 63: 32](R/W1C/H) Reads or clears enable for SDP(0)_ECC(0..1)_LINT[DBE]. */
494 uint64_t sbe : 32; /**< [ 31: 0](R/W1C/H) Reads or clears enable for SDP(0)_ECC(0..1)_LINT[SBE]. */
495 #else /* Word 0 - Little Endian */
496 uint64_t sbe : 32; /**< [ 31: 0](R/W1C/H) Reads or clears enable for SDP(0)_ECC(0..1)_LINT[SBE]. */
497 uint64_t dbe : 32; /**< [ 63: 32](R/W1C/H) Reads or clears enable for SDP(0)_ECC(0..1)_LINT[DBE]. */
498 #endif /* Word 0 - End */
499 } s;
500 /* struct bdk_sdpx_eccx_lint_ena_w1c_s cn; */
501 };
502 typedef union bdk_sdpx_eccx_lint_ena_w1c bdk_sdpx_eccx_lint_ena_w1c_t;
503
504 static inline uint64_t BDK_SDPX_ECCX_LINT_ENA_W1C(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SDPX_ECCX_LINT_ENA_W1C(unsigned long a,unsigned long b)505 static inline uint64_t BDK_SDPX_ECCX_LINT_ENA_W1C(unsigned long a, unsigned long b)
506 {
507 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
508 return 0x874000880060ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x1);
509 __bdk_csr_fatal("SDPX_ECCX_LINT_ENA_W1C", 2, a, b, 0, 0);
510 }
511
512 #define typedef_BDK_SDPX_ECCX_LINT_ENA_W1C(a,b) bdk_sdpx_eccx_lint_ena_w1c_t
513 #define bustype_BDK_SDPX_ECCX_LINT_ENA_W1C(a,b) BDK_CSR_TYPE_NCB
514 #define basename_BDK_SDPX_ECCX_LINT_ENA_W1C(a,b) "SDPX_ECCX_LINT_ENA_W1C"
515 #define device_bar_BDK_SDPX_ECCX_LINT_ENA_W1C(a,b) 0x0 /* PF_BAR0 */
516 #define busnum_BDK_SDPX_ECCX_LINT_ENA_W1C(a,b) (a)
517 #define arguments_BDK_SDPX_ECCX_LINT_ENA_W1C(a,b) (a),(b),-1,-1
518
519 /**
520 * Register (NCB) sdp#_ecc#_lint_ena_w1s
521 *
522 * SDP ECC Interrupt Enable Set Register
523 * This register sets interrupt enable bits.
524 */
525 union bdk_sdpx_eccx_lint_ena_w1s
526 {
527 uint64_t u;
528 struct bdk_sdpx_eccx_lint_ena_w1s_s
529 {
530 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
531 uint64_t dbe : 32; /**< [ 63: 32](R/W1S/H) Reads or sets enable for SDP(0)_ECC(0..1)_LINT[DBE]. */
532 uint64_t sbe : 32; /**< [ 31: 0](R/W1S/H) Reads or sets enable for SDP(0)_ECC(0..1)_LINT[SBE]. */
533 #else /* Word 0 - Little Endian */
534 uint64_t sbe : 32; /**< [ 31: 0](R/W1S/H) Reads or sets enable for SDP(0)_ECC(0..1)_LINT[SBE]. */
535 uint64_t dbe : 32; /**< [ 63: 32](R/W1S/H) Reads or sets enable for SDP(0)_ECC(0..1)_LINT[DBE]. */
536 #endif /* Word 0 - End */
537 } s;
538 /* struct bdk_sdpx_eccx_lint_ena_w1s_s cn; */
539 };
540 typedef union bdk_sdpx_eccx_lint_ena_w1s bdk_sdpx_eccx_lint_ena_w1s_t;
541
542 static inline uint64_t BDK_SDPX_ECCX_LINT_ENA_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SDPX_ECCX_LINT_ENA_W1S(unsigned long a,unsigned long b)543 static inline uint64_t BDK_SDPX_ECCX_LINT_ENA_W1S(unsigned long a, unsigned long b)
544 {
545 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
546 return 0x874000880080ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x1);
547 __bdk_csr_fatal("SDPX_ECCX_LINT_ENA_W1S", 2, a, b, 0, 0);
548 }
549
550 #define typedef_BDK_SDPX_ECCX_LINT_ENA_W1S(a,b) bdk_sdpx_eccx_lint_ena_w1s_t
551 #define bustype_BDK_SDPX_ECCX_LINT_ENA_W1S(a,b) BDK_CSR_TYPE_NCB
552 #define basename_BDK_SDPX_ECCX_LINT_ENA_W1S(a,b) "SDPX_ECCX_LINT_ENA_W1S"
553 #define device_bar_BDK_SDPX_ECCX_LINT_ENA_W1S(a,b) 0x0 /* PF_BAR0 */
554 #define busnum_BDK_SDPX_ECCX_LINT_ENA_W1S(a,b) (a)
555 #define arguments_BDK_SDPX_ECCX_LINT_ENA_W1S(a,b) (a),(b),-1,-1
556
557 /**
558 * Register (NCB) sdp#_ecc#_lint_w1s
559 *
560 * SDP ECC Interrupt Set Register
561 * This register sets interrupt bits.
562 */
563 union bdk_sdpx_eccx_lint_w1s
564 {
565 uint64_t u;
566 struct bdk_sdpx_eccx_lint_w1s_s
567 {
568 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
569 uint64_t dbe : 32; /**< [ 63: 32](R/W1S/H) Reads or sets SDP(0)_ECC(0..1)_LINT[DBE]. */
570 uint64_t sbe : 32; /**< [ 31: 0](R/W1S/H) Reads or sets SDP(0)_ECC(0..1)_LINT[SBE]. */
571 #else /* Word 0 - Little Endian */
572 uint64_t sbe : 32; /**< [ 31: 0](R/W1S/H) Reads or sets SDP(0)_ECC(0..1)_LINT[SBE]. */
573 uint64_t dbe : 32; /**< [ 63: 32](R/W1S/H) Reads or sets SDP(0)_ECC(0..1)_LINT[DBE]. */
574 #endif /* Word 0 - End */
575 } s;
576 /* struct bdk_sdpx_eccx_lint_w1s_s cn; */
577 };
578 typedef union bdk_sdpx_eccx_lint_w1s bdk_sdpx_eccx_lint_w1s_t;
579
580 static inline uint64_t BDK_SDPX_ECCX_LINT_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SDPX_ECCX_LINT_W1S(unsigned long a,unsigned long b)581 static inline uint64_t BDK_SDPX_ECCX_LINT_W1S(unsigned long a, unsigned long b)
582 {
583 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
584 return 0x874000880040ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x1);
585 __bdk_csr_fatal("SDPX_ECCX_LINT_W1S", 2, a, b, 0, 0);
586 }
587
588 #define typedef_BDK_SDPX_ECCX_LINT_W1S(a,b) bdk_sdpx_eccx_lint_w1s_t
589 #define bustype_BDK_SDPX_ECCX_LINT_W1S(a,b) BDK_CSR_TYPE_NCB
590 #define basename_BDK_SDPX_ECCX_LINT_W1S(a,b) "SDPX_ECCX_LINT_W1S"
591 #define device_bar_BDK_SDPX_ECCX_LINT_W1S(a,b) 0x0 /* PF_BAR0 */
592 #define busnum_BDK_SDPX_ECCX_LINT_W1S(a,b) (a)
593 #define arguments_BDK_SDPX_ECCX_LINT_W1S(a,b) (a),(b),-1,-1
594
595 /**
596 * Register (NCB) sdp#_epf#_flr_vf_lint
597 *
598 * SDP Function Level Reset VF Bit Array Registers
599 * These registers are only valid for PEM0 PF0 and PEM2 PF0.
600 */
601 union bdk_sdpx_epfx_flr_vf_lint
602 {
603 uint64_t u;
604 struct bdk_sdpx_epfx_flr_vf_lint_s
605 {
606 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
607 uint64_t vf_int : 64; /**< [ 63: 0](R/W1C/H) When a VF causes an FLR the appropriate VF indexed bit is set. */
608 #else /* Word 0 - Little Endian */
609 uint64_t vf_int : 64; /**< [ 63: 0](R/W1C/H) When a VF causes an FLR the appropriate VF indexed bit is set. */
610 #endif /* Word 0 - End */
611 } s;
612 /* struct bdk_sdpx_epfx_flr_vf_lint_s cn; */
613 };
614 typedef union bdk_sdpx_epfx_flr_vf_lint bdk_sdpx_epfx_flr_vf_lint_t;
615
616 static inline uint64_t BDK_SDPX_EPFX_FLR_VF_LINT(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_FLR_VF_LINT(unsigned long a,unsigned long b)617 static inline uint64_t BDK_SDPX_EPFX_FLR_VF_LINT(unsigned long a, unsigned long b)
618 {
619 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
620 return 0x874000880c00ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x1);
621 __bdk_csr_fatal("SDPX_EPFX_FLR_VF_LINT", 2, a, b, 0, 0);
622 }
623
624 #define typedef_BDK_SDPX_EPFX_FLR_VF_LINT(a,b) bdk_sdpx_epfx_flr_vf_lint_t
625 #define bustype_BDK_SDPX_EPFX_FLR_VF_LINT(a,b) BDK_CSR_TYPE_NCB
626 #define basename_BDK_SDPX_EPFX_FLR_VF_LINT(a,b) "SDPX_EPFX_FLR_VF_LINT"
627 #define device_bar_BDK_SDPX_EPFX_FLR_VF_LINT(a,b) 0x0 /* PF_BAR0 */
628 #define busnum_BDK_SDPX_EPFX_FLR_VF_LINT(a,b) (a)
629 #define arguments_BDK_SDPX_EPFX_FLR_VF_LINT(a,b) (a),(b),-1,-1
630
631 /**
632 * Register (NCB) sdp#_epf#_flr_vf_lint_ena_w1c
633 *
634 * SDP Function Level Reset VF Bit Array Local Enable Clear Registers
635 * This register clears interrupt enable bits.
636 */
637 union bdk_sdpx_epfx_flr_vf_lint_ena_w1c
638 {
639 uint64_t u;
640 struct bdk_sdpx_epfx_flr_vf_lint_ena_w1c_s
641 {
642 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
643 uint64_t vf_int : 64; /**< [ 63: 0](R/W1C/H) Reads or clears enable for SDP(0)_EPF(0..1)_FLR_VF_LINT[VF_INT]. */
644 #else /* Word 0 - Little Endian */
645 uint64_t vf_int : 64; /**< [ 63: 0](R/W1C/H) Reads or clears enable for SDP(0)_EPF(0..1)_FLR_VF_LINT[VF_INT]. */
646 #endif /* Word 0 - End */
647 } s;
648 /* struct bdk_sdpx_epfx_flr_vf_lint_ena_w1c_s cn; */
649 };
650 typedef union bdk_sdpx_epfx_flr_vf_lint_ena_w1c bdk_sdpx_epfx_flr_vf_lint_ena_w1c_t;
651
652 static inline uint64_t BDK_SDPX_EPFX_FLR_VF_LINT_ENA_W1C(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_FLR_VF_LINT_ENA_W1C(unsigned long a,unsigned long b)653 static inline uint64_t BDK_SDPX_EPFX_FLR_VF_LINT_ENA_W1C(unsigned long a, unsigned long b)
654 {
655 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
656 return 0x874000880e00ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x1);
657 __bdk_csr_fatal("SDPX_EPFX_FLR_VF_LINT_ENA_W1C", 2, a, b, 0, 0);
658 }
659
660 #define typedef_BDK_SDPX_EPFX_FLR_VF_LINT_ENA_W1C(a,b) bdk_sdpx_epfx_flr_vf_lint_ena_w1c_t
661 #define bustype_BDK_SDPX_EPFX_FLR_VF_LINT_ENA_W1C(a,b) BDK_CSR_TYPE_NCB
662 #define basename_BDK_SDPX_EPFX_FLR_VF_LINT_ENA_W1C(a,b) "SDPX_EPFX_FLR_VF_LINT_ENA_W1C"
663 #define device_bar_BDK_SDPX_EPFX_FLR_VF_LINT_ENA_W1C(a,b) 0x0 /* PF_BAR0 */
664 #define busnum_BDK_SDPX_EPFX_FLR_VF_LINT_ENA_W1C(a,b) (a)
665 #define arguments_BDK_SDPX_EPFX_FLR_VF_LINT_ENA_W1C(a,b) (a),(b),-1,-1
666
667 /**
668 * Register (NCB) sdp#_epf#_flr_vf_lint_ena_w1s
669 *
670 * SDP Function Level Reset VF Bit Array Local Enable Set Registers
671 * This register sets interrupt enable bits.
672 */
673 union bdk_sdpx_epfx_flr_vf_lint_ena_w1s
674 {
675 uint64_t u;
676 struct bdk_sdpx_epfx_flr_vf_lint_ena_w1s_s
677 {
678 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
679 uint64_t vf_int : 64; /**< [ 63: 0](R/W1S/H) Reads or sets enable for SDP(0)_EPF(0..1)_FLR_VF_LINT[VF_INT]. */
680 #else /* Word 0 - Little Endian */
681 uint64_t vf_int : 64; /**< [ 63: 0](R/W1S/H) Reads or sets enable for SDP(0)_EPF(0..1)_FLR_VF_LINT[VF_INT]. */
682 #endif /* Word 0 - End */
683 } s;
684 /* struct bdk_sdpx_epfx_flr_vf_lint_ena_w1s_s cn; */
685 };
686 typedef union bdk_sdpx_epfx_flr_vf_lint_ena_w1s bdk_sdpx_epfx_flr_vf_lint_ena_w1s_t;
687
688 static inline uint64_t BDK_SDPX_EPFX_FLR_VF_LINT_ENA_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_FLR_VF_LINT_ENA_W1S(unsigned long a,unsigned long b)689 static inline uint64_t BDK_SDPX_EPFX_FLR_VF_LINT_ENA_W1S(unsigned long a, unsigned long b)
690 {
691 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
692 return 0x874000880f00ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x1);
693 __bdk_csr_fatal("SDPX_EPFX_FLR_VF_LINT_ENA_W1S", 2, a, b, 0, 0);
694 }
695
696 #define typedef_BDK_SDPX_EPFX_FLR_VF_LINT_ENA_W1S(a,b) bdk_sdpx_epfx_flr_vf_lint_ena_w1s_t
697 #define bustype_BDK_SDPX_EPFX_FLR_VF_LINT_ENA_W1S(a,b) BDK_CSR_TYPE_NCB
698 #define basename_BDK_SDPX_EPFX_FLR_VF_LINT_ENA_W1S(a,b) "SDPX_EPFX_FLR_VF_LINT_ENA_W1S"
699 #define device_bar_BDK_SDPX_EPFX_FLR_VF_LINT_ENA_W1S(a,b) 0x0 /* PF_BAR0 */
700 #define busnum_BDK_SDPX_EPFX_FLR_VF_LINT_ENA_W1S(a,b) (a)
701 #define arguments_BDK_SDPX_EPFX_FLR_VF_LINT_ENA_W1S(a,b) (a),(b),-1,-1
702
703 /**
704 * Register (NCB) sdp#_epf#_flr_vf_lint_w1s
705 *
706 * SDP Function Level Reset VF Bit Array Set Registers
707 * This register sets interrupt bits.
708 */
709 union bdk_sdpx_epfx_flr_vf_lint_w1s
710 {
711 uint64_t u;
712 struct bdk_sdpx_epfx_flr_vf_lint_w1s_s
713 {
714 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
715 uint64_t vf_int : 64; /**< [ 63: 0](R/W1S/H) Reads or sets SDP(0)_EPF(0..1)_FLR_VF_LINT[VF_INT]. */
716 #else /* Word 0 - Little Endian */
717 uint64_t vf_int : 64; /**< [ 63: 0](R/W1S/H) Reads or sets SDP(0)_EPF(0..1)_FLR_VF_LINT[VF_INT]. */
718 #endif /* Word 0 - End */
719 } s;
720 /* struct bdk_sdpx_epfx_flr_vf_lint_w1s_s cn; */
721 };
722 typedef union bdk_sdpx_epfx_flr_vf_lint_w1s bdk_sdpx_epfx_flr_vf_lint_w1s_t;
723
724 static inline uint64_t BDK_SDPX_EPFX_FLR_VF_LINT_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_FLR_VF_LINT_W1S(unsigned long a,unsigned long b)725 static inline uint64_t BDK_SDPX_EPFX_FLR_VF_LINT_W1S(unsigned long a, unsigned long b)
726 {
727 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
728 return 0x874000880d00ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x1);
729 __bdk_csr_fatal("SDPX_EPFX_FLR_VF_LINT_W1S", 2, a, b, 0, 0);
730 }
731
732 #define typedef_BDK_SDPX_EPFX_FLR_VF_LINT_W1S(a,b) bdk_sdpx_epfx_flr_vf_lint_w1s_t
733 #define bustype_BDK_SDPX_EPFX_FLR_VF_LINT_W1S(a,b) BDK_CSR_TYPE_NCB
734 #define basename_BDK_SDPX_EPFX_FLR_VF_LINT_W1S(a,b) "SDPX_EPFX_FLR_VF_LINT_W1S"
735 #define device_bar_BDK_SDPX_EPFX_FLR_VF_LINT_W1S(a,b) 0x0 /* PF_BAR0 */
736 #define busnum_BDK_SDPX_EPFX_FLR_VF_LINT_W1S(a,b) (a)
737 #define arguments_BDK_SDPX_EPFX_FLR_VF_LINT_W1S(a,b) (a),(b),-1,-1
738
739 /**
740 * Register (NCB) sdp#_epf#_irerr_lint
741 *
742 * SDP Input Error Status Register
743 * This register indicates if an error has been detected on an input ring.
744 * The given register associated with an EPF will be reset due to a PF FLR or MAC Reset.
745 * These registers are not affected by VF FLR.
746 */
747 union bdk_sdpx_epfx_irerr_lint
748 {
749 uint64_t u;
750 struct bdk_sdpx_epfx_irerr_lint_s
751 {
752 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
753 uint64_t ring_err : 64; /**< [ 63: 0](R/W1C/H) Error has been detected on input ring i. */
754 #else /* Word 0 - Little Endian */
755 uint64_t ring_err : 64; /**< [ 63: 0](R/W1C/H) Error has been detected on input ring i. */
756 #endif /* Word 0 - End */
757 } s;
758 /* struct bdk_sdpx_epfx_irerr_lint_s cn; */
759 };
760 typedef union bdk_sdpx_epfx_irerr_lint bdk_sdpx_epfx_irerr_lint_t;
761
762 static inline uint64_t BDK_SDPX_EPFX_IRERR_LINT(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_IRERR_LINT(unsigned long a,unsigned long b)763 static inline uint64_t BDK_SDPX_EPFX_IRERR_LINT(unsigned long a, unsigned long b)
764 {
765 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
766 return 0x874000880400ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x1);
767 __bdk_csr_fatal("SDPX_EPFX_IRERR_LINT", 2, a, b, 0, 0);
768 }
769
770 #define typedef_BDK_SDPX_EPFX_IRERR_LINT(a,b) bdk_sdpx_epfx_irerr_lint_t
771 #define bustype_BDK_SDPX_EPFX_IRERR_LINT(a,b) BDK_CSR_TYPE_NCB
772 #define basename_BDK_SDPX_EPFX_IRERR_LINT(a,b) "SDPX_EPFX_IRERR_LINT"
773 #define device_bar_BDK_SDPX_EPFX_IRERR_LINT(a,b) 0x0 /* PF_BAR0 */
774 #define busnum_BDK_SDPX_EPFX_IRERR_LINT(a,b) (a)
775 #define arguments_BDK_SDPX_EPFX_IRERR_LINT(a,b) (a),(b),-1,-1
776
777 /**
778 * Register (NCB) sdp#_epf#_irerr_lint_ena_w1c
779 *
780 * SDP Input Error Enable Clear Register
781 * This register clears interrupt enable bits.
782 */
783 union bdk_sdpx_epfx_irerr_lint_ena_w1c
784 {
785 uint64_t u;
786 struct bdk_sdpx_epfx_irerr_lint_ena_w1c_s
787 {
788 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
789 uint64_t ring_err : 64; /**< [ 63: 0](R/W1C/H) Reads or clears enable for SDP(0)_EPF(0..1)_IRERR_LINT[RING_ERR]. */
790 #else /* Word 0 - Little Endian */
791 uint64_t ring_err : 64; /**< [ 63: 0](R/W1C/H) Reads or clears enable for SDP(0)_EPF(0..1)_IRERR_LINT[RING_ERR]. */
792 #endif /* Word 0 - End */
793 } s;
794 /* struct bdk_sdpx_epfx_irerr_lint_ena_w1c_s cn; */
795 };
796 typedef union bdk_sdpx_epfx_irerr_lint_ena_w1c bdk_sdpx_epfx_irerr_lint_ena_w1c_t;
797
798 static inline uint64_t BDK_SDPX_EPFX_IRERR_LINT_ENA_W1C(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_IRERR_LINT_ENA_W1C(unsigned long a,unsigned long b)799 static inline uint64_t BDK_SDPX_EPFX_IRERR_LINT_ENA_W1C(unsigned long a, unsigned long b)
800 {
801 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
802 return 0x874000880600ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x1);
803 __bdk_csr_fatal("SDPX_EPFX_IRERR_LINT_ENA_W1C", 2, a, b, 0, 0);
804 }
805
806 #define typedef_BDK_SDPX_EPFX_IRERR_LINT_ENA_W1C(a,b) bdk_sdpx_epfx_irerr_lint_ena_w1c_t
807 #define bustype_BDK_SDPX_EPFX_IRERR_LINT_ENA_W1C(a,b) BDK_CSR_TYPE_NCB
808 #define basename_BDK_SDPX_EPFX_IRERR_LINT_ENA_W1C(a,b) "SDPX_EPFX_IRERR_LINT_ENA_W1C"
809 #define device_bar_BDK_SDPX_EPFX_IRERR_LINT_ENA_W1C(a,b) 0x0 /* PF_BAR0 */
810 #define busnum_BDK_SDPX_EPFX_IRERR_LINT_ENA_W1C(a,b) (a)
811 #define arguments_BDK_SDPX_EPFX_IRERR_LINT_ENA_W1C(a,b) (a),(b),-1,-1
812
813 /**
814 * Register (NCB) sdp#_epf#_irerr_lint_ena_w1s
815 *
816 * SDP Input Error Enable Set Register
817 * This register sets interrupt enable bits.
818 */
819 union bdk_sdpx_epfx_irerr_lint_ena_w1s
820 {
821 uint64_t u;
822 struct bdk_sdpx_epfx_irerr_lint_ena_w1s_s
823 {
824 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
825 uint64_t ring_err : 64; /**< [ 63: 0](R/W1S/H) Reads or sets enable for SDP(0)_EPF(0..1)_IRERR_LINT[RING_ERR]. */
826 #else /* Word 0 - Little Endian */
827 uint64_t ring_err : 64; /**< [ 63: 0](R/W1S/H) Reads or sets enable for SDP(0)_EPF(0..1)_IRERR_LINT[RING_ERR]. */
828 #endif /* Word 0 - End */
829 } s;
830 /* struct bdk_sdpx_epfx_irerr_lint_ena_w1s_s cn; */
831 };
832 typedef union bdk_sdpx_epfx_irerr_lint_ena_w1s bdk_sdpx_epfx_irerr_lint_ena_w1s_t;
833
834 static inline uint64_t BDK_SDPX_EPFX_IRERR_LINT_ENA_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_IRERR_LINT_ENA_W1S(unsigned long a,unsigned long b)835 static inline uint64_t BDK_SDPX_EPFX_IRERR_LINT_ENA_W1S(unsigned long a, unsigned long b)
836 {
837 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
838 return 0x874000880700ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x1);
839 __bdk_csr_fatal("SDPX_EPFX_IRERR_LINT_ENA_W1S", 2, a, b, 0, 0);
840 }
841
842 #define typedef_BDK_SDPX_EPFX_IRERR_LINT_ENA_W1S(a,b) bdk_sdpx_epfx_irerr_lint_ena_w1s_t
843 #define bustype_BDK_SDPX_EPFX_IRERR_LINT_ENA_W1S(a,b) BDK_CSR_TYPE_NCB
844 #define basename_BDK_SDPX_EPFX_IRERR_LINT_ENA_W1S(a,b) "SDPX_EPFX_IRERR_LINT_ENA_W1S"
845 #define device_bar_BDK_SDPX_EPFX_IRERR_LINT_ENA_W1S(a,b) 0x0 /* PF_BAR0 */
846 #define busnum_BDK_SDPX_EPFX_IRERR_LINT_ENA_W1S(a,b) (a)
847 #define arguments_BDK_SDPX_EPFX_IRERR_LINT_ENA_W1S(a,b) (a),(b),-1,-1
848
849 /**
850 * Register (NCB) sdp#_epf#_irerr_lint_w1s
851 *
852 * SDP Input Error Status Set Register
853 * This register sets interrupt bits.
854 */
855 union bdk_sdpx_epfx_irerr_lint_w1s
856 {
857 uint64_t u;
858 struct bdk_sdpx_epfx_irerr_lint_w1s_s
859 {
860 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
861 uint64_t ring_err : 64; /**< [ 63: 0](R/W1S/H) Reads or sets SDP(0)_EPF(0..1)_IRERR_LINT[RING_ERR]. */
862 #else /* Word 0 - Little Endian */
863 uint64_t ring_err : 64; /**< [ 63: 0](R/W1S/H) Reads or sets SDP(0)_EPF(0..1)_IRERR_LINT[RING_ERR]. */
864 #endif /* Word 0 - End */
865 } s;
866 /* struct bdk_sdpx_epfx_irerr_lint_w1s_s cn; */
867 };
868 typedef union bdk_sdpx_epfx_irerr_lint_w1s bdk_sdpx_epfx_irerr_lint_w1s_t;
869
870 static inline uint64_t BDK_SDPX_EPFX_IRERR_LINT_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_IRERR_LINT_W1S(unsigned long a,unsigned long b)871 static inline uint64_t BDK_SDPX_EPFX_IRERR_LINT_W1S(unsigned long a, unsigned long b)
872 {
873 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
874 return 0x874000880500ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x1);
875 __bdk_csr_fatal("SDPX_EPFX_IRERR_LINT_W1S", 2, a, b, 0, 0);
876 }
877
878 #define typedef_BDK_SDPX_EPFX_IRERR_LINT_W1S(a,b) bdk_sdpx_epfx_irerr_lint_w1s_t
879 #define bustype_BDK_SDPX_EPFX_IRERR_LINT_W1S(a,b) BDK_CSR_TYPE_NCB
880 #define basename_BDK_SDPX_EPFX_IRERR_LINT_W1S(a,b) "SDPX_EPFX_IRERR_LINT_W1S"
881 #define device_bar_BDK_SDPX_EPFX_IRERR_LINT_W1S(a,b) 0x0 /* PF_BAR0 */
882 #define busnum_BDK_SDPX_EPFX_IRERR_LINT_W1S(a,b) (a)
883 #define arguments_BDK_SDPX_EPFX_IRERR_LINT_W1S(a,b) (a),(b),-1,-1
884
885 /**
886 * Register (PEXP_NCB) sdp#_epf#_irerr_rint
887 *
888 * SDP Input Error Status Register
889 * This register indicates if an error has been detected on an input ring.
890 * The given register associated with an EPF will be reset due to a PF FLR or MAC Reset.
891 * These registers are not affected by VF FLR.
892 */
893 union bdk_sdpx_epfx_irerr_rint
894 {
895 uint64_t u;
896 struct bdk_sdpx_epfx_irerr_rint_s
897 {
898 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
899 uint64_t ring_err : 64; /**< [ 63: 0](R/W1C/H) Error has been detected on input ring i. */
900 #else /* Word 0 - Little Endian */
901 uint64_t ring_err : 64; /**< [ 63: 0](R/W1C/H) Error has been detected on input ring i. */
902 #endif /* Word 0 - End */
903 } s;
904 /* struct bdk_sdpx_epfx_irerr_rint_s cn; */
905 };
906 typedef union bdk_sdpx_epfx_irerr_rint bdk_sdpx_epfx_irerr_rint_t;
907
908 static inline uint64_t BDK_SDPX_EPFX_IRERR_RINT(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_IRERR_RINT(unsigned long a,unsigned long b)909 static inline uint64_t BDK_SDPX_EPFX_IRERR_RINT(unsigned long a, unsigned long b)
910 {
911 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
912 return 0x874080020080ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1);
913 __bdk_csr_fatal("SDPX_EPFX_IRERR_RINT", 2, a, b, 0, 0);
914 }
915
916 #define typedef_BDK_SDPX_EPFX_IRERR_RINT(a,b) bdk_sdpx_epfx_irerr_rint_t
917 #define bustype_BDK_SDPX_EPFX_IRERR_RINT(a,b) BDK_CSR_TYPE_PEXP_NCB
918 #define basename_BDK_SDPX_EPFX_IRERR_RINT(a,b) "SDPX_EPFX_IRERR_RINT"
919 #define device_bar_BDK_SDPX_EPFX_IRERR_RINT(a,b) 0x0 /* PF_BAR0 */
920 #define busnum_BDK_SDPX_EPFX_IRERR_RINT(a,b) (a)
921 #define arguments_BDK_SDPX_EPFX_IRERR_RINT(a,b) (a),(b),-1,-1
922
923 /**
924 * Register (PEXP_NCB) sdp#_epf#_irerr_rint_ena_w1c
925 *
926 * SDP Input Error Enable Clear Register
927 * This register clears interrupt enable bits.
928 */
929 union bdk_sdpx_epfx_irerr_rint_ena_w1c
930 {
931 uint64_t u;
932 struct bdk_sdpx_epfx_irerr_rint_ena_w1c_s
933 {
934 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
935 uint64_t ring_err : 64; /**< [ 63: 0](R/W1C/H) Reads or clears enable for SDP(0)_EPF(0..1)_IRERR_RINT[RING_ERR]. */
936 #else /* Word 0 - Little Endian */
937 uint64_t ring_err : 64; /**< [ 63: 0](R/W1C/H) Reads or clears enable for SDP(0)_EPF(0..1)_IRERR_RINT[RING_ERR]. */
938 #endif /* Word 0 - End */
939 } s;
940 /* struct bdk_sdpx_epfx_irerr_rint_ena_w1c_s cn; */
941 };
942 typedef union bdk_sdpx_epfx_irerr_rint_ena_w1c bdk_sdpx_epfx_irerr_rint_ena_w1c_t;
943
944 static inline uint64_t BDK_SDPX_EPFX_IRERR_RINT_ENA_W1C(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_IRERR_RINT_ENA_W1C(unsigned long a,unsigned long b)945 static inline uint64_t BDK_SDPX_EPFX_IRERR_RINT_ENA_W1C(unsigned long a, unsigned long b)
946 {
947 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
948 return 0x8740800200a0ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1);
949 __bdk_csr_fatal("SDPX_EPFX_IRERR_RINT_ENA_W1C", 2, a, b, 0, 0);
950 }
951
952 #define typedef_BDK_SDPX_EPFX_IRERR_RINT_ENA_W1C(a,b) bdk_sdpx_epfx_irerr_rint_ena_w1c_t
953 #define bustype_BDK_SDPX_EPFX_IRERR_RINT_ENA_W1C(a,b) BDK_CSR_TYPE_PEXP_NCB
954 #define basename_BDK_SDPX_EPFX_IRERR_RINT_ENA_W1C(a,b) "SDPX_EPFX_IRERR_RINT_ENA_W1C"
955 #define device_bar_BDK_SDPX_EPFX_IRERR_RINT_ENA_W1C(a,b) 0x0 /* PF_BAR0 */
956 #define busnum_BDK_SDPX_EPFX_IRERR_RINT_ENA_W1C(a,b) (a)
957 #define arguments_BDK_SDPX_EPFX_IRERR_RINT_ENA_W1C(a,b) (a),(b),-1,-1
958
959 /**
960 * Register (PEXP_NCB) sdp#_epf#_irerr_rint_ena_w1s
961 *
962 * SDP Input Error Enable Set Register
963 * This register sets interrupt enable bits.
964 */
965 union bdk_sdpx_epfx_irerr_rint_ena_w1s
966 {
967 uint64_t u;
968 struct bdk_sdpx_epfx_irerr_rint_ena_w1s_s
969 {
970 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
971 uint64_t ring_err : 64; /**< [ 63: 0](R/W1S/H) Reads or sets enable for SDP(0)_EPF(0..1)_IRERR_RINT[RING_ERR]. */
972 #else /* Word 0 - Little Endian */
973 uint64_t ring_err : 64; /**< [ 63: 0](R/W1S/H) Reads or sets enable for SDP(0)_EPF(0..1)_IRERR_RINT[RING_ERR]. */
974 #endif /* Word 0 - End */
975 } s;
976 /* struct bdk_sdpx_epfx_irerr_rint_ena_w1s_s cn; */
977 };
978 typedef union bdk_sdpx_epfx_irerr_rint_ena_w1s bdk_sdpx_epfx_irerr_rint_ena_w1s_t;
979
980 static inline uint64_t BDK_SDPX_EPFX_IRERR_RINT_ENA_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_IRERR_RINT_ENA_W1S(unsigned long a,unsigned long b)981 static inline uint64_t BDK_SDPX_EPFX_IRERR_RINT_ENA_W1S(unsigned long a, unsigned long b)
982 {
983 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
984 return 0x8740800200b0ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1);
985 __bdk_csr_fatal("SDPX_EPFX_IRERR_RINT_ENA_W1S", 2, a, b, 0, 0);
986 }
987
988 #define typedef_BDK_SDPX_EPFX_IRERR_RINT_ENA_W1S(a,b) bdk_sdpx_epfx_irerr_rint_ena_w1s_t
989 #define bustype_BDK_SDPX_EPFX_IRERR_RINT_ENA_W1S(a,b) BDK_CSR_TYPE_PEXP_NCB
990 #define basename_BDK_SDPX_EPFX_IRERR_RINT_ENA_W1S(a,b) "SDPX_EPFX_IRERR_RINT_ENA_W1S"
991 #define device_bar_BDK_SDPX_EPFX_IRERR_RINT_ENA_W1S(a,b) 0x0 /* PF_BAR0 */
992 #define busnum_BDK_SDPX_EPFX_IRERR_RINT_ENA_W1S(a,b) (a)
993 #define arguments_BDK_SDPX_EPFX_IRERR_RINT_ENA_W1S(a,b) (a),(b),-1,-1
994
995 /**
996 * Register (PEXP_NCB) sdp#_epf#_irerr_rint_w1s
997 *
998 * SDP Input Error Status Set Register
999 * This register sets interrupt bits.
1000 */
1001 union bdk_sdpx_epfx_irerr_rint_w1s
1002 {
1003 uint64_t u;
1004 struct bdk_sdpx_epfx_irerr_rint_w1s_s
1005 {
1006 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1007 uint64_t ring_err : 64; /**< [ 63: 0](R/W1S/H) Reads or sets SDP(0)_EPF(0..1)_IRERR_RINT[RING_ERR]. */
1008 #else /* Word 0 - Little Endian */
1009 uint64_t ring_err : 64; /**< [ 63: 0](R/W1S/H) Reads or sets SDP(0)_EPF(0..1)_IRERR_RINT[RING_ERR]. */
1010 #endif /* Word 0 - End */
1011 } s;
1012 /* struct bdk_sdpx_epfx_irerr_rint_w1s_s cn; */
1013 };
1014 typedef union bdk_sdpx_epfx_irerr_rint_w1s bdk_sdpx_epfx_irerr_rint_w1s_t;
1015
1016 static inline uint64_t BDK_SDPX_EPFX_IRERR_RINT_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_IRERR_RINT_W1S(unsigned long a,unsigned long b)1017 static inline uint64_t BDK_SDPX_EPFX_IRERR_RINT_W1S(unsigned long a, unsigned long b)
1018 {
1019 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
1020 return 0x874080020090ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1);
1021 __bdk_csr_fatal("SDPX_EPFX_IRERR_RINT_W1S", 2, a, b, 0, 0);
1022 }
1023
1024 #define typedef_BDK_SDPX_EPFX_IRERR_RINT_W1S(a,b) bdk_sdpx_epfx_irerr_rint_w1s_t
1025 #define bustype_BDK_SDPX_EPFX_IRERR_RINT_W1S(a,b) BDK_CSR_TYPE_PEXP_NCB
1026 #define basename_BDK_SDPX_EPFX_IRERR_RINT_W1S(a,b) "SDPX_EPFX_IRERR_RINT_W1S"
1027 #define device_bar_BDK_SDPX_EPFX_IRERR_RINT_W1S(a,b) 0x0 /* PF_BAR0 */
1028 #define busnum_BDK_SDPX_EPFX_IRERR_RINT_W1S(a,b) (a)
1029 #define arguments_BDK_SDPX_EPFX_IRERR_RINT_W1S(a,b) (a),(b),-1,-1
1030
1031 /**
1032 * Register (PEXP_NCB) sdp#_epf#_mbox_rint
1033 *
1034 * SDP Mailbox Interrupt Status Register
1035 * This register indicates which VF/ring has signaled an interrupt.
1036 * The given register associated with an EPF will be reset due to a PF FLR or MAC Reset.
1037 * These registers are not affected by VF FLR.
1038 */
1039 union bdk_sdpx_epfx_mbox_rint
1040 {
1041 uint64_t u;
1042 struct bdk_sdpx_epfx_mbox_rint_s
1043 {
1044 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1045 uint64_t ring_num : 64; /**< [ 63: 0](R/W1C/H) Each bit indicates a ring from 0-63. */
1046 #else /* Word 0 - Little Endian */
1047 uint64_t ring_num : 64; /**< [ 63: 0](R/W1C/H) Each bit indicates a ring from 0-63. */
1048 #endif /* Word 0 - End */
1049 } s;
1050 /* struct bdk_sdpx_epfx_mbox_rint_s cn; */
1051 };
1052 typedef union bdk_sdpx_epfx_mbox_rint bdk_sdpx_epfx_mbox_rint_t;
1053
1054 static inline uint64_t BDK_SDPX_EPFX_MBOX_RINT(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_MBOX_RINT(unsigned long a,unsigned long b)1055 static inline uint64_t BDK_SDPX_EPFX_MBOX_RINT(unsigned long a, unsigned long b)
1056 {
1057 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
1058 return 0x874080020000ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1);
1059 __bdk_csr_fatal("SDPX_EPFX_MBOX_RINT", 2, a, b, 0, 0);
1060 }
1061
1062 #define typedef_BDK_SDPX_EPFX_MBOX_RINT(a,b) bdk_sdpx_epfx_mbox_rint_t
1063 #define bustype_BDK_SDPX_EPFX_MBOX_RINT(a,b) BDK_CSR_TYPE_PEXP_NCB
1064 #define basename_BDK_SDPX_EPFX_MBOX_RINT(a,b) "SDPX_EPFX_MBOX_RINT"
1065 #define device_bar_BDK_SDPX_EPFX_MBOX_RINT(a,b) 0x0 /* PF_BAR0 */
1066 #define busnum_BDK_SDPX_EPFX_MBOX_RINT(a,b) (a)
1067 #define arguments_BDK_SDPX_EPFX_MBOX_RINT(a,b) (a),(b),-1,-1
1068
1069 /**
1070 * Register (PEXP_NCB) sdp#_epf#_mbox_rint_ena_w1c
1071 *
1072 * SDP Mailbox Interrupt Enable Clear Register
1073 * This register clears interrupt enable bits.
1074 */
1075 union bdk_sdpx_epfx_mbox_rint_ena_w1c
1076 {
1077 uint64_t u;
1078 struct bdk_sdpx_epfx_mbox_rint_ena_w1c_s
1079 {
1080 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1081 uint64_t ring_num : 64; /**< [ 63: 0](R/W1C/H) Reads or clears enable for SDP(0)_EPF(0..1)_MBOX_RINT[RING_NUM]. */
1082 #else /* Word 0 - Little Endian */
1083 uint64_t ring_num : 64; /**< [ 63: 0](R/W1C/H) Reads or clears enable for SDP(0)_EPF(0..1)_MBOX_RINT[RING_NUM]. */
1084 #endif /* Word 0 - End */
1085 } s;
1086 /* struct bdk_sdpx_epfx_mbox_rint_ena_w1c_s cn; */
1087 };
1088 typedef union bdk_sdpx_epfx_mbox_rint_ena_w1c bdk_sdpx_epfx_mbox_rint_ena_w1c_t;
1089
1090 static inline uint64_t BDK_SDPX_EPFX_MBOX_RINT_ENA_W1C(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_MBOX_RINT_ENA_W1C(unsigned long a,unsigned long b)1091 static inline uint64_t BDK_SDPX_EPFX_MBOX_RINT_ENA_W1C(unsigned long a, unsigned long b)
1092 {
1093 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
1094 return 0x874080020020ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1);
1095 __bdk_csr_fatal("SDPX_EPFX_MBOX_RINT_ENA_W1C", 2, a, b, 0, 0);
1096 }
1097
1098 #define typedef_BDK_SDPX_EPFX_MBOX_RINT_ENA_W1C(a,b) bdk_sdpx_epfx_mbox_rint_ena_w1c_t
1099 #define bustype_BDK_SDPX_EPFX_MBOX_RINT_ENA_W1C(a,b) BDK_CSR_TYPE_PEXP_NCB
1100 #define basename_BDK_SDPX_EPFX_MBOX_RINT_ENA_W1C(a,b) "SDPX_EPFX_MBOX_RINT_ENA_W1C"
1101 #define device_bar_BDK_SDPX_EPFX_MBOX_RINT_ENA_W1C(a,b) 0x0 /* PF_BAR0 */
1102 #define busnum_BDK_SDPX_EPFX_MBOX_RINT_ENA_W1C(a,b) (a)
1103 #define arguments_BDK_SDPX_EPFX_MBOX_RINT_ENA_W1C(a,b) (a),(b),-1,-1
1104
1105 /**
1106 * Register (PEXP_NCB) sdp#_epf#_mbox_rint_ena_w1s
1107 *
1108 * SDP Mailbox Interrupt Enable Set Register
1109 * This register sets interrupt enable bits.
1110 */
1111 union bdk_sdpx_epfx_mbox_rint_ena_w1s
1112 {
1113 uint64_t u;
1114 struct bdk_sdpx_epfx_mbox_rint_ena_w1s_s
1115 {
1116 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1117 uint64_t ring_num : 64; /**< [ 63: 0](R/W1S/H) Reads or sets enable for SDP(0)_EPF(0..1)_MBOX_RINT[RING_NUM]. */
1118 #else /* Word 0 - Little Endian */
1119 uint64_t ring_num : 64; /**< [ 63: 0](R/W1S/H) Reads or sets enable for SDP(0)_EPF(0..1)_MBOX_RINT[RING_NUM]. */
1120 #endif /* Word 0 - End */
1121 } s;
1122 /* struct bdk_sdpx_epfx_mbox_rint_ena_w1s_s cn; */
1123 };
1124 typedef union bdk_sdpx_epfx_mbox_rint_ena_w1s bdk_sdpx_epfx_mbox_rint_ena_w1s_t;
1125
1126 static inline uint64_t BDK_SDPX_EPFX_MBOX_RINT_ENA_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_MBOX_RINT_ENA_W1S(unsigned long a,unsigned long b)1127 static inline uint64_t BDK_SDPX_EPFX_MBOX_RINT_ENA_W1S(unsigned long a, unsigned long b)
1128 {
1129 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
1130 return 0x874080020030ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1);
1131 __bdk_csr_fatal("SDPX_EPFX_MBOX_RINT_ENA_W1S", 2, a, b, 0, 0);
1132 }
1133
1134 #define typedef_BDK_SDPX_EPFX_MBOX_RINT_ENA_W1S(a,b) bdk_sdpx_epfx_mbox_rint_ena_w1s_t
1135 #define bustype_BDK_SDPX_EPFX_MBOX_RINT_ENA_W1S(a,b) BDK_CSR_TYPE_PEXP_NCB
1136 #define basename_BDK_SDPX_EPFX_MBOX_RINT_ENA_W1S(a,b) "SDPX_EPFX_MBOX_RINT_ENA_W1S"
1137 #define device_bar_BDK_SDPX_EPFX_MBOX_RINT_ENA_W1S(a,b) 0x0 /* PF_BAR0 */
1138 #define busnum_BDK_SDPX_EPFX_MBOX_RINT_ENA_W1S(a,b) (a)
1139 #define arguments_BDK_SDPX_EPFX_MBOX_RINT_ENA_W1S(a,b) (a),(b),-1,-1
1140
1141 /**
1142 * Register (PEXP_NCB) sdp#_epf#_mbox_rint_w1s
1143 *
1144 * SDP Mailbox Interrupt Set Register
1145 * This register sets interrupt bits.
1146 */
1147 union bdk_sdpx_epfx_mbox_rint_w1s
1148 {
1149 uint64_t u;
1150 struct bdk_sdpx_epfx_mbox_rint_w1s_s
1151 {
1152 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1153 uint64_t ring_num : 64; /**< [ 63: 0](R/W1S/H) Reads or sets SDP(0)_EPF(0..1)_MBOX_RINT[RING_NUM]. */
1154 #else /* Word 0 - Little Endian */
1155 uint64_t ring_num : 64; /**< [ 63: 0](R/W1S/H) Reads or sets SDP(0)_EPF(0..1)_MBOX_RINT[RING_NUM]. */
1156 #endif /* Word 0 - End */
1157 } s;
1158 /* struct bdk_sdpx_epfx_mbox_rint_w1s_s cn; */
1159 };
1160 typedef union bdk_sdpx_epfx_mbox_rint_w1s bdk_sdpx_epfx_mbox_rint_w1s_t;
1161
1162 static inline uint64_t BDK_SDPX_EPFX_MBOX_RINT_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_MBOX_RINT_W1S(unsigned long a,unsigned long b)1163 static inline uint64_t BDK_SDPX_EPFX_MBOX_RINT_W1S(unsigned long a, unsigned long b)
1164 {
1165 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
1166 return 0x874080020010ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1);
1167 __bdk_csr_fatal("SDPX_EPFX_MBOX_RINT_W1S", 2, a, b, 0, 0);
1168 }
1169
1170 #define typedef_BDK_SDPX_EPFX_MBOX_RINT_W1S(a,b) bdk_sdpx_epfx_mbox_rint_w1s_t
1171 #define bustype_BDK_SDPX_EPFX_MBOX_RINT_W1S(a,b) BDK_CSR_TYPE_PEXP_NCB
1172 #define basename_BDK_SDPX_EPFX_MBOX_RINT_W1S(a,b) "SDPX_EPFX_MBOX_RINT_W1S"
1173 #define device_bar_BDK_SDPX_EPFX_MBOX_RINT_W1S(a,b) 0x0 /* PF_BAR0 */
1174 #define busnum_BDK_SDPX_EPFX_MBOX_RINT_W1S(a,b) (a)
1175 #define arguments_BDK_SDPX_EPFX_MBOX_RINT_W1S(a,b) (a),(b),-1,-1
1176
1177 /**
1178 * Register (NCB) sdp#_epf#_orerr_lint
1179 *
1180 * SDP Output Error Status Register
1181 * This register indicates if an error has been detected on an output ring.
1182 * The given register associated with an EPF will be reset due to a PF FLR or MAC Reset.
1183 * These registers are not affected by VF FLR.
1184 */
1185 union bdk_sdpx_epfx_orerr_lint
1186 {
1187 uint64_t u;
1188 struct bdk_sdpx_epfx_orerr_lint_s
1189 {
1190 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1191 uint64_t ring_err : 64; /**< [ 63: 0](R/W1C/H) Error has been detected on output ring i. */
1192 #else /* Word 0 - Little Endian */
1193 uint64_t ring_err : 64; /**< [ 63: 0](R/W1C/H) Error has been detected on output ring i. */
1194 #endif /* Word 0 - End */
1195 } s;
1196 /* struct bdk_sdpx_epfx_orerr_lint_s cn; */
1197 };
1198 typedef union bdk_sdpx_epfx_orerr_lint bdk_sdpx_epfx_orerr_lint_t;
1199
1200 static inline uint64_t BDK_SDPX_EPFX_ORERR_LINT(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_ORERR_LINT(unsigned long a,unsigned long b)1201 static inline uint64_t BDK_SDPX_EPFX_ORERR_LINT(unsigned long a, unsigned long b)
1202 {
1203 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
1204 return 0x874000880800ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x1);
1205 __bdk_csr_fatal("SDPX_EPFX_ORERR_LINT", 2, a, b, 0, 0);
1206 }
1207
1208 #define typedef_BDK_SDPX_EPFX_ORERR_LINT(a,b) bdk_sdpx_epfx_orerr_lint_t
1209 #define bustype_BDK_SDPX_EPFX_ORERR_LINT(a,b) BDK_CSR_TYPE_NCB
1210 #define basename_BDK_SDPX_EPFX_ORERR_LINT(a,b) "SDPX_EPFX_ORERR_LINT"
1211 #define device_bar_BDK_SDPX_EPFX_ORERR_LINT(a,b) 0x0 /* PF_BAR0 */
1212 #define busnum_BDK_SDPX_EPFX_ORERR_LINT(a,b) (a)
1213 #define arguments_BDK_SDPX_EPFX_ORERR_LINT(a,b) (a),(b),-1,-1
1214
1215 /**
1216 * Register (NCB) sdp#_epf#_orerr_lint_ena_w1c
1217 *
1218 * SDP Output Error Enable Clear Register
1219 * This register clears interrupt enable bits.
1220 */
1221 union bdk_sdpx_epfx_orerr_lint_ena_w1c
1222 {
1223 uint64_t u;
1224 struct bdk_sdpx_epfx_orerr_lint_ena_w1c_s
1225 {
1226 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1227 uint64_t ring_err : 64; /**< [ 63: 0](R/W1C/H) Reads or clears enable for SDP(0)_EPF(0..1)_ORERR_LINT[RING_ERR]. */
1228 #else /* Word 0 - Little Endian */
1229 uint64_t ring_err : 64; /**< [ 63: 0](R/W1C/H) Reads or clears enable for SDP(0)_EPF(0..1)_ORERR_LINT[RING_ERR]. */
1230 #endif /* Word 0 - End */
1231 } s;
1232 /* struct bdk_sdpx_epfx_orerr_lint_ena_w1c_s cn; */
1233 };
1234 typedef union bdk_sdpx_epfx_orerr_lint_ena_w1c bdk_sdpx_epfx_orerr_lint_ena_w1c_t;
1235
1236 static inline uint64_t BDK_SDPX_EPFX_ORERR_LINT_ENA_W1C(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_ORERR_LINT_ENA_W1C(unsigned long a,unsigned long b)1237 static inline uint64_t BDK_SDPX_EPFX_ORERR_LINT_ENA_W1C(unsigned long a, unsigned long b)
1238 {
1239 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
1240 return 0x874000880a00ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x1);
1241 __bdk_csr_fatal("SDPX_EPFX_ORERR_LINT_ENA_W1C", 2, a, b, 0, 0);
1242 }
1243
1244 #define typedef_BDK_SDPX_EPFX_ORERR_LINT_ENA_W1C(a,b) bdk_sdpx_epfx_orerr_lint_ena_w1c_t
1245 #define bustype_BDK_SDPX_EPFX_ORERR_LINT_ENA_W1C(a,b) BDK_CSR_TYPE_NCB
1246 #define basename_BDK_SDPX_EPFX_ORERR_LINT_ENA_W1C(a,b) "SDPX_EPFX_ORERR_LINT_ENA_W1C"
1247 #define device_bar_BDK_SDPX_EPFX_ORERR_LINT_ENA_W1C(a,b) 0x0 /* PF_BAR0 */
1248 #define busnum_BDK_SDPX_EPFX_ORERR_LINT_ENA_W1C(a,b) (a)
1249 #define arguments_BDK_SDPX_EPFX_ORERR_LINT_ENA_W1C(a,b) (a),(b),-1,-1
1250
1251 /**
1252 * Register (NCB) sdp#_epf#_orerr_lint_ena_w1s
1253 *
1254 * SDP Output Error Enable Set Register
1255 * This register sets interrupt enable bits.
1256 */
1257 union bdk_sdpx_epfx_orerr_lint_ena_w1s
1258 {
1259 uint64_t u;
1260 struct bdk_sdpx_epfx_orerr_lint_ena_w1s_s
1261 {
1262 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1263 uint64_t ring_err : 64; /**< [ 63: 0](R/W1S/H) Reads or sets enable for SDP(0)_EPF(0..1)_ORERR_LINT[RING_ERR]. */
1264 #else /* Word 0 - Little Endian */
1265 uint64_t ring_err : 64; /**< [ 63: 0](R/W1S/H) Reads or sets enable for SDP(0)_EPF(0..1)_ORERR_LINT[RING_ERR]. */
1266 #endif /* Word 0 - End */
1267 } s;
1268 /* struct bdk_sdpx_epfx_orerr_lint_ena_w1s_s cn; */
1269 };
1270 typedef union bdk_sdpx_epfx_orerr_lint_ena_w1s bdk_sdpx_epfx_orerr_lint_ena_w1s_t;
1271
1272 static inline uint64_t BDK_SDPX_EPFX_ORERR_LINT_ENA_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_ORERR_LINT_ENA_W1S(unsigned long a,unsigned long b)1273 static inline uint64_t BDK_SDPX_EPFX_ORERR_LINT_ENA_W1S(unsigned long a, unsigned long b)
1274 {
1275 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
1276 return 0x874000880b00ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x1);
1277 __bdk_csr_fatal("SDPX_EPFX_ORERR_LINT_ENA_W1S", 2, a, b, 0, 0);
1278 }
1279
1280 #define typedef_BDK_SDPX_EPFX_ORERR_LINT_ENA_W1S(a,b) bdk_sdpx_epfx_orerr_lint_ena_w1s_t
1281 #define bustype_BDK_SDPX_EPFX_ORERR_LINT_ENA_W1S(a,b) BDK_CSR_TYPE_NCB
1282 #define basename_BDK_SDPX_EPFX_ORERR_LINT_ENA_W1S(a,b) "SDPX_EPFX_ORERR_LINT_ENA_W1S"
1283 #define device_bar_BDK_SDPX_EPFX_ORERR_LINT_ENA_W1S(a,b) 0x0 /* PF_BAR0 */
1284 #define busnum_BDK_SDPX_EPFX_ORERR_LINT_ENA_W1S(a,b) (a)
1285 #define arguments_BDK_SDPX_EPFX_ORERR_LINT_ENA_W1S(a,b) (a),(b),-1,-1
1286
1287 /**
1288 * Register (NCB) sdp#_epf#_orerr_lint_w1s
1289 *
1290 * SDP Output Error Status Set Register
1291 * This register sets interrupt bits.
1292 */
1293 union bdk_sdpx_epfx_orerr_lint_w1s
1294 {
1295 uint64_t u;
1296 struct bdk_sdpx_epfx_orerr_lint_w1s_s
1297 {
1298 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1299 uint64_t ring_err : 64; /**< [ 63: 0](R/W1S/H) Reads or sets SDP(0)_EPF(0..1)_ORERR_LINT[RING_ERR]. */
1300 #else /* Word 0 - Little Endian */
1301 uint64_t ring_err : 64; /**< [ 63: 0](R/W1S/H) Reads or sets SDP(0)_EPF(0..1)_ORERR_LINT[RING_ERR]. */
1302 #endif /* Word 0 - End */
1303 } s;
1304 /* struct bdk_sdpx_epfx_orerr_lint_w1s_s cn; */
1305 };
1306 typedef union bdk_sdpx_epfx_orerr_lint_w1s bdk_sdpx_epfx_orerr_lint_w1s_t;
1307
1308 static inline uint64_t BDK_SDPX_EPFX_ORERR_LINT_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_ORERR_LINT_W1S(unsigned long a,unsigned long b)1309 static inline uint64_t BDK_SDPX_EPFX_ORERR_LINT_W1S(unsigned long a, unsigned long b)
1310 {
1311 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
1312 return 0x874000880900ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x1);
1313 __bdk_csr_fatal("SDPX_EPFX_ORERR_LINT_W1S", 2, a, b, 0, 0);
1314 }
1315
1316 #define typedef_BDK_SDPX_EPFX_ORERR_LINT_W1S(a,b) bdk_sdpx_epfx_orerr_lint_w1s_t
1317 #define bustype_BDK_SDPX_EPFX_ORERR_LINT_W1S(a,b) BDK_CSR_TYPE_NCB
1318 #define basename_BDK_SDPX_EPFX_ORERR_LINT_W1S(a,b) "SDPX_EPFX_ORERR_LINT_W1S"
1319 #define device_bar_BDK_SDPX_EPFX_ORERR_LINT_W1S(a,b) 0x0 /* PF_BAR0 */
1320 #define busnum_BDK_SDPX_EPFX_ORERR_LINT_W1S(a,b) (a)
1321 #define arguments_BDK_SDPX_EPFX_ORERR_LINT_W1S(a,b) (a),(b),-1,-1
1322
1323 /**
1324 * Register (PEXP_NCB) sdp#_epf#_orerr_rint
1325 *
1326 * SDP Output Error Status Register
1327 * This register indicates if an error has been detected on an output ring.
1328 * The given register associated with an EPF will be reset due to a PF FLR or MAC Reset.
1329 * These registers are not affected by VF FLR.
1330 */
1331 union bdk_sdpx_epfx_orerr_rint
1332 {
1333 uint64_t u;
1334 struct bdk_sdpx_epfx_orerr_rint_s
1335 {
1336 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1337 uint64_t ring_err : 64; /**< [ 63: 0](R/W1C/H) Error has been detected on ring output ring i. */
1338 #else /* Word 0 - Little Endian */
1339 uint64_t ring_err : 64; /**< [ 63: 0](R/W1C/H) Error has been detected on ring output ring i. */
1340 #endif /* Word 0 - End */
1341 } s;
1342 /* struct bdk_sdpx_epfx_orerr_rint_s cn; */
1343 };
1344 typedef union bdk_sdpx_epfx_orerr_rint bdk_sdpx_epfx_orerr_rint_t;
1345
1346 static inline uint64_t BDK_SDPX_EPFX_ORERR_RINT(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_ORERR_RINT(unsigned long a,unsigned long b)1347 static inline uint64_t BDK_SDPX_EPFX_ORERR_RINT(unsigned long a, unsigned long b)
1348 {
1349 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
1350 return 0x874080020100ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1);
1351 __bdk_csr_fatal("SDPX_EPFX_ORERR_RINT", 2, a, b, 0, 0);
1352 }
1353
1354 #define typedef_BDK_SDPX_EPFX_ORERR_RINT(a,b) bdk_sdpx_epfx_orerr_rint_t
1355 #define bustype_BDK_SDPX_EPFX_ORERR_RINT(a,b) BDK_CSR_TYPE_PEXP_NCB
1356 #define basename_BDK_SDPX_EPFX_ORERR_RINT(a,b) "SDPX_EPFX_ORERR_RINT"
1357 #define device_bar_BDK_SDPX_EPFX_ORERR_RINT(a,b) 0x0 /* PF_BAR0 */
1358 #define busnum_BDK_SDPX_EPFX_ORERR_RINT(a,b) (a)
1359 #define arguments_BDK_SDPX_EPFX_ORERR_RINT(a,b) (a),(b),-1,-1
1360
1361 /**
1362 * Register (PEXP_NCB) sdp#_epf#_orerr_rint_ena_w1c
1363 *
1364 * SDP Output Error Enable Clear Register
1365 * This register clears interrupt enable bits.
1366 */
1367 union bdk_sdpx_epfx_orerr_rint_ena_w1c
1368 {
1369 uint64_t u;
1370 struct bdk_sdpx_epfx_orerr_rint_ena_w1c_s
1371 {
1372 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1373 uint64_t ring_err : 64; /**< [ 63: 0](R/W1C/H) Reads or clears enable for SDP(0)_EPF(0..1)_ORERR_RINT[RING_ERR]. */
1374 #else /* Word 0 - Little Endian */
1375 uint64_t ring_err : 64; /**< [ 63: 0](R/W1C/H) Reads or clears enable for SDP(0)_EPF(0..1)_ORERR_RINT[RING_ERR]. */
1376 #endif /* Word 0 - End */
1377 } s;
1378 /* struct bdk_sdpx_epfx_orerr_rint_ena_w1c_s cn; */
1379 };
1380 typedef union bdk_sdpx_epfx_orerr_rint_ena_w1c bdk_sdpx_epfx_orerr_rint_ena_w1c_t;
1381
1382 static inline uint64_t BDK_SDPX_EPFX_ORERR_RINT_ENA_W1C(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_ORERR_RINT_ENA_W1C(unsigned long a,unsigned long b)1383 static inline uint64_t BDK_SDPX_EPFX_ORERR_RINT_ENA_W1C(unsigned long a, unsigned long b)
1384 {
1385 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
1386 return 0x874080020120ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1);
1387 __bdk_csr_fatal("SDPX_EPFX_ORERR_RINT_ENA_W1C", 2, a, b, 0, 0);
1388 }
1389
1390 #define typedef_BDK_SDPX_EPFX_ORERR_RINT_ENA_W1C(a,b) bdk_sdpx_epfx_orerr_rint_ena_w1c_t
1391 #define bustype_BDK_SDPX_EPFX_ORERR_RINT_ENA_W1C(a,b) BDK_CSR_TYPE_PEXP_NCB
1392 #define basename_BDK_SDPX_EPFX_ORERR_RINT_ENA_W1C(a,b) "SDPX_EPFX_ORERR_RINT_ENA_W1C"
1393 #define device_bar_BDK_SDPX_EPFX_ORERR_RINT_ENA_W1C(a,b) 0x0 /* PF_BAR0 */
1394 #define busnum_BDK_SDPX_EPFX_ORERR_RINT_ENA_W1C(a,b) (a)
1395 #define arguments_BDK_SDPX_EPFX_ORERR_RINT_ENA_W1C(a,b) (a),(b),-1,-1
1396
1397 /**
1398 * Register (PEXP_NCB) sdp#_epf#_orerr_rint_ena_w1s
1399 *
1400 * SDP Output Error Enable Set Register
1401 * This register sets interrupt enable bits.
1402 */
1403 union bdk_sdpx_epfx_orerr_rint_ena_w1s
1404 {
1405 uint64_t u;
1406 struct bdk_sdpx_epfx_orerr_rint_ena_w1s_s
1407 {
1408 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1409 uint64_t ring_err : 64; /**< [ 63: 0](R/W1S/H) Reads or sets enable for SDP(0)_EPF(0..1)_ORERR_RINT[RING_ERR]. */
1410 #else /* Word 0 - Little Endian */
1411 uint64_t ring_err : 64; /**< [ 63: 0](R/W1S/H) Reads or sets enable for SDP(0)_EPF(0..1)_ORERR_RINT[RING_ERR]. */
1412 #endif /* Word 0 - End */
1413 } s;
1414 /* struct bdk_sdpx_epfx_orerr_rint_ena_w1s_s cn; */
1415 };
1416 typedef union bdk_sdpx_epfx_orerr_rint_ena_w1s bdk_sdpx_epfx_orerr_rint_ena_w1s_t;
1417
1418 static inline uint64_t BDK_SDPX_EPFX_ORERR_RINT_ENA_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_ORERR_RINT_ENA_W1S(unsigned long a,unsigned long b)1419 static inline uint64_t BDK_SDPX_EPFX_ORERR_RINT_ENA_W1S(unsigned long a, unsigned long b)
1420 {
1421 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
1422 return 0x874080020130ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1);
1423 __bdk_csr_fatal("SDPX_EPFX_ORERR_RINT_ENA_W1S", 2, a, b, 0, 0);
1424 }
1425
1426 #define typedef_BDK_SDPX_EPFX_ORERR_RINT_ENA_W1S(a,b) bdk_sdpx_epfx_orerr_rint_ena_w1s_t
1427 #define bustype_BDK_SDPX_EPFX_ORERR_RINT_ENA_W1S(a,b) BDK_CSR_TYPE_PEXP_NCB
1428 #define basename_BDK_SDPX_EPFX_ORERR_RINT_ENA_W1S(a,b) "SDPX_EPFX_ORERR_RINT_ENA_W1S"
1429 #define device_bar_BDK_SDPX_EPFX_ORERR_RINT_ENA_W1S(a,b) 0x0 /* PF_BAR0 */
1430 #define busnum_BDK_SDPX_EPFX_ORERR_RINT_ENA_W1S(a,b) (a)
1431 #define arguments_BDK_SDPX_EPFX_ORERR_RINT_ENA_W1S(a,b) (a),(b),-1,-1
1432
1433 /**
1434 * Register (PEXP_NCB) sdp#_epf#_orerr_rint_w1s
1435 *
1436 * SDP Output Error Status Set Register
1437 * This register sets interrupt bits.
1438 */
1439 union bdk_sdpx_epfx_orerr_rint_w1s
1440 {
1441 uint64_t u;
1442 struct bdk_sdpx_epfx_orerr_rint_w1s_s
1443 {
1444 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1445 uint64_t ring_err : 64; /**< [ 63: 0](R/W1S/H) Reads or sets SDP(0)_EPF(0..1)_ORERR_RINT[RING_ERR]. */
1446 #else /* Word 0 - Little Endian */
1447 uint64_t ring_err : 64; /**< [ 63: 0](R/W1S/H) Reads or sets SDP(0)_EPF(0..1)_ORERR_RINT[RING_ERR]. */
1448 #endif /* Word 0 - End */
1449 } s;
1450 /* struct bdk_sdpx_epfx_orerr_rint_w1s_s cn; */
1451 };
1452 typedef union bdk_sdpx_epfx_orerr_rint_w1s bdk_sdpx_epfx_orerr_rint_w1s_t;
1453
1454 static inline uint64_t BDK_SDPX_EPFX_ORERR_RINT_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_ORERR_RINT_W1S(unsigned long a,unsigned long b)1455 static inline uint64_t BDK_SDPX_EPFX_ORERR_RINT_W1S(unsigned long a, unsigned long b)
1456 {
1457 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
1458 return 0x874080020110ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1);
1459 __bdk_csr_fatal("SDPX_EPFX_ORERR_RINT_W1S", 2, a, b, 0, 0);
1460 }
1461
1462 #define typedef_BDK_SDPX_EPFX_ORERR_RINT_W1S(a,b) bdk_sdpx_epfx_orerr_rint_w1s_t
1463 #define bustype_BDK_SDPX_EPFX_ORERR_RINT_W1S(a,b) BDK_CSR_TYPE_PEXP_NCB
1464 #define basename_BDK_SDPX_EPFX_ORERR_RINT_W1S(a,b) "SDPX_EPFX_ORERR_RINT_W1S"
1465 #define device_bar_BDK_SDPX_EPFX_ORERR_RINT_W1S(a,b) 0x0 /* PF_BAR0 */
1466 #define busnum_BDK_SDPX_EPFX_ORERR_RINT_W1S(a,b) (a)
1467 #define arguments_BDK_SDPX_EPFX_ORERR_RINT_W1S(a,b) (a),(b),-1,-1
1468
1469 /**
1470 * Register (PEXP_NCB) sdp#_epf#_r#_all_int_status
1471 *
1472 * SDP Combined Interrupt Summary Status Register
1473 * This register contains interrupt status on a per-VF basis. All rings for a given VF
1474 * are located in a single register. Note that access to any ring offset within a given
1475 * VF will return the same value. When the PF reads any ring in this register it will
1476 * return the same value (64 bits each representing one ring.)
1477 *
1478 * Internal:
1479 * These interrupt bits may be set for some rings even after a PF/VF FLR.
1480 * They are not cleared becase the CNTS and LEVELS registers are not reset
1481 * and we wish to make the interrupt state consistent with CNTS/LEVELS even after FLR.
1482 * The CNTS register must be cleared by software as part of initialization after a reset
1483 * (including FLR) which will cause the interrupt state in this register to clear.
1484 */
1485 union bdk_sdpx_epfx_rx_all_int_status
1486 {
1487 uint64_t u;
1488 struct bdk_sdpx_epfx_rx_all_int_status_s
1489 {
1490 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1491 uint64_t intr : 64; /**< [ 63: 0](RO) These bits are interpreted differently for PF access and VF access.
1492
1493 For a PF read:
1494
1495 Each of the 64 bits corresponds to a ring number that is signalling an
1496 interrupt. [INTR]\<ring\> reads as one whenever any of the following are true for
1497 the respective ring R(ring):
1498
1499 * SDP()_EPF()_R()_OUT_CNTS[CNT] \> SDP()_EPF()_R()_OUT_INT_LEVELS[CNT],
1500 * SDP()_EPF()_R()_OUT_CNTS[TIMER] \> SDP()_EPF()_R()_OUT_INT_LEVELS[TIMET],
1501 * SDP()_EPF()_R()_IN_CNTS[CNT] \> SDP()_EPF()_R()_IN_INT_LEVELS[CNT],
1502 * Or, SDP()_EPF()_R()_MBOX_RINT_STATUS[INTR] is set.
1503
1504 Reading this register will isolate the ring(s) that is signalling the interrupt.
1505 To determine the specific interrupt, other registers must be read.
1506
1507 For a VF read:
1508
1509 In this mode, this register identifies the ring number "i" and specific
1510 interrupt being signaled.
1511
1512 Bits \<7:0\> indicate an input interrupt being signaled, where bit i is set if
1513 for the respective ring R(i):
1514 * SDP()_EPF()_R()_IN_CNTS[CNT] \> SDP()_EPF()_R()_IN_INT_LEVELS[CNT].
1515
1516 Bits \<15:8\> indicate an output interrupt being signaled, where bit i is set if
1517 for the respective ring R(i):
1518 * SDP()_EPF()_R()_OUT_CNTS[CNT] \> SDP()_EPF()_R()_OUT_INT_LEVELS[CNT].
1519 * Or, SDP()_EPF()_R()_OUT_CNTS[TIMER] \> SDP()_EPF()_R()_OUT_INT_LEVELS[TIMET].
1520
1521 Bits \<23:16\> indicate a mailbox interrupt being signaled, where bit i is set if
1522 for the respective ring R(i):
1523 * SDP()_EPF()_R()_MBOX_RINT_STATUS[INTR] is set.
1524
1525 Bits \<63:24\> are reserved. */
1526 #else /* Word 0 - Little Endian */
1527 uint64_t intr : 64; /**< [ 63: 0](RO) These bits are interpreted differently for PF access and VF access.
1528
1529 For a PF read:
1530
1531 Each of the 64 bits corresponds to a ring number that is signalling an
1532 interrupt. [INTR]\<ring\> reads as one whenever any of the following are true for
1533 the respective ring R(ring):
1534
1535 * SDP()_EPF()_R()_OUT_CNTS[CNT] \> SDP()_EPF()_R()_OUT_INT_LEVELS[CNT],
1536 * SDP()_EPF()_R()_OUT_CNTS[TIMER] \> SDP()_EPF()_R()_OUT_INT_LEVELS[TIMET],
1537 * SDP()_EPF()_R()_IN_CNTS[CNT] \> SDP()_EPF()_R()_IN_INT_LEVELS[CNT],
1538 * Or, SDP()_EPF()_R()_MBOX_RINT_STATUS[INTR] is set.
1539
1540 Reading this register will isolate the ring(s) that is signalling the interrupt.
1541 To determine the specific interrupt, other registers must be read.
1542
1543 For a VF read:
1544
1545 In this mode, this register identifies the ring number "i" and specific
1546 interrupt being signaled.
1547
1548 Bits \<7:0\> indicate an input interrupt being signaled, where bit i is set if
1549 for the respective ring R(i):
1550 * SDP()_EPF()_R()_IN_CNTS[CNT] \> SDP()_EPF()_R()_IN_INT_LEVELS[CNT].
1551
1552 Bits \<15:8\> indicate an output interrupt being signaled, where bit i is set if
1553 for the respective ring R(i):
1554 * SDP()_EPF()_R()_OUT_CNTS[CNT] \> SDP()_EPF()_R()_OUT_INT_LEVELS[CNT].
1555 * Or, SDP()_EPF()_R()_OUT_CNTS[TIMER] \> SDP()_EPF()_R()_OUT_INT_LEVELS[TIMET].
1556
1557 Bits \<23:16\> indicate a mailbox interrupt being signaled, where bit i is set if
1558 for the respective ring R(i):
1559 * SDP()_EPF()_R()_MBOX_RINT_STATUS[INTR] is set.
1560
1561 Bits \<63:24\> are reserved. */
1562 #endif /* Word 0 - End */
1563 } s;
1564 /* struct bdk_sdpx_epfx_rx_all_int_status_s cn; */
1565 };
1566 typedef union bdk_sdpx_epfx_rx_all_int_status bdk_sdpx_epfx_rx_all_int_status_t;
1567
1568 static inline uint64_t BDK_SDPX_EPFX_RX_ALL_INT_STATUS(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_RX_ALL_INT_STATUS(unsigned long a,unsigned long b,unsigned long c)1569 static inline uint64_t BDK_SDPX_EPFX_RX_ALL_INT_STATUS(unsigned long a, unsigned long b, unsigned long c)
1570 {
1571 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1) && (c<=63)))
1572 return 0x874080010300ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1) + 0x20000ll * ((c) & 0x3f);
1573 __bdk_csr_fatal("SDPX_EPFX_RX_ALL_INT_STATUS", 3, a, b, c, 0);
1574 }
1575
1576 #define typedef_BDK_SDPX_EPFX_RX_ALL_INT_STATUS(a,b,c) bdk_sdpx_epfx_rx_all_int_status_t
1577 #define bustype_BDK_SDPX_EPFX_RX_ALL_INT_STATUS(a,b,c) BDK_CSR_TYPE_PEXP_NCB
1578 #define basename_BDK_SDPX_EPFX_RX_ALL_INT_STATUS(a,b,c) "SDPX_EPFX_RX_ALL_INT_STATUS"
1579 #define device_bar_BDK_SDPX_EPFX_RX_ALL_INT_STATUS(a,b,c) 0x0 /* PF_BAR0 */
1580 #define busnum_BDK_SDPX_EPFX_RX_ALL_INT_STATUS(a,b,c) (a)
1581 #define arguments_BDK_SDPX_EPFX_RX_ALL_INT_STATUS(a,b,c) (a),(b),(c),-1
1582
1583 /**
1584 * Register (PEXP_NCB) sdp#_epf#_r#_err_type
1585 *
1586 * SDP Ring Error Type Register
1587 * These registers indicate which type of error(s) have been detected when
1588 * SDP()_EPF()_IRERR_LINT\<i\> / SDP()_EPF()_ORERR_RINT\<i\> / SDP()_EPF()_ORERR_LINT\<i\> /
1589 * SDP()_EPF()_ORERR_RINT\<i\> is set. Multiple bits can be set at the same time
1590 * if multiple errors have occurred for that ring.
1591 *
1592 * All 64 registers associated with an EPF will be reset due to a PF FLR or MAC Reset.
1593 * These registers are not affected by VF FLR.
1594 */
1595 union bdk_sdpx_epfx_rx_err_type
1596 {
1597 uint64_t u;
1598 struct bdk_sdpx_epfx_rx_err_type_s
1599 {
1600 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1601 uint64_t reserved_35_63 : 29;
1602 uint64_t port_dis : 1; /**< [ 34: 34](R/W1C/H) Output packet arrives targeting a port which is not enabled. */
1603 uint64_t dbell_empty : 1; /**< [ 33: 33](R/W1C/H) The watermark value is set too small, allowing doorbell count to drop below 8. */
1604 uint64_t oring_dma_err : 1; /**< [ 32: 32](R/W1C/H) DMA read error response on output pointer pair fetch. */
1605 uint64_t reserved_8_31 : 24;
1606 uint64_t illegal_fsz : 1; /**< [ 7: 7](R/W1C/H) Illegal FSZ specified in instruction.
1607 For direct gather, FSZ must be \<= 32 for 64B instructions and 0 for 32B instructions.
1608 For direct data/indirect gather, FSZ must be \<= 55 for 64B instructions and \<= 23 for 32B
1609 instructions. This check is done before any length checks. */
1610 uint64_t pkt_dma_err : 1; /**< [ 6: 6](R/W1C/H) DMA read error response on packet fetch. */
1611 uint64_t inst_dma_err : 1; /**< [ 5: 5](R/W1C/H) DMA read error response on instruction fetch. */
1612 uint64_t pkt_toosmall : 1; /**< [ 4: 4](R/W1C/H) Attempted packet read with LEN=0 or LEN \< FSZ. */
1613 uint64_t dir_len_toosmall : 1; /**< [ 3: 3](R/W1C/H) Direct gather combined LEN fields are less than the packet length specified. */
1614 uint64_t ind_dma_err : 1; /**< [ 2: 2](R/W1C/H) DMA read error response on indirect gather list fetch. This could also be caused by
1615 an unaligned gather list, in which case SDP()_DIAG[IN_IND_UNALIGNED] will also be set. */
1616 uint64_t ind_zero_det : 1; /**< [ 1: 1](R/W1C/H) Indirect gather list contains length of 0. */
1617 uint64_t ind_toosmall : 1; /**< [ 0: 0](R/W1C/H) Indirect gather list length specified less than (packet length - FSZ) in instruction. */
1618 #else /* Word 0 - Little Endian */
1619 uint64_t ind_toosmall : 1; /**< [ 0: 0](R/W1C/H) Indirect gather list length specified less than (packet length - FSZ) in instruction. */
1620 uint64_t ind_zero_det : 1; /**< [ 1: 1](R/W1C/H) Indirect gather list contains length of 0. */
1621 uint64_t ind_dma_err : 1; /**< [ 2: 2](R/W1C/H) DMA read error response on indirect gather list fetch. This could also be caused by
1622 an unaligned gather list, in which case SDP()_DIAG[IN_IND_UNALIGNED] will also be set. */
1623 uint64_t dir_len_toosmall : 1; /**< [ 3: 3](R/W1C/H) Direct gather combined LEN fields are less than the packet length specified. */
1624 uint64_t pkt_toosmall : 1; /**< [ 4: 4](R/W1C/H) Attempted packet read with LEN=0 or LEN \< FSZ. */
1625 uint64_t inst_dma_err : 1; /**< [ 5: 5](R/W1C/H) DMA read error response on instruction fetch. */
1626 uint64_t pkt_dma_err : 1; /**< [ 6: 6](R/W1C/H) DMA read error response on packet fetch. */
1627 uint64_t illegal_fsz : 1; /**< [ 7: 7](R/W1C/H) Illegal FSZ specified in instruction.
1628 For direct gather, FSZ must be \<= 32 for 64B instructions and 0 for 32B instructions.
1629 For direct data/indirect gather, FSZ must be \<= 55 for 64B instructions and \<= 23 for 32B
1630 instructions. This check is done before any length checks. */
1631 uint64_t reserved_8_31 : 24;
1632 uint64_t oring_dma_err : 1; /**< [ 32: 32](R/W1C/H) DMA read error response on output pointer pair fetch. */
1633 uint64_t dbell_empty : 1; /**< [ 33: 33](R/W1C/H) The watermark value is set too small, allowing doorbell count to drop below 8. */
1634 uint64_t port_dis : 1; /**< [ 34: 34](R/W1C/H) Output packet arrives targeting a port which is not enabled. */
1635 uint64_t reserved_35_63 : 29;
1636 #endif /* Word 0 - End */
1637 } s;
1638 /* struct bdk_sdpx_epfx_rx_err_type_s cn; */
1639 };
1640 typedef union bdk_sdpx_epfx_rx_err_type bdk_sdpx_epfx_rx_err_type_t;
1641
1642 static inline uint64_t BDK_SDPX_EPFX_RX_ERR_TYPE(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_RX_ERR_TYPE(unsigned long a,unsigned long b,unsigned long c)1643 static inline uint64_t BDK_SDPX_EPFX_RX_ERR_TYPE(unsigned long a, unsigned long b, unsigned long c)
1644 {
1645 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1) && (c<=63)))
1646 return 0x874080010400ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1) + 0x20000ll * ((c) & 0x3f);
1647 __bdk_csr_fatal("SDPX_EPFX_RX_ERR_TYPE", 3, a, b, c, 0);
1648 }
1649
1650 #define typedef_BDK_SDPX_EPFX_RX_ERR_TYPE(a,b,c) bdk_sdpx_epfx_rx_err_type_t
1651 #define bustype_BDK_SDPX_EPFX_RX_ERR_TYPE(a,b,c) BDK_CSR_TYPE_PEXP_NCB
1652 #define basename_BDK_SDPX_EPFX_RX_ERR_TYPE(a,b,c) "SDPX_EPFX_RX_ERR_TYPE"
1653 #define device_bar_BDK_SDPX_EPFX_RX_ERR_TYPE(a,b,c) 0x0 /* PF_BAR0 */
1654 #define busnum_BDK_SDPX_EPFX_RX_ERR_TYPE(a,b,c) (a)
1655 #define arguments_BDK_SDPX_EPFX_RX_ERR_TYPE(a,b,c) (a),(b),(c),-1
1656
1657 /**
1658 * Register (PEXP_NCB) sdp#_epf#_r#_in_byte_cnt
1659 *
1660 * SDP Packet Input Byte Count Register
1661 * This register contains byte counts per ring that have been read into SDP.
1662 * The counter will wrap when it reaches its maximum value. It should be cleared
1663 * before the ring is enabled for an accurate count.
1664 */
1665 union bdk_sdpx_epfx_rx_in_byte_cnt
1666 {
1667 uint64_t u;
1668 struct bdk_sdpx_epfx_rx_in_byte_cnt_s
1669 {
1670 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1671 uint64_t reserved_48_63 : 16;
1672 uint64_t cnt : 48; /**< [ 47: 0](R/W/H) Byte count, can be reset by software by writing SDP()_EPF()_R()_IN_PKT_CNT[CNT]
1673 with 0xFFFFFFFFF. */
1674 #else /* Word 0 - Little Endian */
1675 uint64_t cnt : 48; /**< [ 47: 0](R/W/H) Byte count, can be reset by software by writing SDP()_EPF()_R()_IN_PKT_CNT[CNT]
1676 with 0xFFFFFFFFF. */
1677 uint64_t reserved_48_63 : 16;
1678 #endif /* Word 0 - End */
1679 } s;
1680 /* struct bdk_sdpx_epfx_rx_in_byte_cnt_s cn; */
1681 };
1682 typedef union bdk_sdpx_epfx_rx_in_byte_cnt bdk_sdpx_epfx_rx_in_byte_cnt_t;
1683
1684 static inline uint64_t BDK_SDPX_EPFX_RX_IN_BYTE_CNT(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_RX_IN_BYTE_CNT(unsigned long a,unsigned long b,unsigned long c)1685 static inline uint64_t BDK_SDPX_EPFX_RX_IN_BYTE_CNT(unsigned long a, unsigned long b, unsigned long c)
1686 {
1687 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1) && (c<=63)))
1688 return 0x874080010090ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1) + 0x20000ll * ((c) & 0x3f);
1689 __bdk_csr_fatal("SDPX_EPFX_RX_IN_BYTE_CNT", 3, a, b, c, 0);
1690 }
1691
1692 #define typedef_BDK_SDPX_EPFX_RX_IN_BYTE_CNT(a,b,c) bdk_sdpx_epfx_rx_in_byte_cnt_t
1693 #define bustype_BDK_SDPX_EPFX_RX_IN_BYTE_CNT(a,b,c) BDK_CSR_TYPE_PEXP_NCB
1694 #define basename_BDK_SDPX_EPFX_RX_IN_BYTE_CNT(a,b,c) "SDPX_EPFX_RX_IN_BYTE_CNT"
1695 #define device_bar_BDK_SDPX_EPFX_RX_IN_BYTE_CNT(a,b,c) 0x0 /* PF_BAR0 */
1696 #define busnum_BDK_SDPX_EPFX_RX_IN_BYTE_CNT(a,b,c) (a)
1697 #define arguments_BDK_SDPX_EPFX_RX_IN_BYTE_CNT(a,b,c) (a),(b),(c),-1
1698
1699 /**
1700 * Register (PEXP_NCB) sdp#_epf#_r#_in_cnts
1701 *
1702 * SDP Input Instruction Ring Counts Register
1703 * This register contains the counters for the input instruction rings.
1704 * This register is not affected by reset (including FLR) and must be initialized
1705 * by the VF prior to enabling the ring.
1706 */
1707 union bdk_sdpx_epfx_rx_in_cnts
1708 {
1709 uint64_t u;
1710 struct bdk_sdpx_epfx_rx_in_cnts_s
1711 {
1712 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1713 uint64_t reserved_63 : 1;
1714 uint64_t out_int : 1; /**< [ 62: 62](RO/H) Returns a 1 when:
1715 * SDP()_R()_OUT_CNTS[CNT] \> SDP()_EPF()_R()_OUT_INT_LEVELS[CNT].
1716 * Or, SDP()_R()_OUT_CNTS[TIMER] \> SDP()_EPF()_R()_OUT_INT_LEVELS[TIMET].
1717
1718 To clear the bit, the CNTS register must be written to clear the underlying condition. */
1719 uint64_t in_int : 1; /**< [ 61: 61](RO/H) Returns a 1 when:
1720 * SDP()_EPF()_R()_IN_CNTS[CNT] \> SDP()_EPF()_R()_IN_INT_LEVELS[CNT]
1721
1722 To clear the bit, the SDP()_EPF()_R()_IN_CNTS register must be written to clear the
1723 underlying condition. */
1724 uint64_t mbox_int : 1; /**< [ 60: 60](RO/H) Returns a 1 when:
1725 * SDP()_EPF()_R()_MBOX_RINT_STATUS[INTR] is set
1726
1727 To clear the bit, write SDP()_EPF()_R()_MBOX_PF_VF_INT[INTR] with 1.
1728 This bit is also cleared due to an FLR. */
1729 uint64_t resend : 1; /**< [ 59: 59](WO/H) A write of 1 will resend an MSI-X interrupt message if any of the following
1730 conditions are true for the respective ring:
1731 * SDP()_EPF()_R()_OUT_CNTS[CNT] \> SDP()_EPF()_R()_OUT_INT_LEVELS[CNT].
1732 * SDP()_EPF()_R()_OUT_CNTS[TIMER] \> SDP()_EPF()_R()_OUT_INT_LEVELS[TIMET].
1733 * SDP()_EPF()_R()_IN_CNTS[CNT] \> SDP()_EPF()_R()_IN_INT_LEVELS[CNT].
1734 * SDP()_EPF()_R()_MBOX_RINT_STATUS[INTR] is set. */
1735 uint64_t reserved_32_58 : 27;
1736 uint64_t cnt : 32; /**< [ 31: 0](R/W/H) Packet counter. Hardware adds to [CNT] as it reads packets. On a write
1737 to this CSR, hardware subtracts the amount written to the [CNT] field from
1738 [CNT], which will clear PKT_IN()_INT_STATUS[INTR] if [CNT] becomes \<=
1739 SDP()_EPF()_R()_IN_INT_LEVELS[CNT]. This register should be cleared before
1740 enabling a ring by reading the current value and writing it back. */
1741 #else /* Word 0 - Little Endian */
1742 uint64_t cnt : 32; /**< [ 31: 0](R/W/H) Packet counter. Hardware adds to [CNT] as it reads packets. On a write
1743 to this CSR, hardware subtracts the amount written to the [CNT] field from
1744 [CNT], which will clear PKT_IN()_INT_STATUS[INTR] if [CNT] becomes \<=
1745 SDP()_EPF()_R()_IN_INT_LEVELS[CNT]. This register should be cleared before
1746 enabling a ring by reading the current value and writing it back. */
1747 uint64_t reserved_32_58 : 27;
1748 uint64_t resend : 1; /**< [ 59: 59](WO/H) A write of 1 will resend an MSI-X interrupt message if any of the following
1749 conditions are true for the respective ring:
1750 * SDP()_EPF()_R()_OUT_CNTS[CNT] \> SDP()_EPF()_R()_OUT_INT_LEVELS[CNT].
1751 * SDP()_EPF()_R()_OUT_CNTS[TIMER] \> SDP()_EPF()_R()_OUT_INT_LEVELS[TIMET].
1752 * SDP()_EPF()_R()_IN_CNTS[CNT] \> SDP()_EPF()_R()_IN_INT_LEVELS[CNT].
1753 * SDP()_EPF()_R()_MBOX_RINT_STATUS[INTR] is set. */
1754 uint64_t mbox_int : 1; /**< [ 60: 60](RO/H) Returns a 1 when:
1755 * SDP()_EPF()_R()_MBOX_RINT_STATUS[INTR] is set
1756
1757 To clear the bit, write SDP()_EPF()_R()_MBOX_PF_VF_INT[INTR] with 1.
1758 This bit is also cleared due to an FLR. */
1759 uint64_t in_int : 1; /**< [ 61: 61](RO/H) Returns a 1 when:
1760 * SDP()_EPF()_R()_IN_CNTS[CNT] \> SDP()_EPF()_R()_IN_INT_LEVELS[CNT]
1761
1762 To clear the bit, the SDP()_EPF()_R()_IN_CNTS register must be written to clear the
1763 underlying condition. */
1764 uint64_t out_int : 1; /**< [ 62: 62](RO/H) Returns a 1 when:
1765 * SDP()_R()_OUT_CNTS[CNT] \> SDP()_EPF()_R()_OUT_INT_LEVELS[CNT].
1766 * Or, SDP()_R()_OUT_CNTS[TIMER] \> SDP()_EPF()_R()_OUT_INT_LEVELS[TIMET].
1767
1768 To clear the bit, the CNTS register must be written to clear the underlying condition. */
1769 uint64_t reserved_63 : 1;
1770 #endif /* Word 0 - End */
1771 } s;
1772 /* struct bdk_sdpx_epfx_rx_in_cnts_s cn; */
1773 };
1774 typedef union bdk_sdpx_epfx_rx_in_cnts bdk_sdpx_epfx_rx_in_cnts_t;
1775
1776 static inline uint64_t BDK_SDPX_EPFX_RX_IN_CNTS(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_RX_IN_CNTS(unsigned long a,unsigned long b,unsigned long c)1777 static inline uint64_t BDK_SDPX_EPFX_RX_IN_CNTS(unsigned long a, unsigned long b, unsigned long c)
1778 {
1779 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1) && (c<=63)))
1780 return 0x874080010050ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1) + 0x20000ll * ((c) & 0x3f);
1781 __bdk_csr_fatal("SDPX_EPFX_RX_IN_CNTS", 3, a, b, c, 0);
1782 }
1783
1784 #define typedef_BDK_SDPX_EPFX_RX_IN_CNTS(a,b,c) bdk_sdpx_epfx_rx_in_cnts_t
1785 #define bustype_BDK_SDPX_EPFX_RX_IN_CNTS(a,b,c) BDK_CSR_TYPE_PEXP_NCB
1786 #define basename_BDK_SDPX_EPFX_RX_IN_CNTS(a,b,c) "SDPX_EPFX_RX_IN_CNTS"
1787 #define device_bar_BDK_SDPX_EPFX_RX_IN_CNTS(a,b,c) 0x0 /* PF_BAR0 */
1788 #define busnum_BDK_SDPX_EPFX_RX_IN_CNTS(a,b,c) (a)
1789 #define arguments_BDK_SDPX_EPFX_RX_IN_CNTS(a,b,c) (a),(b),(c),-1
1790
1791 /**
1792 * Register (PEXP_NCB) sdp#_epf#_r#_in_control
1793 *
1794 * SDP Input Instruction Ring Control Register
1795 * This register is the control for read operations on the input instruction rings.
1796 * This register is not affected by reset (including FLR) and must be initialized
1797 * by the VF prior to enabling the ring. Also, this register cannot be written
1798 * while either of the following conditions is true:
1799 * * [IDLE] is clear.
1800 * * Or, SDP()_EPF()_R()_IN_ENABLE[ENB] is set.
1801 */
1802 union bdk_sdpx_epfx_rx_in_control
1803 {
1804 uint64_t u;
1805 struct bdk_sdpx_epfx_rx_in_control_s
1806 {
1807 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1808 uint64_t reserved_52_63 : 12;
1809 uint64_t rpvf : 4; /**< [ 51: 48](RO/H) The number of rings assigned to this VF.
1810 Read only copy of SDP()_EPF()_RINFO[RPVF] */
1811 uint64_t reserved_29_47 : 19;
1812 uint64_t idle : 1; /**< [ 28: 28](RO/H) Asserted when this ring has no packets in-flight. */
1813 uint64_t reserved_27 : 1;
1814 uint64_t rdsize : 2; /**< [ 26: 25](R/W) Number of instructions to be read in one read request. Two-bit values are:
1815 0x0 = 1 instruction.
1816 0x1 = 2 instructions.
1817 0x2 = 4 instructions.
1818 0x3 = 8 instructions. */
1819 uint64_t is64b : 1; /**< [ 24: 24](R/W) If 1, the ring uses 64-byte instructions.
1820 If 0, the ring uses 32-byte instructions. */
1821 uint64_t reserved_9_23 : 15;
1822 uint64_t d_nsr : 1; /**< [ 8: 8](R/W/H) [D_NSR] is ADDRTYPE\<1\> for first direct and gather DPTR reads. ADDRTYPE\<1\> is the
1823 no-snoop attribute for PCIe. */
1824 uint64_t d_esr : 2; /**< [ 7: 6](R/W/H) [D_ESR] is ES\<1:0\> for first direct and gather DPTR reads.
1825 ES\<1:0\> is the endian-swap attribute for these MAC memory space reads.
1826 Enumerated by SLI_ENDIANSWAP_E. */
1827 uint64_t d_ror : 1; /**< [ 5: 5](R/W/H) [D_ROR] is ADDRTYPE\<0\> for first direct and gather DPTR reads. ADDRTYPE\<0\> is the
1828 relaxed-order attribute for PCIe. */
1829 uint64_t reserved_4 : 1;
1830 uint64_t nsr : 1; /**< [ 3: 3](R/W/H) [NSR] is ADDRTYPE\<1\> for input instruction reads (from
1831 SDP()_EPF()_R()_IN_INSTR_BADDR) and first indirect DPTR reads. ADDRTYPE\<1\>
1832 is the no-snoop attribute for PCIe. */
1833 uint64_t esr : 2; /**< [ 2: 1](R/W/H) [ESR] is ES\<1:0\> for input instruction reads (from
1834 SDP()_EPF()_R()_IN_INSTR_BADDR) and first indirect DPTR reads. ES\<1:0\> is
1835 the endian-swap attribute for these MAC memory space reads.
1836 Enumerated by SLI_ENDIANSWAP_E. */
1837 uint64_t ror : 1; /**< [ 0: 0](R/W/H) [ROR] is ADDRTYPE\<0\> for input instruction reads (from
1838 SDP()_EPF()_R()_IN_INSTR_BADDR) and first indirect DPTR reads.
1839 ADDRTYPE\<0\> is the relaxed-order attribute for PCIe. */
1840 #else /* Word 0 - Little Endian */
1841 uint64_t ror : 1; /**< [ 0: 0](R/W/H) [ROR] is ADDRTYPE\<0\> for input instruction reads (from
1842 SDP()_EPF()_R()_IN_INSTR_BADDR) and first indirect DPTR reads.
1843 ADDRTYPE\<0\> is the relaxed-order attribute for PCIe. */
1844 uint64_t esr : 2; /**< [ 2: 1](R/W/H) [ESR] is ES\<1:0\> for input instruction reads (from
1845 SDP()_EPF()_R()_IN_INSTR_BADDR) and first indirect DPTR reads. ES\<1:0\> is
1846 the endian-swap attribute for these MAC memory space reads.
1847 Enumerated by SLI_ENDIANSWAP_E. */
1848 uint64_t nsr : 1; /**< [ 3: 3](R/W/H) [NSR] is ADDRTYPE\<1\> for input instruction reads (from
1849 SDP()_EPF()_R()_IN_INSTR_BADDR) and first indirect DPTR reads. ADDRTYPE\<1\>
1850 is the no-snoop attribute for PCIe. */
1851 uint64_t reserved_4 : 1;
1852 uint64_t d_ror : 1; /**< [ 5: 5](R/W/H) [D_ROR] is ADDRTYPE\<0\> for first direct and gather DPTR reads. ADDRTYPE\<0\> is the
1853 relaxed-order attribute for PCIe. */
1854 uint64_t d_esr : 2; /**< [ 7: 6](R/W/H) [D_ESR] is ES\<1:0\> for first direct and gather DPTR reads.
1855 ES\<1:0\> is the endian-swap attribute for these MAC memory space reads.
1856 Enumerated by SLI_ENDIANSWAP_E. */
1857 uint64_t d_nsr : 1; /**< [ 8: 8](R/W/H) [D_NSR] is ADDRTYPE\<1\> for first direct and gather DPTR reads. ADDRTYPE\<1\> is the
1858 no-snoop attribute for PCIe. */
1859 uint64_t reserved_9_23 : 15;
1860 uint64_t is64b : 1; /**< [ 24: 24](R/W) If 1, the ring uses 64-byte instructions.
1861 If 0, the ring uses 32-byte instructions. */
1862 uint64_t rdsize : 2; /**< [ 26: 25](R/W) Number of instructions to be read in one read request. Two-bit values are:
1863 0x0 = 1 instruction.
1864 0x1 = 2 instructions.
1865 0x2 = 4 instructions.
1866 0x3 = 8 instructions. */
1867 uint64_t reserved_27 : 1;
1868 uint64_t idle : 1; /**< [ 28: 28](RO/H) Asserted when this ring has no packets in-flight. */
1869 uint64_t reserved_29_47 : 19;
1870 uint64_t rpvf : 4; /**< [ 51: 48](RO/H) The number of rings assigned to this VF.
1871 Read only copy of SDP()_EPF()_RINFO[RPVF] */
1872 uint64_t reserved_52_63 : 12;
1873 #endif /* Word 0 - End */
1874 } s;
1875 /* struct bdk_sdpx_epfx_rx_in_control_s cn; */
1876 };
1877 typedef union bdk_sdpx_epfx_rx_in_control bdk_sdpx_epfx_rx_in_control_t;
1878
1879 static inline uint64_t BDK_SDPX_EPFX_RX_IN_CONTROL(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_RX_IN_CONTROL(unsigned long a,unsigned long b,unsigned long c)1880 static inline uint64_t BDK_SDPX_EPFX_RX_IN_CONTROL(unsigned long a, unsigned long b, unsigned long c)
1881 {
1882 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1) && (c<=63)))
1883 return 0x874080010000ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1) + 0x20000ll * ((c) & 0x3f);
1884 __bdk_csr_fatal("SDPX_EPFX_RX_IN_CONTROL", 3, a, b, c, 0);
1885 }
1886
1887 #define typedef_BDK_SDPX_EPFX_RX_IN_CONTROL(a,b,c) bdk_sdpx_epfx_rx_in_control_t
1888 #define bustype_BDK_SDPX_EPFX_RX_IN_CONTROL(a,b,c) BDK_CSR_TYPE_PEXP_NCB
1889 #define basename_BDK_SDPX_EPFX_RX_IN_CONTROL(a,b,c) "SDPX_EPFX_RX_IN_CONTROL"
1890 #define device_bar_BDK_SDPX_EPFX_RX_IN_CONTROL(a,b,c) 0x0 /* PF_BAR0 */
1891 #define busnum_BDK_SDPX_EPFX_RX_IN_CONTROL(a,b,c) (a)
1892 #define arguments_BDK_SDPX_EPFX_RX_IN_CONTROL(a,b,c) (a),(b),(c),-1
1893
1894 /**
1895 * Register (PEXP_NCB) sdp#_epf#_r#_in_enable
1896 *
1897 * SDP Input Instruction Ring Enable Register
1898 * This register is the enable for read operations on the input instruction rings.
1899 */
1900 union bdk_sdpx_epfx_rx_in_enable
1901 {
1902 uint64_t u;
1903 struct bdk_sdpx_epfx_rx_in_enable_s
1904 {
1905 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1906 uint64_t reserved_1_63 : 63;
1907 uint64_t enb : 1; /**< [ 0: 0](R/W/H) Enable for the input ring. Various errors and FLR events can clear this bit.
1908 Software can also clear this bit at anytime. The bit may not be set unless
1909 SDP()_EPF()_R()_IN_CONTROL[IDLE] == 0. */
1910 #else /* Word 0 - Little Endian */
1911 uint64_t enb : 1; /**< [ 0: 0](R/W/H) Enable for the input ring. Various errors and FLR events can clear this bit.
1912 Software can also clear this bit at anytime. The bit may not be set unless
1913 SDP()_EPF()_R()_IN_CONTROL[IDLE] == 0. */
1914 uint64_t reserved_1_63 : 63;
1915 #endif /* Word 0 - End */
1916 } s;
1917 /* struct bdk_sdpx_epfx_rx_in_enable_s cn; */
1918 };
1919 typedef union bdk_sdpx_epfx_rx_in_enable bdk_sdpx_epfx_rx_in_enable_t;
1920
1921 static inline uint64_t BDK_SDPX_EPFX_RX_IN_ENABLE(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_RX_IN_ENABLE(unsigned long a,unsigned long b,unsigned long c)1922 static inline uint64_t BDK_SDPX_EPFX_RX_IN_ENABLE(unsigned long a, unsigned long b, unsigned long c)
1923 {
1924 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1) && (c<=63)))
1925 return 0x874080010010ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1) + 0x20000ll * ((c) & 0x3f);
1926 __bdk_csr_fatal("SDPX_EPFX_RX_IN_ENABLE", 3, a, b, c, 0);
1927 }
1928
1929 #define typedef_BDK_SDPX_EPFX_RX_IN_ENABLE(a,b,c) bdk_sdpx_epfx_rx_in_enable_t
1930 #define bustype_BDK_SDPX_EPFX_RX_IN_ENABLE(a,b,c) BDK_CSR_TYPE_PEXP_NCB
1931 #define basename_BDK_SDPX_EPFX_RX_IN_ENABLE(a,b,c) "SDPX_EPFX_RX_IN_ENABLE"
1932 #define device_bar_BDK_SDPX_EPFX_RX_IN_ENABLE(a,b,c) 0x0 /* PF_BAR0 */
1933 #define busnum_BDK_SDPX_EPFX_RX_IN_ENABLE(a,b,c) (a)
1934 #define arguments_BDK_SDPX_EPFX_RX_IN_ENABLE(a,b,c) (a),(b),(c),-1
1935
1936 /**
1937 * Register (PEXP_NCB) sdp#_epf#_r#_in_instr_baddr
1938 *
1939 * SDP Input Instruction Ring Base Address Register
1940 * This register contains the base address for the input instruction ring.
1941 * This register is not affected by reset (including FLR) and must be initialized
1942 * by the VF prior to enabling the ring. Also, this register cannot be written
1943 * while either of the following conditions is true:
1944 * * SDP()_EPF()_R()_IN_CONTROL[IDLE] is clear.
1945 * * Or, SDP()_EPF()_R()_IN_ENABLE[ENB] is set.
1946 */
1947 union bdk_sdpx_epfx_rx_in_instr_baddr
1948 {
1949 uint64_t u;
1950 struct bdk_sdpx_epfx_rx_in_instr_baddr_s
1951 {
1952 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1953 uint64_t addr : 60; /**< [ 63: 4](R/W) Base address for input instruction ring. Must be 16-byte aligned. */
1954 uint64_t reserved_0_3 : 4;
1955 #else /* Word 0 - Little Endian */
1956 uint64_t reserved_0_3 : 4;
1957 uint64_t addr : 60; /**< [ 63: 4](R/W) Base address for input instruction ring. Must be 16-byte aligned. */
1958 #endif /* Word 0 - End */
1959 } s;
1960 /* struct bdk_sdpx_epfx_rx_in_instr_baddr_s cn; */
1961 };
1962 typedef union bdk_sdpx_epfx_rx_in_instr_baddr bdk_sdpx_epfx_rx_in_instr_baddr_t;
1963
1964 static inline uint64_t BDK_SDPX_EPFX_RX_IN_INSTR_BADDR(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_RX_IN_INSTR_BADDR(unsigned long a,unsigned long b,unsigned long c)1965 static inline uint64_t BDK_SDPX_EPFX_RX_IN_INSTR_BADDR(unsigned long a, unsigned long b, unsigned long c)
1966 {
1967 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1) && (c<=63)))
1968 return 0x874080010020ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1) + 0x20000ll * ((c) & 0x3f);
1969 __bdk_csr_fatal("SDPX_EPFX_RX_IN_INSTR_BADDR", 3, a, b, c, 0);
1970 }
1971
1972 #define typedef_BDK_SDPX_EPFX_RX_IN_INSTR_BADDR(a,b,c) bdk_sdpx_epfx_rx_in_instr_baddr_t
1973 #define bustype_BDK_SDPX_EPFX_RX_IN_INSTR_BADDR(a,b,c) BDK_CSR_TYPE_PEXP_NCB
1974 #define basename_BDK_SDPX_EPFX_RX_IN_INSTR_BADDR(a,b,c) "SDPX_EPFX_RX_IN_INSTR_BADDR"
1975 #define device_bar_BDK_SDPX_EPFX_RX_IN_INSTR_BADDR(a,b,c) 0x0 /* PF_BAR0 */
1976 #define busnum_BDK_SDPX_EPFX_RX_IN_INSTR_BADDR(a,b,c) (a)
1977 #define arguments_BDK_SDPX_EPFX_RX_IN_INSTR_BADDR(a,b,c) (a),(b),(c),-1
1978
1979 /**
1980 * Register (PEXP_NCB) sdp#_epf#_r#_in_instr_dbell
1981 *
1982 * SDP Input Instruction Ring Input Doorbell Registers
1983 * This register contains the doorbell and base-address offset for the next read operation.
1984 * This register is not affected by reset (including FLR) and must be initialized
1985 * by the VF prior to enabling the ring.
1986 */
1987 union bdk_sdpx_epfx_rx_in_instr_dbell
1988 {
1989 uint64_t u;
1990 struct bdk_sdpx_epfx_rx_in_instr_dbell_s
1991 {
1992 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1993 uint64_t aoff : 32; /**< [ 63: 32](RO/H) Address offset. The offset from the SDP()_EPF()_R()_IN_INSTR_BADDR where the
1994 next pointer is read. A write of 0xFFFFFFFF to [DBELL] clears [DBELL] and [AOFF]. */
1995 uint64_t dbell : 32; /**< [ 31: 0](R/W/H) Pointer list doorbell count. Write operations to this field increments the present
1996 value here. Read operations return the present value. The value of this field is
1997 decremented as read operations are issued for instructions. A write of 0xFFFFFFFF
1998 to this field clears [DBELL] and [AOFF]. This register should be cleared before
1999 enabling a ring. */
2000 #else /* Word 0 - Little Endian */
2001 uint64_t dbell : 32; /**< [ 31: 0](R/W/H) Pointer list doorbell count. Write operations to this field increments the present
2002 value here. Read operations return the present value. The value of this field is
2003 decremented as read operations are issued for instructions. A write of 0xFFFFFFFF
2004 to this field clears [DBELL] and [AOFF]. This register should be cleared before
2005 enabling a ring. */
2006 uint64_t aoff : 32; /**< [ 63: 32](RO/H) Address offset. The offset from the SDP()_EPF()_R()_IN_INSTR_BADDR where the
2007 next pointer is read. A write of 0xFFFFFFFF to [DBELL] clears [DBELL] and [AOFF]. */
2008 #endif /* Word 0 - End */
2009 } s;
2010 /* struct bdk_sdpx_epfx_rx_in_instr_dbell_s cn; */
2011 };
2012 typedef union bdk_sdpx_epfx_rx_in_instr_dbell bdk_sdpx_epfx_rx_in_instr_dbell_t;
2013
2014 static inline uint64_t BDK_SDPX_EPFX_RX_IN_INSTR_DBELL(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_RX_IN_INSTR_DBELL(unsigned long a,unsigned long b,unsigned long c)2015 static inline uint64_t BDK_SDPX_EPFX_RX_IN_INSTR_DBELL(unsigned long a, unsigned long b, unsigned long c)
2016 {
2017 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1) && (c<=63)))
2018 return 0x874080010040ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1) + 0x20000ll * ((c) & 0x3f);
2019 __bdk_csr_fatal("SDPX_EPFX_RX_IN_INSTR_DBELL", 3, a, b, c, 0);
2020 }
2021
2022 #define typedef_BDK_SDPX_EPFX_RX_IN_INSTR_DBELL(a,b,c) bdk_sdpx_epfx_rx_in_instr_dbell_t
2023 #define bustype_BDK_SDPX_EPFX_RX_IN_INSTR_DBELL(a,b,c) BDK_CSR_TYPE_PEXP_NCB
2024 #define basename_BDK_SDPX_EPFX_RX_IN_INSTR_DBELL(a,b,c) "SDPX_EPFX_RX_IN_INSTR_DBELL"
2025 #define device_bar_BDK_SDPX_EPFX_RX_IN_INSTR_DBELL(a,b,c) 0x0 /* PF_BAR0 */
2026 #define busnum_BDK_SDPX_EPFX_RX_IN_INSTR_DBELL(a,b,c) (a)
2027 #define arguments_BDK_SDPX_EPFX_RX_IN_INSTR_DBELL(a,b,c) (a),(b),(c),-1
2028
2029 /**
2030 * Register (PEXP_NCB) sdp#_epf#_r#_in_instr_rsize
2031 *
2032 * SDP Input Instruction Ring Size Register
2033 * This register contains the input instruction ring size.
2034 * This register is not affected by reset (including FLR) and must be initialized
2035 * by the VF prior to enabling the ring. Also, this register cannot be written
2036 * while either of the following conditions is true:
2037 * * SDP()_EPF()_R()_IN_CONTROL[IDLE] is clear.
2038 * * or, SDP()_EPF()_R()_IN_ENABLE[ENB] is set.
2039 */
2040 union bdk_sdpx_epfx_rx_in_instr_rsize
2041 {
2042 uint64_t u;
2043 struct bdk_sdpx_epfx_rx_in_instr_rsize_s
2044 {
2045 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2046 uint64_t reserved_32_63 : 32;
2047 uint64_t rsize : 32; /**< [ 31: 0](R/W) Ring size (number of instructions). */
2048 #else /* Word 0 - Little Endian */
2049 uint64_t rsize : 32; /**< [ 31: 0](R/W) Ring size (number of instructions). */
2050 uint64_t reserved_32_63 : 32;
2051 #endif /* Word 0 - End */
2052 } s;
2053 /* struct bdk_sdpx_epfx_rx_in_instr_rsize_s cn; */
2054 };
2055 typedef union bdk_sdpx_epfx_rx_in_instr_rsize bdk_sdpx_epfx_rx_in_instr_rsize_t;
2056
2057 static inline uint64_t BDK_SDPX_EPFX_RX_IN_INSTR_RSIZE(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_RX_IN_INSTR_RSIZE(unsigned long a,unsigned long b,unsigned long c)2058 static inline uint64_t BDK_SDPX_EPFX_RX_IN_INSTR_RSIZE(unsigned long a, unsigned long b, unsigned long c)
2059 {
2060 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1) && (c<=63)))
2061 return 0x874080010030ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1) + 0x20000ll * ((c) & 0x3f);
2062 __bdk_csr_fatal("SDPX_EPFX_RX_IN_INSTR_RSIZE", 3, a, b, c, 0);
2063 }
2064
2065 #define typedef_BDK_SDPX_EPFX_RX_IN_INSTR_RSIZE(a,b,c) bdk_sdpx_epfx_rx_in_instr_rsize_t
2066 #define bustype_BDK_SDPX_EPFX_RX_IN_INSTR_RSIZE(a,b,c) BDK_CSR_TYPE_PEXP_NCB
2067 #define basename_BDK_SDPX_EPFX_RX_IN_INSTR_RSIZE(a,b,c) "SDPX_EPFX_RX_IN_INSTR_RSIZE"
2068 #define device_bar_BDK_SDPX_EPFX_RX_IN_INSTR_RSIZE(a,b,c) 0x0 /* PF_BAR0 */
2069 #define busnum_BDK_SDPX_EPFX_RX_IN_INSTR_RSIZE(a,b,c) (a)
2070 #define arguments_BDK_SDPX_EPFX_RX_IN_INSTR_RSIZE(a,b,c) (a),(b),(c),-1
2071
2072 /**
2073 * Register (PEXP_NCB) sdp#_epf#_r#_in_int_levels
2074 *
2075 * SDP Input Instruction Interrupt Levels Register
2076 * This register contains input instruction interrupt levels.
2077 * This register is not affected by reset (including FLR) and must be initialized
2078 * by the VF prior to enabling the ring.
2079 */
2080 union bdk_sdpx_epfx_rx_in_int_levels
2081 {
2082 uint64_t u;
2083 struct bdk_sdpx_epfx_rx_in_int_levels_s
2084 {
2085 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2086 uint64_t reserved_32_63 : 32;
2087 uint64_t cnt : 32; /**< [ 31: 0](R/W) Input packet counter interrupt threshold. An MSI-X interrupt will be generated
2088 whenever SDP()_EPF()_R()_IN_CNTS[CNT] \> [CNT]. Whenever software changes the value of
2089 [CNT], it should also subsequently write the corresponding SDP()_R()_IN_CNTS[CNT] CSR
2090 (with a value of zero if desired) to ensure that the hardware correspondingly updates
2091 SDP()_EPF()_R()_IN_CNTS[IN_INT] */
2092 #else /* Word 0 - Little Endian */
2093 uint64_t cnt : 32; /**< [ 31: 0](R/W) Input packet counter interrupt threshold. An MSI-X interrupt will be generated
2094 whenever SDP()_EPF()_R()_IN_CNTS[CNT] \> [CNT]. Whenever software changes the value of
2095 [CNT], it should also subsequently write the corresponding SDP()_R()_IN_CNTS[CNT] CSR
2096 (with a value of zero if desired) to ensure that the hardware correspondingly updates
2097 SDP()_EPF()_R()_IN_CNTS[IN_INT] */
2098 uint64_t reserved_32_63 : 32;
2099 #endif /* Word 0 - End */
2100 } s;
2101 /* struct bdk_sdpx_epfx_rx_in_int_levels_s cn; */
2102 };
2103 typedef union bdk_sdpx_epfx_rx_in_int_levels bdk_sdpx_epfx_rx_in_int_levels_t;
2104
2105 static inline uint64_t BDK_SDPX_EPFX_RX_IN_INT_LEVELS(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_RX_IN_INT_LEVELS(unsigned long a,unsigned long b,unsigned long c)2106 static inline uint64_t BDK_SDPX_EPFX_RX_IN_INT_LEVELS(unsigned long a, unsigned long b, unsigned long c)
2107 {
2108 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1) && (c<=63)))
2109 return 0x874080010060ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1) + 0x20000ll * ((c) & 0x3f);
2110 __bdk_csr_fatal("SDPX_EPFX_RX_IN_INT_LEVELS", 3, a, b, c, 0);
2111 }
2112
2113 #define typedef_BDK_SDPX_EPFX_RX_IN_INT_LEVELS(a,b,c) bdk_sdpx_epfx_rx_in_int_levels_t
2114 #define bustype_BDK_SDPX_EPFX_RX_IN_INT_LEVELS(a,b,c) BDK_CSR_TYPE_PEXP_NCB
2115 #define basename_BDK_SDPX_EPFX_RX_IN_INT_LEVELS(a,b,c) "SDPX_EPFX_RX_IN_INT_LEVELS"
2116 #define device_bar_BDK_SDPX_EPFX_RX_IN_INT_LEVELS(a,b,c) 0x0 /* PF_BAR0 */
2117 #define busnum_BDK_SDPX_EPFX_RX_IN_INT_LEVELS(a,b,c) (a)
2118 #define arguments_BDK_SDPX_EPFX_RX_IN_INT_LEVELS(a,b,c) (a),(b),(c),-1
2119
2120 /**
2121 * Register (PEXP_NCB) sdp#_epf#_r#_in_int_status
2122 *
2123 * SDP Ring Input Packet Interrupt Status Register
2124 * This register contains interrupt status on a per-VF basis. All rings for a given VF
2125 * are located in a single register. Note that access to any ring offset within a given
2126 * VF will return the same value. When the PF reads any ring in this register it will
2127 * return the same value (64 bits each representing one ring.)
2128 */
2129 union bdk_sdpx_epfx_rx_in_int_status
2130 {
2131 uint64_t u;
2132 struct bdk_sdpx_epfx_rx_in_int_status_s
2133 {
2134 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2135 uint64_t intr : 64; /**< [ 63: 0](RO) Interrupt bits for VF rings (0..i). [INTR[i]] reads as one whenever:
2136
2137 * SDP()_EPF()_R()_IN_CNTS[CNT] \> SDP()_EPF()_R()_IN_INT_LEVELS[CNT]
2138
2139 [INTR] can cause an MSI-X interrupt.
2140
2141 Note that "i" depends on the SDP()_EPF()_RINFO configuration.
2142
2143 Internal:
2144 These interrupt bits are not cleared due to FLR becase the CNTS and
2145 LEVELS registers are not reset and we wish to make the interrupt state
2146 consistent with CNTS/LEVELS even after FLR. The CNTS register must be
2147 cleared by software as part of initialization after a reset (including FLR)
2148 which will cause the interrupt state to clear. */
2149 #else /* Word 0 - Little Endian */
2150 uint64_t intr : 64; /**< [ 63: 0](RO) Interrupt bits for VF rings (0..i). [INTR[i]] reads as one whenever:
2151
2152 * SDP()_EPF()_R()_IN_CNTS[CNT] \> SDP()_EPF()_R()_IN_INT_LEVELS[CNT]
2153
2154 [INTR] can cause an MSI-X interrupt.
2155
2156 Note that "i" depends on the SDP()_EPF()_RINFO configuration.
2157
2158 Internal:
2159 These interrupt bits are not cleared due to FLR becase the CNTS and
2160 LEVELS registers are not reset and we wish to make the interrupt state
2161 consistent with CNTS/LEVELS even after FLR. The CNTS register must be
2162 cleared by software as part of initialization after a reset (including FLR)
2163 which will cause the interrupt state to clear. */
2164 #endif /* Word 0 - End */
2165 } s;
2166 /* struct bdk_sdpx_epfx_rx_in_int_status_s cn; */
2167 };
2168 typedef union bdk_sdpx_epfx_rx_in_int_status bdk_sdpx_epfx_rx_in_int_status_t;
2169
2170 static inline uint64_t BDK_SDPX_EPFX_RX_IN_INT_STATUS(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_RX_IN_INT_STATUS(unsigned long a,unsigned long b,unsigned long c)2171 static inline uint64_t BDK_SDPX_EPFX_RX_IN_INT_STATUS(unsigned long a, unsigned long b, unsigned long c)
2172 {
2173 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1) && (c<=63)))
2174 return 0x874080010070ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1) + 0x20000ll * ((c) & 0x3f);
2175 __bdk_csr_fatal("SDPX_EPFX_RX_IN_INT_STATUS", 3, a, b, c, 0);
2176 }
2177
2178 #define typedef_BDK_SDPX_EPFX_RX_IN_INT_STATUS(a,b,c) bdk_sdpx_epfx_rx_in_int_status_t
2179 #define bustype_BDK_SDPX_EPFX_RX_IN_INT_STATUS(a,b,c) BDK_CSR_TYPE_PEXP_NCB
2180 #define basename_BDK_SDPX_EPFX_RX_IN_INT_STATUS(a,b,c) "SDPX_EPFX_RX_IN_INT_STATUS"
2181 #define device_bar_BDK_SDPX_EPFX_RX_IN_INT_STATUS(a,b,c) 0x0 /* PF_BAR0 */
2182 #define busnum_BDK_SDPX_EPFX_RX_IN_INT_STATUS(a,b,c) (a)
2183 #define arguments_BDK_SDPX_EPFX_RX_IN_INT_STATUS(a,b,c) (a),(b),(c),-1
2184
2185 /**
2186 * Register (PEXP_NCB) sdp#_epf#_r#_in_pkt_cnt
2187 *
2188 * SDP Packet Input Packet Count Register
2189 * This register contains packet counts per ring that have been read into SDP.
2190 * The counter will wrap when it reaches its maximum value. It should be cleared
2191 * before the ring is enabled for an accurate count.
2192 */
2193 union bdk_sdpx_epfx_rx_in_pkt_cnt
2194 {
2195 uint64_t u;
2196 struct bdk_sdpx_epfx_rx_in_pkt_cnt_s
2197 {
2198 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2199 uint64_t reserved_36_63 : 28;
2200 uint64_t cnt : 36; /**< [ 35: 0](R/W/H) Packet count, can be written by software to any value. If a value of 0xFFFFFFFFF is
2201 written to this field, it will cause this field as well as SDP()_EPF()_R()_IN_BYTE_CNT to
2202 clear. */
2203 #else /* Word 0 - Little Endian */
2204 uint64_t cnt : 36; /**< [ 35: 0](R/W/H) Packet count, can be written by software to any value. If a value of 0xFFFFFFFFF is
2205 written to this field, it will cause this field as well as SDP()_EPF()_R()_IN_BYTE_CNT to
2206 clear. */
2207 uint64_t reserved_36_63 : 28;
2208 #endif /* Word 0 - End */
2209 } s;
2210 /* struct bdk_sdpx_epfx_rx_in_pkt_cnt_s cn; */
2211 };
2212 typedef union bdk_sdpx_epfx_rx_in_pkt_cnt bdk_sdpx_epfx_rx_in_pkt_cnt_t;
2213
2214 static inline uint64_t BDK_SDPX_EPFX_RX_IN_PKT_CNT(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_RX_IN_PKT_CNT(unsigned long a,unsigned long b,unsigned long c)2215 static inline uint64_t BDK_SDPX_EPFX_RX_IN_PKT_CNT(unsigned long a, unsigned long b, unsigned long c)
2216 {
2217 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1) && (c<=63)))
2218 return 0x874080010080ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1) + 0x20000ll * ((c) & 0x3f);
2219 __bdk_csr_fatal("SDPX_EPFX_RX_IN_PKT_CNT", 3, a, b, c, 0);
2220 }
2221
2222 #define typedef_BDK_SDPX_EPFX_RX_IN_PKT_CNT(a,b,c) bdk_sdpx_epfx_rx_in_pkt_cnt_t
2223 #define bustype_BDK_SDPX_EPFX_RX_IN_PKT_CNT(a,b,c) BDK_CSR_TYPE_PEXP_NCB
2224 #define basename_BDK_SDPX_EPFX_RX_IN_PKT_CNT(a,b,c) "SDPX_EPFX_RX_IN_PKT_CNT"
2225 #define device_bar_BDK_SDPX_EPFX_RX_IN_PKT_CNT(a,b,c) 0x0 /* PF_BAR0 */
2226 #define busnum_BDK_SDPX_EPFX_RX_IN_PKT_CNT(a,b,c) (a)
2227 #define arguments_BDK_SDPX_EPFX_RX_IN_PKT_CNT(a,b,c) (a),(b),(c),-1
2228
2229 /**
2230 * Register (PEXP_NCB) sdp#_epf#_r#_mbox_pf_vf_data
2231 *
2232 * SDP PF to VF Mailbox Data Registers
2233 * These registers are used for communication of data from the PF to VF.
2234 * A write to this register from the PF will cause the corresponding bit in
2235 * SDP()_EPF()_R()_MBOX_PF_VF_INT[INTR] to be set, along with other bits in
2236 * SDP()_EPF()_R()_MBOX_RINT_STATUS, SDP()_EPF()_R()_OUT_CNTS[MBOX_INT], and
2237 * SDP()_EPF()_R()_IN_CNTS[MBOX_INT].
2238 */
2239 union bdk_sdpx_epfx_rx_mbox_pf_vf_data
2240 {
2241 uint64_t u;
2242 struct bdk_sdpx_epfx_rx_mbox_pf_vf_data_s
2243 {
2244 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2245 uint64_t data : 64; /**< [ 63: 0](R/W) Communication data from PF to VF. */
2246 #else /* Word 0 - Little Endian */
2247 uint64_t data : 64; /**< [ 63: 0](R/W) Communication data from PF to VF. */
2248 #endif /* Word 0 - End */
2249 } s;
2250 /* struct bdk_sdpx_epfx_rx_mbox_pf_vf_data_s cn; */
2251 };
2252 typedef union bdk_sdpx_epfx_rx_mbox_pf_vf_data bdk_sdpx_epfx_rx_mbox_pf_vf_data_t;
2253
2254 static inline uint64_t BDK_SDPX_EPFX_RX_MBOX_PF_VF_DATA(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_RX_MBOX_PF_VF_DATA(unsigned long a,unsigned long b,unsigned long c)2255 static inline uint64_t BDK_SDPX_EPFX_RX_MBOX_PF_VF_DATA(unsigned long a, unsigned long b, unsigned long c)
2256 {
2257 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1) && (c<=63)))
2258 return 0x874080010210ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1) + 0x20000ll * ((c) & 0x3f);
2259 __bdk_csr_fatal("SDPX_EPFX_RX_MBOX_PF_VF_DATA", 3, a, b, c, 0);
2260 }
2261
2262 #define typedef_BDK_SDPX_EPFX_RX_MBOX_PF_VF_DATA(a,b,c) bdk_sdpx_epfx_rx_mbox_pf_vf_data_t
2263 #define bustype_BDK_SDPX_EPFX_RX_MBOX_PF_VF_DATA(a,b,c) BDK_CSR_TYPE_PEXP_NCB
2264 #define basename_BDK_SDPX_EPFX_RX_MBOX_PF_VF_DATA(a,b,c) "SDPX_EPFX_RX_MBOX_PF_VF_DATA"
2265 #define device_bar_BDK_SDPX_EPFX_RX_MBOX_PF_VF_DATA(a,b,c) 0x0 /* PF_BAR0 */
2266 #define busnum_BDK_SDPX_EPFX_RX_MBOX_PF_VF_DATA(a,b,c) (a)
2267 #define arguments_BDK_SDPX_EPFX_RX_MBOX_PF_VF_DATA(a,b,c) (a),(b),(c),-1
2268
2269 /**
2270 * Register (PEXP_NCB) sdp#_epf#_r#_mbox_pf_vf_int
2271 *
2272 * SDP Packet PF to VF Mailbox Interrupt Register
2273 * These registers contain interrupt status and enable for the PF to VF mailbox communication
2274 * registers. A write to SDP()_EPF()_R()_MBOX_VF_PF_DATA from the PF will cause the [INTR] bit
2275 * in this register to set, along with corresponding bits in SDP()_EPF()_R()_MBOX_RINT_STATUS,
2276 * SDP()_EPF()_R()_OUT_CNTS[MBOX_INT], and SDP()_EPF()_R()_IN_CNTS[MBOX_INT].
2277 * All of these bits are cleared by writing 1 to the [INTR] bit in this register.
2278 * If the [ENAB] bit is set, then an MSI-X interrupt will also be generated when the [INTR] bit
2279 * is set. This register is cleared also due to an FLR.
2280 */
2281 union bdk_sdpx_epfx_rx_mbox_pf_vf_int
2282 {
2283 uint64_t u;
2284 struct bdk_sdpx_epfx_rx_mbox_pf_vf_int_s
2285 {
2286 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2287 uint64_t reserved_2_63 : 62;
2288 uint64_t enab : 1; /**< [ 1: 1](R/W) PF to VF mailbox interrupt enable. */
2289 uint64_t intr : 1; /**< [ 0: 0](R/W1C/H) PF to VF mailbox interrupt signal. */
2290 #else /* Word 0 - Little Endian */
2291 uint64_t intr : 1; /**< [ 0: 0](R/W1C/H) PF to VF mailbox interrupt signal. */
2292 uint64_t enab : 1; /**< [ 1: 1](R/W) PF to VF mailbox interrupt enable. */
2293 uint64_t reserved_2_63 : 62;
2294 #endif /* Word 0 - End */
2295 } s;
2296 /* struct bdk_sdpx_epfx_rx_mbox_pf_vf_int_s cn; */
2297 };
2298 typedef union bdk_sdpx_epfx_rx_mbox_pf_vf_int bdk_sdpx_epfx_rx_mbox_pf_vf_int_t;
2299
2300 static inline uint64_t BDK_SDPX_EPFX_RX_MBOX_PF_VF_INT(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_RX_MBOX_PF_VF_INT(unsigned long a,unsigned long b,unsigned long c)2301 static inline uint64_t BDK_SDPX_EPFX_RX_MBOX_PF_VF_INT(unsigned long a, unsigned long b, unsigned long c)
2302 {
2303 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1) && (c<=63)))
2304 return 0x874080010220ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1) + 0x20000ll * ((c) & 0x3f);
2305 __bdk_csr_fatal("SDPX_EPFX_RX_MBOX_PF_VF_INT", 3, a, b, c, 0);
2306 }
2307
2308 #define typedef_BDK_SDPX_EPFX_RX_MBOX_PF_VF_INT(a,b,c) bdk_sdpx_epfx_rx_mbox_pf_vf_int_t
2309 #define bustype_BDK_SDPX_EPFX_RX_MBOX_PF_VF_INT(a,b,c) BDK_CSR_TYPE_PEXP_NCB
2310 #define basename_BDK_SDPX_EPFX_RX_MBOX_PF_VF_INT(a,b,c) "SDPX_EPFX_RX_MBOX_PF_VF_INT"
2311 #define device_bar_BDK_SDPX_EPFX_RX_MBOX_PF_VF_INT(a,b,c) 0x0 /* PF_BAR0 */
2312 #define busnum_BDK_SDPX_EPFX_RX_MBOX_PF_VF_INT(a,b,c) (a)
2313 #define arguments_BDK_SDPX_EPFX_RX_MBOX_PF_VF_INT(a,b,c) (a),(b),(c),-1
2314
2315 /**
2316 * Register (PEXP_NCB) sdp#_epf#_r#_mbox_rint_status
2317 *
2318 * SDP Mailbox Interrupt Status Register
2319 * This register contains PF-\>VF mailbox interrupt status on a per-VF basis.
2320 * All rings for a given VF are located in a single register. Note that access to any ring offset
2321 * within a given VF will return the same value. When the PF reads any ring in this register it
2322 * will return the same value (64 bits each representing one ring.)
2323 */
2324 union bdk_sdpx_epfx_rx_mbox_rint_status
2325 {
2326 uint64_t u;
2327 struct bdk_sdpx_epfx_rx_mbox_rint_status_s
2328 {
2329 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2330 uint64_t intr : 64; /**< [ 63: 0](RO) Interrupt bits for VF rings (0..i). [INTR[i]] reads as one whenever a mailbox
2331 interrupt has been signaled by the PF and not cleared by the VF.
2332 These bits are cleared by writing SDP()_EPF()_R()_MBOX_PF_VF_INT[INTR]
2333 them with a 1, or due to an FLR.
2334
2335 [INTR] can cause an MSI-X interrupt.
2336
2337 Note that "i" depends on the SDP()_EPF()_RINFO configuration. */
2338 #else /* Word 0 - Little Endian */
2339 uint64_t intr : 64; /**< [ 63: 0](RO) Interrupt bits for VF rings (0..i). [INTR[i]] reads as one whenever a mailbox
2340 interrupt has been signaled by the PF and not cleared by the VF.
2341 These bits are cleared by writing SDP()_EPF()_R()_MBOX_PF_VF_INT[INTR]
2342 them with a 1, or due to an FLR.
2343
2344 [INTR] can cause an MSI-X interrupt.
2345
2346 Note that "i" depends on the SDP()_EPF()_RINFO configuration. */
2347 #endif /* Word 0 - End */
2348 } s;
2349 /* struct bdk_sdpx_epfx_rx_mbox_rint_status_s cn; */
2350 };
2351 typedef union bdk_sdpx_epfx_rx_mbox_rint_status bdk_sdpx_epfx_rx_mbox_rint_status_t;
2352
2353 static inline uint64_t BDK_SDPX_EPFX_RX_MBOX_RINT_STATUS(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_RX_MBOX_RINT_STATUS(unsigned long a,unsigned long b,unsigned long c)2354 static inline uint64_t BDK_SDPX_EPFX_RX_MBOX_RINT_STATUS(unsigned long a, unsigned long b, unsigned long c)
2355 {
2356 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1) && (c<=63)))
2357 return 0x874080010200ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1) + 0x20000ll * ((c) & 0x3f);
2358 __bdk_csr_fatal("SDPX_EPFX_RX_MBOX_RINT_STATUS", 3, a, b, c, 0);
2359 }
2360
2361 #define typedef_BDK_SDPX_EPFX_RX_MBOX_RINT_STATUS(a,b,c) bdk_sdpx_epfx_rx_mbox_rint_status_t
2362 #define bustype_BDK_SDPX_EPFX_RX_MBOX_RINT_STATUS(a,b,c) BDK_CSR_TYPE_PEXP_NCB
2363 #define basename_BDK_SDPX_EPFX_RX_MBOX_RINT_STATUS(a,b,c) "SDPX_EPFX_RX_MBOX_RINT_STATUS"
2364 #define device_bar_BDK_SDPX_EPFX_RX_MBOX_RINT_STATUS(a,b,c) 0x0 /* PF_BAR0 */
2365 #define busnum_BDK_SDPX_EPFX_RX_MBOX_RINT_STATUS(a,b,c) (a)
2366 #define arguments_BDK_SDPX_EPFX_RX_MBOX_RINT_STATUS(a,b,c) (a),(b),(c),-1
2367
2368 /**
2369 * Register (PEXP_NCB) sdp#_epf#_r#_mbox_vf_pf_data
2370 *
2371 * SDP VF to PF Mailbox Data Registers
2372 * These registers are used for communication of data from the VF to PF.
2373 * A write by the VF to this register will cause the corresponding bit in
2374 * SDP()_MBOX_EPF()_INT to be set to be set, and an MSI-X message to be generated.
2375 * To clear the interrupt condition, the PF should write a 1 to SDP()_MBOX_EPF()_INT.
2376 */
2377 union bdk_sdpx_epfx_rx_mbox_vf_pf_data
2378 {
2379 uint64_t u;
2380 struct bdk_sdpx_epfx_rx_mbox_vf_pf_data_s
2381 {
2382 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2383 uint64_t data : 64; /**< [ 63: 0](R/W) Communication data from VF to PF. */
2384 #else /* Word 0 - Little Endian */
2385 uint64_t data : 64; /**< [ 63: 0](R/W) Communication data from VF to PF. */
2386 #endif /* Word 0 - End */
2387 } s;
2388 /* struct bdk_sdpx_epfx_rx_mbox_vf_pf_data_s cn; */
2389 };
2390 typedef union bdk_sdpx_epfx_rx_mbox_vf_pf_data bdk_sdpx_epfx_rx_mbox_vf_pf_data_t;
2391
2392 static inline uint64_t BDK_SDPX_EPFX_RX_MBOX_VF_PF_DATA(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_RX_MBOX_VF_PF_DATA(unsigned long a,unsigned long b,unsigned long c)2393 static inline uint64_t BDK_SDPX_EPFX_RX_MBOX_VF_PF_DATA(unsigned long a, unsigned long b, unsigned long c)
2394 {
2395 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1) && (c<=63)))
2396 return 0x874080010230ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1) + 0x20000ll * ((c) & 0x3f);
2397 __bdk_csr_fatal("SDPX_EPFX_RX_MBOX_VF_PF_DATA", 3, a, b, c, 0);
2398 }
2399
2400 #define typedef_BDK_SDPX_EPFX_RX_MBOX_VF_PF_DATA(a,b,c) bdk_sdpx_epfx_rx_mbox_vf_pf_data_t
2401 #define bustype_BDK_SDPX_EPFX_RX_MBOX_VF_PF_DATA(a,b,c) BDK_CSR_TYPE_PEXP_NCB
2402 #define basename_BDK_SDPX_EPFX_RX_MBOX_VF_PF_DATA(a,b,c) "SDPX_EPFX_RX_MBOX_VF_PF_DATA"
2403 #define device_bar_BDK_SDPX_EPFX_RX_MBOX_VF_PF_DATA(a,b,c) 0x0 /* PF_BAR0 */
2404 #define busnum_BDK_SDPX_EPFX_RX_MBOX_VF_PF_DATA(a,b,c) (a)
2405 #define arguments_BDK_SDPX_EPFX_RX_MBOX_VF_PF_DATA(a,b,c) (a),(b),(c),-1
2406
2407 /**
2408 * Register (PEXP_NCB) sdp#_epf#_r#_out_byte_cnt
2409 *
2410 * SDP Packet Output Byte Count Register
2411 * This register contains byte counts per ring that have been written to memory by SDP.
2412 * The counter will wrap when it reaches its maximum value. It should be cleared
2413 * before the ring is enabled for an accurate count.
2414 */
2415 union bdk_sdpx_epfx_rx_out_byte_cnt
2416 {
2417 uint64_t u;
2418 struct bdk_sdpx_epfx_rx_out_byte_cnt_s
2419 {
2420 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2421 uint64_t reserved_48_63 : 16;
2422 uint64_t cnt : 48; /**< [ 47: 0](R/W/H) Byte count, can be reset by software by writing SDP()_EPF()_R()_OUT_PKT_CNT[CNT]
2423 with 0xFFFFFFFFF. */
2424 #else /* Word 0 - Little Endian */
2425 uint64_t cnt : 48; /**< [ 47: 0](R/W/H) Byte count, can be reset by software by writing SDP()_EPF()_R()_OUT_PKT_CNT[CNT]
2426 with 0xFFFFFFFFF. */
2427 uint64_t reserved_48_63 : 16;
2428 #endif /* Word 0 - End */
2429 } s;
2430 /* struct bdk_sdpx_epfx_rx_out_byte_cnt_s cn; */
2431 };
2432 typedef union bdk_sdpx_epfx_rx_out_byte_cnt bdk_sdpx_epfx_rx_out_byte_cnt_t;
2433
2434 static inline uint64_t BDK_SDPX_EPFX_RX_OUT_BYTE_CNT(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_RX_OUT_BYTE_CNT(unsigned long a,unsigned long b,unsigned long c)2435 static inline uint64_t BDK_SDPX_EPFX_RX_OUT_BYTE_CNT(unsigned long a, unsigned long b, unsigned long c)
2436 {
2437 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1) && (c<=63)))
2438 return 0x874080010190ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1) + 0x20000ll * ((c) & 0x3f);
2439 __bdk_csr_fatal("SDPX_EPFX_RX_OUT_BYTE_CNT", 3, a, b, c, 0);
2440 }
2441
2442 #define typedef_BDK_SDPX_EPFX_RX_OUT_BYTE_CNT(a,b,c) bdk_sdpx_epfx_rx_out_byte_cnt_t
2443 #define bustype_BDK_SDPX_EPFX_RX_OUT_BYTE_CNT(a,b,c) BDK_CSR_TYPE_PEXP_NCB
2444 #define basename_BDK_SDPX_EPFX_RX_OUT_BYTE_CNT(a,b,c) "SDPX_EPFX_RX_OUT_BYTE_CNT"
2445 #define device_bar_BDK_SDPX_EPFX_RX_OUT_BYTE_CNT(a,b,c) 0x0 /* PF_BAR0 */
2446 #define busnum_BDK_SDPX_EPFX_RX_OUT_BYTE_CNT(a,b,c) (a)
2447 #define arguments_BDK_SDPX_EPFX_RX_OUT_BYTE_CNT(a,b,c) (a),(b),(c),-1
2448
2449 /**
2450 * Register (PEXP_NCB) sdp#_epf#_r#_out_cnts
2451 *
2452 * SDP Packet Output Counts Register
2453 * This register contains the counters for SDP output ports.
2454 * This register is not affected by reset (including FLR) and must be initialized
2455 * by the VF prior to enabling the ring.
2456 */
2457 union bdk_sdpx_epfx_rx_out_cnts
2458 {
2459 uint64_t u;
2460 struct bdk_sdpx_epfx_rx_out_cnts_s
2461 {
2462 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2463 uint64_t reserved_63 : 1;
2464 uint64_t out_int : 1; /**< [ 62: 62](RO/H) Returns a 1 when:
2465 * SDP()_EPF()_R()_OUT_CNTS[CNT] \> SDP()_EPF()_R()_OUT_INT_LEVELS[CNT].
2466 * Or, SDP()_EPF()_R()_OUT_CNTS[TIMER] \> SDP()_EPF()_R()_OUT_INT_LEVELS[TIMET].
2467
2468 To clear the bit, the CNTS register must be written to clear the underlying condition. */
2469 uint64_t in_int : 1; /**< [ 61: 61](RO/H) Returns a 1 when:
2470 * SDP()_EPF()_R()_IN_CNTS[CNT] \> SDP()_EPF()_R()_IN_INT_LEVELS[CNT].
2471
2472 To clear the bit, the SDP()_EPF()_R()_IN_CNTS register must be written to clear the
2473 underlying condition. */
2474 uint64_t mbox_int : 1; /**< [ 60: 60](RO/H) Returns a 1 when:
2475 * SDP()_EPF()_R()_MBOX_RINT_STATUS[INTR] is set.
2476
2477 To clear the bit, write SDP()_EPF()_R()_MBOX_PF_VF_INT[INTR] with 1.
2478 This bit is also cleared due to an FLR. */
2479 uint64_t resend : 1; /**< [ 59: 59](WO/H) A write of 1 will resend an MSI-X interrupt message if any of the following
2480 conditions are true for the respective ring R():
2481 * SDP()_EPF()_R()_OUT_CNTS[CNT] \> SDP()_EPF()_R()_OUT_INT_LEVELS[CNT],
2482 * SDP()_EPF()_R()_OUT_CNTS[TIMER] \> SDP()_EPF()_R()_OUT_INT_LEVELS[TIMET],
2483 * SDP()_EPF()_R()_IN_CNTS[CNT] \> SDP()_EPF()_R()_IN_INT_LEVELS[CNT],
2484 * SDP()_EPF()_R()_MBOX_RINT_STATUS[INTR] is set. */
2485 uint64_t reserved_54_58 : 5;
2486 uint64_t timer : 22; /**< [ 53: 32](RO/H) Timer, incremented every 1024 coprocessor-clock cycles when [CNT] is
2487 not zero. The hardware clears [TIMER] when [CNT]
2488 goes to 0. The first increment of this count can occur between 0 to
2489 1023 coprocessor-clock cycles after [CNT] becomes nonzero. */
2490 uint64_t cnt : 32; /**< [ 31: 0](R/W/H) Packet counter. Hardware adds to [CNT] as it sends packets out. On a write
2491 to this CSR, hardware subtracts the amount written to the [CNT] field from
2492 [CNT], which will clear SDP()_EPF()_R()_OUT_INT_STATUS[INTR] if [CNT] becomes \<=
2493 SDP()_EPF()_R()_OUT_INT_LEVELS[CNT]. When SDP()_EPF()_R()_OUT_INT_LEVELS[BMODE] is clear,
2494 the hardware adds 1 to [CNT] per packet. When SDP()_EPF()_R()_OUT_INT_LEVELS[BMODE] is
2495 set,
2496 the hardware adds the packet length to [CNT] per packet. */
2497 #else /* Word 0 - Little Endian */
2498 uint64_t cnt : 32; /**< [ 31: 0](R/W/H) Packet counter. Hardware adds to [CNT] as it sends packets out. On a write
2499 to this CSR, hardware subtracts the amount written to the [CNT] field from
2500 [CNT], which will clear SDP()_EPF()_R()_OUT_INT_STATUS[INTR] if [CNT] becomes \<=
2501 SDP()_EPF()_R()_OUT_INT_LEVELS[CNT]. When SDP()_EPF()_R()_OUT_INT_LEVELS[BMODE] is clear,
2502 the hardware adds 1 to [CNT] per packet. When SDP()_EPF()_R()_OUT_INT_LEVELS[BMODE] is
2503 set,
2504 the hardware adds the packet length to [CNT] per packet. */
2505 uint64_t timer : 22; /**< [ 53: 32](RO/H) Timer, incremented every 1024 coprocessor-clock cycles when [CNT] is
2506 not zero. The hardware clears [TIMER] when [CNT]
2507 goes to 0. The first increment of this count can occur between 0 to
2508 1023 coprocessor-clock cycles after [CNT] becomes nonzero. */
2509 uint64_t reserved_54_58 : 5;
2510 uint64_t resend : 1; /**< [ 59: 59](WO/H) A write of 1 will resend an MSI-X interrupt message if any of the following
2511 conditions are true for the respective ring R():
2512 * SDP()_EPF()_R()_OUT_CNTS[CNT] \> SDP()_EPF()_R()_OUT_INT_LEVELS[CNT],
2513 * SDP()_EPF()_R()_OUT_CNTS[TIMER] \> SDP()_EPF()_R()_OUT_INT_LEVELS[TIMET],
2514 * SDP()_EPF()_R()_IN_CNTS[CNT] \> SDP()_EPF()_R()_IN_INT_LEVELS[CNT],
2515 * SDP()_EPF()_R()_MBOX_RINT_STATUS[INTR] is set. */
2516 uint64_t mbox_int : 1; /**< [ 60: 60](RO/H) Returns a 1 when:
2517 * SDP()_EPF()_R()_MBOX_RINT_STATUS[INTR] is set.
2518
2519 To clear the bit, write SDP()_EPF()_R()_MBOX_PF_VF_INT[INTR] with 1.
2520 This bit is also cleared due to an FLR. */
2521 uint64_t in_int : 1; /**< [ 61: 61](RO/H) Returns a 1 when:
2522 * SDP()_EPF()_R()_IN_CNTS[CNT] \> SDP()_EPF()_R()_IN_INT_LEVELS[CNT].
2523
2524 To clear the bit, the SDP()_EPF()_R()_IN_CNTS register must be written to clear the
2525 underlying condition. */
2526 uint64_t out_int : 1; /**< [ 62: 62](RO/H) Returns a 1 when:
2527 * SDP()_EPF()_R()_OUT_CNTS[CNT] \> SDP()_EPF()_R()_OUT_INT_LEVELS[CNT].
2528 * Or, SDP()_EPF()_R()_OUT_CNTS[TIMER] \> SDP()_EPF()_R()_OUT_INT_LEVELS[TIMET].
2529
2530 To clear the bit, the CNTS register must be written to clear the underlying condition. */
2531 uint64_t reserved_63 : 1;
2532 #endif /* Word 0 - End */
2533 } s;
2534 /* struct bdk_sdpx_epfx_rx_out_cnts_s cn; */
2535 };
2536 typedef union bdk_sdpx_epfx_rx_out_cnts bdk_sdpx_epfx_rx_out_cnts_t;
2537
2538 static inline uint64_t BDK_SDPX_EPFX_RX_OUT_CNTS(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_RX_OUT_CNTS(unsigned long a,unsigned long b,unsigned long c)2539 static inline uint64_t BDK_SDPX_EPFX_RX_OUT_CNTS(unsigned long a, unsigned long b, unsigned long c)
2540 {
2541 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1) && (c<=63)))
2542 return 0x874080010100ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1) + 0x20000ll * ((c) & 0x3f);
2543 __bdk_csr_fatal("SDPX_EPFX_RX_OUT_CNTS", 3, a, b, c, 0);
2544 }
2545
2546 #define typedef_BDK_SDPX_EPFX_RX_OUT_CNTS(a,b,c) bdk_sdpx_epfx_rx_out_cnts_t
2547 #define bustype_BDK_SDPX_EPFX_RX_OUT_CNTS(a,b,c) BDK_CSR_TYPE_PEXP_NCB
2548 #define basename_BDK_SDPX_EPFX_RX_OUT_CNTS(a,b,c) "SDPX_EPFX_RX_OUT_CNTS"
2549 #define device_bar_BDK_SDPX_EPFX_RX_OUT_CNTS(a,b,c) 0x0 /* PF_BAR0 */
2550 #define busnum_BDK_SDPX_EPFX_RX_OUT_CNTS(a,b,c) (a)
2551 #define arguments_BDK_SDPX_EPFX_RX_OUT_CNTS(a,b,c) (a),(b),(c),-1
2552
2553 /**
2554 * Register (PEXP_NCB) sdp#_epf#_r#_out_control
2555 *
2556 * SDP Packet Output Control Register
2557 * This register contains control bits for output packet rings.
2558 * This register is not affected by reset (including FLR) and must be initialized
2559 * by the VF prior to enabling the ring. Also, this register cannot be written
2560 * while either of the following conditions is true:
2561 * * SDP()_EPF()_R()_OUT_CONTROL[IDLE] is clear.
2562 * * Or, SDP()_EPF()_R()_OUT_ENABLE[ENB] is set.
2563 */
2564 union bdk_sdpx_epfx_rx_out_control
2565 {
2566 uint64_t u;
2567 struct bdk_sdpx_epfx_rx_out_control_s
2568 {
2569 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2570 uint64_t reserved_37_63 : 27;
2571 uint64_t idle : 1; /**< [ 36: 36](RO/H) Asserted when this ring has no packets in-flight. */
2572 uint64_t es_i : 2; /**< [ 35: 34](R/W) [ES_I] is ES\<1:0\> for info buffer write operations to buffer/info
2573 pair MAC memory space addresses fetched from packet output ring. ES\<1:0\> is the
2574 endian-swap attribute for these MAC memory space writes. */
2575 uint64_t nsr_i : 1; /**< [ 33: 33](R/W) [NSR] is ADDRTYPE\<1\> for info buffer write operations to buffer/info
2576 pair MAC memory space addresses fetched from packet output ring. ADDRTYPE\<1\> is
2577 the no-snoop attribute for PCIe. */
2578 uint64_t ror_i : 1; /**< [ 32: 32](R/W) [ROR] is ADDRTYPE\<0\> for info buffer write operations to buffer/info
2579 pair MAC memory space addresses fetched from packet output ring. ADDRTYPE\<0\> is
2580 the relaxed-order attribute for PCIe. */
2581 uint64_t es_d : 2; /**< [ 31: 30](R/W) [ES] is ES\<1:0\> for data buffer write operations to buffer/info
2582 pair MAC memory space addresses fetched from packet output ring. ES\<1:0\> is the
2583 endian-swap attribute for these MAC memory space writes. */
2584 uint64_t nsr_d : 1; /**< [ 29: 29](R/W) [NSR] is ADDRTYPE\<1\> for data buffer write operations to buffer/info
2585 pair MAC memory space addresses fetched from packet output ring. ADDRTYPE\<1\> is
2586 the no-snoop attribute for PCIe. */
2587 uint64_t ror_d : 1; /**< [ 28: 28](R/W) [ROR] is ADDRTYPE\<0\> for data buffer write operations to buffer/info
2588 pair MAC memory space addresses fetched from packet output ring. ADDRTYPE\<0\> is
2589 the relaxed-order attribute for PCIe. */
2590 uint64_t es_p : 2; /**< [ 27: 26](R/W) [ES_P] is ES\<1:0\> for the packet output ring reads that fetch buffer/info pointer pairs
2591 (from SLI_PKT()_SLIST_BADDR[ADDR]+). ES\<1:0\> is the endian-swap attribute for these
2592 MAC memory space reads. */
2593 uint64_t nsr_p : 1; /**< [ 25: 25](R/W) [NSR_P] is ADDRTYPE\<1\> for the packet output ring reads that fetch buffer/info pointer
2594 pairs (from SLI_PKT()_SLIST_BADDR[ADDR]+). ADDRTYPE\<1\> is the no-snoop attribute for PCIe. */
2595 uint64_t ror_p : 1; /**< [ 24: 24](R/W) [ROR_P] is ADDRTYPE\<0\> for the packet output ring reads that fetch buffer/info pointer
2596 pairs (from SLI_PKT()_SLIST_BADDR[ADDR]+). ADDRTYPE\<0\> is the relaxed-order attribute
2597 for PCIe. */
2598 uint64_t imode : 1; /**< [ 23: 23](R/W) When IMODE=1, packet output ring is in info-pointer mode; otherwise the packet output ring
2599 is in buffer-pointer-only mode. */
2600 uint64_t isize : 7; /**< [ 22: 16](R/W/H) Info bytes size (bytes) for the output port. Legal sizes are 0 to 120. Not used
2601 in buffer-pointer-only mode. If a value is written that is between 120-127 then
2602 a value of 120 will be forced by hardware. */
2603 uint64_t bsize : 16; /**< [ 15: 0](R/W/H) Buffer size (bytes) for the output ring. The minimum size is 128 bytes; if a value
2604 smaller than 128 is written, hardware will force a value of 128. */
2605 #else /* Word 0 - Little Endian */
2606 uint64_t bsize : 16; /**< [ 15: 0](R/W/H) Buffer size (bytes) for the output ring. The minimum size is 128 bytes; if a value
2607 smaller than 128 is written, hardware will force a value of 128. */
2608 uint64_t isize : 7; /**< [ 22: 16](R/W/H) Info bytes size (bytes) for the output port. Legal sizes are 0 to 120. Not used
2609 in buffer-pointer-only mode. If a value is written that is between 120-127 then
2610 a value of 120 will be forced by hardware. */
2611 uint64_t imode : 1; /**< [ 23: 23](R/W) When IMODE=1, packet output ring is in info-pointer mode; otherwise the packet output ring
2612 is in buffer-pointer-only mode. */
2613 uint64_t ror_p : 1; /**< [ 24: 24](R/W) [ROR_P] is ADDRTYPE\<0\> for the packet output ring reads that fetch buffer/info pointer
2614 pairs (from SLI_PKT()_SLIST_BADDR[ADDR]+). ADDRTYPE\<0\> is the relaxed-order attribute
2615 for PCIe. */
2616 uint64_t nsr_p : 1; /**< [ 25: 25](R/W) [NSR_P] is ADDRTYPE\<1\> for the packet output ring reads that fetch buffer/info pointer
2617 pairs (from SLI_PKT()_SLIST_BADDR[ADDR]+). ADDRTYPE\<1\> is the no-snoop attribute for PCIe. */
2618 uint64_t es_p : 2; /**< [ 27: 26](R/W) [ES_P] is ES\<1:0\> for the packet output ring reads that fetch buffer/info pointer pairs
2619 (from SLI_PKT()_SLIST_BADDR[ADDR]+). ES\<1:0\> is the endian-swap attribute for these
2620 MAC memory space reads. */
2621 uint64_t ror_d : 1; /**< [ 28: 28](R/W) [ROR] is ADDRTYPE\<0\> for data buffer write operations to buffer/info
2622 pair MAC memory space addresses fetched from packet output ring. ADDRTYPE\<0\> is
2623 the relaxed-order attribute for PCIe. */
2624 uint64_t nsr_d : 1; /**< [ 29: 29](R/W) [NSR] is ADDRTYPE\<1\> for data buffer write operations to buffer/info
2625 pair MAC memory space addresses fetched from packet output ring. ADDRTYPE\<1\> is
2626 the no-snoop attribute for PCIe. */
2627 uint64_t es_d : 2; /**< [ 31: 30](R/W) [ES] is ES\<1:0\> for data buffer write operations to buffer/info
2628 pair MAC memory space addresses fetched from packet output ring. ES\<1:0\> is the
2629 endian-swap attribute for these MAC memory space writes. */
2630 uint64_t ror_i : 1; /**< [ 32: 32](R/W) [ROR] is ADDRTYPE\<0\> for info buffer write operations to buffer/info
2631 pair MAC memory space addresses fetched from packet output ring. ADDRTYPE\<0\> is
2632 the relaxed-order attribute for PCIe. */
2633 uint64_t nsr_i : 1; /**< [ 33: 33](R/W) [NSR] is ADDRTYPE\<1\> for info buffer write operations to buffer/info
2634 pair MAC memory space addresses fetched from packet output ring. ADDRTYPE\<1\> is
2635 the no-snoop attribute for PCIe. */
2636 uint64_t es_i : 2; /**< [ 35: 34](R/W) [ES_I] is ES\<1:0\> for info buffer write operations to buffer/info
2637 pair MAC memory space addresses fetched from packet output ring. ES\<1:0\> is the
2638 endian-swap attribute for these MAC memory space writes. */
2639 uint64_t idle : 1; /**< [ 36: 36](RO/H) Asserted when this ring has no packets in-flight. */
2640 uint64_t reserved_37_63 : 27;
2641 #endif /* Word 0 - End */
2642 } s;
2643 /* struct bdk_sdpx_epfx_rx_out_control_s cn; */
2644 };
2645 typedef union bdk_sdpx_epfx_rx_out_control bdk_sdpx_epfx_rx_out_control_t;
2646
2647 static inline uint64_t BDK_SDPX_EPFX_RX_OUT_CONTROL(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_RX_OUT_CONTROL(unsigned long a,unsigned long b,unsigned long c)2648 static inline uint64_t BDK_SDPX_EPFX_RX_OUT_CONTROL(unsigned long a, unsigned long b, unsigned long c)
2649 {
2650 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1) && (c<=63)))
2651 return 0x874080010150ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1) + 0x20000ll * ((c) & 0x3f);
2652 __bdk_csr_fatal("SDPX_EPFX_RX_OUT_CONTROL", 3, a, b, c, 0);
2653 }
2654
2655 #define typedef_BDK_SDPX_EPFX_RX_OUT_CONTROL(a,b,c) bdk_sdpx_epfx_rx_out_control_t
2656 #define bustype_BDK_SDPX_EPFX_RX_OUT_CONTROL(a,b,c) BDK_CSR_TYPE_PEXP_NCB
2657 #define basename_BDK_SDPX_EPFX_RX_OUT_CONTROL(a,b,c) "SDPX_EPFX_RX_OUT_CONTROL"
2658 #define device_bar_BDK_SDPX_EPFX_RX_OUT_CONTROL(a,b,c) 0x0 /* PF_BAR0 */
2659 #define busnum_BDK_SDPX_EPFX_RX_OUT_CONTROL(a,b,c) (a)
2660 #define arguments_BDK_SDPX_EPFX_RX_OUT_CONTROL(a,b,c) (a),(b),(c),-1
2661
2662 /**
2663 * Register (PEXP_NCB) sdp#_epf#_r#_out_enable
2664 *
2665 * SDP Packet Output Enable Register
2666 * This register is the enable for the output pointer rings.
2667 */
2668 union bdk_sdpx_epfx_rx_out_enable
2669 {
2670 uint64_t u;
2671 struct bdk_sdpx_epfx_rx_out_enable_s
2672 {
2673 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2674 uint64_t reserved_1_63 : 63;
2675 uint64_t enb : 1; /**< [ 0: 0](R/W/H) Enable for the output ring i. This bit can be cleared by hardware if certain
2676 errors occur or an FLR is indicated by the remote host. It can be cleared by
2677 software at any time. It cannot be set unless SDP()_EPF()_R()_OUT_CONTROL[IDLE] == 0. */
2678 #else /* Word 0 - Little Endian */
2679 uint64_t enb : 1; /**< [ 0: 0](R/W/H) Enable for the output ring i. This bit can be cleared by hardware if certain
2680 errors occur or an FLR is indicated by the remote host. It can be cleared by
2681 software at any time. It cannot be set unless SDP()_EPF()_R()_OUT_CONTROL[IDLE] == 0. */
2682 uint64_t reserved_1_63 : 63;
2683 #endif /* Word 0 - End */
2684 } s;
2685 /* struct bdk_sdpx_epfx_rx_out_enable_s cn; */
2686 };
2687 typedef union bdk_sdpx_epfx_rx_out_enable bdk_sdpx_epfx_rx_out_enable_t;
2688
2689 static inline uint64_t BDK_SDPX_EPFX_RX_OUT_ENABLE(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_RX_OUT_ENABLE(unsigned long a,unsigned long b,unsigned long c)2690 static inline uint64_t BDK_SDPX_EPFX_RX_OUT_ENABLE(unsigned long a, unsigned long b, unsigned long c)
2691 {
2692 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1) && (c<=63)))
2693 return 0x874080010160ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1) + 0x20000ll * ((c) & 0x3f);
2694 __bdk_csr_fatal("SDPX_EPFX_RX_OUT_ENABLE", 3, a, b, c, 0);
2695 }
2696
2697 #define typedef_BDK_SDPX_EPFX_RX_OUT_ENABLE(a,b,c) bdk_sdpx_epfx_rx_out_enable_t
2698 #define bustype_BDK_SDPX_EPFX_RX_OUT_ENABLE(a,b,c) BDK_CSR_TYPE_PEXP_NCB
2699 #define basename_BDK_SDPX_EPFX_RX_OUT_ENABLE(a,b,c) "SDPX_EPFX_RX_OUT_ENABLE"
2700 #define device_bar_BDK_SDPX_EPFX_RX_OUT_ENABLE(a,b,c) 0x0 /* PF_BAR0 */
2701 #define busnum_BDK_SDPX_EPFX_RX_OUT_ENABLE(a,b,c) (a)
2702 #define arguments_BDK_SDPX_EPFX_RX_OUT_ENABLE(a,b,c) (a),(b),(c),-1
2703
2704 /**
2705 * Register (PEXP_NCB) sdp#_epf#_r#_out_int_levels
2706 *
2707 * SDP Packet Output Interrupt Levels Register
2708 * This register contains SDP output packet interrupt levels.
2709 * This register is not affected by reset (including FLR) and must be initialized
2710 * by the VF prior to enabling the ring.
2711 */
2712 union bdk_sdpx_epfx_rx_out_int_levels
2713 {
2714 uint64_t u;
2715 struct bdk_sdpx_epfx_rx_out_int_levels_s
2716 {
2717 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2718 uint64_t bmode : 1; /**< [ 63: 63](R/W) Determines whether SDP()_EPF()_R()_OUT_CNTS[CNT] is a byte or packet counter. When
2719 [BMODE]=1,
2720 SDP()_EPF()_R()_OUT_CNTS[CNT] is a byte counter, else SDP()_EPF()_R()_OUT_CNTS[CNT] is a
2721 packet
2722 counter. */
2723 uint64_t reserved_54_62 : 9;
2724 uint64_t timet : 22; /**< [ 53: 32](R/W) Output port counter time interrupt threshold. An MSI-X interrupt will be generated
2725 whenever SDP()_EPF()_R()_OUT_CNTS[TIMER] \> [TIMET]. Whenever software changes the value of
2726 [TIMET], it should also subsequently write the corresponding SDP()_EPF()_R()_OUT_CNTS CSR
2727 (with
2728 a value of zero if desired) to ensure that the hardware correspondingly updates
2729 SDP()_EPF()_R()_OUT_CNTS[OUT_INT]. */
2730 uint64_t cnt : 32; /**< [ 31: 0](R/W) Output port counter interrupt threshold. An MSI-X interrupt will be generated
2731 whenever SDP()_EPF()_R()_OUT_CNTS[CNT] \> [CNT]. Whenever software changes the value of
2732 [CNT], it should also subsequently write the corresponding SDP()_EPF()_R()_OUT_CNTS CSR
2733 (with a
2734 value of zero if desired) to ensure that the hardware correspondingly updates
2735 SDP()_EPF()_R()_OUT_CNTS[OUT_INT]. */
2736 #else /* Word 0 - Little Endian */
2737 uint64_t cnt : 32; /**< [ 31: 0](R/W) Output port counter interrupt threshold. An MSI-X interrupt will be generated
2738 whenever SDP()_EPF()_R()_OUT_CNTS[CNT] \> [CNT]. Whenever software changes the value of
2739 [CNT], it should also subsequently write the corresponding SDP()_EPF()_R()_OUT_CNTS CSR
2740 (with a
2741 value of zero if desired) to ensure that the hardware correspondingly updates
2742 SDP()_EPF()_R()_OUT_CNTS[OUT_INT]. */
2743 uint64_t timet : 22; /**< [ 53: 32](R/W) Output port counter time interrupt threshold. An MSI-X interrupt will be generated
2744 whenever SDP()_EPF()_R()_OUT_CNTS[TIMER] \> [TIMET]. Whenever software changes the value of
2745 [TIMET], it should also subsequently write the corresponding SDP()_EPF()_R()_OUT_CNTS CSR
2746 (with
2747 a value of zero if desired) to ensure that the hardware correspondingly updates
2748 SDP()_EPF()_R()_OUT_CNTS[OUT_INT]. */
2749 uint64_t reserved_54_62 : 9;
2750 uint64_t bmode : 1; /**< [ 63: 63](R/W) Determines whether SDP()_EPF()_R()_OUT_CNTS[CNT] is a byte or packet counter. When
2751 [BMODE]=1,
2752 SDP()_EPF()_R()_OUT_CNTS[CNT] is a byte counter, else SDP()_EPF()_R()_OUT_CNTS[CNT] is a
2753 packet
2754 counter. */
2755 #endif /* Word 0 - End */
2756 } s;
2757 /* struct bdk_sdpx_epfx_rx_out_int_levels_s cn; */
2758 };
2759 typedef union bdk_sdpx_epfx_rx_out_int_levels bdk_sdpx_epfx_rx_out_int_levels_t;
2760
2761 static inline uint64_t BDK_SDPX_EPFX_RX_OUT_INT_LEVELS(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_RX_OUT_INT_LEVELS(unsigned long a,unsigned long b,unsigned long c)2762 static inline uint64_t BDK_SDPX_EPFX_RX_OUT_INT_LEVELS(unsigned long a, unsigned long b, unsigned long c)
2763 {
2764 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1) && (c<=63)))
2765 return 0x874080010110ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1) + 0x20000ll * ((c) & 0x3f);
2766 __bdk_csr_fatal("SDPX_EPFX_RX_OUT_INT_LEVELS", 3, a, b, c, 0);
2767 }
2768
2769 #define typedef_BDK_SDPX_EPFX_RX_OUT_INT_LEVELS(a,b,c) bdk_sdpx_epfx_rx_out_int_levels_t
2770 #define bustype_BDK_SDPX_EPFX_RX_OUT_INT_LEVELS(a,b,c) BDK_CSR_TYPE_PEXP_NCB
2771 #define basename_BDK_SDPX_EPFX_RX_OUT_INT_LEVELS(a,b,c) "SDPX_EPFX_RX_OUT_INT_LEVELS"
2772 #define device_bar_BDK_SDPX_EPFX_RX_OUT_INT_LEVELS(a,b,c) 0x0 /* PF_BAR0 */
2773 #define busnum_BDK_SDPX_EPFX_RX_OUT_INT_LEVELS(a,b,c) (a)
2774 #define arguments_BDK_SDPX_EPFX_RX_OUT_INT_LEVELS(a,b,c) (a),(b),(c),-1
2775
2776 /**
2777 * Register (PEXP_NCB) sdp#_epf#_r#_out_int_status
2778 *
2779 * SDP Output Packet Interrupt Status Register
2780 * This register contains interrupt status on a per-VF basis. All rings for a given VF
2781 * are located in a single register. Note that access to any ring offset within a given
2782 * VF will return the same value. When the PF reads any ring in this register it will
2783 * return the same value (64 bits each representing one ring.)
2784 */
2785 union bdk_sdpx_epfx_rx_out_int_status
2786 {
2787 uint64_t u;
2788 struct bdk_sdpx_epfx_rx_out_int_status_s
2789 {
2790 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2791 uint64_t intr : 64; /**< [ 63: 0](RO) Packet output interrupt bit for a given VFR's ports (0..i). [INTR]\<ring\> reads
2792 as one whenever for the respective ring R(ring):
2793
2794 * SDP()_EPF()_R()_OUT_CNTS[CNT] \> SDP()_EPF()_R()_OUT_INT_LEVELS[CNT].
2795
2796 * Or, SDP()_EPF()_R()_OUT_CNTS[TIMER] \> SDP()_EPF()_R()_OUT_INT_LEVELS[TIMET].
2797
2798 [INTR] can cause an MSI-X interrupt.
2799
2800 Internal:
2801 These interrupt bits are not cleared due to FLR becase the CNTS and
2802 LEVELS registers are not reset and we wish to make the interrupt state
2803 consistent with CNTS/LEVELS even after FLR. The CNTS register must be
2804 cleared by software as part of initialization after a reset (including FLR)
2805 which will cause the interrupt state to clear. */
2806 #else /* Word 0 - Little Endian */
2807 uint64_t intr : 64; /**< [ 63: 0](RO) Packet output interrupt bit for a given VFR's ports (0..i). [INTR]\<ring\> reads
2808 as one whenever for the respective ring R(ring):
2809
2810 * SDP()_EPF()_R()_OUT_CNTS[CNT] \> SDP()_EPF()_R()_OUT_INT_LEVELS[CNT].
2811
2812 * Or, SDP()_EPF()_R()_OUT_CNTS[TIMER] \> SDP()_EPF()_R()_OUT_INT_LEVELS[TIMET].
2813
2814 [INTR] can cause an MSI-X interrupt.
2815
2816 Internal:
2817 These interrupt bits are not cleared due to FLR becase the CNTS and
2818 LEVELS registers are not reset and we wish to make the interrupt state
2819 consistent with CNTS/LEVELS even after FLR. The CNTS register must be
2820 cleared by software as part of initialization after a reset (including FLR)
2821 which will cause the interrupt state to clear. */
2822 #endif /* Word 0 - End */
2823 } s;
2824 /* struct bdk_sdpx_epfx_rx_out_int_status_s cn; */
2825 };
2826 typedef union bdk_sdpx_epfx_rx_out_int_status bdk_sdpx_epfx_rx_out_int_status_t;
2827
2828 static inline uint64_t BDK_SDPX_EPFX_RX_OUT_INT_STATUS(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_RX_OUT_INT_STATUS(unsigned long a,unsigned long b,unsigned long c)2829 static inline uint64_t BDK_SDPX_EPFX_RX_OUT_INT_STATUS(unsigned long a, unsigned long b, unsigned long c)
2830 {
2831 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1) && (c<=63)))
2832 return 0x874080010170ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1) + 0x20000ll * ((c) & 0x3f);
2833 __bdk_csr_fatal("SDPX_EPFX_RX_OUT_INT_STATUS", 3, a, b, c, 0);
2834 }
2835
2836 #define typedef_BDK_SDPX_EPFX_RX_OUT_INT_STATUS(a,b,c) bdk_sdpx_epfx_rx_out_int_status_t
2837 #define bustype_BDK_SDPX_EPFX_RX_OUT_INT_STATUS(a,b,c) BDK_CSR_TYPE_PEXP_NCB
2838 #define basename_BDK_SDPX_EPFX_RX_OUT_INT_STATUS(a,b,c) "SDPX_EPFX_RX_OUT_INT_STATUS"
2839 #define device_bar_BDK_SDPX_EPFX_RX_OUT_INT_STATUS(a,b,c) 0x0 /* PF_BAR0 */
2840 #define busnum_BDK_SDPX_EPFX_RX_OUT_INT_STATUS(a,b,c) (a)
2841 #define arguments_BDK_SDPX_EPFX_RX_OUT_INT_STATUS(a,b,c) (a),(b),(c),-1
2842
2843 /**
2844 * Register (PEXP_NCB) sdp#_epf#_r#_out_pkt_cnt
2845 *
2846 * SDP Packet Output Packet Count Register
2847 * This register contains packet counts per ring that have been written to memory by SDP.
2848 * The counter will wrap when it reaches its maximum value. It should be cleared
2849 * before the ring is enabled for an accurate count.
2850 */
2851 union bdk_sdpx_epfx_rx_out_pkt_cnt
2852 {
2853 uint64_t u;
2854 struct bdk_sdpx_epfx_rx_out_pkt_cnt_s
2855 {
2856 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2857 uint64_t reserved_36_63 : 28;
2858 uint64_t cnt : 36; /**< [ 35: 0](R/W/H) Packet count, can be written by software to any value. If a value of 0xFFFFFFFFF is
2859 written to this field, it will cause this field as well as SDP()_EPF()_R()_OUT_BYTE_CNT to
2860 clear. */
2861 #else /* Word 0 - Little Endian */
2862 uint64_t cnt : 36; /**< [ 35: 0](R/W/H) Packet count, can be written by software to any value. If a value of 0xFFFFFFFFF is
2863 written to this field, it will cause this field as well as SDP()_EPF()_R()_OUT_BYTE_CNT to
2864 clear. */
2865 uint64_t reserved_36_63 : 28;
2866 #endif /* Word 0 - End */
2867 } s;
2868 /* struct bdk_sdpx_epfx_rx_out_pkt_cnt_s cn; */
2869 };
2870 typedef union bdk_sdpx_epfx_rx_out_pkt_cnt bdk_sdpx_epfx_rx_out_pkt_cnt_t;
2871
2872 static inline uint64_t BDK_SDPX_EPFX_RX_OUT_PKT_CNT(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_RX_OUT_PKT_CNT(unsigned long a,unsigned long b,unsigned long c)2873 static inline uint64_t BDK_SDPX_EPFX_RX_OUT_PKT_CNT(unsigned long a, unsigned long b, unsigned long c)
2874 {
2875 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1) && (c<=63)))
2876 return 0x874080010180ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1) + 0x20000ll * ((c) & 0x3f);
2877 __bdk_csr_fatal("SDPX_EPFX_RX_OUT_PKT_CNT", 3, a, b, c, 0);
2878 }
2879
2880 #define typedef_BDK_SDPX_EPFX_RX_OUT_PKT_CNT(a,b,c) bdk_sdpx_epfx_rx_out_pkt_cnt_t
2881 #define bustype_BDK_SDPX_EPFX_RX_OUT_PKT_CNT(a,b,c) BDK_CSR_TYPE_PEXP_NCB
2882 #define basename_BDK_SDPX_EPFX_RX_OUT_PKT_CNT(a,b,c) "SDPX_EPFX_RX_OUT_PKT_CNT"
2883 #define device_bar_BDK_SDPX_EPFX_RX_OUT_PKT_CNT(a,b,c) 0x0 /* PF_BAR0 */
2884 #define busnum_BDK_SDPX_EPFX_RX_OUT_PKT_CNT(a,b,c) (a)
2885 #define arguments_BDK_SDPX_EPFX_RX_OUT_PKT_CNT(a,b,c) (a),(b),(c),-1
2886
2887 /**
2888 * Register (PEXP_NCB) sdp#_epf#_r#_out_slist_baddr
2889 *
2890 * SDP Packet Ring Base Address Register
2891 * This register contains the base address for the output ring.
2892 * This register is not affected by reset (including FLR) and must be initialized
2893 * by the VF prior to enabling the ring. Also, this register cannot be written
2894 * while either of the following conditions is true:
2895 * * SDP()_EPF()_R()_OUT_CONTROL[IDLE] is clear.
2896 * * Or, SDP()_EPF()_R()_OUT_ENABLE[ENB] is set.
2897 */
2898 union bdk_sdpx_epfx_rx_out_slist_baddr
2899 {
2900 uint64_t u;
2901 struct bdk_sdpx_epfx_rx_out_slist_baddr_s
2902 {
2903 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2904 uint64_t addr : 60; /**< [ 63: 4](R/W) Base address for the output ring, which is an array with
2905 SDP()_EPF()_R()_OUT_SLIST_FIFO_RSIZE[RSIZE] entries, each entry being a
2906 SDP_BUF_INFO_PAIR_S.
2907
2908 SDP()_EPF()_R()_OUT_SLIST_BADDR contains a byte address that must be 16-byte
2909 aligned, so SDP()_EPF()_R()_OUT_SLIST_BADDR\<3:0\> must be zero. */
2910 uint64_t reserved_0_3 : 4;
2911 #else /* Word 0 - Little Endian */
2912 uint64_t reserved_0_3 : 4;
2913 uint64_t addr : 60; /**< [ 63: 4](R/W) Base address for the output ring, which is an array with
2914 SDP()_EPF()_R()_OUT_SLIST_FIFO_RSIZE[RSIZE] entries, each entry being a
2915 SDP_BUF_INFO_PAIR_S.
2916
2917 SDP()_EPF()_R()_OUT_SLIST_BADDR contains a byte address that must be 16-byte
2918 aligned, so SDP()_EPF()_R()_OUT_SLIST_BADDR\<3:0\> must be zero. */
2919 #endif /* Word 0 - End */
2920 } s;
2921 /* struct bdk_sdpx_epfx_rx_out_slist_baddr_s cn; */
2922 };
2923 typedef union bdk_sdpx_epfx_rx_out_slist_baddr bdk_sdpx_epfx_rx_out_slist_baddr_t;
2924
2925 static inline uint64_t BDK_SDPX_EPFX_RX_OUT_SLIST_BADDR(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_RX_OUT_SLIST_BADDR(unsigned long a,unsigned long b,unsigned long c)2926 static inline uint64_t BDK_SDPX_EPFX_RX_OUT_SLIST_BADDR(unsigned long a, unsigned long b, unsigned long c)
2927 {
2928 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1) && (c<=63)))
2929 return 0x874080010120ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1) + 0x20000ll * ((c) & 0x3f);
2930 __bdk_csr_fatal("SDPX_EPFX_RX_OUT_SLIST_BADDR", 3, a, b, c, 0);
2931 }
2932
2933 #define typedef_BDK_SDPX_EPFX_RX_OUT_SLIST_BADDR(a,b,c) bdk_sdpx_epfx_rx_out_slist_baddr_t
2934 #define bustype_BDK_SDPX_EPFX_RX_OUT_SLIST_BADDR(a,b,c) BDK_CSR_TYPE_PEXP_NCB
2935 #define basename_BDK_SDPX_EPFX_RX_OUT_SLIST_BADDR(a,b,c) "SDPX_EPFX_RX_OUT_SLIST_BADDR"
2936 #define device_bar_BDK_SDPX_EPFX_RX_OUT_SLIST_BADDR(a,b,c) 0x0 /* PF_BAR0 */
2937 #define busnum_BDK_SDPX_EPFX_RX_OUT_SLIST_BADDR(a,b,c) (a)
2938 #define arguments_BDK_SDPX_EPFX_RX_OUT_SLIST_BADDR(a,b,c) (a),(b),(c),-1
2939
2940 /**
2941 * Register (PEXP_NCB) sdp#_epf#_r#_out_slist_dbell
2942 *
2943 * SDP Packet Base-Address Offset and Doorbell Registers
2944 * This register contains the doorbell and base-address offset for the next read operation.
2945 * This register is not affected by reset (including FLR) and must be initialized
2946 * by the VF prior to enabling the ring.
2947 */
2948 union bdk_sdpx_epfx_rx_out_slist_dbell
2949 {
2950 uint64_t u;
2951 struct bdk_sdpx_epfx_rx_out_slist_dbell_s
2952 {
2953 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2954 uint64_t aoff : 32; /**< [ 63: 32](RO/H) Address offset. The offset from the SDP()_EPF()_R()_OUT_SLIST_BADDR where the next pointer
2955 is read.
2956 A write of 0xFFFFFFFF to [DBELL] clears [DBELL] and [AOFF]. */
2957 uint64_t dbell : 32; /**< [ 31: 0](R/W/H) Pointer pair list doorbell count. Write operations to this field increments the present
2958 value here. Read operations return the present value. The value of this field is
2959 decremented as read operations are issued for scatter pointers. A write of 0xFFFFFFFF
2960 to this field clears [DBELL] and [AOFF]. The value of this field is in number of
2961 SDP_BUF_INFO_PAIR_S's. This register should be cleared before enabling a ring. */
2962 #else /* Word 0 - Little Endian */
2963 uint64_t dbell : 32; /**< [ 31: 0](R/W/H) Pointer pair list doorbell count. Write operations to this field increments the present
2964 value here. Read operations return the present value. The value of this field is
2965 decremented as read operations are issued for scatter pointers. A write of 0xFFFFFFFF
2966 to this field clears [DBELL] and [AOFF]. The value of this field is in number of
2967 SDP_BUF_INFO_PAIR_S's. This register should be cleared before enabling a ring. */
2968 uint64_t aoff : 32; /**< [ 63: 32](RO/H) Address offset. The offset from the SDP()_EPF()_R()_OUT_SLIST_BADDR where the next pointer
2969 is read.
2970 A write of 0xFFFFFFFF to [DBELL] clears [DBELL] and [AOFF]. */
2971 #endif /* Word 0 - End */
2972 } s;
2973 /* struct bdk_sdpx_epfx_rx_out_slist_dbell_s cn; */
2974 };
2975 typedef union bdk_sdpx_epfx_rx_out_slist_dbell bdk_sdpx_epfx_rx_out_slist_dbell_t;
2976
2977 static inline uint64_t BDK_SDPX_EPFX_RX_OUT_SLIST_DBELL(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_RX_OUT_SLIST_DBELL(unsigned long a,unsigned long b,unsigned long c)2978 static inline uint64_t BDK_SDPX_EPFX_RX_OUT_SLIST_DBELL(unsigned long a, unsigned long b, unsigned long c)
2979 {
2980 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1) && (c<=63)))
2981 return 0x874080010140ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1) + 0x20000ll * ((c) & 0x3f);
2982 __bdk_csr_fatal("SDPX_EPFX_RX_OUT_SLIST_DBELL", 3, a, b, c, 0);
2983 }
2984
2985 #define typedef_BDK_SDPX_EPFX_RX_OUT_SLIST_DBELL(a,b,c) bdk_sdpx_epfx_rx_out_slist_dbell_t
2986 #define bustype_BDK_SDPX_EPFX_RX_OUT_SLIST_DBELL(a,b,c) BDK_CSR_TYPE_PEXP_NCB
2987 #define basename_BDK_SDPX_EPFX_RX_OUT_SLIST_DBELL(a,b,c) "SDPX_EPFX_RX_OUT_SLIST_DBELL"
2988 #define device_bar_BDK_SDPX_EPFX_RX_OUT_SLIST_DBELL(a,b,c) 0x0 /* PF_BAR0 */
2989 #define busnum_BDK_SDPX_EPFX_RX_OUT_SLIST_DBELL(a,b,c) (a)
2990 #define arguments_BDK_SDPX_EPFX_RX_OUT_SLIST_DBELL(a,b,c) (a),(b),(c),-1
2991
2992 /**
2993 * Register (PEXP_NCB) sdp#_epf#_r#_out_slist_rsize
2994 *
2995 * SDP Packet Ring Size Register
2996 * This register contains the output packet ring size.
2997 * This register is not affected by reset (including FLR) and must be initialized
2998 * by the VF prior to enabling the ring. Also, this register cannot be written
2999 * while either of the following conditions is true:
3000 * * SDP()_EPF()_R()_OUT_CONTROL[IDLE] is clear.
3001 * * Or, SDP()_EPF()_R()_OUT_ENABLE[ENB] is set.
3002 */
3003 union bdk_sdpx_epfx_rx_out_slist_rsize
3004 {
3005 uint64_t u;
3006 struct bdk_sdpx_epfx_rx_out_slist_rsize_s
3007 {
3008 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3009 uint64_t reserved_32_63 : 32;
3010 uint64_t rsize : 32; /**< [ 31: 0](R/W/H) Ring size (number of SDP_BUF_INFO_PAIR_S's). This value must be 16 or
3011 greater. If a value is written that is less than 16, then hardware
3012 will force a value of 16 to be written. */
3013 #else /* Word 0 - Little Endian */
3014 uint64_t rsize : 32; /**< [ 31: 0](R/W/H) Ring size (number of SDP_BUF_INFO_PAIR_S's). This value must be 16 or
3015 greater. If a value is written that is less than 16, then hardware
3016 will force a value of 16 to be written. */
3017 uint64_t reserved_32_63 : 32;
3018 #endif /* Word 0 - End */
3019 } s;
3020 /* struct bdk_sdpx_epfx_rx_out_slist_rsize_s cn; */
3021 };
3022 typedef union bdk_sdpx_epfx_rx_out_slist_rsize bdk_sdpx_epfx_rx_out_slist_rsize_t;
3023
3024 static inline uint64_t BDK_SDPX_EPFX_RX_OUT_SLIST_RSIZE(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_RX_OUT_SLIST_RSIZE(unsigned long a,unsigned long b,unsigned long c)3025 static inline uint64_t BDK_SDPX_EPFX_RX_OUT_SLIST_RSIZE(unsigned long a, unsigned long b, unsigned long c)
3026 {
3027 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1) && (c<=63)))
3028 return 0x874080010130ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1) + 0x20000ll * ((c) & 0x3f);
3029 __bdk_csr_fatal("SDPX_EPFX_RX_OUT_SLIST_RSIZE", 3, a, b, c, 0);
3030 }
3031
3032 #define typedef_BDK_SDPX_EPFX_RX_OUT_SLIST_RSIZE(a,b,c) bdk_sdpx_epfx_rx_out_slist_rsize_t
3033 #define bustype_BDK_SDPX_EPFX_RX_OUT_SLIST_RSIZE(a,b,c) BDK_CSR_TYPE_PEXP_NCB
3034 #define basename_BDK_SDPX_EPFX_RX_OUT_SLIST_RSIZE(a,b,c) "SDPX_EPFX_RX_OUT_SLIST_RSIZE"
3035 #define device_bar_BDK_SDPX_EPFX_RX_OUT_SLIST_RSIZE(a,b,c) 0x0 /* PF_BAR0 */
3036 #define busnum_BDK_SDPX_EPFX_RX_OUT_SLIST_RSIZE(a,b,c) (a)
3037 #define arguments_BDK_SDPX_EPFX_RX_OUT_SLIST_RSIZE(a,b,c) (a),(b),(c),-1
3038
3039 /**
3040 * Register (PEXP_NCB) sdp#_epf#_r#_vf_num
3041 *
3042 * SDP Ring Error Type Register
3043 * These registers provide the virtual function number for each ring (both input and
3044 * output). They must be programmed by the PF along with SDP()_EPF()_RINFO before
3045 * the given ring is enabled. They are not accessible by the VF.
3046 *
3047 * All 64 registers associated with an EPF will be reset due to a PF FLR or MAC Reset.
3048 * These registers are not affected by VF FLR.
3049 */
3050 union bdk_sdpx_epfx_rx_vf_num
3051 {
3052 uint64_t u;
3053 struct bdk_sdpx_epfx_rx_vf_num_s
3054 {
3055 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3056 uint64_t reserved_7_63 : 57;
3057 uint64_t vf_num : 7; /**< [ 6: 0](R/W) The function that the ring belongs to. If equal to 0, the ring belongs
3058 to the physical function. If nonzero, this field is the virtual function
3059 that the ring belongs to.
3060
3061 [VF_NUM] configuration must match SDP()_EPF()_RINFO configuration.
3062
3063 [VF_NUM] applies to the ring pair, which includes both this input
3064 ring and to the output ring of the same index. */
3065 #else /* Word 0 - Little Endian */
3066 uint64_t vf_num : 7; /**< [ 6: 0](R/W) The function that the ring belongs to. If equal to 0, the ring belongs
3067 to the physical function. If nonzero, this field is the virtual function
3068 that the ring belongs to.
3069
3070 [VF_NUM] configuration must match SDP()_EPF()_RINFO configuration.
3071
3072 [VF_NUM] applies to the ring pair, which includes both this input
3073 ring and to the output ring of the same index. */
3074 uint64_t reserved_7_63 : 57;
3075 #endif /* Word 0 - End */
3076 } s;
3077 /* struct bdk_sdpx_epfx_rx_vf_num_s cn; */
3078 };
3079 typedef union bdk_sdpx_epfx_rx_vf_num bdk_sdpx_epfx_rx_vf_num_t;
3080
3081 static inline uint64_t BDK_SDPX_EPFX_RX_VF_NUM(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_SDPX_EPFX_RX_VF_NUM(unsigned long a,unsigned long b,unsigned long c)3082 static inline uint64_t BDK_SDPX_EPFX_RX_VF_NUM(unsigned long a, unsigned long b, unsigned long c)
3083 {
3084 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1) && (c<=63)))
3085 return 0x874080010500ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1) + 0x20000ll * ((c) & 0x3f);
3086 __bdk_csr_fatal("SDPX_EPFX_RX_VF_NUM", 3, a, b, c, 0);
3087 }
3088
3089 #define typedef_BDK_SDPX_EPFX_RX_VF_NUM(a,b,c) bdk_sdpx_epfx_rx_vf_num_t
3090 #define bustype_BDK_SDPX_EPFX_RX_VF_NUM(a,b,c) BDK_CSR_TYPE_PEXP_NCB
3091 #define basename_BDK_SDPX_EPFX_RX_VF_NUM(a,b,c) "SDPX_EPFX_RX_VF_NUM"
3092 #define device_bar_BDK_SDPX_EPFX_RX_VF_NUM(a,b,c) 0x0 /* PF_BAR0 */
3093 #define busnum_BDK_SDPX_EPFX_RX_VF_NUM(a,b,c) (a)
3094 #define arguments_BDK_SDPX_EPFX_RX_VF_NUM(a,b,c) (a),(b),(c),-1
3095
3096 /**
3097 * Register (PEXP_NCB) sdp#_scratch#
3098 *
3099 * SDP Scratch Register
3100 * These registers are general purpose 64-bit scratch registers for software use.
3101 */
3102 union bdk_sdpx_scratchx
3103 {
3104 uint64_t u;
3105 struct bdk_sdpx_scratchx_s
3106 {
3107 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3108 uint64_t data : 64; /**< [ 63: 0](R/W) The value in this register is totally software defined. */
3109 #else /* Word 0 - Little Endian */
3110 uint64_t data : 64; /**< [ 63: 0](R/W) The value in this register is totally software defined. */
3111 #endif /* Word 0 - End */
3112 } s;
3113 /* struct bdk_sdpx_scratchx_s cn; */
3114 };
3115 typedef union bdk_sdpx_scratchx bdk_sdpx_scratchx_t;
3116
3117 static inline uint64_t BDK_SDPX_SCRATCHX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SDPX_SCRATCHX(unsigned long a,unsigned long b)3118 static inline uint64_t BDK_SDPX_SCRATCHX(unsigned long a, unsigned long b)
3119 {
3120 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=3)))
3121 return 0x874080020180ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x3);
3122 __bdk_csr_fatal("SDPX_SCRATCHX", 2, a, b, 0, 0);
3123 }
3124
3125 #define typedef_BDK_SDPX_SCRATCHX(a,b) bdk_sdpx_scratchx_t
3126 #define bustype_BDK_SDPX_SCRATCHX(a,b) BDK_CSR_TYPE_PEXP_NCB
3127 #define basename_BDK_SDPX_SCRATCHX(a,b) "SDPX_SCRATCHX"
3128 #define device_bar_BDK_SDPX_SCRATCHX(a,b) 0x0 /* PF_BAR0 */
3129 #define busnum_BDK_SDPX_SCRATCHX(a,b) (a)
3130 #define arguments_BDK_SDPX_SCRATCHX(a,b) (a),(b),-1,-1
3131
3132 /**
3133 * Register (NCB) sli#_bar3_addr
3134 *
3135 * SLI BAR3 Address Register
3136 * This register configures PEM BAR3 accesses.
3137 */
3138 union bdk_slix_bar3_addr
3139 {
3140 uint64_t u;
3141 struct bdk_slix_bar3_addr_s
3142 {
3143 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3144 uint64_t wvirt : 1; /**< [ 63: 63](R/W) Virtual:
3145 0 = [RD_ADDR] is a physical addresses.
3146 1 = [RD_ADDR] is a virtual address. */
3147 uint64_t reserved_49_62 : 14;
3148 uint64_t rd_addr : 30; /**< [ 48: 19](R/W) Base address for PEM BAR3 transactions that is appended to the 512KB offset.
3149 The reset value is the PEM base address of the EPROM,
3150 PEM()_EROM(). */
3151 uint64_t reserved_0_18 : 19;
3152 #else /* Word 0 - Little Endian */
3153 uint64_t reserved_0_18 : 19;
3154 uint64_t rd_addr : 30; /**< [ 48: 19](R/W) Base address for PEM BAR3 transactions that is appended to the 512KB offset.
3155 The reset value is the PEM base address of the EPROM,
3156 PEM()_EROM(). */
3157 uint64_t reserved_49_62 : 14;
3158 uint64_t wvirt : 1; /**< [ 63: 63](R/W) Virtual:
3159 0 = [RD_ADDR] is a physical addresses.
3160 1 = [RD_ADDR] is a virtual address. */
3161 #endif /* Word 0 - End */
3162 } s;
3163 /* struct bdk_slix_bar3_addr_s cn; */
3164 };
3165 typedef union bdk_slix_bar3_addr bdk_slix_bar3_addr_t;
3166
3167 static inline uint64_t BDK_SLIX_BAR3_ADDR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SLIX_BAR3_ADDR(unsigned long a)3168 static inline uint64_t BDK_SLIX_BAR3_ADDR(unsigned long a)
3169 {
3170 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a==0))
3171 return 0x874001002400ll + 0x1000000000ll * ((a) & 0x0);
3172 __bdk_csr_fatal("SLIX_BAR3_ADDR", 1, a, 0, 0, 0);
3173 }
3174
3175 #define typedef_BDK_SLIX_BAR3_ADDR(a) bdk_slix_bar3_addr_t
3176 #define bustype_BDK_SLIX_BAR3_ADDR(a) BDK_CSR_TYPE_NCB
3177 #define basename_BDK_SLIX_BAR3_ADDR(a) "SLIX_BAR3_ADDR"
3178 #define device_bar_BDK_SLIX_BAR3_ADDR(a) 0x0 /* PF_BAR0 */
3179 #define busnum_BDK_SLIX_BAR3_ADDR(a) (a)
3180 #define arguments_BDK_SLIX_BAR3_ADDR(a) (a),-1,-1,-1
3181
3182 /**
3183 * Register (NCB) sli#_bist_status
3184 *
3185 * SLI BIST Status Register
3186 * This register contains results from BIST runs of MAC's memories: 0 = pass (or BIST in
3187 * progress/never run), 1 = fail.
3188 */
3189 union bdk_slix_bist_status
3190 {
3191 uint64_t u;
3192 struct bdk_slix_bist_status_s
3193 {
3194 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3195 uint64_t reserved_31_63 : 33;
3196 uint64_t status : 31; /**< [ 30: 0](RO) BIST status.
3197 Internal:
3198 22 = sli_nod_nfif_bstatus.
3199 21 = csr_region_mem_bstatus.
3200 20 = sncf0_ffifo_bstatus.
3201 19 = sndfh0_ffifo_bstatus.
3202 18 = sndfl0_ffifo_bstatus.
3203 17 = sncf1_ffifo_bstatus.
3204 16 = sndfh1_ffifo_bstatus.
3205 15 = sndfl1_ffifo_bstatus.
3206 14 = sncf2_ffifo_bstatus.
3207 13 = sndfh2_ffifo_bstatus.
3208 12 = sndfl2_ffifo_bstatus.
3209 11 = p2n_port0_tlp_cpl_fifo_bstatus.
3210 10 = p2n_port0_tlp_n_fifo_bstatus.
3211 9 = p2n_port0_tlp_p_fifo_bstatus.
3212 8 = p2n_port1_tlp_cpl_fifo_bstatus.
3213 7 = p2n_port1_tlp_n_fifo_bstatus.
3214 6 = p2n_port1_tlp_p_fifo_bstatus.
3215 5 = p2n_port2_tlp_cpl_fifo_bstatus.
3216 4 = p2n_port2_tlp_n_fifo_bstatus.
3217 3 = p2n_port2_tlp_p_fifo_bstatus.
3218 2 = cpl0_fifo_bstatus.
3219 1 = cpl1_fifo_bstatus.
3220 0 = cpl2_fifo_bstatus. */
3221 #else /* Word 0 - Little Endian */
3222 uint64_t status : 31; /**< [ 30: 0](RO) BIST status.
3223 Internal:
3224 22 = sli_nod_nfif_bstatus.
3225 21 = csr_region_mem_bstatus.
3226 20 = sncf0_ffifo_bstatus.
3227 19 = sndfh0_ffifo_bstatus.
3228 18 = sndfl0_ffifo_bstatus.
3229 17 = sncf1_ffifo_bstatus.
3230 16 = sndfh1_ffifo_bstatus.
3231 15 = sndfl1_ffifo_bstatus.
3232 14 = sncf2_ffifo_bstatus.
3233 13 = sndfh2_ffifo_bstatus.
3234 12 = sndfl2_ffifo_bstatus.
3235 11 = p2n_port0_tlp_cpl_fifo_bstatus.
3236 10 = p2n_port0_tlp_n_fifo_bstatus.
3237 9 = p2n_port0_tlp_p_fifo_bstatus.
3238 8 = p2n_port1_tlp_cpl_fifo_bstatus.
3239 7 = p2n_port1_tlp_n_fifo_bstatus.
3240 6 = p2n_port1_tlp_p_fifo_bstatus.
3241 5 = p2n_port2_tlp_cpl_fifo_bstatus.
3242 4 = p2n_port2_tlp_n_fifo_bstatus.
3243 3 = p2n_port2_tlp_p_fifo_bstatus.
3244 2 = cpl0_fifo_bstatus.
3245 1 = cpl1_fifo_bstatus.
3246 0 = cpl2_fifo_bstatus. */
3247 uint64_t reserved_31_63 : 33;
3248 #endif /* Word 0 - End */
3249 } s;
3250 struct bdk_slix_bist_status_cn81xx
3251 {
3252 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3253 uint64_t reserved_23_63 : 41;
3254 uint64_t status : 23; /**< [ 22: 0](RO) BIST status.
3255 Internal:
3256 22 = sli_nod_nfif_bstatus.
3257 21 = csr_region_mem_bstatus.
3258 20 = sncf0_ffifo_bstatus.
3259 19 = sndfh0_ffifo_bstatus.
3260 18 = sndfl0_ffifo_bstatus.
3261 17 = sncf1_ffifo_bstatus.
3262 16 = sndfh1_ffifo_bstatus.
3263 15 = sndfl1_ffifo_bstatus.
3264 14 = sncf2_ffifo_bstatus.
3265 13 = sndfh2_ffifo_bstatus.
3266 12 = sndfl2_ffifo_bstatus.
3267 11 = p2n_port0_tlp_cpl_fifo_bstatus.
3268 10 = p2n_port0_tlp_n_fifo_bstatus.
3269 9 = p2n_port0_tlp_p_fifo_bstatus.
3270 8 = p2n_port1_tlp_cpl_fifo_bstatus.
3271 7 = p2n_port1_tlp_n_fifo_bstatus.
3272 6 = p2n_port1_tlp_p_fifo_bstatus.
3273 5 = p2n_port2_tlp_cpl_fifo_bstatus.
3274 4 = p2n_port2_tlp_n_fifo_bstatus.
3275 3 = p2n_port2_tlp_p_fifo_bstatus.
3276 2 = cpl0_fifo_bstatus.
3277 1 = cpl1_fifo_bstatus.
3278 0 = cpl2_fifo_bstatus. */
3279 #else /* Word 0 - Little Endian */
3280 uint64_t status : 23; /**< [ 22: 0](RO) BIST status.
3281 Internal:
3282 22 = sli_nod_nfif_bstatus.
3283 21 = csr_region_mem_bstatus.
3284 20 = sncf0_ffifo_bstatus.
3285 19 = sndfh0_ffifo_bstatus.
3286 18 = sndfl0_ffifo_bstatus.
3287 17 = sncf1_ffifo_bstatus.
3288 16 = sndfh1_ffifo_bstatus.
3289 15 = sndfl1_ffifo_bstatus.
3290 14 = sncf2_ffifo_bstatus.
3291 13 = sndfh2_ffifo_bstatus.
3292 12 = sndfl2_ffifo_bstatus.
3293 11 = p2n_port0_tlp_cpl_fifo_bstatus.
3294 10 = p2n_port0_tlp_n_fifo_bstatus.
3295 9 = p2n_port0_tlp_p_fifo_bstatus.
3296 8 = p2n_port1_tlp_cpl_fifo_bstatus.
3297 7 = p2n_port1_tlp_n_fifo_bstatus.
3298 6 = p2n_port1_tlp_p_fifo_bstatus.
3299 5 = p2n_port2_tlp_cpl_fifo_bstatus.
3300 4 = p2n_port2_tlp_n_fifo_bstatus.
3301 3 = p2n_port2_tlp_p_fifo_bstatus.
3302 2 = cpl0_fifo_bstatus.
3303 1 = cpl1_fifo_bstatus.
3304 0 = cpl2_fifo_bstatus. */
3305 uint64_t reserved_23_63 : 41;
3306 #endif /* Word 0 - End */
3307 } cn81xx;
3308 /* struct bdk_slix_bist_status_cn81xx cn88xx; */
3309 struct bdk_slix_bist_status_cn83xx
3310 {
3311 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3312 uint64_t reserved_31_63 : 33;
3313 uint64_t status : 31; /**< [ 30: 0](RO/H) BIST status. One bit per memory, enumerated by SLI_RAMS_E. */
3314 #else /* Word 0 - Little Endian */
3315 uint64_t status : 31; /**< [ 30: 0](RO/H) BIST status. One bit per memory, enumerated by SLI_RAMS_E. */
3316 uint64_t reserved_31_63 : 33;
3317 #endif /* Word 0 - End */
3318 } cn83xx;
3319 };
3320 typedef union bdk_slix_bist_status bdk_slix_bist_status_t;
3321
3322 static inline uint64_t BDK_SLIX_BIST_STATUS(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SLIX_BIST_STATUS(unsigned long a)3323 static inline uint64_t BDK_SLIX_BIST_STATUS(unsigned long a)
3324 {
3325 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
3326 return 0x874001002180ll + 0x1000000000ll * ((a) & 0x0);
3327 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a==0))
3328 return 0x874001002180ll + 0x1000000000ll * ((a) & 0x0);
3329 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
3330 return 0x874001002180ll + 0x1000000000ll * ((a) & 0x1);
3331 __bdk_csr_fatal("SLIX_BIST_STATUS", 1, a, 0, 0, 0);
3332 }
3333
3334 #define typedef_BDK_SLIX_BIST_STATUS(a) bdk_slix_bist_status_t
3335 #define bustype_BDK_SLIX_BIST_STATUS(a) BDK_CSR_TYPE_NCB
3336 #define basename_BDK_SLIX_BIST_STATUS(a) "SLIX_BIST_STATUS"
3337 #define device_bar_BDK_SLIX_BIST_STATUS(a) 0x0 /* PF_BAR0 */
3338 #define busnum_BDK_SLIX_BIST_STATUS(a) (a)
3339 #define arguments_BDK_SLIX_BIST_STATUS(a) (a),-1,-1,-1
3340
3341 /**
3342 * Register (NCB) sli#_const
3343 *
3344 * SLI Constants Register
3345 * This register contains constants for software discovery.
3346 */
3347 union bdk_slix_const
3348 {
3349 uint64_t u;
3350 struct bdk_slix_const_s
3351 {
3352 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3353 uint64_t reserved_32_63 : 32;
3354 uint64_t pems : 32; /**< [ 31: 0](RO) Bit mask of which PEMs are connected to this SLI.
3355 If PEMs are fuse disabled they will still appear in this register.
3356
3357 E.g. for a single SLI connected to PEM0, PEM1 and PEM2 is 0x7. If PEM1 is fuse
3358 disabled, still is 0x7, because software needs to continue to know that PEM2
3359 remains MAC number 2 as far as the SLI registers, e.g. SLI()_S2M_MAC()_CTL, are
3360 concerned. */
3361 #else /* Word 0 - Little Endian */
3362 uint64_t pems : 32; /**< [ 31: 0](RO) Bit mask of which PEMs are connected to this SLI.
3363 If PEMs are fuse disabled they will still appear in this register.
3364
3365 E.g. for a single SLI connected to PEM0, PEM1 and PEM2 is 0x7. If PEM1 is fuse
3366 disabled, still is 0x7, because software needs to continue to know that PEM2
3367 remains MAC number 2 as far as the SLI registers, e.g. SLI()_S2M_MAC()_CTL, are
3368 concerned. */
3369 uint64_t reserved_32_63 : 32;
3370 #endif /* Word 0 - End */
3371 } s;
3372 /* struct bdk_slix_const_s cn; */
3373 };
3374 typedef union bdk_slix_const bdk_slix_const_t;
3375
3376 static inline uint64_t BDK_SLIX_CONST(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SLIX_CONST(unsigned long a)3377 static inline uint64_t BDK_SLIX_CONST(unsigned long a)
3378 {
3379 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
3380 return 0x874001002020ll + 0x1000000000ll * ((a) & 0x0);
3381 __bdk_csr_fatal("SLIX_CONST", 1, a, 0, 0, 0);
3382 }
3383
3384 #define typedef_BDK_SLIX_CONST(a) bdk_slix_const_t
3385 #define bustype_BDK_SLIX_CONST(a) BDK_CSR_TYPE_NCB
3386 #define basename_BDK_SLIX_CONST(a) "SLIX_CONST"
3387 #define device_bar_BDK_SLIX_CONST(a) 0x0 /* PF_BAR0 */
3388 #define busnum_BDK_SLIX_CONST(a) (a)
3389 #define arguments_BDK_SLIX_CONST(a) (a),-1,-1,-1
3390
3391 /**
3392 * Register (NCB) sli#_const1
3393 *
3394 * SLI Constants Register 1
3395 * This register contains constants for software discovery.
3396 */
3397 union bdk_slix_const1
3398 {
3399 uint64_t u;
3400 struct bdk_slix_const1_s
3401 {
3402 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3403 uint64_t reserved_0_63 : 64;
3404 #else /* Word 0 - Little Endian */
3405 uint64_t reserved_0_63 : 64;
3406 #endif /* Word 0 - End */
3407 } s;
3408 /* struct bdk_slix_const1_s cn; */
3409 };
3410 typedef union bdk_slix_const1 bdk_slix_const1_t;
3411
3412 static inline uint64_t BDK_SLIX_CONST1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SLIX_CONST1(unsigned long a)3413 static inline uint64_t BDK_SLIX_CONST1(unsigned long a)
3414 {
3415 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
3416 return 0x874001002030ll + 0x1000000000ll * ((a) & 0x0);
3417 __bdk_csr_fatal("SLIX_CONST1", 1, a, 0, 0, 0);
3418 }
3419
3420 #define typedef_BDK_SLIX_CONST1(a) bdk_slix_const1_t
3421 #define bustype_BDK_SLIX_CONST1(a) BDK_CSR_TYPE_NCB
3422 #define basename_BDK_SLIX_CONST1(a) "SLIX_CONST1"
3423 #define device_bar_BDK_SLIX_CONST1(a) 0x0 /* PF_BAR0 */
3424 #define busnum_BDK_SLIX_CONST1(a) (a)
3425 #define arguments_BDK_SLIX_CONST1(a) (a),-1,-1,-1
3426
3427 /**
3428 * Register (PEXP_NCB) sli#_data_out_cnt#
3429 *
3430 * SLI Data Out Count Register
3431 * This register contains the EXEC data out FIFO count and the data unload counter.
3432 */
3433 union bdk_slix_data_out_cntx
3434 {
3435 uint64_t u;
3436 struct bdk_slix_data_out_cntx_s
3437 {
3438 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3439 uint64_t reserved_24_63 : 40;
3440 uint64_t ucnt : 16; /**< [ 23: 8](RO/H) FIFO unload count. This counter is incremented by 1 every time a word is removed from
3441 data out FIFO, whose count is shown in [FCNT]. */
3442 uint64_t reserved_6_7 : 2;
3443 uint64_t fcnt : 6; /**< [ 5: 0](RO/H) FIFO data out count. Number of address data words presently buffered in the FIFO. */
3444 #else /* Word 0 - Little Endian */
3445 uint64_t fcnt : 6; /**< [ 5: 0](RO/H) FIFO data out count. Number of address data words presently buffered in the FIFO. */
3446 uint64_t reserved_6_7 : 2;
3447 uint64_t ucnt : 16; /**< [ 23: 8](RO/H) FIFO unload count. This counter is incremented by 1 every time a word is removed from
3448 data out FIFO, whose count is shown in [FCNT]. */
3449 uint64_t reserved_24_63 : 40;
3450 #endif /* Word 0 - End */
3451 } s;
3452 /* struct bdk_slix_data_out_cntx_s cn; */
3453 };
3454 typedef union bdk_slix_data_out_cntx bdk_slix_data_out_cntx_t;
3455
3456 static inline uint64_t BDK_SLIX_DATA_OUT_CNTX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_DATA_OUT_CNTX(unsigned long a,unsigned long b)3457 static inline uint64_t BDK_SLIX_DATA_OUT_CNTX(unsigned long a, unsigned long b)
3458 {
3459 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b<=2)))
3460 return 0x874000001080ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x3);
3461 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=2)))
3462 return 0x874000001080ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x3);
3463 __bdk_csr_fatal("SLIX_DATA_OUT_CNTX", 2, a, b, 0, 0);
3464 }
3465
3466 #define typedef_BDK_SLIX_DATA_OUT_CNTX(a,b) bdk_slix_data_out_cntx_t
3467 #define bustype_BDK_SLIX_DATA_OUT_CNTX(a,b) BDK_CSR_TYPE_PEXP_NCB
3468 #define basename_BDK_SLIX_DATA_OUT_CNTX(a,b) "SLIX_DATA_OUT_CNTX"
3469 #define device_bar_BDK_SLIX_DATA_OUT_CNTX(a,b) 0x0 /* PF_BAR0 */
3470 #define busnum_BDK_SLIX_DATA_OUT_CNTX(a,b) (a)
3471 #define arguments_BDK_SLIX_DATA_OUT_CNTX(a,b) (a),(b),-1,-1
3472
3473 /**
3474 * Register (NCB) sli#_eco
3475 *
3476 * INTERNAL: SLI ECO Register
3477 */
3478 union bdk_slix_eco
3479 {
3480 uint64_t u;
3481 struct bdk_slix_eco_s
3482 {
3483 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3484 uint64_t reserved_32_63 : 32;
3485 uint64_t eco_rw : 32; /**< [ 31: 0](R/W) Internal:
3486 Reserved for ECO usage. */
3487 #else /* Word 0 - Little Endian */
3488 uint64_t eco_rw : 32; /**< [ 31: 0](R/W) Internal:
3489 Reserved for ECO usage. */
3490 uint64_t reserved_32_63 : 32;
3491 #endif /* Word 0 - End */
3492 } s;
3493 /* struct bdk_slix_eco_s cn; */
3494 };
3495 typedef union bdk_slix_eco bdk_slix_eco_t;
3496
3497 static inline uint64_t BDK_SLIX_ECO(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SLIX_ECO(unsigned long a)3498 static inline uint64_t BDK_SLIX_ECO(unsigned long a)
3499 {
3500 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a==0))
3501 return 0x874001002800ll + 0x1000000000ll * ((a) & 0x0);
3502 __bdk_csr_fatal("SLIX_ECO", 1, a, 0, 0, 0);
3503 }
3504
3505 #define typedef_BDK_SLIX_ECO(a) bdk_slix_eco_t
3506 #define bustype_BDK_SLIX_ECO(a) BDK_CSR_TYPE_NCB
3507 #define basename_BDK_SLIX_ECO(a) "SLIX_ECO"
3508 #define device_bar_BDK_SLIX_ECO(a) 0x0 /* PF_BAR0 */
3509 #define busnum_BDK_SLIX_ECO(a) (a)
3510 #define arguments_BDK_SLIX_ECO(a) (a),-1,-1,-1
3511
3512 /**
3513 * Register (NCB) sli#_end_merge
3514 *
3515 * SLI End Merge Register
3516 * Writing this register will cause a merge to end.
3517 */
3518 union bdk_slix_end_merge
3519 {
3520 uint64_t u;
3521 struct bdk_slix_end_merge_s
3522 {
3523 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3524 uint64_t reserved_0_63 : 64;
3525 #else /* Word 0 - Little Endian */
3526 uint64_t reserved_0_63 : 64;
3527 #endif /* Word 0 - End */
3528 } s;
3529 /* struct bdk_slix_end_merge_s cn; */
3530 };
3531 typedef union bdk_slix_end_merge bdk_slix_end_merge_t;
3532
3533 static inline uint64_t BDK_SLIX_END_MERGE(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SLIX_END_MERGE(unsigned long a)3534 static inline uint64_t BDK_SLIX_END_MERGE(unsigned long a)
3535 {
3536 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
3537 return 0x874001002300ll + 0x1000000000ll * ((a) & 0x0);
3538 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a==0))
3539 return 0x874001002300ll + 0x1000000000ll * ((a) & 0x0);
3540 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
3541 return 0x874001002300ll + 0x1000000000ll * ((a) & 0x1);
3542 __bdk_csr_fatal("SLIX_END_MERGE", 1, a, 0, 0, 0);
3543 }
3544
3545 #define typedef_BDK_SLIX_END_MERGE(a) bdk_slix_end_merge_t
3546 #define bustype_BDK_SLIX_END_MERGE(a) BDK_CSR_TYPE_NCB
3547 #define basename_BDK_SLIX_END_MERGE(a) "SLIX_END_MERGE"
3548 #define device_bar_BDK_SLIX_END_MERGE(a) 0x0 /* PF_BAR0 */
3549 #define busnum_BDK_SLIX_END_MERGE(a) (a)
3550 #define arguments_BDK_SLIX_END_MERGE(a) (a),-1,-1,-1
3551
3552 /**
3553 * Register (PEXP_NCB) sli#_epf#_data_out_cnt
3554 *
3555 * SLI Data Out Count Register
3556 * This register contains the EXEC data out FIFO count and the data unload counter.
3557 */
3558 union bdk_slix_epfx_data_out_cnt
3559 {
3560 uint64_t u;
3561 struct bdk_slix_epfx_data_out_cnt_s
3562 {
3563 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3564 uint64_t reserved_24_63 : 40;
3565 uint64_t ucnt : 16; /**< [ 23: 8](RO/H) FIFO unload count. This counter is incremented by 1 every time a word is removed from
3566 data out FIFO, whose count is shown in [FCNT]. */
3567 uint64_t reserved_6_7 : 2;
3568 uint64_t fcnt : 6; /**< [ 5: 0](RO/H) FIFO data out count. Number of address data words presently buffered in the FIFO. */
3569 #else /* Word 0 - Little Endian */
3570 uint64_t fcnt : 6; /**< [ 5: 0](RO/H) FIFO data out count. Number of address data words presently buffered in the FIFO. */
3571 uint64_t reserved_6_7 : 2;
3572 uint64_t ucnt : 16; /**< [ 23: 8](RO/H) FIFO unload count. This counter is incremented by 1 every time a word is removed from
3573 data out FIFO, whose count is shown in [FCNT]. */
3574 uint64_t reserved_24_63 : 40;
3575 #endif /* Word 0 - End */
3576 } s;
3577 /* struct bdk_slix_epfx_data_out_cnt_s cn; */
3578 };
3579 typedef union bdk_slix_epfx_data_out_cnt bdk_slix_epfx_data_out_cnt_t;
3580
3581 static inline uint64_t BDK_SLIX_EPFX_DATA_OUT_CNT(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_EPFX_DATA_OUT_CNT(unsigned long a,unsigned long b)3582 static inline uint64_t BDK_SLIX_EPFX_DATA_OUT_CNT(unsigned long a, unsigned long b)
3583 {
3584 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=3)))
3585 return 0x874080028120ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x3);
3586 __bdk_csr_fatal("SLIX_EPFX_DATA_OUT_CNT", 2, a, b, 0, 0);
3587 }
3588
3589 #define typedef_BDK_SLIX_EPFX_DATA_OUT_CNT(a,b) bdk_slix_epfx_data_out_cnt_t
3590 #define bustype_BDK_SLIX_EPFX_DATA_OUT_CNT(a,b) BDK_CSR_TYPE_PEXP_NCB
3591 #define basename_BDK_SLIX_EPFX_DATA_OUT_CNT(a,b) "SLIX_EPFX_DATA_OUT_CNT"
3592 #define device_bar_BDK_SLIX_EPFX_DATA_OUT_CNT(a,b) 0x0 /* PF_BAR0 */
3593 #define busnum_BDK_SLIX_EPFX_DATA_OUT_CNT(a,b) (a)
3594 #define arguments_BDK_SLIX_EPFX_DATA_OUT_CNT(a,b) (a),(b),-1,-1
3595
3596 /**
3597 * Register (PEXP_NCB) sli#_epf#_dma_cnt#
3598 *
3599 * SLI DMA Count Registers
3600 * These registers contain the DMA count values.
3601 */
3602 union bdk_slix_epfx_dma_cntx
3603 {
3604 uint64_t u;
3605 struct bdk_slix_epfx_dma_cntx_s
3606 {
3607 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3608 uint64_t reserved_32_63 : 32;
3609 uint64_t cnt : 32; /**< [ 31: 0](R/W/H) The DMA counter. SLI/DPI hardware subtracts the written value from
3610 the counter whenever software writes this CSR. SLI/DPI hardware increments this
3611 counter after completing an OUTBOUND or EXTERNAL-ONLY DMA instruction
3612 with DPI_DMA_INSTR_HDR_S[CA] set DPI_DMA_INSTR_HDR_S[CSEL] equal to this
3613 CSR index. These increments may cause interrupts.
3614 See SLI_EPF()_DMA_INT_LEVEL() and SLI_EPF()_DMA_RINT[DCNT,DTIME]. */
3615 #else /* Word 0 - Little Endian */
3616 uint64_t cnt : 32; /**< [ 31: 0](R/W/H) The DMA counter. SLI/DPI hardware subtracts the written value from
3617 the counter whenever software writes this CSR. SLI/DPI hardware increments this
3618 counter after completing an OUTBOUND or EXTERNAL-ONLY DMA instruction
3619 with DPI_DMA_INSTR_HDR_S[CA] set DPI_DMA_INSTR_HDR_S[CSEL] equal to this
3620 CSR index. These increments may cause interrupts.
3621 See SLI_EPF()_DMA_INT_LEVEL() and SLI_EPF()_DMA_RINT[DCNT,DTIME]. */
3622 uint64_t reserved_32_63 : 32;
3623 #endif /* Word 0 - End */
3624 } s;
3625 /* struct bdk_slix_epfx_dma_cntx_s cn; */
3626 };
3627 typedef union bdk_slix_epfx_dma_cntx bdk_slix_epfx_dma_cntx_t;
3628
3629 static inline uint64_t BDK_SLIX_EPFX_DMA_CNTX(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_SLIX_EPFX_DMA_CNTX(unsigned long a,unsigned long b,unsigned long c)3630 static inline uint64_t BDK_SLIX_EPFX_DMA_CNTX(unsigned long a, unsigned long b, unsigned long c)
3631 {
3632 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=3) && (c<=1)))
3633 return 0x874080028680ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x3) + 0x10ll * ((c) & 0x1);
3634 __bdk_csr_fatal("SLIX_EPFX_DMA_CNTX", 3, a, b, c, 0);
3635 }
3636
3637 #define typedef_BDK_SLIX_EPFX_DMA_CNTX(a,b,c) bdk_slix_epfx_dma_cntx_t
3638 #define bustype_BDK_SLIX_EPFX_DMA_CNTX(a,b,c) BDK_CSR_TYPE_PEXP_NCB
3639 #define basename_BDK_SLIX_EPFX_DMA_CNTX(a,b,c) "SLIX_EPFX_DMA_CNTX"
3640 #define device_bar_BDK_SLIX_EPFX_DMA_CNTX(a,b,c) 0x0 /* PF_BAR0 */
3641 #define busnum_BDK_SLIX_EPFX_DMA_CNTX(a,b,c) (a)
3642 #define arguments_BDK_SLIX_EPFX_DMA_CNTX(a,b,c) (a),(b),(c),-1
3643
3644 /**
3645 * Register (PEXP_NCB) sli#_epf#_dma_int_level#
3646 *
3647 * SLI DMA Interrupt Level Registers
3648 * These registers contain the thresholds for DMA count and timer interrupts.
3649 */
3650 union bdk_slix_epfx_dma_int_levelx
3651 {
3652 uint64_t u;
3653 struct bdk_slix_epfx_dma_int_levelx_s
3654 {
3655 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3656 uint64_t tim : 32; /**< [ 63: 32](R/W) Whenever the SLI_EPF()_DMA_TIM()[TIM] timer exceeds this value,
3657 SLI_EPF()_DMA_RINT[DTIME\<x\>] is set. The SLI_EPF()_DMA_TIM()[TIM] timer
3658 increments every SLI clock whenever SLI_EPF()_DMA_CNT()[CNT] != 0, and is cleared
3659 when SLI_EPF()_DMA_CNT()[CNT] is written to a non zero value. */
3660 uint64_t cnt : 32; /**< [ 31: 0](R/W) Whenever SLI_EPF()_DMA_CNT()[CNT] exceeds this value, SLI_EPF()_DMA_RINT[DCNT\<x\>]
3661 is set. */
3662 #else /* Word 0 - Little Endian */
3663 uint64_t cnt : 32; /**< [ 31: 0](R/W) Whenever SLI_EPF()_DMA_CNT()[CNT] exceeds this value, SLI_EPF()_DMA_RINT[DCNT\<x\>]
3664 is set. */
3665 uint64_t tim : 32; /**< [ 63: 32](R/W) Whenever the SLI_EPF()_DMA_TIM()[TIM] timer exceeds this value,
3666 SLI_EPF()_DMA_RINT[DTIME\<x\>] is set. The SLI_EPF()_DMA_TIM()[TIM] timer
3667 increments every SLI clock whenever SLI_EPF()_DMA_CNT()[CNT] != 0, and is cleared
3668 when SLI_EPF()_DMA_CNT()[CNT] is written to a non zero value. */
3669 #endif /* Word 0 - End */
3670 } s;
3671 /* struct bdk_slix_epfx_dma_int_levelx_s cn; */
3672 };
3673 typedef union bdk_slix_epfx_dma_int_levelx bdk_slix_epfx_dma_int_levelx_t;
3674
3675 static inline uint64_t BDK_SLIX_EPFX_DMA_INT_LEVELX(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_SLIX_EPFX_DMA_INT_LEVELX(unsigned long a,unsigned long b,unsigned long c)3676 static inline uint64_t BDK_SLIX_EPFX_DMA_INT_LEVELX(unsigned long a, unsigned long b, unsigned long c)
3677 {
3678 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=3) && (c<=1)))
3679 return 0x874080028600ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x3) + 0x10ll * ((c) & 0x1);
3680 __bdk_csr_fatal("SLIX_EPFX_DMA_INT_LEVELX", 3, a, b, c, 0);
3681 }
3682
3683 #define typedef_BDK_SLIX_EPFX_DMA_INT_LEVELX(a,b,c) bdk_slix_epfx_dma_int_levelx_t
3684 #define bustype_BDK_SLIX_EPFX_DMA_INT_LEVELX(a,b,c) BDK_CSR_TYPE_PEXP_NCB
3685 #define basename_BDK_SLIX_EPFX_DMA_INT_LEVELX(a,b,c) "SLIX_EPFX_DMA_INT_LEVELX"
3686 #define device_bar_BDK_SLIX_EPFX_DMA_INT_LEVELX(a,b,c) 0x0 /* PF_BAR0 */
3687 #define busnum_BDK_SLIX_EPFX_DMA_INT_LEVELX(a,b,c) (a)
3688 #define arguments_BDK_SLIX_EPFX_DMA_INT_LEVELX(a,b,c) (a),(b),(c),-1
3689
3690 /**
3691 * Register (PEXP_NCB) sli#_epf#_dma_rint
3692 *
3693 * SLI/DPI DTIME/DCNT/DMAFI Interrupt Registers
3694 * These registers contain interrupts related to the DPI DMA engines.
3695 * The given register associated with an EPF will be reset due to a PF FLR or MAC reset.
3696 * These registers are not affected by VF FLR.
3697 */
3698 union bdk_slix_epfx_dma_rint
3699 {
3700 uint64_t u;
3701 struct bdk_slix_epfx_dma_rint_s
3702 {
3703 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3704 uint64_t reserved_6_63 : 58;
3705 uint64_t dtime : 2; /**< [ 5: 4](R/W1C/H) Whenever SLI_EPF()_DMA_CNT()[CNT] is not 0, the SLI_EPF()_DMA_TIM()[TIM]
3706 timer increments every SLI clock. [DTIME]\<x\> is set whenever
3707 SLI_EPF()_DMA_TIM()[TIM] \> SLI_EPF()_DMA_INT_LEVEL()[TIM].
3708 [DTIME]\<x\> is cleared when writing a non zero value to SLI_EPF()_DMA_CNT()[CNT]
3709 causing SLI_EPF()_DMA_TIM()[TIM] to clear to 0 and
3710 SLI_EPF()_DMA_TIM()[TIM] to fall below SLI_EPF()_DMA_INT_LEVEL()[TIM]. */
3711 uint64_t dcnt : 2; /**< [ 3: 2](R/W1C/H) [DCNT]\<x\> is set whenever SLI_EPF()_DMA_CNT()[CNT] \> SLI_EPF()_DMA_INT_LEVEL()[CNT].
3712 [DCNT]\<x\> is normally cleared by decreasing SLI_EPF()_DMA_CNT()[CNT]. */
3713 uint64_t dmafi : 2; /**< [ 1: 0](R/W1C/H) DMA set forced interrupts. Set by SLI/DPI after completing a DPI DMA
3714 Instruction with DPI_DMA_INSTR_HDR_S[FI] set. */
3715 #else /* Word 0 - Little Endian */
3716 uint64_t dmafi : 2; /**< [ 1: 0](R/W1C/H) DMA set forced interrupts. Set by SLI/DPI after completing a DPI DMA
3717 Instruction with DPI_DMA_INSTR_HDR_S[FI] set. */
3718 uint64_t dcnt : 2; /**< [ 3: 2](R/W1C/H) [DCNT]\<x\> is set whenever SLI_EPF()_DMA_CNT()[CNT] \> SLI_EPF()_DMA_INT_LEVEL()[CNT].
3719 [DCNT]\<x\> is normally cleared by decreasing SLI_EPF()_DMA_CNT()[CNT]. */
3720 uint64_t dtime : 2; /**< [ 5: 4](R/W1C/H) Whenever SLI_EPF()_DMA_CNT()[CNT] is not 0, the SLI_EPF()_DMA_TIM()[TIM]
3721 timer increments every SLI clock. [DTIME]\<x\> is set whenever
3722 SLI_EPF()_DMA_TIM()[TIM] \> SLI_EPF()_DMA_INT_LEVEL()[TIM].
3723 [DTIME]\<x\> is cleared when writing a non zero value to SLI_EPF()_DMA_CNT()[CNT]
3724 causing SLI_EPF()_DMA_TIM()[TIM] to clear to 0 and
3725 SLI_EPF()_DMA_TIM()[TIM] to fall below SLI_EPF()_DMA_INT_LEVEL()[TIM]. */
3726 uint64_t reserved_6_63 : 58;
3727 #endif /* Word 0 - End */
3728 } s;
3729 /* struct bdk_slix_epfx_dma_rint_s cn; */
3730 };
3731 typedef union bdk_slix_epfx_dma_rint bdk_slix_epfx_dma_rint_t;
3732
3733 static inline uint64_t BDK_SLIX_EPFX_DMA_RINT(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_EPFX_DMA_RINT(unsigned long a,unsigned long b)3734 static inline uint64_t BDK_SLIX_EPFX_DMA_RINT(unsigned long a, unsigned long b)
3735 {
3736 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=3)))
3737 return 0x874080028500ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x3);
3738 __bdk_csr_fatal("SLIX_EPFX_DMA_RINT", 2, a, b, 0, 0);
3739 }
3740
3741 #define typedef_BDK_SLIX_EPFX_DMA_RINT(a,b) bdk_slix_epfx_dma_rint_t
3742 #define bustype_BDK_SLIX_EPFX_DMA_RINT(a,b) BDK_CSR_TYPE_PEXP_NCB
3743 #define basename_BDK_SLIX_EPFX_DMA_RINT(a,b) "SLIX_EPFX_DMA_RINT"
3744 #define device_bar_BDK_SLIX_EPFX_DMA_RINT(a,b) 0x0 /* PF_BAR0 */
3745 #define busnum_BDK_SLIX_EPFX_DMA_RINT(a,b) (a)
3746 #define arguments_BDK_SLIX_EPFX_DMA_RINT(a,b) (a),(b),-1,-1
3747
3748 /**
3749 * Register (PEXP_NCB) sli#_epf#_dma_rint_ena_w1c
3750 *
3751 * SLI/DPI DTIME/DCNT/DMAFI Interrupt Remote Enable Clear Registers
3752 * This register clears interrupt enable bits.
3753 */
3754 union bdk_slix_epfx_dma_rint_ena_w1c
3755 {
3756 uint64_t u;
3757 struct bdk_slix_epfx_dma_rint_ena_w1c_s
3758 {
3759 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3760 uint64_t reserved_6_63 : 58;
3761 uint64_t dtime : 2; /**< [ 5: 4](R/W1C/H) Reads or clears enable for SLI(0)_EPF(0..3)_DMA_RINT[DTIME]. */
3762 uint64_t dcnt : 2; /**< [ 3: 2](R/W1C/H) Reads or clears enable for SLI(0)_EPF(0..3)_DMA_RINT[DCNT]. */
3763 uint64_t dmafi : 2; /**< [ 1: 0](R/W1C/H) Reads or clears enable for SLI(0)_EPF(0..3)_DMA_RINT[DMAFI]. */
3764 #else /* Word 0 - Little Endian */
3765 uint64_t dmafi : 2; /**< [ 1: 0](R/W1C/H) Reads or clears enable for SLI(0)_EPF(0..3)_DMA_RINT[DMAFI]. */
3766 uint64_t dcnt : 2; /**< [ 3: 2](R/W1C/H) Reads or clears enable for SLI(0)_EPF(0..3)_DMA_RINT[DCNT]. */
3767 uint64_t dtime : 2; /**< [ 5: 4](R/W1C/H) Reads or clears enable for SLI(0)_EPF(0..3)_DMA_RINT[DTIME]. */
3768 uint64_t reserved_6_63 : 58;
3769 #endif /* Word 0 - End */
3770 } s;
3771 /* struct bdk_slix_epfx_dma_rint_ena_w1c_s cn; */
3772 };
3773 typedef union bdk_slix_epfx_dma_rint_ena_w1c bdk_slix_epfx_dma_rint_ena_w1c_t;
3774
3775 static inline uint64_t BDK_SLIX_EPFX_DMA_RINT_ENA_W1C(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_EPFX_DMA_RINT_ENA_W1C(unsigned long a,unsigned long b)3776 static inline uint64_t BDK_SLIX_EPFX_DMA_RINT_ENA_W1C(unsigned long a, unsigned long b)
3777 {
3778 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=3)))
3779 return 0x874080028540ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x3);
3780 __bdk_csr_fatal("SLIX_EPFX_DMA_RINT_ENA_W1C", 2, a, b, 0, 0);
3781 }
3782
3783 #define typedef_BDK_SLIX_EPFX_DMA_RINT_ENA_W1C(a,b) bdk_slix_epfx_dma_rint_ena_w1c_t
3784 #define bustype_BDK_SLIX_EPFX_DMA_RINT_ENA_W1C(a,b) BDK_CSR_TYPE_PEXP_NCB
3785 #define basename_BDK_SLIX_EPFX_DMA_RINT_ENA_W1C(a,b) "SLIX_EPFX_DMA_RINT_ENA_W1C"
3786 #define device_bar_BDK_SLIX_EPFX_DMA_RINT_ENA_W1C(a,b) 0x0 /* PF_BAR0 */
3787 #define busnum_BDK_SLIX_EPFX_DMA_RINT_ENA_W1C(a,b) (a)
3788 #define arguments_BDK_SLIX_EPFX_DMA_RINT_ENA_W1C(a,b) (a),(b),-1,-1
3789
3790 /**
3791 * Register (PEXP_NCB) sli#_epf#_dma_rint_ena_w1s
3792 *
3793 * SLI/DPI DTIME/DCNT/DMAFI Interrupt Remote Enable Set Registers
3794 * This register sets interrupt enable bits.
3795 */
3796 union bdk_slix_epfx_dma_rint_ena_w1s
3797 {
3798 uint64_t u;
3799 struct bdk_slix_epfx_dma_rint_ena_w1s_s
3800 {
3801 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3802 uint64_t reserved_6_63 : 58;
3803 uint64_t dtime : 2; /**< [ 5: 4](R/W1S/H) Reads or sets enable for SLI(0)_EPF(0..3)_DMA_RINT[DTIME]. */
3804 uint64_t dcnt : 2; /**< [ 3: 2](R/W1S/H) Reads or sets enable for SLI(0)_EPF(0..3)_DMA_RINT[DCNT]. */
3805 uint64_t dmafi : 2; /**< [ 1: 0](R/W1S/H) Reads or sets enable for SLI(0)_EPF(0..3)_DMA_RINT[DMAFI]. */
3806 #else /* Word 0 - Little Endian */
3807 uint64_t dmafi : 2; /**< [ 1: 0](R/W1S/H) Reads or sets enable for SLI(0)_EPF(0..3)_DMA_RINT[DMAFI]. */
3808 uint64_t dcnt : 2; /**< [ 3: 2](R/W1S/H) Reads or sets enable for SLI(0)_EPF(0..3)_DMA_RINT[DCNT]. */
3809 uint64_t dtime : 2; /**< [ 5: 4](R/W1S/H) Reads or sets enable for SLI(0)_EPF(0..3)_DMA_RINT[DTIME]. */
3810 uint64_t reserved_6_63 : 58;
3811 #endif /* Word 0 - End */
3812 } s;
3813 /* struct bdk_slix_epfx_dma_rint_ena_w1s_s cn; */
3814 };
3815 typedef union bdk_slix_epfx_dma_rint_ena_w1s bdk_slix_epfx_dma_rint_ena_w1s_t;
3816
3817 static inline uint64_t BDK_SLIX_EPFX_DMA_RINT_ENA_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_EPFX_DMA_RINT_ENA_W1S(unsigned long a,unsigned long b)3818 static inline uint64_t BDK_SLIX_EPFX_DMA_RINT_ENA_W1S(unsigned long a, unsigned long b)
3819 {
3820 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=3)))
3821 return 0x874080028550ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x3);
3822 __bdk_csr_fatal("SLIX_EPFX_DMA_RINT_ENA_W1S", 2, a, b, 0, 0);
3823 }
3824
3825 #define typedef_BDK_SLIX_EPFX_DMA_RINT_ENA_W1S(a,b) bdk_slix_epfx_dma_rint_ena_w1s_t
3826 #define bustype_BDK_SLIX_EPFX_DMA_RINT_ENA_W1S(a,b) BDK_CSR_TYPE_PEXP_NCB
3827 #define basename_BDK_SLIX_EPFX_DMA_RINT_ENA_W1S(a,b) "SLIX_EPFX_DMA_RINT_ENA_W1S"
3828 #define device_bar_BDK_SLIX_EPFX_DMA_RINT_ENA_W1S(a,b) 0x0 /* PF_BAR0 */
3829 #define busnum_BDK_SLIX_EPFX_DMA_RINT_ENA_W1S(a,b) (a)
3830 #define arguments_BDK_SLIX_EPFX_DMA_RINT_ENA_W1S(a,b) (a),(b),-1,-1
3831
3832 /**
3833 * Register (PEXP_NCB) sli#_epf#_dma_rint_w1s
3834 *
3835 * SLI/DPI DTIME/DCNT/DMAFI Interrupt Set Registers
3836 * This register sets interrupt bits.
3837 */
3838 union bdk_slix_epfx_dma_rint_w1s
3839 {
3840 uint64_t u;
3841 struct bdk_slix_epfx_dma_rint_w1s_s
3842 {
3843 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3844 uint64_t reserved_6_63 : 58;
3845 uint64_t dtime : 2; /**< [ 5: 4](R/W1S/H) Reads or sets SLI(0)_EPF(0..3)_DMA_RINT[DTIME]. */
3846 uint64_t dcnt : 2; /**< [ 3: 2](R/W1S/H) Reads or sets SLI(0)_EPF(0..3)_DMA_RINT[DCNT]. */
3847 uint64_t dmafi : 2; /**< [ 1: 0](R/W1S/H) Reads or sets SLI(0)_EPF(0..3)_DMA_RINT[DMAFI]. */
3848 #else /* Word 0 - Little Endian */
3849 uint64_t dmafi : 2; /**< [ 1: 0](R/W1S/H) Reads or sets SLI(0)_EPF(0..3)_DMA_RINT[DMAFI]. */
3850 uint64_t dcnt : 2; /**< [ 3: 2](R/W1S/H) Reads or sets SLI(0)_EPF(0..3)_DMA_RINT[DCNT]. */
3851 uint64_t dtime : 2; /**< [ 5: 4](R/W1S/H) Reads or sets SLI(0)_EPF(0..3)_DMA_RINT[DTIME]. */
3852 uint64_t reserved_6_63 : 58;
3853 #endif /* Word 0 - End */
3854 } s;
3855 /* struct bdk_slix_epfx_dma_rint_w1s_s cn; */
3856 };
3857 typedef union bdk_slix_epfx_dma_rint_w1s bdk_slix_epfx_dma_rint_w1s_t;
3858
3859 static inline uint64_t BDK_SLIX_EPFX_DMA_RINT_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_EPFX_DMA_RINT_W1S(unsigned long a,unsigned long b)3860 static inline uint64_t BDK_SLIX_EPFX_DMA_RINT_W1S(unsigned long a, unsigned long b)
3861 {
3862 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=3)))
3863 return 0x874080028510ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x3);
3864 __bdk_csr_fatal("SLIX_EPFX_DMA_RINT_W1S", 2, a, b, 0, 0);
3865 }
3866
3867 #define typedef_BDK_SLIX_EPFX_DMA_RINT_W1S(a,b) bdk_slix_epfx_dma_rint_w1s_t
3868 #define bustype_BDK_SLIX_EPFX_DMA_RINT_W1S(a,b) BDK_CSR_TYPE_PEXP_NCB
3869 #define basename_BDK_SLIX_EPFX_DMA_RINT_W1S(a,b) "SLIX_EPFX_DMA_RINT_W1S"
3870 #define device_bar_BDK_SLIX_EPFX_DMA_RINT_W1S(a,b) 0x0 /* PF_BAR0 */
3871 #define busnum_BDK_SLIX_EPFX_DMA_RINT_W1S(a,b) (a)
3872 #define arguments_BDK_SLIX_EPFX_DMA_RINT_W1S(a,b) (a),(b),-1,-1
3873
3874 /**
3875 * Register (PEXP_NCB) sli#_epf#_dma_tim#
3876 *
3877 * SLI DMA Timer Registers
3878 * These registers contain the DMA timer values.
3879 */
3880 union bdk_slix_epfx_dma_timx
3881 {
3882 uint64_t u;
3883 struct bdk_slix_epfx_dma_timx_s
3884 {
3885 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3886 uint64_t reserved_32_63 : 32;
3887 uint64_t tim : 32; /**< [ 31: 0](RO/H) The DMA timer value. The timer increments when
3888 SLI_EPF()_DMA_CNT()[CNT]!=0 and clears when SLI_EPF()_DMA_RINT[DTIME\<x\>] is written with
3889 one. */
3890 #else /* Word 0 - Little Endian */
3891 uint64_t tim : 32; /**< [ 31: 0](RO/H) The DMA timer value. The timer increments when
3892 SLI_EPF()_DMA_CNT()[CNT]!=0 and clears when SLI_EPF()_DMA_RINT[DTIME\<x\>] is written with
3893 one. */
3894 uint64_t reserved_32_63 : 32;
3895 #endif /* Word 0 - End */
3896 } s;
3897 /* struct bdk_slix_epfx_dma_timx_s cn; */
3898 };
3899 typedef union bdk_slix_epfx_dma_timx bdk_slix_epfx_dma_timx_t;
3900
3901 static inline uint64_t BDK_SLIX_EPFX_DMA_TIMX(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_SLIX_EPFX_DMA_TIMX(unsigned long a,unsigned long b,unsigned long c)3902 static inline uint64_t BDK_SLIX_EPFX_DMA_TIMX(unsigned long a, unsigned long b, unsigned long c)
3903 {
3904 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=3) && (c<=1)))
3905 return 0x874080028700ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x3) + 0x10ll * ((c) & 0x1);
3906 __bdk_csr_fatal("SLIX_EPFX_DMA_TIMX", 3, a, b, c, 0);
3907 }
3908
3909 #define typedef_BDK_SLIX_EPFX_DMA_TIMX(a,b,c) bdk_slix_epfx_dma_timx_t
3910 #define bustype_BDK_SLIX_EPFX_DMA_TIMX(a,b,c) BDK_CSR_TYPE_PEXP_NCB
3911 #define basename_BDK_SLIX_EPFX_DMA_TIMX(a,b,c) "SLIX_EPFX_DMA_TIMX"
3912 #define device_bar_BDK_SLIX_EPFX_DMA_TIMX(a,b,c) 0x0 /* PF_BAR0 */
3913 #define busnum_BDK_SLIX_EPFX_DMA_TIMX(a,b,c) (a)
3914 #define arguments_BDK_SLIX_EPFX_DMA_TIMX(a,b,c) (a),(b),(c),-1
3915
3916 /**
3917 * Register (NCB) sli#_epf#_dma_vf_lint
3918 *
3919 * SLI DMA Error Response VF Bit Array Registers
3920 * When an error response is received for a VF PP transaction read, the appropriate VF indexed
3921 * bit is set. The appropriate PF should read the appropriate register.
3922 * These registers are only valid for PEM0 PF0 and PEM2 PF0.
3923 */
3924 union bdk_slix_epfx_dma_vf_lint
3925 {
3926 uint64_t u;
3927 struct bdk_slix_epfx_dma_vf_lint_s
3928 {
3929 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3930 uint64_t vf_int : 64; /**< [ 63: 0](R/W1C/H) When an error response is received for a VF DMA transaction read, the appropriate VF
3931 indexed bit is set. */
3932 #else /* Word 0 - Little Endian */
3933 uint64_t vf_int : 64; /**< [ 63: 0](R/W1C/H) When an error response is received for a VF DMA transaction read, the appropriate VF
3934 indexed bit is set. */
3935 #endif /* Word 0 - End */
3936 } s;
3937 /* struct bdk_slix_epfx_dma_vf_lint_s cn; */
3938 };
3939 typedef union bdk_slix_epfx_dma_vf_lint bdk_slix_epfx_dma_vf_lint_t;
3940
3941 static inline uint64_t BDK_SLIX_EPFX_DMA_VF_LINT(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_EPFX_DMA_VF_LINT(unsigned long a,unsigned long b)3942 static inline uint64_t BDK_SLIX_EPFX_DMA_VF_LINT(unsigned long a, unsigned long b)
3943 {
3944 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
3945 return 0x874000002000ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x1);
3946 __bdk_csr_fatal("SLIX_EPFX_DMA_VF_LINT", 2, a, b, 0, 0);
3947 }
3948
3949 #define typedef_BDK_SLIX_EPFX_DMA_VF_LINT(a,b) bdk_slix_epfx_dma_vf_lint_t
3950 #define bustype_BDK_SLIX_EPFX_DMA_VF_LINT(a,b) BDK_CSR_TYPE_NCB
3951 #define basename_BDK_SLIX_EPFX_DMA_VF_LINT(a,b) "SLIX_EPFX_DMA_VF_LINT"
3952 #define device_bar_BDK_SLIX_EPFX_DMA_VF_LINT(a,b) 0x0 /* PF_BAR0 */
3953 #define busnum_BDK_SLIX_EPFX_DMA_VF_LINT(a,b) (a)
3954 #define arguments_BDK_SLIX_EPFX_DMA_VF_LINT(a,b) (a),(b),-1,-1
3955
3956 /**
3957 * Register (NCB) sli#_epf#_dma_vf_lint_ena_w1c
3958 *
3959 * SLI DMA Error Response VF Bit Array Local Enable Clear Registers
3960 * This register clears interrupt enable bits.
3961 */
3962 union bdk_slix_epfx_dma_vf_lint_ena_w1c
3963 {
3964 uint64_t u;
3965 struct bdk_slix_epfx_dma_vf_lint_ena_w1c_s
3966 {
3967 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3968 uint64_t vf_int : 64; /**< [ 63: 0](R/W1C/H) Reads or clears enable for SLI(0)_EPF(0..1)_DMA_VF_LINT[VF_INT]. */
3969 #else /* Word 0 - Little Endian */
3970 uint64_t vf_int : 64; /**< [ 63: 0](R/W1C/H) Reads or clears enable for SLI(0)_EPF(0..1)_DMA_VF_LINT[VF_INT]. */
3971 #endif /* Word 0 - End */
3972 } s;
3973 /* struct bdk_slix_epfx_dma_vf_lint_ena_w1c_s cn; */
3974 };
3975 typedef union bdk_slix_epfx_dma_vf_lint_ena_w1c bdk_slix_epfx_dma_vf_lint_ena_w1c_t;
3976
3977 static inline uint64_t BDK_SLIX_EPFX_DMA_VF_LINT_ENA_W1C(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_EPFX_DMA_VF_LINT_ENA_W1C(unsigned long a,unsigned long b)3978 static inline uint64_t BDK_SLIX_EPFX_DMA_VF_LINT_ENA_W1C(unsigned long a, unsigned long b)
3979 {
3980 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
3981 return 0x874000002200ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x1);
3982 __bdk_csr_fatal("SLIX_EPFX_DMA_VF_LINT_ENA_W1C", 2, a, b, 0, 0);
3983 }
3984
3985 #define typedef_BDK_SLIX_EPFX_DMA_VF_LINT_ENA_W1C(a,b) bdk_slix_epfx_dma_vf_lint_ena_w1c_t
3986 #define bustype_BDK_SLIX_EPFX_DMA_VF_LINT_ENA_W1C(a,b) BDK_CSR_TYPE_NCB
3987 #define basename_BDK_SLIX_EPFX_DMA_VF_LINT_ENA_W1C(a,b) "SLIX_EPFX_DMA_VF_LINT_ENA_W1C"
3988 #define device_bar_BDK_SLIX_EPFX_DMA_VF_LINT_ENA_W1C(a,b) 0x0 /* PF_BAR0 */
3989 #define busnum_BDK_SLIX_EPFX_DMA_VF_LINT_ENA_W1C(a,b) (a)
3990 #define arguments_BDK_SLIX_EPFX_DMA_VF_LINT_ENA_W1C(a,b) (a),(b),-1,-1
3991
3992 /**
3993 * Register (NCB) sli#_epf#_dma_vf_lint_ena_w1s
3994 *
3995 * SLI DMA Error Response VF Bit Array Local Enable Set Registers
3996 * This register sets interrupt enable bits.
3997 */
3998 union bdk_slix_epfx_dma_vf_lint_ena_w1s
3999 {
4000 uint64_t u;
4001 struct bdk_slix_epfx_dma_vf_lint_ena_w1s_s
4002 {
4003 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4004 uint64_t vf_int : 64; /**< [ 63: 0](R/W1S/H) Reads or sets enable for SLI(0)_EPF(0..1)_DMA_VF_LINT[VF_INT]. */
4005 #else /* Word 0 - Little Endian */
4006 uint64_t vf_int : 64; /**< [ 63: 0](R/W1S/H) Reads or sets enable for SLI(0)_EPF(0..1)_DMA_VF_LINT[VF_INT]. */
4007 #endif /* Word 0 - End */
4008 } s;
4009 /* struct bdk_slix_epfx_dma_vf_lint_ena_w1s_s cn; */
4010 };
4011 typedef union bdk_slix_epfx_dma_vf_lint_ena_w1s bdk_slix_epfx_dma_vf_lint_ena_w1s_t;
4012
4013 static inline uint64_t BDK_SLIX_EPFX_DMA_VF_LINT_ENA_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_EPFX_DMA_VF_LINT_ENA_W1S(unsigned long a,unsigned long b)4014 static inline uint64_t BDK_SLIX_EPFX_DMA_VF_LINT_ENA_W1S(unsigned long a, unsigned long b)
4015 {
4016 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
4017 return 0x874000002300ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x1);
4018 __bdk_csr_fatal("SLIX_EPFX_DMA_VF_LINT_ENA_W1S", 2, a, b, 0, 0);
4019 }
4020
4021 #define typedef_BDK_SLIX_EPFX_DMA_VF_LINT_ENA_W1S(a,b) bdk_slix_epfx_dma_vf_lint_ena_w1s_t
4022 #define bustype_BDK_SLIX_EPFX_DMA_VF_LINT_ENA_W1S(a,b) BDK_CSR_TYPE_NCB
4023 #define basename_BDK_SLIX_EPFX_DMA_VF_LINT_ENA_W1S(a,b) "SLIX_EPFX_DMA_VF_LINT_ENA_W1S"
4024 #define device_bar_BDK_SLIX_EPFX_DMA_VF_LINT_ENA_W1S(a,b) 0x0 /* PF_BAR0 */
4025 #define busnum_BDK_SLIX_EPFX_DMA_VF_LINT_ENA_W1S(a,b) (a)
4026 #define arguments_BDK_SLIX_EPFX_DMA_VF_LINT_ENA_W1S(a,b) (a),(b),-1,-1
4027
4028 /**
4029 * Register (NCB) sli#_epf#_dma_vf_lint_w1s
4030 *
4031 * SLI DMA Error Response VF Bit Array Set Registers
4032 * This register sets interrupt bits.
4033 */
4034 union bdk_slix_epfx_dma_vf_lint_w1s
4035 {
4036 uint64_t u;
4037 struct bdk_slix_epfx_dma_vf_lint_w1s_s
4038 {
4039 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4040 uint64_t vf_int : 64; /**< [ 63: 0](R/W1S/H) Reads or sets SLI(0)_EPF(0..1)_DMA_VF_LINT[VF_INT]. */
4041 #else /* Word 0 - Little Endian */
4042 uint64_t vf_int : 64; /**< [ 63: 0](R/W1S/H) Reads or sets SLI(0)_EPF(0..1)_DMA_VF_LINT[VF_INT]. */
4043 #endif /* Word 0 - End */
4044 } s;
4045 /* struct bdk_slix_epfx_dma_vf_lint_w1s_s cn; */
4046 };
4047 typedef union bdk_slix_epfx_dma_vf_lint_w1s bdk_slix_epfx_dma_vf_lint_w1s_t;
4048
4049 static inline uint64_t BDK_SLIX_EPFX_DMA_VF_LINT_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_EPFX_DMA_VF_LINT_W1S(unsigned long a,unsigned long b)4050 static inline uint64_t BDK_SLIX_EPFX_DMA_VF_LINT_W1S(unsigned long a, unsigned long b)
4051 {
4052 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
4053 return 0x874000002100ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x1);
4054 __bdk_csr_fatal("SLIX_EPFX_DMA_VF_LINT_W1S", 2, a, b, 0, 0);
4055 }
4056
4057 #define typedef_BDK_SLIX_EPFX_DMA_VF_LINT_W1S(a,b) bdk_slix_epfx_dma_vf_lint_w1s_t
4058 #define bustype_BDK_SLIX_EPFX_DMA_VF_LINT_W1S(a,b) BDK_CSR_TYPE_NCB
4059 #define basename_BDK_SLIX_EPFX_DMA_VF_LINT_W1S(a,b) "SLIX_EPFX_DMA_VF_LINT_W1S"
4060 #define device_bar_BDK_SLIX_EPFX_DMA_VF_LINT_W1S(a,b) 0x0 /* PF_BAR0 */
4061 #define busnum_BDK_SLIX_EPFX_DMA_VF_LINT_W1S(a,b) (a)
4062 #define arguments_BDK_SLIX_EPFX_DMA_VF_LINT_W1S(a,b) (a),(b),-1,-1
4063
4064 /**
4065 * Register (PEXP_NCB) sli#_epf#_dma_vf_rint
4066 *
4067 * SLI DMA Error Response VF Bit Array Registers
4068 * When an error response is received for a VF PP transaction read, the appropriate VF indexed
4069 * bit is set. The appropriate PF should read the appropriate register.
4070 * The given register associated with an EPF will be reset due to a PF FLR or MAC reset.
4071 * These registers are not affected by VF FLR.
4072 * These registers are only valid for PEM0 PF0 and PEM2 PF0.
4073 */
4074 union bdk_slix_epfx_dma_vf_rint
4075 {
4076 uint64_t u;
4077 struct bdk_slix_epfx_dma_vf_rint_s
4078 {
4079 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4080 uint64_t vf_int : 64; /**< [ 63: 0](R/W1C/H) When an error response is received for a VF DMA transaction read, the appropriate VF
4081 indexed bit is set. */
4082 #else /* Word 0 - Little Endian */
4083 uint64_t vf_int : 64; /**< [ 63: 0](R/W1C/H) When an error response is received for a VF DMA transaction read, the appropriate VF
4084 indexed bit is set. */
4085 #endif /* Word 0 - End */
4086 } s;
4087 /* struct bdk_slix_epfx_dma_vf_rint_s cn; */
4088 };
4089 typedef union bdk_slix_epfx_dma_vf_rint bdk_slix_epfx_dma_vf_rint_t;
4090
4091 static inline uint64_t BDK_SLIX_EPFX_DMA_VF_RINT(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_EPFX_DMA_VF_RINT(unsigned long a,unsigned long b)4092 static inline uint64_t BDK_SLIX_EPFX_DMA_VF_RINT(unsigned long a, unsigned long b)
4093 {
4094 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
4095 return 0x874080028400ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1);
4096 __bdk_csr_fatal("SLIX_EPFX_DMA_VF_RINT", 2, a, b, 0, 0);
4097 }
4098
4099 #define typedef_BDK_SLIX_EPFX_DMA_VF_RINT(a,b) bdk_slix_epfx_dma_vf_rint_t
4100 #define bustype_BDK_SLIX_EPFX_DMA_VF_RINT(a,b) BDK_CSR_TYPE_PEXP_NCB
4101 #define basename_BDK_SLIX_EPFX_DMA_VF_RINT(a,b) "SLIX_EPFX_DMA_VF_RINT"
4102 #define device_bar_BDK_SLIX_EPFX_DMA_VF_RINT(a,b) 0x0 /* PF_BAR0 */
4103 #define busnum_BDK_SLIX_EPFX_DMA_VF_RINT(a,b) (a)
4104 #define arguments_BDK_SLIX_EPFX_DMA_VF_RINT(a,b) (a),(b),-1,-1
4105
4106 /**
4107 * Register (PEXP_NCB) sli#_epf#_dma_vf_rint_ena_w1c
4108 *
4109 * SLI DMA Error Response VF Bit Array Local Enable Clear Registers
4110 * This register clears interrupt enable bits.
4111 */
4112 union bdk_slix_epfx_dma_vf_rint_ena_w1c
4113 {
4114 uint64_t u;
4115 struct bdk_slix_epfx_dma_vf_rint_ena_w1c_s
4116 {
4117 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4118 uint64_t vf_int : 64; /**< [ 63: 0](R/W1C/H) Reads or clears enable for SLI(0)_EPF(0..1)_DMA_VF_RINT[VF_INT]. */
4119 #else /* Word 0 - Little Endian */
4120 uint64_t vf_int : 64; /**< [ 63: 0](R/W1C/H) Reads or clears enable for SLI(0)_EPF(0..1)_DMA_VF_RINT[VF_INT]. */
4121 #endif /* Word 0 - End */
4122 } s;
4123 /* struct bdk_slix_epfx_dma_vf_rint_ena_w1c_s cn; */
4124 };
4125 typedef union bdk_slix_epfx_dma_vf_rint_ena_w1c bdk_slix_epfx_dma_vf_rint_ena_w1c_t;
4126
4127 static inline uint64_t BDK_SLIX_EPFX_DMA_VF_RINT_ENA_W1C(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_EPFX_DMA_VF_RINT_ENA_W1C(unsigned long a,unsigned long b)4128 static inline uint64_t BDK_SLIX_EPFX_DMA_VF_RINT_ENA_W1C(unsigned long a, unsigned long b)
4129 {
4130 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
4131 return 0x874080028420ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1);
4132 __bdk_csr_fatal("SLIX_EPFX_DMA_VF_RINT_ENA_W1C", 2, a, b, 0, 0);
4133 }
4134
4135 #define typedef_BDK_SLIX_EPFX_DMA_VF_RINT_ENA_W1C(a,b) bdk_slix_epfx_dma_vf_rint_ena_w1c_t
4136 #define bustype_BDK_SLIX_EPFX_DMA_VF_RINT_ENA_W1C(a,b) BDK_CSR_TYPE_PEXP_NCB
4137 #define basename_BDK_SLIX_EPFX_DMA_VF_RINT_ENA_W1C(a,b) "SLIX_EPFX_DMA_VF_RINT_ENA_W1C"
4138 #define device_bar_BDK_SLIX_EPFX_DMA_VF_RINT_ENA_W1C(a,b) 0x0 /* PF_BAR0 */
4139 #define busnum_BDK_SLIX_EPFX_DMA_VF_RINT_ENA_W1C(a,b) (a)
4140 #define arguments_BDK_SLIX_EPFX_DMA_VF_RINT_ENA_W1C(a,b) (a),(b),-1,-1
4141
4142 /**
4143 * Register (PEXP_NCB) sli#_epf#_dma_vf_rint_ena_w1s
4144 *
4145 * SLI DMA Error Response VF Bit Array Local Enable Set Registers
4146 * This register sets interrupt enable bits.
4147 */
4148 union bdk_slix_epfx_dma_vf_rint_ena_w1s
4149 {
4150 uint64_t u;
4151 struct bdk_slix_epfx_dma_vf_rint_ena_w1s_s
4152 {
4153 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4154 uint64_t vf_int : 64; /**< [ 63: 0](R/W1S/H) Reads or sets enable for SLI(0)_EPF(0..1)_DMA_VF_RINT[VF_INT]. */
4155 #else /* Word 0 - Little Endian */
4156 uint64_t vf_int : 64; /**< [ 63: 0](R/W1S/H) Reads or sets enable for SLI(0)_EPF(0..1)_DMA_VF_RINT[VF_INT]. */
4157 #endif /* Word 0 - End */
4158 } s;
4159 /* struct bdk_slix_epfx_dma_vf_rint_ena_w1s_s cn; */
4160 };
4161 typedef union bdk_slix_epfx_dma_vf_rint_ena_w1s bdk_slix_epfx_dma_vf_rint_ena_w1s_t;
4162
4163 static inline uint64_t BDK_SLIX_EPFX_DMA_VF_RINT_ENA_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_EPFX_DMA_VF_RINT_ENA_W1S(unsigned long a,unsigned long b)4164 static inline uint64_t BDK_SLIX_EPFX_DMA_VF_RINT_ENA_W1S(unsigned long a, unsigned long b)
4165 {
4166 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
4167 return 0x874080028430ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1);
4168 __bdk_csr_fatal("SLIX_EPFX_DMA_VF_RINT_ENA_W1S", 2, a, b, 0, 0);
4169 }
4170
4171 #define typedef_BDK_SLIX_EPFX_DMA_VF_RINT_ENA_W1S(a,b) bdk_slix_epfx_dma_vf_rint_ena_w1s_t
4172 #define bustype_BDK_SLIX_EPFX_DMA_VF_RINT_ENA_W1S(a,b) BDK_CSR_TYPE_PEXP_NCB
4173 #define basename_BDK_SLIX_EPFX_DMA_VF_RINT_ENA_W1S(a,b) "SLIX_EPFX_DMA_VF_RINT_ENA_W1S"
4174 #define device_bar_BDK_SLIX_EPFX_DMA_VF_RINT_ENA_W1S(a,b) 0x0 /* PF_BAR0 */
4175 #define busnum_BDK_SLIX_EPFX_DMA_VF_RINT_ENA_W1S(a,b) (a)
4176 #define arguments_BDK_SLIX_EPFX_DMA_VF_RINT_ENA_W1S(a,b) (a),(b),-1,-1
4177
4178 /**
4179 * Register (PEXP_NCB) sli#_epf#_dma_vf_rint_w1s
4180 *
4181 * SLI DMA Error Response VF Bit Array Set Registers
4182 * This register sets interrupt bits.
4183 */
4184 union bdk_slix_epfx_dma_vf_rint_w1s
4185 {
4186 uint64_t u;
4187 struct bdk_slix_epfx_dma_vf_rint_w1s_s
4188 {
4189 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4190 uint64_t vf_int : 64; /**< [ 63: 0](R/W1S/H) Reads or sets SLI(0)_EPF(0..1)_DMA_VF_RINT[VF_INT]. */
4191 #else /* Word 0 - Little Endian */
4192 uint64_t vf_int : 64; /**< [ 63: 0](R/W1S/H) Reads or sets SLI(0)_EPF(0..1)_DMA_VF_RINT[VF_INT]. */
4193 #endif /* Word 0 - End */
4194 } s;
4195 /* struct bdk_slix_epfx_dma_vf_rint_w1s_s cn; */
4196 };
4197 typedef union bdk_slix_epfx_dma_vf_rint_w1s bdk_slix_epfx_dma_vf_rint_w1s_t;
4198
4199 static inline uint64_t BDK_SLIX_EPFX_DMA_VF_RINT_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_EPFX_DMA_VF_RINT_W1S(unsigned long a,unsigned long b)4200 static inline uint64_t BDK_SLIX_EPFX_DMA_VF_RINT_W1S(unsigned long a, unsigned long b)
4201 {
4202 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
4203 return 0x874080028410ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1);
4204 __bdk_csr_fatal("SLIX_EPFX_DMA_VF_RINT_W1S", 2, a, b, 0, 0);
4205 }
4206
4207 #define typedef_BDK_SLIX_EPFX_DMA_VF_RINT_W1S(a,b) bdk_slix_epfx_dma_vf_rint_w1s_t
4208 #define bustype_BDK_SLIX_EPFX_DMA_VF_RINT_W1S(a,b) BDK_CSR_TYPE_PEXP_NCB
4209 #define basename_BDK_SLIX_EPFX_DMA_VF_RINT_W1S(a,b) "SLIX_EPFX_DMA_VF_RINT_W1S"
4210 #define device_bar_BDK_SLIX_EPFX_DMA_VF_RINT_W1S(a,b) 0x0 /* PF_BAR0 */
4211 #define busnum_BDK_SLIX_EPFX_DMA_VF_RINT_W1S(a,b) (a)
4212 #define arguments_BDK_SLIX_EPFX_DMA_VF_RINT_W1S(a,b) (a),(b),-1,-1
4213
4214 /**
4215 * Register (NCB) sli#_epf#_misc_lint
4216 *
4217 * SLI MAC Interrupt Summary Register
4218 * This register contains the different interrupt-summary bits for one MAC in the SLI.
4219 * This set of interrupt registers are aliased to SLI(0)_MAC(0..3)_INT_SUM.
4220 * SLI(0)_EPF(0..3)_MISC_LINT_W1S aliases to SLI(0)_MAC(0..3)_INT_SUM_W1S.
4221 * SLI(0)_EPF(0..3)_MISC_LINT_ENA_W1C aliases to SLI(0)_MAC(0..3)_INT_ENA_W1C.
4222 * SLI(0)_EPF(0..3)_MISC_LINT_ENA_W1S aliases to SLI(0)_MAC(0..3)_INT_ENA_W1S.
4223 */
4224 union bdk_slix_epfx_misc_lint
4225 {
4226 uint64_t u;
4227 struct bdk_slix_epfx_misc_lint_s
4228 {
4229 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4230 uint64_t reserved_7_63 : 57;
4231 uint64_t flr : 1; /**< [ 6: 6](R/W1C/H) A FLR occurred for the PF on the corresponding MAC. */
4232 uint64_t dmapf_err : 1; /**< [ 5: 5](R/W1C/H) An error response was received for a PF DMA transaction read. */
4233 uint64_t pppf_err : 1; /**< [ 4: 4](R/W1C/H) Set when an error response is received for a PF PP transaction read. */
4234 uint64_t un_wi : 1; /**< [ 3: 3](R/W1C/H) Received unsupported N-TLP for window register from the corresponding MAC. This
4235 occurs when the window registers are disabled and a window register access occurs. */
4236 uint64_t un_b0 : 1; /**< [ 2: 2](R/W1C/H) Received unsupported N-TLP for Bar 0 from the corresponding MAC. This occurs
4237 when the BAR 0 address space is disabled. */
4238 uint64_t up_wi : 1; /**< [ 1: 1](R/W1C/H) Received unsupported P-TLP for window register from the corresponding MAC. This
4239 occurs when the window registers are disabled and a window register access
4240 occurs. */
4241 uint64_t up_b0 : 1; /**< [ 0: 0](R/W1C/H) Received unsupported P-TLP for Bar 0 from the corresponding MAC. This occurs
4242 when the BAR 0 address space is disabled. */
4243 #else /* Word 0 - Little Endian */
4244 uint64_t up_b0 : 1; /**< [ 0: 0](R/W1C/H) Received unsupported P-TLP for Bar 0 from the corresponding MAC. This occurs
4245 when the BAR 0 address space is disabled. */
4246 uint64_t up_wi : 1; /**< [ 1: 1](R/W1C/H) Received unsupported P-TLP for window register from the corresponding MAC. This
4247 occurs when the window registers are disabled and a window register access
4248 occurs. */
4249 uint64_t un_b0 : 1; /**< [ 2: 2](R/W1C/H) Received unsupported N-TLP for Bar 0 from the corresponding MAC. This occurs
4250 when the BAR 0 address space is disabled. */
4251 uint64_t un_wi : 1; /**< [ 3: 3](R/W1C/H) Received unsupported N-TLP for window register from the corresponding MAC. This
4252 occurs when the window registers are disabled and a window register access occurs. */
4253 uint64_t pppf_err : 1; /**< [ 4: 4](R/W1C/H) Set when an error response is received for a PF PP transaction read. */
4254 uint64_t dmapf_err : 1; /**< [ 5: 5](R/W1C/H) An error response was received for a PF DMA transaction read. */
4255 uint64_t flr : 1; /**< [ 6: 6](R/W1C/H) A FLR occurred for the PF on the corresponding MAC. */
4256 uint64_t reserved_7_63 : 57;
4257 #endif /* Word 0 - End */
4258 } s;
4259 /* struct bdk_slix_epfx_misc_lint_s cn; */
4260 };
4261 typedef union bdk_slix_epfx_misc_lint bdk_slix_epfx_misc_lint_t;
4262
4263 static inline uint64_t BDK_SLIX_EPFX_MISC_LINT(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_EPFX_MISC_LINT(unsigned long a,unsigned long b)4264 static inline uint64_t BDK_SLIX_EPFX_MISC_LINT(unsigned long a, unsigned long b)
4265 {
4266 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=3)))
4267 return 0x874000002400ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x3);
4268 __bdk_csr_fatal("SLIX_EPFX_MISC_LINT", 2, a, b, 0, 0);
4269 }
4270
4271 #define typedef_BDK_SLIX_EPFX_MISC_LINT(a,b) bdk_slix_epfx_misc_lint_t
4272 #define bustype_BDK_SLIX_EPFX_MISC_LINT(a,b) BDK_CSR_TYPE_NCB
4273 #define basename_BDK_SLIX_EPFX_MISC_LINT(a,b) "SLIX_EPFX_MISC_LINT"
4274 #define device_bar_BDK_SLIX_EPFX_MISC_LINT(a,b) 0x0 /* PF_BAR0 */
4275 #define busnum_BDK_SLIX_EPFX_MISC_LINT(a,b) (a)
4276 #define arguments_BDK_SLIX_EPFX_MISC_LINT(a,b) (a),(b),-1,-1
4277
4278 /**
4279 * Register (NCB) sli#_epf#_misc_lint_ena_w1c
4280 *
4281 * SLI MAC Interrupt Enable Clear Register
4282 * This register clears interrupt enable bits.
4283 */
4284 union bdk_slix_epfx_misc_lint_ena_w1c
4285 {
4286 uint64_t u;
4287 struct bdk_slix_epfx_misc_lint_ena_w1c_s
4288 {
4289 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4290 uint64_t reserved_7_63 : 57;
4291 uint64_t flr : 1; /**< [ 6: 6](R/W1C/H) Reads or clears enable for SLI(0)_EPF(0..3)_MISC_LINT[FLR]. */
4292 uint64_t dmapf_err : 1; /**< [ 5: 5](R/W1C/H) Reads or clears enable for SLI(0)_EPF(0..3)_MISC_LINT[DMAPF_ERR]. */
4293 uint64_t pppf_err : 1; /**< [ 4: 4](R/W1C/H) Reads or clears enable for SLI(0)_EPF(0..3)_MISC_LINT[PPPF_ERR]. */
4294 uint64_t un_wi : 1; /**< [ 3: 3](R/W1C/H) Reads or clears enable for SLI(0)_EPF(0..3)_MISC_LINT[UN_WI]. */
4295 uint64_t un_b0 : 1; /**< [ 2: 2](R/W1C/H) Reads or clears enable for SLI(0)_EPF(0..3)_MISC_LINT[UN_B0]. */
4296 uint64_t up_wi : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for SLI(0)_EPF(0..3)_MISC_LINT[UP_WI]. */
4297 uint64_t up_b0 : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for SLI(0)_EPF(0..3)_MISC_LINT[UP_B0]. */
4298 #else /* Word 0 - Little Endian */
4299 uint64_t up_b0 : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for SLI(0)_EPF(0..3)_MISC_LINT[UP_B0]. */
4300 uint64_t up_wi : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for SLI(0)_EPF(0..3)_MISC_LINT[UP_WI]. */
4301 uint64_t un_b0 : 1; /**< [ 2: 2](R/W1C/H) Reads or clears enable for SLI(0)_EPF(0..3)_MISC_LINT[UN_B0]. */
4302 uint64_t un_wi : 1; /**< [ 3: 3](R/W1C/H) Reads or clears enable for SLI(0)_EPF(0..3)_MISC_LINT[UN_WI]. */
4303 uint64_t pppf_err : 1; /**< [ 4: 4](R/W1C/H) Reads or clears enable for SLI(0)_EPF(0..3)_MISC_LINT[PPPF_ERR]. */
4304 uint64_t dmapf_err : 1; /**< [ 5: 5](R/W1C/H) Reads or clears enable for SLI(0)_EPF(0..3)_MISC_LINT[DMAPF_ERR]. */
4305 uint64_t flr : 1; /**< [ 6: 6](R/W1C/H) Reads or clears enable for SLI(0)_EPF(0..3)_MISC_LINT[FLR]. */
4306 uint64_t reserved_7_63 : 57;
4307 #endif /* Word 0 - End */
4308 } s;
4309 /* struct bdk_slix_epfx_misc_lint_ena_w1c_s cn; */
4310 };
4311 typedef union bdk_slix_epfx_misc_lint_ena_w1c bdk_slix_epfx_misc_lint_ena_w1c_t;
4312
4313 static inline uint64_t BDK_SLIX_EPFX_MISC_LINT_ENA_W1C(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_EPFX_MISC_LINT_ENA_W1C(unsigned long a,unsigned long b)4314 static inline uint64_t BDK_SLIX_EPFX_MISC_LINT_ENA_W1C(unsigned long a, unsigned long b)
4315 {
4316 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=3)))
4317 return 0x874000002600ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x3);
4318 __bdk_csr_fatal("SLIX_EPFX_MISC_LINT_ENA_W1C", 2, a, b, 0, 0);
4319 }
4320
4321 #define typedef_BDK_SLIX_EPFX_MISC_LINT_ENA_W1C(a,b) bdk_slix_epfx_misc_lint_ena_w1c_t
4322 #define bustype_BDK_SLIX_EPFX_MISC_LINT_ENA_W1C(a,b) BDK_CSR_TYPE_NCB
4323 #define basename_BDK_SLIX_EPFX_MISC_LINT_ENA_W1C(a,b) "SLIX_EPFX_MISC_LINT_ENA_W1C"
4324 #define device_bar_BDK_SLIX_EPFX_MISC_LINT_ENA_W1C(a,b) 0x0 /* PF_BAR0 */
4325 #define busnum_BDK_SLIX_EPFX_MISC_LINT_ENA_W1C(a,b) (a)
4326 #define arguments_BDK_SLIX_EPFX_MISC_LINT_ENA_W1C(a,b) (a),(b),-1,-1
4327
4328 /**
4329 * Register (NCB) sli#_epf#_misc_lint_ena_w1s
4330 *
4331 * SLI MAC Interrupt Enable Set Register
4332 * This register sets interrupt enable bits.
4333 */
4334 union bdk_slix_epfx_misc_lint_ena_w1s
4335 {
4336 uint64_t u;
4337 struct bdk_slix_epfx_misc_lint_ena_w1s_s
4338 {
4339 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4340 uint64_t reserved_7_63 : 57;
4341 uint64_t flr : 1; /**< [ 6: 6](R/W1S/H) Reads or sets enable for SLI(0)_EPF(0..3)_MISC_LINT[FLR]. */
4342 uint64_t dmapf_err : 1; /**< [ 5: 5](R/W1S/H) Reads or sets enable for SLI(0)_EPF(0..3)_MISC_LINT[DMAPF_ERR]. */
4343 uint64_t pppf_err : 1; /**< [ 4: 4](R/W1S/H) Reads or sets enable for SLI(0)_EPF(0..3)_MISC_LINT[PPPF_ERR]. */
4344 uint64_t un_wi : 1; /**< [ 3: 3](R/W1S/H) Reads or sets enable for SLI(0)_EPF(0..3)_MISC_LINT[UN_WI]. */
4345 uint64_t un_b0 : 1; /**< [ 2: 2](R/W1S/H) Reads or sets enable for SLI(0)_EPF(0..3)_MISC_LINT[UN_B0]. */
4346 uint64_t up_wi : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for SLI(0)_EPF(0..3)_MISC_LINT[UP_WI]. */
4347 uint64_t up_b0 : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for SLI(0)_EPF(0..3)_MISC_LINT[UP_B0]. */
4348 #else /* Word 0 - Little Endian */
4349 uint64_t up_b0 : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for SLI(0)_EPF(0..3)_MISC_LINT[UP_B0]. */
4350 uint64_t up_wi : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for SLI(0)_EPF(0..3)_MISC_LINT[UP_WI]. */
4351 uint64_t un_b0 : 1; /**< [ 2: 2](R/W1S/H) Reads or sets enable for SLI(0)_EPF(0..3)_MISC_LINT[UN_B0]. */
4352 uint64_t un_wi : 1; /**< [ 3: 3](R/W1S/H) Reads or sets enable for SLI(0)_EPF(0..3)_MISC_LINT[UN_WI]. */
4353 uint64_t pppf_err : 1; /**< [ 4: 4](R/W1S/H) Reads or sets enable for SLI(0)_EPF(0..3)_MISC_LINT[PPPF_ERR]. */
4354 uint64_t dmapf_err : 1; /**< [ 5: 5](R/W1S/H) Reads or sets enable for SLI(0)_EPF(0..3)_MISC_LINT[DMAPF_ERR]. */
4355 uint64_t flr : 1; /**< [ 6: 6](R/W1S/H) Reads or sets enable for SLI(0)_EPF(0..3)_MISC_LINT[FLR]. */
4356 uint64_t reserved_7_63 : 57;
4357 #endif /* Word 0 - End */
4358 } s;
4359 /* struct bdk_slix_epfx_misc_lint_ena_w1s_s cn; */
4360 };
4361 typedef union bdk_slix_epfx_misc_lint_ena_w1s bdk_slix_epfx_misc_lint_ena_w1s_t;
4362
4363 static inline uint64_t BDK_SLIX_EPFX_MISC_LINT_ENA_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_EPFX_MISC_LINT_ENA_W1S(unsigned long a,unsigned long b)4364 static inline uint64_t BDK_SLIX_EPFX_MISC_LINT_ENA_W1S(unsigned long a, unsigned long b)
4365 {
4366 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=3)))
4367 return 0x874000002700ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x3);
4368 __bdk_csr_fatal("SLIX_EPFX_MISC_LINT_ENA_W1S", 2, a, b, 0, 0);
4369 }
4370
4371 #define typedef_BDK_SLIX_EPFX_MISC_LINT_ENA_W1S(a,b) bdk_slix_epfx_misc_lint_ena_w1s_t
4372 #define bustype_BDK_SLIX_EPFX_MISC_LINT_ENA_W1S(a,b) BDK_CSR_TYPE_NCB
4373 #define basename_BDK_SLIX_EPFX_MISC_LINT_ENA_W1S(a,b) "SLIX_EPFX_MISC_LINT_ENA_W1S"
4374 #define device_bar_BDK_SLIX_EPFX_MISC_LINT_ENA_W1S(a,b) 0x0 /* PF_BAR0 */
4375 #define busnum_BDK_SLIX_EPFX_MISC_LINT_ENA_W1S(a,b) (a)
4376 #define arguments_BDK_SLIX_EPFX_MISC_LINT_ENA_W1S(a,b) (a),(b),-1,-1
4377
4378 /**
4379 * Register (NCB) sli#_epf#_misc_lint_w1s
4380 *
4381 * SLI MAC Interrupt Set Register
4382 * This register sets interrupt bits.
4383 */
4384 union bdk_slix_epfx_misc_lint_w1s
4385 {
4386 uint64_t u;
4387 struct bdk_slix_epfx_misc_lint_w1s_s
4388 {
4389 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4390 uint64_t reserved_7_63 : 57;
4391 uint64_t flr : 1; /**< [ 6: 6](R/W1S/H) Reads or sets SLI(0)_EPF(0..3)_MISC_LINT[FLR]. */
4392 uint64_t dmapf_err : 1; /**< [ 5: 5](R/W1S/H) Reads or sets SLI(0)_EPF(0..3)_MISC_LINT[DMAPF_ERR]. */
4393 uint64_t pppf_err : 1; /**< [ 4: 4](R/W1S/H) Reads or sets SLI(0)_EPF(0..3)_MISC_LINT[PPPF_ERR]. */
4394 uint64_t un_wi : 1; /**< [ 3: 3](R/W1S/H) Reads or sets SLI(0)_EPF(0..3)_MISC_LINT[UN_WI]. */
4395 uint64_t un_b0 : 1; /**< [ 2: 2](R/W1S/H) Reads or sets SLI(0)_EPF(0..3)_MISC_LINT[UN_B0]. */
4396 uint64_t up_wi : 1; /**< [ 1: 1](R/W1S/H) Reads or sets SLI(0)_EPF(0..3)_MISC_LINT[UP_WI]. */
4397 uint64_t up_b0 : 1; /**< [ 0: 0](R/W1S/H) Reads or sets SLI(0)_EPF(0..3)_MISC_LINT[UP_B0]. */
4398 #else /* Word 0 - Little Endian */
4399 uint64_t up_b0 : 1; /**< [ 0: 0](R/W1S/H) Reads or sets SLI(0)_EPF(0..3)_MISC_LINT[UP_B0]. */
4400 uint64_t up_wi : 1; /**< [ 1: 1](R/W1S/H) Reads or sets SLI(0)_EPF(0..3)_MISC_LINT[UP_WI]. */
4401 uint64_t un_b0 : 1; /**< [ 2: 2](R/W1S/H) Reads or sets SLI(0)_EPF(0..3)_MISC_LINT[UN_B0]. */
4402 uint64_t un_wi : 1; /**< [ 3: 3](R/W1S/H) Reads or sets SLI(0)_EPF(0..3)_MISC_LINT[UN_WI]. */
4403 uint64_t pppf_err : 1; /**< [ 4: 4](R/W1S/H) Reads or sets SLI(0)_EPF(0..3)_MISC_LINT[PPPF_ERR]. */
4404 uint64_t dmapf_err : 1; /**< [ 5: 5](R/W1S/H) Reads or sets SLI(0)_EPF(0..3)_MISC_LINT[DMAPF_ERR]. */
4405 uint64_t flr : 1; /**< [ 6: 6](R/W1S/H) Reads or sets SLI(0)_EPF(0..3)_MISC_LINT[FLR]. */
4406 uint64_t reserved_7_63 : 57;
4407 #endif /* Word 0 - End */
4408 } s;
4409 /* struct bdk_slix_epfx_misc_lint_w1s_s cn; */
4410 };
4411 typedef union bdk_slix_epfx_misc_lint_w1s bdk_slix_epfx_misc_lint_w1s_t;
4412
4413 static inline uint64_t BDK_SLIX_EPFX_MISC_LINT_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_EPFX_MISC_LINT_W1S(unsigned long a,unsigned long b)4414 static inline uint64_t BDK_SLIX_EPFX_MISC_LINT_W1S(unsigned long a, unsigned long b)
4415 {
4416 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=3)))
4417 return 0x874000002500ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x3);
4418 __bdk_csr_fatal("SLIX_EPFX_MISC_LINT_W1S", 2, a, b, 0, 0);
4419 }
4420
4421 #define typedef_BDK_SLIX_EPFX_MISC_LINT_W1S(a,b) bdk_slix_epfx_misc_lint_w1s_t
4422 #define bustype_BDK_SLIX_EPFX_MISC_LINT_W1S(a,b) BDK_CSR_TYPE_NCB
4423 #define basename_BDK_SLIX_EPFX_MISC_LINT_W1S(a,b) "SLIX_EPFX_MISC_LINT_W1S"
4424 #define device_bar_BDK_SLIX_EPFX_MISC_LINT_W1S(a,b) 0x0 /* PF_BAR0 */
4425 #define busnum_BDK_SLIX_EPFX_MISC_LINT_W1S(a,b) (a)
4426 #define arguments_BDK_SLIX_EPFX_MISC_LINT_W1S(a,b) (a),(b),-1,-1
4427
4428 /**
4429 * Register (PEXP_NCB) sli#_epf#_misc_rint
4430 *
4431 * SLI MAC Interrupt Summary Register
4432 * This register contains the different interrupt-summary bits for one MAC in the SLI.
4433 * The given register associated with an EPF will be reset due to a PF FLR or MAC reset.
4434 * These registers are not affected by VF FLR.
4435 */
4436 union bdk_slix_epfx_misc_rint
4437 {
4438 uint64_t u;
4439 struct bdk_slix_epfx_misc_rint_s
4440 {
4441 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4442 uint64_t reserved_6_63 : 58;
4443 uint64_t dmapf_err : 1; /**< [ 5: 5](R/W1C/H) Set when an error response is received for a PF DMA transaction read. */
4444 uint64_t pppf_err : 1; /**< [ 4: 4](R/W1C/H) Set when an error response is received for a PF PP transaction read. */
4445 uint64_t un_wi : 1; /**< [ 3: 3](R/W1C/H) Received unsupported N-TLP for window register from the corresponding MAC. This
4446 occurs when the window registers are disabled and a window register access
4447 occurs. */
4448 uint64_t un_b0 : 1; /**< [ 2: 2](R/W1C/H) Received unsupported N-TLP for Bar 0 from the corresponding MAC. This occurs
4449 when the BAR 0 address space is disabled. */
4450 uint64_t up_wi : 1; /**< [ 1: 1](R/W1C/H) Received unsupported P-TLP for window register from the corresponding MAC. This
4451 occurs when the window registers are disabled and a window register access
4452 occurs. */
4453 uint64_t up_b0 : 1; /**< [ 0: 0](R/W1C/H) Received unsupported P-TLP for Bar 0 from the corresponding MAC. This occurs
4454 when the BAR 0 address space is disabled. */
4455 #else /* Word 0 - Little Endian */
4456 uint64_t up_b0 : 1; /**< [ 0: 0](R/W1C/H) Received unsupported P-TLP for Bar 0 from the corresponding MAC. This occurs
4457 when the BAR 0 address space is disabled. */
4458 uint64_t up_wi : 1; /**< [ 1: 1](R/W1C/H) Received unsupported P-TLP for window register from the corresponding MAC. This
4459 occurs when the window registers are disabled and a window register access
4460 occurs. */
4461 uint64_t un_b0 : 1; /**< [ 2: 2](R/W1C/H) Received unsupported N-TLP for Bar 0 from the corresponding MAC. This occurs
4462 when the BAR 0 address space is disabled. */
4463 uint64_t un_wi : 1; /**< [ 3: 3](R/W1C/H) Received unsupported N-TLP for window register from the corresponding MAC. This
4464 occurs when the window registers are disabled and a window register access
4465 occurs. */
4466 uint64_t pppf_err : 1; /**< [ 4: 4](R/W1C/H) Set when an error response is received for a PF PP transaction read. */
4467 uint64_t dmapf_err : 1; /**< [ 5: 5](R/W1C/H) Set when an error response is received for a PF DMA transaction read. */
4468 uint64_t reserved_6_63 : 58;
4469 #endif /* Word 0 - End */
4470 } s;
4471 /* struct bdk_slix_epfx_misc_rint_s cn; */
4472 };
4473 typedef union bdk_slix_epfx_misc_rint bdk_slix_epfx_misc_rint_t;
4474
4475 static inline uint64_t BDK_SLIX_EPFX_MISC_RINT(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_EPFX_MISC_RINT(unsigned long a,unsigned long b)4476 static inline uint64_t BDK_SLIX_EPFX_MISC_RINT(unsigned long a, unsigned long b)
4477 {
4478 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=3)))
4479 return 0x874080028240ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x3);
4480 __bdk_csr_fatal("SLIX_EPFX_MISC_RINT", 2, a, b, 0, 0);
4481 }
4482
4483 #define typedef_BDK_SLIX_EPFX_MISC_RINT(a,b) bdk_slix_epfx_misc_rint_t
4484 #define bustype_BDK_SLIX_EPFX_MISC_RINT(a,b) BDK_CSR_TYPE_PEXP_NCB
4485 #define basename_BDK_SLIX_EPFX_MISC_RINT(a,b) "SLIX_EPFX_MISC_RINT"
4486 #define device_bar_BDK_SLIX_EPFX_MISC_RINT(a,b) 0x0 /* PF_BAR0 */
4487 #define busnum_BDK_SLIX_EPFX_MISC_RINT(a,b) (a)
4488 #define arguments_BDK_SLIX_EPFX_MISC_RINT(a,b) (a),(b),-1,-1
4489
4490 /**
4491 * Register (PEXP_NCB) sli#_epf#_misc_rint_ena_w1c
4492 *
4493 * SLI MAC Interrupt Enable Clear Register
4494 * This register clears interrupt enable bits.
4495 */
4496 union bdk_slix_epfx_misc_rint_ena_w1c
4497 {
4498 uint64_t u;
4499 struct bdk_slix_epfx_misc_rint_ena_w1c_s
4500 {
4501 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4502 uint64_t reserved_6_63 : 58;
4503 uint64_t dmapf_err : 1; /**< [ 5: 5](R/W1C/H) Reads or clears enable for SLI(0)_EPF(0..3)_MISC_RINT[DMAPF_ERR]. */
4504 uint64_t pppf_err : 1; /**< [ 4: 4](R/W1C/H) Reads or clears enable for SLI(0)_EPF(0..3)_MISC_RINT[PPPF_ERR]. */
4505 uint64_t un_wi : 1; /**< [ 3: 3](R/W1C/H) Reads or clears enable for SLI(0)_EPF(0..3)_MISC_RINT[UN_WI]. */
4506 uint64_t un_b0 : 1; /**< [ 2: 2](R/W1C/H) Reads or clears enable for SLI(0)_EPF(0..3)_MISC_RINT[UN_B0]. */
4507 uint64_t up_wi : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for SLI(0)_EPF(0..3)_MISC_RINT[UP_WI]. */
4508 uint64_t up_b0 : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for SLI(0)_EPF(0..3)_MISC_RINT[UP_B0]. */
4509 #else /* Word 0 - Little Endian */
4510 uint64_t up_b0 : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for SLI(0)_EPF(0..3)_MISC_RINT[UP_B0]. */
4511 uint64_t up_wi : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for SLI(0)_EPF(0..3)_MISC_RINT[UP_WI]. */
4512 uint64_t un_b0 : 1; /**< [ 2: 2](R/W1C/H) Reads or clears enable for SLI(0)_EPF(0..3)_MISC_RINT[UN_B0]. */
4513 uint64_t un_wi : 1; /**< [ 3: 3](R/W1C/H) Reads or clears enable for SLI(0)_EPF(0..3)_MISC_RINT[UN_WI]. */
4514 uint64_t pppf_err : 1; /**< [ 4: 4](R/W1C/H) Reads or clears enable for SLI(0)_EPF(0..3)_MISC_RINT[PPPF_ERR]. */
4515 uint64_t dmapf_err : 1; /**< [ 5: 5](R/W1C/H) Reads or clears enable for SLI(0)_EPF(0..3)_MISC_RINT[DMAPF_ERR]. */
4516 uint64_t reserved_6_63 : 58;
4517 #endif /* Word 0 - End */
4518 } s;
4519 /* struct bdk_slix_epfx_misc_rint_ena_w1c_s cn; */
4520 };
4521 typedef union bdk_slix_epfx_misc_rint_ena_w1c bdk_slix_epfx_misc_rint_ena_w1c_t;
4522
4523 static inline uint64_t BDK_SLIX_EPFX_MISC_RINT_ENA_W1C(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_EPFX_MISC_RINT_ENA_W1C(unsigned long a,unsigned long b)4524 static inline uint64_t BDK_SLIX_EPFX_MISC_RINT_ENA_W1C(unsigned long a, unsigned long b)
4525 {
4526 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=3)))
4527 return 0x874080028260ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x3);
4528 __bdk_csr_fatal("SLIX_EPFX_MISC_RINT_ENA_W1C", 2, a, b, 0, 0);
4529 }
4530
4531 #define typedef_BDK_SLIX_EPFX_MISC_RINT_ENA_W1C(a,b) bdk_slix_epfx_misc_rint_ena_w1c_t
4532 #define bustype_BDK_SLIX_EPFX_MISC_RINT_ENA_W1C(a,b) BDK_CSR_TYPE_PEXP_NCB
4533 #define basename_BDK_SLIX_EPFX_MISC_RINT_ENA_W1C(a,b) "SLIX_EPFX_MISC_RINT_ENA_W1C"
4534 #define device_bar_BDK_SLIX_EPFX_MISC_RINT_ENA_W1C(a,b) 0x0 /* PF_BAR0 */
4535 #define busnum_BDK_SLIX_EPFX_MISC_RINT_ENA_W1C(a,b) (a)
4536 #define arguments_BDK_SLIX_EPFX_MISC_RINT_ENA_W1C(a,b) (a),(b),-1,-1
4537
4538 /**
4539 * Register (PEXP_NCB) sli#_epf#_misc_rint_ena_w1s
4540 *
4541 * SLI MAC Interrupt Enable Set Register
4542 * This register sets interrupt enable bits.
4543 */
4544 union bdk_slix_epfx_misc_rint_ena_w1s
4545 {
4546 uint64_t u;
4547 struct bdk_slix_epfx_misc_rint_ena_w1s_s
4548 {
4549 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4550 uint64_t reserved_6_63 : 58;
4551 uint64_t dmapf_err : 1; /**< [ 5: 5](R/W1S/H) Reads or sets enable for SLI(0)_EPF(0..3)_MISC_RINT[DMAPF_ERR]. */
4552 uint64_t pppf_err : 1; /**< [ 4: 4](R/W1S/H) Reads or sets enable for SLI(0)_EPF(0..3)_MISC_RINT[PPPF_ERR]. */
4553 uint64_t un_wi : 1; /**< [ 3: 3](R/W1S/H) Reads or sets enable for SLI(0)_EPF(0..3)_MISC_RINT[UN_WI]. */
4554 uint64_t un_b0 : 1; /**< [ 2: 2](R/W1S/H) Reads or sets enable for SLI(0)_EPF(0..3)_MISC_RINT[UN_B0]. */
4555 uint64_t up_wi : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for SLI(0)_EPF(0..3)_MISC_RINT[UP_WI]. */
4556 uint64_t up_b0 : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for SLI(0)_EPF(0..3)_MISC_RINT[UP_B0]. */
4557 #else /* Word 0 - Little Endian */
4558 uint64_t up_b0 : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for SLI(0)_EPF(0..3)_MISC_RINT[UP_B0]. */
4559 uint64_t up_wi : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for SLI(0)_EPF(0..3)_MISC_RINT[UP_WI]. */
4560 uint64_t un_b0 : 1; /**< [ 2: 2](R/W1S/H) Reads or sets enable for SLI(0)_EPF(0..3)_MISC_RINT[UN_B0]. */
4561 uint64_t un_wi : 1; /**< [ 3: 3](R/W1S/H) Reads or sets enable for SLI(0)_EPF(0..3)_MISC_RINT[UN_WI]. */
4562 uint64_t pppf_err : 1; /**< [ 4: 4](R/W1S/H) Reads or sets enable for SLI(0)_EPF(0..3)_MISC_RINT[PPPF_ERR]. */
4563 uint64_t dmapf_err : 1; /**< [ 5: 5](R/W1S/H) Reads or sets enable for SLI(0)_EPF(0..3)_MISC_RINT[DMAPF_ERR]. */
4564 uint64_t reserved_6_63 : 58;
4565 #endif /* Word 0 - End */
4566 } s;
4567 /* struct bdk_slix_epfx_misc_rint_ena_w1s_s cn; */
4568 };
4569 typedef union bdk_slix_epfx_misc_rint_ena_w1s bdk_slix_epfx_misc_rint_ena_w1s_t;
4570
4571 static inline uint64_t BDK_SLIX_EPFX_MISC_RINT_ENA_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_EPFX_MISC_RINT_ENA_W1S(unsigned long a,unsigned long b)4572 static inline uint64_t BDK_SLIX_EPFX_MISC_RINT_ENA_W1S(unsigned long a, unsigned long b)
4573 {
4574 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=3)))
4575 return 0x874080028270ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x3);
4576 __bdk_csr_fatal("SLIX_EPFX_MISC_RINT_ENA_W1S", 2, a, b, 0, 0);
4577 }
4578
4579 #define typedef_BDK_SLIX_EPFX_MISC_RINT_ENA_W1S(a,b) bdk_slix_epfx_misc_rint_ena_w1s_t
4580 #define bustype_BDK_SLIX_EPFX_MISC_RINT_ENA_W1S(a,b) BDK_CSR_TYPE_PEXP_NCB
4581 #define basename_BDK_SLIX_EPFX_MISC_RINT_ENA_W1S(a,b) "SLIX_EPFX_MISC_RINT_ENA_W1S"
4582 #define device_bar_BDK_SLIX_EPFX_MISC_RINT_ENA_W1S(a,b) 0x0 /* PF_BAR0 */
4583 #define busnum_BDK_SLIX_EPFX_MISC_RINT_ENA_W1S(a,b) (a)
4584 #define arguments_BDK_SLIX_EPFX_MISC_RINT_ENA_W1S(a,b) (a),(b),-1,-1
4585
4586 /**
4587 * Register (PEXP_NCB) sli#_epf#_misc_rint_w1s
4588 *
4589 * SLI MAC Interrupt Set Register
4590 * This register sets interrupt bits.
4591 */
4592 union bdk_slix_epfx_misc_rint_w1s
4593 {
4594 uint64_t u;
4595 struct bdk_slix_epfx_misc_rint_w1s_s
4596 {
4597 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4598 uint64_t reserved_6_63 : 58;
4599 uint64_t dmapf_err : 1; /**< [ 5: 5](R/W1S/H) Reads or sets SLI(0)_EPF(0..3)_MISC_RINT[DMAPF_ERR]. */
4600 uint64_t pppf_err : 1; /**< [ 4: 4](R/W1S/H) Reads or sets SLI(0)_EPF(0..3)_MISC_RINT[PPPF_ERR]. */
4601 uint64_t un_wi : 1; /**< [ 3: 3](R/W1S/H) Reads or sets SLI(0)_EPF(0..3)_MISC_RINT[UN_WI]. */
4602 uint64_t un_b0 : 1; /**< [ 2: 2](R/W1S/H) Reads or sets SLI(0)_EPF(0..3)_MISC_RINT[UN_B0]. */
4603 uint64_t up_wi : 1; /**< [ 1: 1](R/W1S/H) Reads or sets SLI(0)_EPF(0..3)_MISC_RINT[UP_WI]. */
4604 uint64_t up_b0 : 1; /**< [ 0: 0](R/W1S/H) Reads or sets SLI(0)_EPF(0..3)_MISC_RINT[UP_B0]. */
4605 #else /* Word 0 - Little Endian */
4606 uint64_t up_b0 : 1; /**< [ 0: 0](R/W1S/H) Reads or sets SLI(0)_EPF(0..3)_MISC_RINT[UP_B0]. */
4607 uint64_t up_wi : 1; /**< [ 1: 1](R/W1S/H) Reads or sets SLI(0)_EPF(0..3)_MISC_RINT[UP_WI]. */
4608 uint64_t un_b0 : 1; /**< [ 2: 2](R/W1S/H) Reads or sets SLI(0)_EPF(0..3)_MISC_RINT[UN_B0]. */
4609 uint64_t un_wi : 1; /**< [ 3: 3](R/W1S/H) Reads or sets SLI(0)_EPF(0..3)_MISC_RINT[UN_WI]. */
4610 uint64_t pppf_err : 1; /**< [ 4: 4](R/W1S/H) Reads or sets SLI(0)_EPF(0..3)_MISC_RINT[PPPF_ERR]. */
4611 uint64_t dmapf_err : 1; /**< [ 5: 5](R/W1S/H) Reads or sets SLI(0)_EPF(0..3)_MISC_RINT[DMAPF_ERR]. */
4612 uint64_t reserved_6_63 : 58;
4613 #endif /* Word 0 - End */
4614 } s;
4615 /* struct bdk_slix_epfx_misc_rint_w1s_s cn; */
4616 };
4617 typedef union bdk_slix_epfx_misc_rint_w1s bdk_slix_epfx_misc_rint_w1s_t;
4618
4619 static inline uint64_t BDK_SLIX_EPFX_MISC_RINT_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_EPFX_MISC_RINT_W1S(unsigned long a,unsigned long b)4620 static inline uint64_t BDK_SLIX_EPFX_MISC_RINT_W1S(unsigned long a, unsigned long b)
4621 {
4622 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=3)))
4623 return 0x874080028250ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x3);
4624 __bdk_csr_fatal("SLIX_EPFX_MISC_RINT_W1S", 2, a, b, 0, 0);
4625 }
4626
4627 #define typedef_BDK_SLIX_EPFX_MISC_RINT_W1S(a,b) bdk_slix_epfx_misc_rint_w1s_t
4628 #define bustype_BDK_SLIX_EPFX_MISC_RINT_W1S(a,b) BDK_CSR_TYPE_PEXP_NCB
4629 #define basename_BDK_SLIX_EPFX_MISC_RINT_W1S(a,b) "SLIX_EPFX_MISC_RINT_W1S"
4630 #define device_bar_BDK_SLIX_EPFX_MISC_RINT_W1S(a,b) 0x0 /* PF_BAR0 */
4631 #define busnum_BDK_SLIX_EPFX_MISC_RINT_W1S(a,b) (a)
4632 #define arguments_BDK_SLIX_EPFX_MISC_RINT_W1S(a,b) (a),(b),-1,-1
4633
4634 /**
4635 * Register (NCB) sli#_epf#_pp_vf_lint
4636 *
4637 * SLI PP Error Response VF Bit Array Registers
4638 * When an error response is received for a VF PP transaction read, the appropriate VF indexed
4639 * bit is set. The appropriate PF should read the appropriate register.
4640 * These registers are only valid for PEM0 PF0 and PEM2 PF0.
4641 */
4642 union bdk_slix_epfx_pp_vf_lint
4643 {
4644 uint64_t u;
4645 struct bdk_slix_epfx_pp_vf_lint_s
4646 {
4647 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4648 uint64_t vf_int : 64; /**< [ 63: 0](R/W1C/H) When an error response is received for a VF PP transaction read, the appropriate VF
4649 indexed bit is set. */
4650 #else /* Word 0 - Little Endian */
4651 uint64_t vf_int : 64; /**< [ 63: 0](R/W1C/H) When an error response is received for a VF PP transaction read, the appropriate VF
4652 indexed bit is set. */
4653 #endif /* Word 0 - End */
4654 } s;
4655 /* struct bdk_slix_epfx_pp_vf_lint_s cn; */
4656 };
4657 typedef union bdk_slix_epfx_pp_vf_lint bdk_slix_epfx_pp_vf_lint_t;
4658
4659 static inline uint64_t BDK_SLIX_EPFX_PP_VF_LINT(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_EPFX_PP_VF_LINT(unsigned long a,unsigned long b)4660 static inline uint64_t BDK_SLIX_EPFX_PP_VF_LINT(unsigned long a, unsigned long b)
4661 {
4662 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
4663 return 0x874000002800ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x1);
4664 __bdk_csr_fatal("SLIX_EPFX_PP_VF_LINT", 2, a, b, 0, 0);
4665 }
4666
4667 #define typedef_BDK_SLIX_EPFX_PP_VF_LINT(a,b) bdk_slix_epfx_pp_vf_lint_t
4668 #define bustype_BDK_SLIX_EPFX_PP_VF_LINT(a,b) BDK_CSR_TYPE_NCB
4669 #define basename_BDK_SLIX_EPFX_PP_VF_LINT(a,b) "SLIX_EPFX_PP_VF_LINT"
4670 #define device_bar_BDK_SLIX_EPFX_PP_VF_LINT(a,b) 0x0 /* PF_BAR0 */
4671 #define busnum_BDK_SLIX_EPFX_PP_VF_LINT(a,b) (a)
4672 #define arguments_BDK_SLIX_EPFX_PP_VF_LINT(a,b) (a),(b),-1,-1
4673
4674 /**
4675 * Register (NCB) sli#_epf#_pp_vf_lint_ena_w1c
4676 *
4677 * SLI PP Error Response VF Bit Array Local Enable Clear Registers
4678 * This register clears interrupt enable bits.
4679 */
4680 union bdk_slix_epfx_pp_vf_lint_ena_w1c
4681 {
4682 uint64_t u;
4683 struct bdk_slix_epfx_pp_vf_lint_ena_w1c_s
4684 {
4685 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4686 uint64_t vf_int : 64; /**< [ 63: 0](R/W1C/H) Reads or clears enable for SLI(0)_EPF(0..1)_PP_VF_LINT[VF_INT]. */
4687 #else /* Word 0 - Little Endian */
4688 uint64_t vf_int : 64; /**< [ 63: 0](R/W1C/H) Reads or clears enable for SLI(0)_EPF(0..1)_PP_VF_LINT[VF_INT]. */
4689 #endif /* Word 0 - End */
4690 } s;
4691 /* struct bdk_slix_epfx_pp_vf_lint_ena_w1c_s cn; */
4692 };
4693 typedef union bdk_slix_epfx_pp_vf_lint_ena_w1c bdk_slix_epfx_pp_vf_lint_ena_w1c_t;
4694
4695 static inline uint64_t BDK_SLIX_EPFX_PP_VF_LINT_ENA_W1C(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_EPFX_PP_VF_LINT_ENA_W1C(unsigned long a,unsigned long b)4696 static inline uint64_t BDK_SLIX_EPFX_PP_VF_LINT_ENA_W1C(unsigned long a, unsigned long b)
4697 {
4698 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
4699 return 0x874000002a00ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x1);
4700 __bdk_csr_fatal("SLIX_EPFX_PP_VF_LINT_ENA_W1C", 2, a, b, 0, 0);
4701 }
4702
4703 #define typedef_BDK_SLIX_EPFX_PP_VF_LINT_ENA_W1C(a,b) bdk_slix_epfx_pp_vf_lint_ena_w1c_t
4704 #define bustype_BDK_SLIX_EPFX_PP_VF_LINT_ENA_W1C(a,b) BDK_CSR_TYPE_NCB
4705 #define basename_BDK_SLIX_EPFX_PP_VF_LINT_ENA_W1C(a,b) "SLIX_EPFX_PP_VF_LINT_ENA_W1C"
4706 #define device_bar_BDK_SLIX_EPFX_PP_VF_LINT_ENA_W1C(a,b) 0x0 /* PF_BAR0 */
4707 #define busnum_BDK_SLIX_EPFX_PP_VF_LINT_ENA_W1C(a,b) (a)
4708 #define arguments_BDK_SLIX_EPFX_PP_VF_LINT_ENA_W1C(a,b) (a),(b),-1,-1
4709
4710 /**
4711 * Register (NCB) sli#_epf#_pp_vf_lint_ena_w1s
4712 *
4713 * SLI PP Error Response VF Bit Array Local Enable Set Registers
4714 * This register sets interrupt enable bits.
4715 */
4716 union bdk_slix_epfx_pp_vf_lint_ena_w1s
4717 {
4718 uint64_t u;
4719 struct bdk_slix_epfx_pp_vf_lint_ena_w1s_s
4720 {
4721 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4722 uint64_t vf_int : 64; /**< [ 63: 0](R/W1S/H) Reads or sets enable for SLI(0)_EPF(0..1)_PP_VF_LINT[VF_INT]. */
4723 #else /* Word 0 - Little Endian */
4724 uint64_t vf_int : 64; /**< [ 63: 0](R/W1S/H) Reads or sets enable for SLI(0)_EPF(0..1)_PP_VF_LINT[VF_INT]. */
4725 #endif /* Word 0 - End */
4726 } s;
4727 /* struct bdk_slix_epfx_pp_vf_lint_ena_w1s_s cn; */
4728 };
4729 typedef union bdk_slix_epfx_pp_vf_lint_ena_w1s bdk_slix_epfx_pp_vf_lint_ena_w1s_t;
4730
4731 static inline uint64_t BDK_SLIX_EPFX_PP_VF_LINT_ENA_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_EPFX_PP_VF_LINT_ENA_W1S(unsigned long a,unsigned long b)4732 static inline uint64_t BDK_SLIX_EPFX_PP_VF_LINT_ENA_W1S(unsigned long a, unsigned long b)
4733 {
4734 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
4735 return 0x874000002b00ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x1);
4736 __bdk_csr_fatal("SLIX_EPFX_PP_VF_LINT_ENA_W1S", 2, a, b, 0, 0);
4737 }
4738
4739 #define typedef_BDK_SLIX_EPFX_PP_VF_LINT_ENA_W1S(a,b) bdk_slix_epfx_pp_vf_lint_ena_w1s_t
4740 #define bustype_BDK_SLIX_EPFX_PP_VF_LINT_ENA_W1S(a,b) BDK_CSR_TYPE_NCB
4741 #define basename_BDK_SLIX_EPFX_PP_VF_LINT_ENA_W1S(a,b) "SLIX_EPFX_PP_VF_LINT_ENA_W1S"
4742 #define device_bar_BDK_SLIX_EPFX_PP_VF_LINT_ENA_W1S(a,b) 0x0 /* PF_BAR0 */
4743 #define busnum_BDK_SLIX_EPFX_PP_VF_LINT_ENA_W1S(a,b) (a)
4744 #define arguments_BDK_SLIX_EPFX_PP_VF_LINT_ENA_W1S(a,b) (a),(b),-1,-1
4745
4746 /**
4747 * Register (NCB) sli#_epf#_pp_vf_lint_w1s
4748 *
4749 * SLI PP Error Response VF Bit Array Set Registers
4750 * This register sets interrupt bits.
4751 */
4752 union bdk_slix_epfx_pp_vf_lint_w1s
4753 {
4754 uint64_t u;
4755 struct bdk_slix_epfx_pp_vf_lint_w1s_s
4756 {
4757 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4758 uint64_t vf_int : 64; /**< [ 63: 0](R/W1S/H) Reads or sets SLI(0)_EPF(0..1)_PP_VF_LINT[VF_INT]. */
4759 #else /* Word 0 - Little Endian */
4760 uint64_t vf_int : 64; /**< [ 63: 0](R/W1S/H) Reads or sets SLI(0)_EPF(0..1)_PP_VF_LINT[VF_INT]. */
4761 #endif /* Word 0 - End */
4762 } s;
4763 /* struct bdk_slix_epfx_pp_vf_lint_w1s_s cn; */
4764 };
4765 typedef union bdk_slix_epfx_pp_vf_lint_w1s bdk_slix_epfx_pp_vf_lint_w1s_t;
4766
4767 static inline uint64_t BDK_SLIX_EPFX_PP_VF_LINT_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_EPFX_PP_VF_LINT_W1S(unsigned long a,unsigned long b)4768 static inline uint64_t BDK_SLIX_EPFX_PP_VF_LINT_W1S(unsigned long a, unsigned long b)
4769 {
4770 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
4771 return 0x874000002900ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x1);
4772 __bdk_csr_fatal("SLIX_EPFX_PP_VF_LINT_W1S", 2, a, b, 0, 0);
4773 }
4774
4775 #define typedef_BDK_SLIX_EPFX_PP_VF_LINT_W1S(a,b) bdk_slix_epfx_pp_vf_lint_w1s_t
4776 #define bustype_BDK_SLIX_EPFX_PP_VF_LINT_W1S(a,b) BDK_CSR_TYPE_NCB
4777 #define basename_BDK_SLIX_EPFX_PP_VF_LINT_W1S(a,b) "SLIX_EPFX_PP_VF_LINT_W1S"
4778 #define device_bar_BDK_SLIX_EPFX_PP_VF_LINT_W1S(a,b) 0x0 /* PF_BAR0 */
4779 #define busnum_BDK_SLIX_EPFX_PP_VF_LINT_W1S(a,b) (a)
4780 #define arguments_BDK_SLIX_EPFX_PP_VF_LINT_W1S(a,b) (a),(b),-1,-1
4781
4782 /**
4783 * Register (PEXP_NCB) sli#_epf#_pp_vf_rint
4784 *
4785 * SLI PP Error Response VF Bit Array Registers
4786 * When an error response is received for a VF PP transaction read, the appropriate VF indexed
4787 * bit is set. The appropriate PF should read the appropriate register.
4788 * The given register associated with an EPF will be reset due to a PF FLR or MAC reset.
4789 * These registers are not affected by VF FLR.
4790 * These registers are only valid for PEM0 PF0 and PEM2 PF0.
4791 */
4792 union bdk_slix_epfx_pp_vf_rint
4793 {
4794 uint64_t u;
4795 struct bdk_slix_epfx_pp_vf_rint_s
4796 {
4797 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4798 uint64_t vf_int : 64; /**< [ 63: 0](R/W1C/H) When an error response is received for a VF PP transaction read, the appropriate VF
4799 indexed bit is set. */
4800 #else /* Word 0 - Little Endian */
4801 uint64_t vf_int : 64; /**< [ 63: 0](R/W1C/H) When an error response is received for a VF PP transaction read, the appropriate VF
4802 indexed bit is set. */
4803 #endif /* Word 0 - End */
4804 } s;
4805 /* struct bdk_slix_epfx_pp_vf_rint_s cn; */
4806 };
4807 typedef union bdk_slix_epfx_pp_vf_rint bdk_slix_epfx_pp_vf_rint_t;
4808
4809 static inline uint64_t BDK_SLIX_EPFX_PP_VF_RINT(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_EPFX_PP_VF_RINT(unsigned long a,unsigned long b)4810 static inline uint64_t BDK_SLIX_EPFX_PP_VF_RINT(unsigned long a, unsigned long b)
4811 {
4812 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
4813 return 0x8740800282c0ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1);
4814 __bdk_csr_fatal("SLIX_EPFX_PP_VF_RINT", 2, a, b, 0, 0);
4815 }
4816
4817 #define typedef_BDK_SLIX_EPFX_PP_VF_RINT(a,b) bdk_slix_epfx_pp_vf_rint_t
4818 #define bustype_BDK_SLIX_EPFX_PP_VF_RINT(a,b) BDK_CSR_TYPE_PEXP_NCB
4819 #define basename_BDK_SLIX_EPFX_PP_VF_RINT(a,b) "SLIX_EPFX_PP_VF_RINT"
4820 #define device_bar_BDK_SLIX_EPFX_PP_VF_RINT(a,b) 0x0 /* PF_BAR0 */
4821 #define busnum_BDK_SLIX_EPFX_PP_VF_RINT(a,b) (a)
4822 #define arguments_BDK_SLIX_EPFX_PP_VF_RINT(a,b) (a),(b),-1,-1
4823
4824 /**
4825 * Register (PEXP_NCB) sli#_epf#_pp_vf_rint_ena_w1c
4826 *
4827 * SLI PP Error Response VF Bit Array Remote Enable Clear Registers
4828 * This register clears interrupt enable bits.
4829 */
4830 union bdk_slix_epfx_pp_vf_rint_ena_w1c
4831 {
4832 uint64_t u;
4833 struct bdk_slix_epfx_pp_vf_rint_ena_w1c_s
4834 {
4835 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4836 uint64_t vf_int : 64; /**< [ 63: 0](R/W1C/H) Reads or clears enable for SLI(0)_EPF(0..1)_PP_VF_RINT[VF_INT]. */
4837 #else /* Word 0 - Little Endian */
4838 uint64_t vf_int : 64; /**< [ 63: 0](R/W1C/H) Reads or clears enable for SLI(0)_EPF(0..1)_PP_VF_RINT[VF_INT]. */
4839 #endif /* Word 0 - End */
4840 } s;
4841 /* struct bdk_slix_epfx_pp_vf_rint_ena_w1c_s cn; */
4842 };
4843 typedef union bdk_slix_epfx_pp_vf_rint_ena_w1c bdk_slix_epfx_pp_vf_rint_ena_w1c_t;
4844
4845 static inline uint64_t BDK_SLIX_EPFX_PP_VF_RINT_ENA_W1C(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_EPFX_PP_VF_RINT_ENA_W1C(unsigned long a,unsigned long b)4846 static inline uint64_t BDK_SLIX_EPFX_PP_VF_RINT_ENA_W1C(unsigned long a, unsigned long b)
4847 {
4848 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
4849 return 0x8740800282e0ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1);
4850 __bdk_csr_fatal("SLIX_EPFX_PP_VF_RINT_ENA_W1C", 2, a, b, 0, 0);
4851 }
4852
4853 #define typedef_BDK_SLIX_EPFX_PP_VF_RINT_ENA_W1C(a,b) bdk_slix_epfx_pp_vf_rint_ena_w1c_t
4854 #define bustype_BDK_SLIX_EPFX_PP_VF_RINT_ENA_W1C(a,b) BDK_CSR_TYPE_PEXP_NCB
4855 #define basename_BDK_SLIX_EPFX_PP_VF_RINT_ENA_W1C(a,b) "SLIX_EPFX_PP_VF_RINT_ENA_W1C"
4856 #define device_bar_BDK_SLIX_EPFX_PP_VF_RINT_ENA_W1C(a,b) 0x0 /* PF_BAR0 */
4857 #define busnum_BDK_SLIX_EPFX_PP_VF_RINT_ENA_W1C(a,b) (a)
4858 #define arguments_BDK_SLIX_EPFX_PP_VF_RINT_ENA_W1C(a,b) (a),(b),-1,-1
4859
4860 /**
4861 * Register (PEXP_NCB) sli#_epf#_pp_vf_rint_ena_w1s
4862 *
4863 * SLI PP Error Response VF Bit Array Remote Enable Set Registers
4864 * This register sets interrupt enable bits.
4865 */
4866 union bdk_slix_epfx_pp_vf_rint_ena_w1s
4867 {
4868 uint64_t u;
4869 struct bdk_slix_epfx_pp_vf_rint_ena_w1s_s
4870 {
4871 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4872 uint64_t vf_int : 64; /**< [ 63: 0](R/W1S/H) Reads or sets enable for SLI(0)_EPF(0..1)_PP_VF_RINT[VF_INT]. */
4873 #else /* Word 0 - Little Endian */
4874 uint64_t vf_int : 64; /**< [ 63: 0](R/W1S/H) Reads or sets enable for SLI(0)_EPF(0..1)_PP_VF_RINT[VF_INT]. */
4875 #endif /* Word 0 - End */
4876 } s;
4877 /* struct bdk_slix_epfx_pp_vf_rint_ena_w1s_s cn; */
4878 };
4879 typedef union bdk_slix_epfx_pp_vf_rint_ena_w1s bdk_slix_epfx_pp_vf_rint_ena_w1s_t;
4880
4881 static inline uint64_t BDK_SLIX_EPFX_PP_VF_RINT_ENA_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_EPFX_PP_VF_RINT_ENA_W1S(unsigned long a,unsigned long b)4882 static inline uint64_t BDK_SLIX_EPFX_PP_VF_RINT_ENA_W1S(unsigned long a, unsigned long b)
4883 {
4884 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
4885 return 0x8740800282f0ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1);
4886 __bdk_csr_fatal("SLIX_EPFX_PP_VF_RINT_ENA_W1S", 2, a, b, 0, 0);
4887 }
4888
4889 #define typedef_BDK_SLIX_EPFX_PP_VF_RINT_ENA_W1S(a,b) bdk_slix_epfx_pp_vf_rint_ena_w1s_t
4890 #define bustype_BDK_SLIX_EPFX_PP_VF_RINT_ENA_W1S(a,b) BDK_CSR_TYPE_PEXP_NCB
4891 #define basename_BDK_SLIX_EPFX_PP_VF_RINT_ENA_W1S(a,b) "SLIX_EPFX_PP_VF_RINT_ENA_W1S"
4892 #define device_bar_BDK_SLIX_EPFX_PP_VF_RINT_ENA_W1S(a,b) 0x0 /* PF_BAR0 */
4893 #define busnum_BDK_SLIX_EPFX_PP_VF_RINT_ENA_W1S(a,b) (a)
4894 #define arguments_BDK_SLIX_EPFX_PP_VF_RINT_ENA_W1S(a,b) (a),(b),-1,-1
4895
4896 /**
4897 * Register (PEXP_NCB) sli#_epf#_pp_vf_rint_w1s
4898 *
4899 * SLI PP Error Response VF Bit Array Set Registers
4900 * This register sets interrupt bits.
4901 */
4902 union bdk_slix_epfx_pp_vf_rint_w1s
4903 {
4904 uint64_t u;
4905 struct bdk_slix_epfx_pp_vf_rint_w1s_s
4906 {
4907 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4908 uint64_t vf_int : 64; /**< [ 63: 0](R/W1S/H) Reads or sets SLI(0)_EPF(0..1)_PP_VF_RINT[VF_INT]. */
4909 #else /* Word 0 - Little Endian */
4910 uint64_t vf_int : 64; /**< [ 63: 0](R/W1S/H) Reads or sets SLI(0)_EPF(0..1)_PP_VF_RINT[VF_INT]. */
4911 #endif /* Word 0 - End */
4912 } s;
4913 /* struct bdk_slix_epfx_pp_vf_rint_w1s_s cn; */
4914 };
4915 typedef union bdk_slix_epfx_pp_vf_rint_w1s bdk_slix_epfx_pp_vf_rint_w1s_t;
4916
4917 static inline uint64_t BDK_SLIX_EPFX_PP_VF_RINT_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_EPFX_PP_VF_RINT_W1S(unsigned long a,unsigned long b)4918 static inline uint64_t BDK_SLIX_EPFX_PP_VF_RINT_W1S(unsigned long a, unsigned long b)
4919 {
4920 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=1)))
4921 return 0x8740800282d0ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x1);
4922 __bdk_csr_fatal("SLIX_EPFX_PP_VF_RINT_W1S", 2, a, b, 0, 0);
4923 }
4924
4925 #define typedef_BDK_SLIX_EPFX_PP_VF_RINT_W1S(a,b) bdk_slix_epfx_pp_vf_rint_w1s_t
4926 #define bustype_BDK_SLIX_EPFX_PP_VF_RINT_W1S(a,b) BDK_CSR_TYPE_PEXP_NCB
4927 #define basename_BDK_SLIX_EPFX_PP_VF_RINT_W1S(a,b) "SLIX_EPFX_PP_VF_RINT_W1S"
4928 #define device_bar_BDK_SLIX_EPFX_PP_VF_RINT_W1S(a,b) 0x0 /* PF_BAR0 */
4929 #define busnum_BDK_SLIX_EPFX_PP_VF_RINT_W1S(a,b) (a)
4930 #define arguments_BDK_SLIX_EPFX_PP_VF_RINT_W1S(a,b) (a),(b),-1,-1
4931
4932 /**
4933 * Register (PEXP_NCB) sli#_epf#_scratch
4934 *
4935 * SLI Scratch Register
4936 * These registers are general purpose 64-bit scratch registers for software use.
4937 */
4938 union bdk_slix_epfx_scratch
4939 {
4940 uint64_t u;
4941 struct bdk_slix_epfx_scratch_s
4942 {
4943 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4944 uint64_t data : 64; /**< [ 63: 0](R/W) The value in this register is totally software defined. */
4945 #else /* Word 0 - Little Endian */
4946 uint64_t data : 64; /**< [ 63: 0](R/W) The value in this register is totally software defined. */
4947 #endif /* Word 0 - End */
4948 } s;
4949 /* struct bdk_slix_epfx_scratch_s cn; */
4950 };
4951 typedef union bdk_slix_epfx_scratch bdk_slix_epfx_scratch_t;
4952
4953 static inline uint64_t BDK_SLIX_EPFX_SCRATCH(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_EPFX_SCRATCH(unsigned long a,unsigned long b)4954 static inline uint64_t BDK_SLIX_EPFX_SCRATCH(unsigned long a, unsigned long b)
4955 {
4956 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=3)))
4957 return 0x874080028100ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x3);
4958 __bdk_csr_fatal("SLIX_EPFX_SCRATCH", 2, a, b, 0, 0);
4959 }
4960
4961 #define typedef_BDK_SLIX_EPFX_SCRATCH(a,b) bdk_slix_epfx_scratch_t
4962 #define bustype_BDK_SLIX_EPFX_SCRATCH(a,b) BDK_CSR_TYPE_PEXP_NCB
4963 #define basename_BDK_SLIX_EPFX_SCRATCH(a,b) "SLIX_EPFX_SCRATCH"
4964 #define device_bar_BDK_SLIX_EPFX_SCRATCH(a,b) 0x0 /* PF_BAR0 */
4965 #define busnum_BDK_SLIX_EPFX_SCRATCH(a,b) (a)
4966 #define arguments_BDK_SLIX_EPFX_SCRATCH(a,b) (a),(b),-1,-1
4967
4968 /**
4969 * Register (NCB) sli#_lmac_const0#
4970 *
4971 * SLI Logical MAC Capabilities Register 0
4972 * These registers along with SLI()_LMAC_CONST1() create a table of logical MAC
4973 * capabilities. Each entry is 128 bits, with half the information in SLI()_LMAC_CONST0()
4974 * and half in SLI()_LMAC_CONST1().
4975 * The list ends with an entry where [V] is clear.
4976 *
4977 * Internal:
4978 * For CN81XX the table is as follows:
4979 * * SLI(0)_LMAC_CONST0/1(0) [ V=1 EP=0 IFTY=0 IFN=0 MAC=0 PF=0 EPF=0 VFS=0 RINGS=0 ].
4980 * * SLI(0)_LMAC_CONST0/1(1) [ V=1 EP=0 IFTY=0 IFN=1 MAC=1 PF=0 EPF=1 VFS=0 RINGS=0 ].
4981 * * SLI(0)_LMAC_CONST0/1(2) [ V=1 EP=0 IFTY=0 IFN=2 MAC=2 PF=0 EPF=2 VFS=0 RINGS=0 ].
4982 * * SLI(0)_LMAC_CONST0/1(3) [ V=0 ].
4983 *
4984 * For CN83XX the table is as follows:
4985 * * SLI(0)_LMAC_CONST0/1(0) [ V=1 EP=1 IFTY=0 IFN=0 MAC=0 PF=0 EPF=0 VFS=64 RINGS=64 ].
4986 * * SLI(0)_LMAC_CONST0/1(1) [ V=1 EP=1 IFTY=0 IFN=1 MAC=1 PF=0 EPF=2 VFS=0 RINGS=0 ].
4987 * * SLI(0)_LMAC_CONST0/1(2) [ V=1 EP=1 IFTY=0 IFN=2 MAC=2 PF=0 EPF=1 VFS=64 RINGS=64 ].
4988 * * SLI(0)_LMAC_CONST0/1(3) [ V=1 EP=1 IFTY=0 IFN=3 MAC=3 PF=0 EPF=3 VFS=0 RINGS=0 ].
4989 * * SLI(0)_LMAC_CONST0/1(4) [ V=0 ].
4990 */
4991 union bdk_slix_lmac_const0x
4992 {
4993 uint64_t u;
4994 struct bdk_slix_lmac_const0x_s
4995 {
4996 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4997 uint64_t reserved_40_63 : 24;
4998 uint64_t epf : 8; /**< [ 39: 32](RO) EPF number. Indicates the index number to EPF registers, e.g. the second index
4999 of SDP()_EPF()_MBOX_RINT. */
5000 uint64_t pf : 8; /**< [ 31: 24](RO) Physical function number. Indicates the PF number as viewed from the external
5001 PCI bus. */
5002 uint64_t mac : 8; /**< [ 23: 16](RO) Relative MAC number. Indicates the index number to MAC registers, e.g. the
5003 second index of SLI()_S2M_MAC()_CTL. */
5004 uint64_t ifn : 8; /**< [ 15: 8](RO) Interface number. Indicates the physical PEM number. */
5005 uint64_t ifty : 4; /**< [ 7: 4](RO) Interface type.
5006 0x0 = PEM. */
5007 uint64_t reserved_2_3 : 2;
5008 uint64_t ep : 1; /**< [ 1: 1](RO) Endpoint.
5009 0 = This MAC/PF does not support endpoint mode; many registers are not
5010 implemented including input and output ring-based registers. MSI-X message
5011 generation is also not implemented.
5012 1 = This MAC/PF combination supports endpoint mode. */
5013 uint64_t v : 1; /**< [ 0: 0](RO) Valid entry.
5014 0 = Fields in this register will all be zero. This ends the list of capabilities.
5015 1 = Fields are valid. There will be at least one subsequent list entry. */
5016 #else /* Word 0 - Little Endian */
5017 uint64_t v : 1; /**< [ 0: 0](RO) Valid entry.
5018 0 = Fields in this register will all be zero. This ends the list of capabilities.
5019 1 = Fields are valid. There will be at least one subsequent list entry. */
5020 uint64_t ep : 1; /**< [ 1: 1](RO) Endpoint.
5021 0 = This MAC/PF does not support endpoint mode; many registers are not
5022 implemented including input and output ring-based registers. MSI-X message
5023 generation is also not implemented.
5024 1 = This MAC/PF combination supports endpoint mode. */
5025 uint64_t reserved_2_3 : 2;
5026 uint64_t ifty : 4; /**< [ 7: 4](RO) Interface type.
5027 0x0 = PEM. */
5028 uint64_t ifn : 8; /**< [ 15: 8](RO) Interface number. Indicates the physical PEM number. */
5029 uint64_t mac : 8; /**< [ 23: 16](RO) Relative MAC number. Indicates the index number to MAC registers, e.g. the
5030 second index of SLI()_S2M_MAC()_CTL. */
5031 uint64_t pf : 8; /**< [ 31: 24](RO) Physical function number. Indicates the PF number as viewed from the external
5032 PCI bus. */
5033 uint64_t epf : 8; /**< [ 39: 32](RO) EPF number. Indicates the index number to EPF registers, e.g. the second index
5034 of SDP()_EPF()_MBOX_RINT. */
5035 uint64_t reserved_40_63 : 24;
5036 #endif /* Word 0 - End */
5037 } s;
5038 /* struct bdk_slix_lmac_const0x_s cn; */
5039 };
5040 typedef union bdk_slix_lmac_const0x bdk_slix_lmac_const0x_t;
5041
5042 static inline uint64_t BDK_SLIX_LMAC_CONST0X(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_LMAC_CONST0X(unsigned long a,unsigned long b)5043 static inline uint64_t BDK_SLIX_LMAC_CONST0X(unsigned long a, unsigned long b)
5044 {
5045 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b<=4)))
5046 return 0x874001004000ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x7);
5047 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=4)))
5048 return 0x874001004000ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x7);
5049 __bdk_csr_fatal("SLIX_LMAC_CONST0X", 2, a, b, 0, 0);
5050 }
5051
5052 #define typedef_BDK_SLIX_LMAC_CONST0X(a,b) bdk_slix_lmac_const0x_t
5053 #define bustype_BDK_SLIX_LMAC_CONST0X(a,b) BDK_CSR_TYPE_NCB
5054 #define basename_BDK_SLIX_LMAC_CONST0X(a,b) "SLIX_LMAC_CONST0X"
5055 #define device_bar_BDK_SLIX_LMAC_CONST0X(a,b) 0x0 /* PF_BAR0 */
5056 #define busnum_BDK_SLIX_LMAC_CONST0X(a,b) (a)
5057 #define arguments_BDK_SLIX_LMAC_CONST0X(a,b) (a),(b),-1,-1
5058
5059 /**
5060 * Register (NCB) sli#_lmac_const1#
5061 *
5062 * SLI Logical MAC Capabilities Register 1
5063 * See SLI()_LMAC_CONST0().
5064 */
5065 union bdk_slix_lmac_const1x
5066 {
5067 uint64_t u;
5068 struct bdk_slix_lmac_const1x_s
5069 {
5070 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5071 uint64_t reserved_32_63 : 32;
5072 uint64_t rings : 16; /**< [ 31: 16](RO) Number of rings.
5073 If [EP] is set then this field indicates the number of rings assigned
5074 to the physical function (which can also be shared with its associated
5075 virtual functions by means of the SLI()_EPF()_RINFO register.)
5076 If [EP] is clear then this field will be zero. */
5077 uint64_t vfs : 16; /**< [ 15: 0](RO) Number of virtual functions.
5078 The maximum number that may be programmed into SLI()_S2M_REG()_ACC2[VF]. */
5079 #else /* Word 0 - Little Endian */
5080 uint64_t vfs : 16; /**< [ 15: 0](RO) Number of virtual functions.
5081 The maximum number that may be programmed into SLI()_S2M_REG()_ACC2[VF]. */
5082 uint64_t rings : 16; /**< [ 31: 16](RO) Number of rings.
5083 If [EP] is set then this field indicates the number of rings assigned
5084 to the physical function (which can also be shared with its associated
5085 virtual functions by means of the SLI()_EPF()_RINFO register.)
5086 If [EP] is clear then this field will be zero. */
5087 uint64_t reserved_32_63 : 32;
5088 #endif /* Word 0 - End */
5089 } s;
5090 /* struct bdk_slix_lmac_const1x_s cn; */
5091 };
5092 typedef union bdk_slix_lmac_const1x bdk_slix_lmac_const1x_t;
5093
5094 static inline uint64_t BDK_SLIX_LMAC_CONST1X(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_LMAC_CONST1X(unsigned long a,unsigned long b)5095 static inline uint64_t BDK_SLIX_LMAC_CONST1X(unsigned long a, unsigned long b)
5096 {
5097 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b<=4)))
5098 return 0x874001004008ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x7);
5099 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=4)))
5100 return 0x874001004008ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x7);
5101 __bdk_csr_fatal("SLIX_LMAC_CONST1X", 2, a, b, 0, 0);
5102 }
5103
5104 #define typedef_BDK_SLIX_LMAC_CONST1X(a,b) bdk_slix_lmac_const1x_t
5105 #define bustype_BDK_SLIX_LMAC_CONST1X(a,b) BDK_CSR_TYPE_NCB
5106 #define basename_BDK_SLIX_LMAC_CONST1X(a,b) "SLIX_LMAC_CONST1X"
5107 #define device_bar_BDK_SLIX_LMAC_CONST1X(a,b) 0x0 /* PF_BAR0 */
5108 #define busnum_BDK_SLIX_LMAC_CONST1X(a,b) (a)
5109 #define arguments_BDK_SLIX_LMAC_CONST1X(a,b) (a),(b),-1,-1
5110
5111 /**
5112 * Register (NCB) sli#_m2s_mac#_ctl
5113 *
5114 * SLI Control Port Registers
5115 * This register controls the functionality of the SLI's M2S in regards to a MAC.
5116 * Internal:
5117 * In 78xx was SLI()_CTL_PORT() and SLI()_S2M_PORT()_CTL.
5118 */
5119 union bdk_slix_m2s_macx_ctl
5120 {
5121 uint64_t u;
5122 struct bdk_slix_m2s_macx_ctl_s
5123 {
5124 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5125 uint64_t reserved_21_63 : 43;
5126 uint64_t bige : 1; /**< [ 20: 20](R/W) Atomics sent on NCBI will be marked as big endian. If the link partner is
5127 big-endian and the processors are big-endian, this allows exchange of big-endian
5128 atomics without byte swapping. */
5129 uint64_t wait_pxfr : 1; /**< [ 19: 19](R/W) When set, will cause a posted TLP write from a MAC to follow the following sequence:
5130 (having this bit set will cut the posted-TLP performance about 50%).
5131 _ 1. Request the NCBI.
5132 _ 2. Wait for the grant and send the transfer on the NCBI.
5133 _ 3. Start the next posted TLP.
5134
5135 For diagnostic use only. */
5136 uint64_t wvirt : 1; /**< [ 18: 18](R/W) Write virtual:
5137 1 = Addresses in SLI()_WIN_WR_ADDR and SLI()_WIN_RD_ADDR are virtual addresses.
5138 0 = Addresses are physical addresses. */
5139 uint64_t dis_port : 1; /**< [ 17: 17](R/W1C/H) When set, the output to the MAC is disabled. This occurs when the MAC reset line
5140 transitions from de-asserted to asserted. Writing a 1 to this location clears this
5141 condition when the MAC is no longer in reset and the output to the MAC is at the beginning
5142 of a transfer. */
5143 uint64_t waitl_com : 1; /**< [ 16: 16](R/W) When set, causes the SLI to wait for a store done from the L2C for any
5144 previously sent stores, before sending additional completions to the L2C from
5145 the MAC.
5146 0 = More aggressive, higher-performance behavior. Suitable when device drivers are
5147 appropriately written for performance and do not assume that IO reads force all DMAs
5148 to be complete.
5149 1 = Compliant, lower-performing behavior. Enforce PCI-compliant completion
5150 versus posted/non-posted ordering. */
5151 uint64_t reserved_7_15 : 9;
5152 uint64_t ctlp_ro : 1; /**< [ 6: 6](R/W) Relaxed ordering enable for completion TLPS. This permits the SLI to use the RO bit sent
5153 from
5154 the MACs. See WAITL_COM. */
5155 uint64_t ptlp_ro : 1; /**< [ 5: 5](R/W) Relaxed ordering enable for posted TLPS. This permits the SLI to use the RO bit sent from
5156 the MACs. See WAIT_COM. */
5157 uint64_t wind_d : 1; /**< [ 4: 4](R/W) Window disable. When set, disables access to the window registers from the MAC. */
5158 uint64_t bar0_d : 1; /**< [ 3: 3](R/W) BAR0 disable. When set, disables access from the MAC to SLI BAR0 registers. */
5159 uint64_t ld_cmd : 2; /**< [ 2: 1](R/W) When SLI issues a load command to the L2C that is to be cached, this field selects the
5160 type of load command to use. Un-cached loads will use LDT:
5161 0x0 = LDD.
5162 0x1 = LDI.
5163 0x2 = LDE.
5164 0x3 = LDY. */
5165 uint64_t wait_com : 1; /**< [ 0: 0](R/W) Wait for commit. When set, causes the SLI to wait for a store done from the L2C before
5166 sending additional stores to the L2C from the MAC. The SLI requests a commit on the last
5167 store if more than one STORE operation is required on the NCB. Most applications will not
5168 notice a difference, so this bit should not be set. Setting the bit is more conservative
5169 on ordering, lower performance. */
5170 #else /* Word 0 - Little Endian */
5171 uint64_t wait_com : 1; /**< [ 0: 0](R/W) Wait for commit. When set, causes the SLI to wait for a store done from the L2C before
5172 sending additional stores to the L2C from the MAC. The SLI requests a commit on the last
5173 store if more than one STORE operation is required on the NCB. Most applications will not
5174 notice a difference, so this bit should not be set. Setting the bit is more conservative
5175 on ordering, lower performance. */
5176 uint64_t ld_cmd : 2; /**< [ 2: 1](R/W) When SLI issues a load command to the L2C that is to be cached, this field selects the
5177 type of load command to use. Un-cached loads will use LDT:
5178 0x0 = LDD.
5179 0x1 = LDI.
5180 0x2 = LDE.
5181 0x3 = LDY. */
5182 uint64_t bar0_d : 1; /**< [ 3: 3](R/W) BAR0 disable. When set, disables access from the MAC to SLI BAR0 registers. */
5183 uint64_t wind_d : 1; /**< [ 4: 4](R/W) Window disable. When set, disables access to the window registers from the MAC. */
5184 uint64_t ptlp_ro : 1; /**< [ 5: 5](R/W) Relaxed ordering enable for posted TLPS. This permits the SLI to use the RO bit sent from
5185 the MACs. See WAIT_COM. */
5186 uint64_t ctlp_ro : 1; /**< [ 6: 6](R/W) Relaxed ordering enable for completion TLPS. This permits the SLI to use the RO bit sent
5187 from
5188 the MACs. See WAITL_COM. */
5189 uint64_t reserved_7_15 : 9;
5190 uint64_t waitl_com : 1; /**< [ 16: 16](R/W) When set, causes the SLI to wait for a store done from the L2C for any
5191 previously sent stores, before sending additional completions to the L2C from
5192 the MAC.
5193 0 = More aggressive, higher-performance behavior. Suitable when device drivers are
5194 appropriately written for performance and do not assume that IO reads force all DMAs
5195 to be complete.
5196 1 = Compliant, lower-performing behavior. Enforce PCI-compliant completion
5197 versus posted/non-posted ordering. */
5198 uint64_t dis_port : 1; /**< [ 17: 17](R/W1C/H) When set, the output to the MAC is disabled. This occurs when the MAC reset line
5199 transitions from de-asserted to asserted. Writing a 1 to this location clears this
5200 condition when the MAC is no longer in reset and the output to the MAC is at the beginning
5201 of a transfer. */
5202 uint64_t wvirt : 1; /**< [ 18: 18](R/W) Write virtual:
5203 1 = Addresses in SLI()_WIN_WR_ADDR and SLI()_WIN_RD_ADDR are virtual addresses.
5204 0 = Addresses are physical addresses. */
5205 uint64_t wait_pxfr : 1; /**< [ 19: 19](R/W) When set, will cause a posted TLP write from a MAC to follow the following sequence:
5206 (having this bit set will cut the posted-TLP performance about 50%).
5207 _ 1. Request the NCBI.
5208 _ 2. Wait for the grant and send the transfer on the NCBI.
5209 _ 3. Start the next posted TLP.
5210
5211 For diagnostic use only. */
5212 uint64_t bige : 1; /**< [ 20: 20](R/W) Atomics sent on NCBI will be marked as big endian. If the link partner is
5213 big-endian and the processors are big-endian, this allows exchange of big-endian
5214 atomics without byte swapping. */
5215 uint64_t reserved_21_63 : 43;
5216 #endif /* Word 0 - End */
5217 } s;
5218 struct bdk_slix_m2s_macx_ctl_cn88xxp1
5219 {
5220 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5221 uint64_t reserved_19_63 : 45;
5222 uint64_t wvirt : 1; /**< [ 18: 18](R/W) Write virtual:
5223 1 = Addresses in SLI()_WIN_WR_ADDR and SLI()_WIN_RD_ADDR are virtual addresses.
5224 0 = Addresses are physical addresses. */
5225 uint64_t dis_port : 1; /**< [ 17: 17](R/W1C/H) When set, the output to the MAC is disabled. This occurs when the MAC reset line
5226 transitions from de-asserted to asserted. Writing a 1 to this location clears this
5227 condition when the MAC is no longer in reset and the output to the MAC is at the beginning
5228 of a transfer. */
5229 uint64_t waitl_com : 1; /**< [ 16: 16](R/W) When set, causes the SLI to wait for a store done from the L2C for any
5230 previously sent stores, before sending additional completions to the L2C from
5231 the MAC.
5232 0 = More aggressive, higher-performance behavior. Suitable when device drivers are
5233 appropriately written for performance and do not assume that IO reads force all DMAs
5234 to be complete.
5235 1 = Compliant, lower-performing behavior. Enforce PCI-compliant completion
5236 versus posted/non-posted ordering. */
5237 uint64_t reserved_7_15 : 9;
5238 uint64_t ctlp_ro : 1; /**< [ 6: 6](R/W) Relaxed ordering enable for completion TLPS. This permits the SLI to use the RO bit sent
5239 from
5240 the MACs. See WAITL_COM. */
5241 uint64_t ptlp_ro : 1; /**< [ 5: 5](R/W) Relaxed ordering enable for posted TLPS. This permits the SLI to use the RO bit sent from
5242 the MACs. See WAIT_COM. */
5243 uint64_t wind_d : 1; /**< [ 4: 4](R/W) Window disable. When set, disables access to the window registers from the MAC. */
5244 uint64_t bar0_d : 1; /**< [ 3: 3](R/W) BAR0 disable. When set, disables access from the MAC to SLI BAR0 registers. */
5245 uint64_t ld_cmd : 2; /**< [ 2: 1](R/W) When SLI issues a load command to the L2C that is to be cached, this field selects the
5246 type of load command to use. Un-cached loads will use LDT:
5247 0x0 = LDD.
5248 0x1 = LDI.
5249 0x2 = LDE.
5250 0x3 = LDY. */
5251 uint64_t wait_com : 1; /**< [ 0: 0](R/W) Wait for commit. When set, causes the SLI to wait for a store done from the L2C before
5252 sending additional stores to the L2C from the MAC. The SLI requests a commit on the last
5253 store if more than one STORE operation is required on the NCB. Most applications will not
5254 notice a difference, so this bit should not be set. Setting the bit is more conservative
5255 on ordering, lower performance. */
5256 #else /* Word 0 - Little Endian */
5257 uint64_t wait_com : 1; /**< [ 0: 0](R/W) Wait for commit. When set, causes the SLI to wait for a store done from the L2C before
5258 sending additional stores to the L2C from the MAC. The SLI requests a commit on the last
5259 store if more than one STORE operation is required on the NCB. Most applications will not
5260 notice a difference, so this bit should not be set. Setting the bit is more conservative
5261 on ordering, lower performance. */
5262 uint64_t ld_cmd : 2; /**< [ 2: 1](R/W) When SLI issues a load command to the L2C that is to be cached, this field selects the
5263 type of load command to use. Un-cached loads will use LDT:
5264 0x0 = LDD.
5265 0x1 = LDI.
5266 0x2 = LDE.
5267 0x3 = LDY. */
5268 uint64_t bar0_d : 1; /**< [ 3: 3](R/W) BAR0 disable. When set, disables access from the MAC to SLI BAR0 registers. */
5269 uint64_t wind_d : 1; /**< [ 4: 4](R/W) Window disable. When set, disables access to the window registers from the MAC. */
5270 uint64_t ptlp_ro : 1; /**< [ 5: 5](R/W) Relaxed ordering enable for posted TLPS. This permits the SLI to use the RO bit sent from
5271 the MACs. See WAIT_COM. */
5272 uint64_t ctlp_ro : 1; /**< [ 6: 6](R/W) Relaxed ordering enable for completion TLPS. This permits the SLI to use the RO bit sent
5273 from
5274 the MACs. See WAITL_COM. */
5275 uint64_t reserved_7_15 : 9;
5276 uint64_t waitl_com : 1; /**< [ 16: 16](R/W) When set, causes the SLI to wait for a store done from the L2C for any
5277 previously sent stores, before sending additional completions to the L2C from
5278 the MAC.
5279 0 = More aggressive, higher-performance behavior. Suitable when device drivers are
5280 appropriately written for performance and do not assume that IO reads force all DMAs
5281 to be complete.
5282 1 = Compliant, lower-performing behavior. Enforce PCI-compliant completion
5283 versus posted/non-posted ordering. */
5284 uint64_t dis_port : 1; /**< [ 17: 17](R/W1C/H) When set, the output to the MAC is disabled. This occurs when the MAC reset line
5285 transitions from de-asserted to asserted. Writing a 1 to this location clears this
5286 condition when the MAC is no longer in reset and the output to the MAC is at the beginning
5287 of a transfer. */
5288 uint64_t wvirt : 1; /**< [ 18: 18](R/W) Write virtual:
5289 1 = Addresses in SLI()_WIN_WR_ADDR and SLI()_WIN_RD_ADDR are virtual addresses.
5290 0 = Addresses are physical addresses. */
5291 uint64_t reserved_19_63 : 45;
5292 #endif /* Word 0 - End */
5293 } cn88xxp1;
5294 /* struct bdk_slix_m2s_macx_ctl_s cn81xx; */
5295 /* struct bdk_slix_m2s_macx_ctl_s cn83xx; */
5296 struct bdk_slix_m2s_macx_ctl_cn88xxp2
5297 {
5298 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5299 uint64_t reserved_20_63 : 44;
5300 uint64_t wait_pxfr : 1; /**< [ 19: 19](R/W) When set, will cause a posted TLP write from a MAC to follow the following sequence:
5301 (having this bit set will cut the posted-TLP performance about 50%).
5302 _ 1. Request the NCBI.
5303 _ 2. Wait for the grant and send the transfer on the NCBI.
5304 _ 3. Start the next posted TLP.
5305
5306 For diagnostic use only. */
5307 uint64_t wvirt : 1; /**< [ 18: 18](R/W) Write virtual:
5308 1 = Addresses in SLI()_WIN_WR_ADDR and SLI()_WIN_RD_ADDR are virtual addresses.
5309 0 = Addresses are physical addresses. */
5310 uint64_t dis_port : 1; /**< [ 17: 17](R/W1C/H) When set, the output to the MAC is disabled. This occurs when the MAC reset line
5311 transitions from de-asserted to asserted. Writing a 1 to this location clears this
5312 condition when the MAC is no longer in reset and the output to the MAC is at the beginning
5313 of a transfer. */
5314 uint64_t waitl_com : 1; /**< [ 16: 16](R/W) When set, causes the SLI to wait for a store done from the L2C for any
5315 previously sent stores, before sending additional completions to the L2C from
5316 the MAC.
5317 0 = More aggressive, higher-performance behavior. Suitable when device drivers are
5318 appropriately written for performance and do not assume that IO reads force all DMAs
5319 to be complete.
5320 1 = Compliant, lower-performing behavior. Enforce PCI-compliant completion
5321 versus posted/non-posted ordering. */
5322 uint64_t reserved_7_15 : 9;
5323 uint64_t ctlp_ro : 1; /**< [ 6: 6](R/W) Relaxed ordering enable for completion TLPS. This permits the SLI to use the RO bit sent
5324 from
5325 the MACs. See WAITL_COM. */
5326 uint64_t ptlp_ro : 1; /**< [ 5: 5](R/W) Relaxed ordering enable for posted TLPS. This permits the SLI to use the RO bit sent from
5327 the MACs. See WAIT_COM. */
5328 uint64_t wind_d : 1; /**< [ 4: 4](R/W) Window disable. When set, disables access to the window registers from the MAC. */
5329 uint64_t bar0_d : 1; /**< [ 3: 3](R/W) BAR0 disable. When set, disables access from the MAC to SLI BAR0 registers. */
5330 uint64_t ld_cmd : 2; /**< [ 2: 1](R/W) When SLI issues a load command to the L2C that is to be cached, this field selects the
5331 type of load command to use. Un-cached loads will use LDT:
5332 0x0 = LDD.
5333 0x1 = LDI.
5334 0x2 = LDE.
5335 0x3 = LDY. */
5336 uint64_t wait_com : 1; /**< [ 0: 0](R/W) Wait for commit. When set, causes the SLI to wait for a store done from the L2C before
5337 sending additional stores to the L2C from the MAC. The SLI requests a commit on the last
5338 store if more than one STORE operation is required on the NCB. Most applications will not
5339 notice a difference, so this bit should not be set. Setting the bit is more conservative
5340 on ordering, lower performance. */
5341 #else /* Word 0 - Little Endian */
5342 uint64_t wait_com : 1; /**< [ 0: 0](R/W) Wait for commit. When set, causes the SLI to wait for a store done from the L2C before
5343 sending additional stores to the L2C from the MAC. The SLI requests a commit on the last
5344 store if more than one STORE operation is required on the NCB. Most applications will not
5345 notice a difference, so this bit should not be set. Setting the bit is more conservative
5346 on ordering, lower performance. */
5347 uint64_t ld_cmd : 2; /**< [ 2: 1](R/W) When SLI issues a load command to the L2C that is to be cached, this field selects the
5348 type of load command to use. Un-cached loads will use LDT:
5349 0x0 = LDD.
5350 0x1 = LDI.
5351 0x2 = LDE.
5352 0x3 = LDY. */
5353 uint64_t bar0_d : 1; /**< [ 3: 3](R/W) BAR0 disable. When set, disables access from the MAC to SLI BAR0 registers. */
5354 uint64_t wind_d : 1; /**< [ 4: 4](R/W) Window disable. When set, disables access to the window registers from the MAC. */
5355 uint64_t ptlp_ro : 1; /**< [ 5: 5](R/W) Relaxed ordering enable for posted TLPS. This permits the SLI to use the RO bit sent from
5356 the MACs. See WAIT_COM. */
5357 uint64_t ctlp_ro : 1; /**< [ 6: 6](R/W) Relaxed ordering enable for completion TLPS. This permits the SLI to use the RO bit sent
5358 from
5359 the MACs. See WAITL_COM. */
5360 uint64_t reserved_7_15 : 9;
5361 uint64_t waitl_com : 1; /**< [ 16: 16](R/W) When set, causes the SLI to wait for a store done from the L2C for any
5362 previously sent stores, before sending additional completions to the L2C from
5363 the MAC.
5364 0 = More aggressive, higher-performance behavior. Suitable when device drivers are
5365 appropriately written for performance and do not assume that IO reads force all DMAs
5366 to be complete.
5367 1 = Compliant, lower-performing behavior. Enforce PCI-compliant completion
5368 versus posted/non-posted ordering. */
5369 uint64_t dis_port : 1; /**< [ 17: 17](R/W1C/H) When set, the output to the MAC is disabled. This occurs when the MAC reset line
5370 transitions from de-asserted to asserted. Writing a 1 to this location clears this
5371 condition when the MAC is no longer in reset and the output to the MAC is at the beginning
5372 of a transfer. */
5373 uint64_t wvirt : 1; /**< [ 18: 18](R/W) Write virtual:
5374 1 = Addresses in SLI()_WIN_WR_ADDR and SLI()_WIN_RD_ADDR are virtual addresses.
5375 0 = Addresses are physical addresses. */
5376 uint64_t wait_pxfr : 1; /**< [ 19: 19](R/W) When set, will cause a posted TLP write from a MAC to follow the following sequence:
5377 (having this bit set will cut the posted-TLP performance about 50%).
5378 _ 1. Request the NCBI.
5379 _ 2. Wait for the grant and send the transfer on the NCBI.
5380 _ 3. Start the next posted TLP.
5381
5382 For diagnostic use only. */
5383 uint64_t reserved_20_63 : 44;
5384 #endif /* Word 0 - End */
5385 } cn88xxp2;
5386 };
5387 typedef union bdk_slix_m2s_macx_ctl bdk_slix_m2s_macx_ctl_t;
5388
5389 static inline uint64_t BDK_SLIX_M2S_MACX_CTL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_M2S_MACX_CTL(unsigned long a,unsigned long b)5390 static inline uint64_t BDK_SLIX_M2S_MACX_CTL(unsigned long a, unsigned long b)
5391 {
5392 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b<=2)))
5393 return 0x874001002100ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x3);
5394 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=3)))
5395 return 0x874001002100ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x3);
5396 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=2)))
5397 return 0x874001002100ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x3);
5398 __bdk_csr_fatal("SLIX_M2S_MACX_CTL", 2, a, b, 0, 0);
5399 }
5400
5401 #define typedef_BDK_SLIX_M2S_MACX_CTL(a,b) bdk_slix_m2s_macx_ctl_t
5402 #define bustype_BDK_SLIX_M2S_MACX_CTL(a,b) BDK_CSR_TYPE_NCB
5403 #define basename_BDK_SLIX_M2S_MACX_CTL(a,b) "SLIX_M2S_MACX_CTL"
5404 #define device_bar_BDK_SLIX_M2S_MACX_CTL(a,b) 0x0 /* PF_BAR0 */
5405 #define busnum_BDK_SLIX_M2S_MACX_CTL(a,b) (a)
5406 #define arguments_BDK_SLIX_M2S_MACX_CTL(a,b) (a),(b),-1,-1
5407
5408 /**
5409 * Register (NCB) sli#_mac#_int_ena_w1c
5410 *
5411 * SLI MAC Interrupt Enable Clear Register
5412 * This register clears interrupt enable bits.
5413 */
5414 union bdk_slix_macx_int_ena_w1c
5415 {
5416 uint64_t u;
5417 struct bdk_slix_macx_int_ena_w1c_s
5418 {
5419 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5420 uint64_t reserved_4_63 : 60;
5421 uint64_t un_wi : 1; /**< [ 3: 3](R/W1C/H) Reads or clears enable for SLI(0..1)_MAC(0..2)_INT_SUM[UN_WI]. */
5422 uint64_t un_b0 : 1; /**< [ 2: 2](R/W1C/H) Reads or clears enable for SLI(0..1)_MAC(0..2)_INT_SUM[UN_B0]. */
5423 uint64_t up_wi : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for SLI(0..1)_MAC(0..2)_INT_SUM[UP_WI]. */
5424 uint64_t up_b0 : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for SLI(0..1)_MAC(0..2)_INT_SUM[UP_B0]. */
5425 #else /* Word 0 - Little Endian */
5426 uint64_t up_b0 : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for SLI(0..1)_MAC(0..2)_INT_SUM[UP_B0]. */
5427 uint64_t up_wi : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for SLI(0..1)_MAC(0..2)_INT_SUM[UP_WI]. */
5428 uint64_t un_b0 : 1; /**< [ 2: 2](R/W1C/H) Reads or clears enable for SLI(0..1)_MAC(0..2)_INT_SUM[UN_B0]. */
5429 uint64_t un_wi : 1; /**< [ 3: 3](R/W1C/H) Reads or clears enable for SLI(0..1)_MAC(0..2)_INT_SUM[UN_WI]. */
5430 uint64_t reserved_4_63 : 60;
5431 #endif /* Word 0 - End */
5432 } s;
5433 struct bdk_slix_macx_int_ena_w1c_cn81xx
5434 {
5435 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5436 uint64_t reserved_4_63 : 60;
5437 uint64_t un_wi : 1; /**< [ 3: 3](R/W1C/H) Reads or clears enable for SLI(0)_MAC(0..2)_INT_SUM[UN_WI]. */
5438 uint64_t un_b0 : 1; /**< [ 2: 2](R/W1C/H) Reads or clears enable for SLI(0)_MAC(0..2)_INT_SUM[UN_B0]. */
5439 uint64_t up_wi : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for SLI(0)_MAC(0..2)_INT_SUM[UP_WI]. */
5440 uint64_t up_b0 : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for SLI(0)_MAC(0..2)_INT_SUM[UP_B0]. */
5441 #else /* Word 0 - Little Endian */
5442 uint64_t up_b0 : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for SLI(0)_MAC(0..2)_INT_SUM[UP_B0]. */
5443 uint64_t up_wi : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for SLI(0)_MAC(0..2)_INT_SUM[UP_WI]. */
5444 uint64_t un_b0 : 1; /**< [ 2: 2](R/W1C/H) Reads or clears enable for SLI(0)_MAC(0..2)_INT_SUM[UN_B0]. */
5445 uint64_t un_wi : 1; /**< [ 3: 3](R/W1C/H) Reads or clears enable for SLI(0)_MAC(0..2)_INT_SUM[UN_WI]. */
5446 uint64_t reserved_4_63 : 60;
5447 #endif /* Word 0 - End */
5448 } cn81xx;
5449 /* struct bdk_slix_macx_int_ena_w1c_s cn88xx; */
5450 struct bdk_slix_macx_int_ena_w1c_cn83xx
5451 {
5452 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5453 uint64_t reserved_4_63 : 60;
5454 uint64_t un_wi : 1; /**< [ 3: 3](R/W1C/H) Reads or clears enable for SLI(0)_MAC(0..3)_INT_SUM[UN_WI]. */
5455 uint64_t un_b0 : 1; /**< [ 2: 2](R/W1C/H) Reads or clears enable for SLI(0)_MAC(0..3)_INT_SUM[UN_B0]. */
5456 uint64_t up_wi : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for SLI(0)_MAC(0..3)_INT_SUM[UP_WI]. */
5457 uint64_t up_b0 : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for SLI(0)_MAC(0..3)_INT_SUM[UP_B0]. */
5458 #else /* Word 0 - Little Endian */
5459 uint64_t up_b0 : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for SLI(0)_MAC(0..3)_INT_SUM[UP_B0]. */
5460 uint64_t up_wi : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for SLI(0)_MAC(0..3)_INT_SUM[UP_WI]. */
5461 uint64_t un_b0 : 1; /**< [ 2: 2](R/W1C/H) Reads or clears enable for SLI(0)_MAC(0..3)_INT_SUM[UN_B0]. */
5462 uint64_t un_wi : 1; /**< [ 3: 3](R/W1C/H) Reads or clears enable for SLI(0)_MAC(0..3)_INT_SUM[UN_WI]. */
5463 uint64_t reserved_4_63 : 60;
5464 #endif /* Word 0 - End */
5465 } cn83xx;
5466 };
5467 typedef union bdk_slix_macx_int_ena_w1c bdk_slix_macx_int_ena_w1c_t;
5468
5469 static inline uint64_t BDK_SLIX_MACX_INT_ENA_W1C(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_MACX_INT_ENA_W1C(unsigned long a,unsigned long b)5470 static inline uint64_t BDK_SLIX_MACX_INT_ENA_W1C(unsigned long a, unsigned long b)
5471 {
5472 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b<=2)))
5473 return 0x874000001200ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x3);
5474 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=3)))
5475 return 0x874000001200ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x3);
5476 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=2)))
5477 return 0x874000001200ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x3);
5478 __bdk_csr_fatal("SLIX_MACX_INT_ENA_W1C", 2, a, b, 0, 0);
5479 }
5480
5481 #define typedef_BDK_SLIX_MACX_INT_ENA_W1C(a,b) bdk_slix_macx_int_ena_w1c_t
5482 #define bustype_BDK_SLIX_MACX_INT_ENA_W1C(a,b) BDK_CSR_TYPE_NCB
5483 #define basename_BDK_SLIX_MACX_INT_ENA_W1C(a,b) "SLIX_MACX_INT_ENA_W1C"
5484 #define device_bar_BDK_SLIX_MACX_INT_ENA_W1C(a,b) 0x0 /* PF_BAR0 */
5485 #define busnum_BDK_SLIX_MACX_INT_ENA_W1C(a,b) (a)
5486 #define arguments_BDK_SLIX_MACX_INT_ENA_W1C(a,b) (a),(b),-1,-1
5487
5488 /**
5489 * Register (NCB) sli#_mac#_int_ena_w1s
5490 *
5491 * SLI MAC Interrupt Enable Set Register
5492 * This register sets interrupt enable bits.
5493 */
5494 union bdk_slix_macx_int_ena_w1s
5495 {
5496 uint64_t u;
5497 struct bdk_slix_macx_int_ena_w1s_s
5498 {
5499 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5500 uint64_t reserved_4_63 : 60;
5501 uint64_t un_wi : 1; /**< [ 3: 3](R/W1S/H) Reads or sets enable for SLI(0..1)_MAC(0..2)_INT_SUM[UN_WI]. */
5502 uint64_t un_b0 : 1; /**< [ 2: 2](R/W1S/H) Reads or sets enable for SLI(0..1)_MAC(0..2)_INT_SUM[UN_B0]. */
5503 uint64_t up_wi : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for SLI(0..1)_MAC(0..2)_INT_SUM[UP_WI]. */
5504 uint64_t up_b0 : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for SLI(0..1)_MAC(0..2)_INT_SUM[UP_B0]. */
5505 #else /* Word 0 - Little Endian */
5506 uint64_t up_b0 : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for SLI(0..1)_MAC(0..2)_INT_SUM[UP_B0]. */
5507 uint64_t up_wi : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for SLI(0..1)_MAC(0..2)_INT_SUM[UP_WI]. */
5508 uint64_t un_b0 : 1; /**< [ 2: 2](R/W1S/H) Reads or sets enable for SLI(0..1)_MAC(0..2)_INT_SUM[UN_B0]. */
5509 uint64_t un_wi : 1; /**< [ 3: 3](R/W1S/H) Reads or sets enable for SLI(0..1)_MAC(0..2)_INT_SUM[UN_WI]. */
5510 uint64_t reserved_4_63 : 60;
5511 #endif /* Word 0 - End */
5512 } s;
5513 struct bdk_slix_macx_int_ena_w1s_cn81xx
5514 {
5515 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5516 uint64_t reserved_4_63 : 60;
5517 uint64_t un_wi : 1; /**< [ 3: 3](R/W1S/H) Reads or sets enable for SLI(0)_MAC(0..2)_INT_SUM[UN_WI]. */
5518 uint64_t un_b0 : 1; /**< [ 2: 2](R/W1S/H) Reads or sets enable for SLI(0)_MAC(0..2)_INT_SUM[UN_B0]. */
5519 uint64_t up_wi : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for SLI(0)_MAC(0..2)_INT_SUM[UP_WI]. */
5520 uint64_t up_b0 : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for SLI(0)_MAC(0..2)_INT_SUM[UP_B0]. */
5521 #else /* Word 0 - Little Endian */
5522 uint64_t up_b0 : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for SLI(0)_MAC(0..2)_INT_SUM[UP_B0]. */
5523 uint64_t up_wi : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for SLI(0)_MAC(0..2)_INT_SUM[UP_WI]. */
5524 uint64_t un_b0 : 1; /**< [ 2: 2](R/W1S/H) Reads or sets enable for SLI(0)_MAC(0..2)_INT_SUM[UN_B0]. */
5525 uint64_t un_wi : 1; /**< [ 3: 3](R/W1S/H) Reads or sets enable for SLI(0)_MAC(0..2)_INT_SUM[UN_WI]. */
5526 uint64_t reserved_4_63 : 60;
5527 #endif /* Word 0 - End */
5528 } cn81xx;
5529 /* struct bdk_slix_macx_int_ena_w1s_s cn88xx; */
5530 struct bdk_slix_macx_int_ena_w1s_cn83xx
5531 {
5532 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5533 uint64_t reserved_4_63 : 60;
5534 uint64_t un_wi : 1; /**< [ 3: 3](R/W1S/H) Reads or sets enable for SLI(0)_MAC(0..3)_INT_SUM[UN_WI]. */
5535 uint64_t un_b0 : 1; /**< [ 2: 2](R/W1S/H) Reads or sets enable for SLI(0)_MAC(0..3)_INT_SUM[UN_B0]. */
5536 uint64_t up_wi : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for SLI(0)_MAC(0..3)_INT_SUM[UP_WI]. */
5537 uint64_t up_b0 : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for SLI(0)_MAC(0..3)_INT_SUM[UP_B0]. */
5538 #else /* Word 0 - Little Endian */
5539 uint64_t up_b0 : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for SLI(0)_MAC(0..3)_INT_SUM[UP_B0]. */
5540 uint64_t up_wi : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for SLI(0)_MAC(0..3)_INT_SUM[UP_WI]. */
5541 uint64_t un_b0 : 1; /**< [ 2: 2](R/W1S/H) Reads or sets enable for SLI(0)_MAC(0..3)_INT_SUM[UN_B0]. */
5542 uint64_t un_wi : 1; /**< [ 3: 3](R/W1S/H) Reads or sets enable for SLI(0)_MAC(0..3)_INT_SUM[UN_WI]. */
5543 uint64_t reserved_4_63 : 60;
5544 #endif /* Word 0 - End */
5545 } cn83xx;
5546 };
5547 typedef union bdk_slix_macx_int_ena_w1s bdk_slix_macx_int_ena_w1s_t;
5548
5549 static inline uint64_t BDK_SLIX_MACX_INT_ENA_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_MACX_INT_ENA_W1S(unsigned long a,unsigned long b)5550 static inline uint64_t BDK_SLIX_MACX_INT_ENA_W1S(unsigned long a, unsigned long b)
5551 {
5552 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b<=2)))
5553 return 0x874000001280ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x3);
5554 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=3)))
5555 return 0x874000001280ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x3);
5556 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=2)))
5557 return 0x874000001280ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x3);
5558 __bdk_csr_fatal("SLIX_MACX_INT_ENA_W1S", 2, a, b, 0, 0);
5559 }
5560
5561 #define typedef_BDK_SLIX_MACX_INT_ENA_W1S(a,b) bdk_slix_macx_int_ena_w1s_t
5562 #define bustype_BDK_SLIX_MACX_INT_ENA_W1S(a,b) BDK_CSR_TYPE_NCB
5563 #define basename_BDK_SLIX_MACX_INT_ENA_W1S(a,b) "SLIX_MACX_INT_ENA_W1S"
5564 #define device_bar_BDK_SLIX_MACX_INT_ENA_W1S(a,b) 0x0 /* PF_BAR0 */
5565 #define busnum_BDK_SLIX_MACX_INT_ENA_W1S(a,b) (a)
5566 #define arguments_BDK_SLIX_MACX_INT_ENA_W1S(a,b) (a),(b),-1,-1
5567
5568 /**
5569 * Register (NCB) sli#_mac#_int_sum
5570 *
5571 * SLI MAC Interrupt Summary Register
5572 * This register contains the different interrupt-summary bits for one MAC in the SLI.
5573 */
5574 union bdk_slix_macx_int_sum
5575 {
5576 uint64_t u;
5577 struct bdk_slix_macx_int_sum_s
5578 {
5579 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5580 uint64_t reserved_4_63 : 60;
5581 uint64_t un_wi : 1; /**< [ 3: 3](R/W1C/H) Received unsupported N-TLP for window register from MAC(0..2). This occurs when the window
5582 registers are disabled and a window register access occurs. */
5583 uint64_t un_b0 : 1; /**< [ 2: 2](R/W1C/H) Received unsupported N-TLP for Bar 0 from MAC(0..2). This occurs when the BAR 0 address
5584 space is disabled. */
5585 uint64_t up_wi : 1; /**< [ 1: 1](R/W1C/H) Received unsupported P-TLP for window register from MAC(0..2). This occurs when the window
5586 registers are disabled and a window register access occurs. */
5587 uint64_t up_b0 : 1; /**< [ 0: 0](R/W1C/H) Received unsupported P-TLP for Bar 0 from MAC(0..2). This occurs when the BAR 0 address
5588 space is disabled. */
5589 #else /* Word 0 - Little Endian */
5590 uint64_t up_b0 : 1; /**< [ 0: 0](R/W1C/H) Received unsupported P-TLP for Bar 0 from MAC(0..2). This occurs when the BAR 0 address
5591 space is disabled. */
5592 uint64_t up_wi : 1; /**< [ 1: 1](R/W1C/H) Received unsupported P-TLP for window register from MAC(0..2). This occurs when the window
5593 registers are disabled and a window register access occurs. */
5594 uint64_t un_b0 : 1; /**< [ 2: 2](R/W1C/H) Received unsupported N-TLP for Bar 0 from MAC(0..2). This occurs when the BAR 0 address
5595 space is disabled. */
5596 uint64_t un_wi : 1; /**< [ 3: 3](R/W1C/H) Received unsupported N-TLP for window register from MAC(0..2). This occurs when the window
5597 registers are disabled and a window register access occurs. */
5598 uint64_t reserved_4_63 : 60;
5599 #endif /* Word 0 - End */
5600 } s;
5601 /* struct bdk_slix_macx_int_sum_s cn81xx; */
5602 /* struct bdk_slix_macx_int_sum_s cn88xx; */
5603 struct bdk_slix_macx_int_sum_cn83xx
5604 {
5605 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5606 uint64_t reserved_4_63 : 60;
5607 uint64_t un_wi : 1; /**< [ 3: 3](R/W1C/H) Received unsupported N-TLP for window register from the corresponding MAC. This
5608 occurs when the window registers are disabled and a window register access occurs. */
5609 uint64_t un_b0 : 1; /**< [ 2: 2](R/W1C/H) Received unsupported N-TLP for Bar 0 from the corresponding MAC. This occurs
5610 when the BAR 0 address space is disabled. */
5611 uint64_t up_wi : 1; /**< [ 1: 1](R/W1C/H) Received unsupported P-TLP for window register from the corresponding MAC. This
5612 occurs when the window registers are disabled and a window register access occurs. */
5613 uint64_t up_b0 : 1; /**< [ 0: 0](R/W1C/H) Received unsupported P-TLP for Bar 0 from the corresponding MAC. This occurs
5614 when the BAR 0 address space is disabled. */
5615 #else /* Word 0 - Little Endian */
5616 uint64_t up_b0 : 1; /**< [ 0: 0](R/W1C/H) Received unsupported P-TLP for Bar 0 from the corresponding MAC. This occurs
5617 when the BAR 0 address space is disabled. */
5618 uint64_t up_wi : 1; /**< [ 1: 1](R/W1C/H) Received unsupported P-TLP for window register from the corresponding MAC. This
5619 occurs when the window registers are disabled and a window register access occurs. */
5620 uint64_t un_b0 : 1; /**< [ 2: 2](R/W1C/H) Received unsupported N-TLP for Bar 0 from the corresponding MAC. This occurs
5621 when the BAR 0 address space is disabled. */
5622 uint64_t un_wi : 1; /**< [ 3: 3](R/W1C/H) Received unsupported N-TLP for window register from the corresponding MAC. This
5623 occurs when the window registers are disabled and a window register access occurs. */
5624 uint64_t reserved_4_63 : 60;
5625 #endif /* Word 0 - End */
5626 } cn83xx;
5627 };
5628 typedef union bdk_slix_macx_int_sum bdk_slix_macx_int_sum_t;
5629
5630 static inline uint64_t BDK_SLIX_MACX_INT_SUM(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_MACX_INT_SUM(unsigned long a,unsigned long b)5631 static inline uint64_t BDK_SLIX_MACX_INT_SUM(unsigned long a, unsigned long b)
5632 {
5633 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b<=2)))
5634 return 0x874000001100ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x3);
5635 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=3)))
5636 return 0x874000001100ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x3);
5637 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=2)))
5638 return 0x874000001100ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x3);
5639 __bdk_csr_fatal("SLIX_MACX_INT_SUM", 2, a, b, 0, 0);
5640 }
5641
5642 #define typedef_BDK_SLIX_MACX_INT_SUM(a,b) bdk_slix_macx_int_sum_t
5643 #define bustype_BDK_SLIX_MACX_INT_SUM(a,b) BDK_CSR_TYPE_NCB
5644 #define basename_BDK_SLIX_MACX_INT_SUM(a,b) "SLIX_MACX_INT_SUM"
5645 #define device_bar_BDK_SLIX_MACX_INT_SUM(a,b) 0x0 /* PF_BAR0 */
5646 #define busnum_BDK_SLIX_MACX_INT_SUM(a,b) (a)
5647 #define arguments_BDK_SLIX_MACX_INT_SUM(a,b) (a),(b),-1,-1
5648
5649 /**
5650 * Register (NCB) sli#_mac#_int_sum_w1s
5651 *
5652 * SLI MAC Interrupt Set Register
5653 * This register sets interrupt bits.
5654 */
5655 union bdk_slix_macx_int_sum_w1s
5656 {
5657 uint64_t u;
5658 struct bdk_slix_macx_int_sum_w1s_s
5659 {
5660 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5661 uint64_t reserved_4_63 : 60;
5662 uint64_t un_wi : 1; /**< [ 3: 3](R/W1S/H) Reads or sets SLI(0..1)_MAC(0..2)_INT_SUM[UN_WI]. */
5663 uint64_t un_b0 : 1; /**< [ 2: 2](R/W1S/H) Reads or sets SLI(0..1)_MAC(0..2)_INT_SUM[UN_B0]. */
5664 uint64_t up_wi : 1; /**< [ 1: 1](R/W1S/H) Reads or sets SLI(0..1)_MAC(0..2)_INT_SUM[UP_WI]. */
5665 uint64_t up_b0 : 1; /**< [ 0: 0](R/W1S/H) Reads or sets SLI(0..1)_MAC(0..2)_INT_SUM[UP_B0]. */
5666 #else /* Word 0 - Little Endian */
5667 uint64_t up_b0 : 1; /**< [ 0: 0](R/W1S/H) Reads or sets SLI(0..1)_MAC(0..2)_INT_SUM[UP_B0]. */
5668 uint64_t up_wi : 1; /**< [ 1: 1](R/W1S/H) Reads or sets SLI(0..1)_MAC(0..2)_INT_SUM[UP_WI]. */
5669 uint64_t un_b0 : 1; /**< [ 2: 2](R/W1S/H) Reads or sets SLI(0..1)_MAC(0..2)_INT_SUM[UN_B0]. */
5670 uint64_t un_wi : 1; /**< [ 3: 3](R/W1S/H) Reads or sets SLI(0..1)_MAC(0..2)_INT_SUM[UN_WI]. */
5671 uint64_t reserved_4_63 : 60;
5672 #endif /* Word 0 - End */
5673 } s;
5674 struct bdk_slix_macx_int_sum_w1s_cn81xx
5675 {
5676 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5677 uint64_t reserved_4_63 : 60;
5678 uint64_t un_wi : 1; /**< [ 3: 3](R/W1S/H) Reads or sets SLI(0)_MAC(0..2)_INT_SUM[UN_WI]. */
5679 uint64_t un_b0 : 1; /**< [ 2: 2](R/W1S/H) Reads or sets SLI(0)_MAC(0..2)_INT_SUM[UN_B0]. */
5680 uint64_t up_wi : 1; /**< [ 1: 1](R/W1S/H) Reads or sets SLI(0)_MAC(0..2)_INT_SUM[UP_WI]. */
5681 uint64_t up_b0 : 1; /**< [ 0: 0](R/W1S/H) Reads or sets SLI(0)_MAC(0..2)_INT_SUM[UP_B0]. */
5682 #else /* Word 0 - Little Endian */
5683 uint64_t up_b0 : 1; /**< [ 0: 0](R/W1S/H) Reads or sets SLI(0)_MAC(0..2)_INT_SUM[UP_B0]. */
5684 uint64_t up_wi : 1; /**< [ 1: 1](R/W1S/H) Reads or sets SLI(0)_MAC(0..2)_INT_SUM[UP_WI]. */
5685 uint64_t un_b0 : 1; /**< [ 2: 2](R/W1S/H) Reads or sets SLI(0)_MAC(0..2)_INT_SUM[UN_B0]. */
5686 uint64_t un_wi : 1; /**< [ 3: 3](R/W1S/H) Reads or sets SLI(0)_MAC(0..2)_INT_SUM[UN_WI]. */
5687 uint64_t reserved_4_63 : 60;
5688 #endif /* Word 0 - End */
5689 } cn81xx;
5690 /* struct bdk_slix_macx_int_sum_w1s_s cn88xx; */
5691 struct bdk_slix_macx_int_sum_w1s_cn83xx
5692 {
5693 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5694 uint64_t reserved_4_63 : 60;
5695 uint64_t un_wi : 1; /**< [ 3: 3](R/W1S/H) Reads or sets SLI(0)_MAC(0..3)_INT_SUM[UN_WI]. */
5696 uint64_t un_b0 : 1; /**< [ 2: 2](R/W1S/H) Reads or sets SLI(0)_MAC(0..3)_INT_SUM[UN_B0]. */
5697 uint64_t up_wi : 1; /**< [ 1: 1](R/W1S/H) Reads or sets SLI(0)_MAC(0..3)_INT_SUM[UP_WI]. */
5698 uint64_t up_b0 : 1; /**< [ 0: 0](R/W1S/H) Reads or sets SLI(0)_MAC(0..3)_INT_SUM[UP_B0]. */
5699 #else /* Word 0 - Little Endian */
5700 uint64_t up_b0 : 1; /**< [ 0: 0](R/W1S/H) Reads or sets SLI(0)_MAC(0..3)_INT_SUM[UP_B0]. */
5701 uint64_t up_wi : 1; /**< [ 1: 1](R/W1S/H) Reads or sets SLI(0)_MAC(0..3)_INT_SUM[UP_WI]. */
5702 uint64_t un_b0 : 1; /**< [ 2: 2](R/W1S/H) Reads or sets SLI(0)_MAC(0..3)_INT_SUM[UN_B0]. */
5703 uint64_t un_wi : 1; /**< [ 3: 3](R/W1S/H) Reads or sets SLI(0)_MAC(0..3)_INT_SUM[UN_WI]. */
5704 uint64_t reserved_4_63 : 60;
5705 #endif /* Word 0 - End */
5706 } cn83xx;
5707 };
5708 typedef union bdk_slix_macx_int_sum_w1s bdk_slix_macx_int_sum_w1s_t;
5709
5710 static inline uint64_t BDK_SLIX_MACX_INT_SUM_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_MACX_INT_SUM_W1S(unsigned long a,unsigned long b)5711 static inline uint64_t BDK_SLIX_MACX_INT_SUM_W1S(unsigned long a, unsigned long b)
5712 {
5713 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b<=2)))
5714 return 0x874000001180ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x3);
5715 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=3)))
5716 return 0x874000001180ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x3);
5717 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=2)))
5718 return 0x874000001180ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x3);
5719 __bdk_csr_fatal("SLIX_MACX_INT_SUM_W1S", 2, a, b, 0, 0);
5720 }
5721
5722 #define typedef_BDK_SLIX_MACX_INT_SUM_W1S(a,b) bdk_slix_macx_int_sum_w1s_t
5723 #define bustype_BDK_SLIX_MACX_INT_SUM_W1S(a,b) BDK_CSR_TYPE_NCB
5724 #define basename_BDK_SLIX_MACX_INT_SUM_W1S(a,b) "SLIX_MACX_INT_SUM_W1S"
5725 #define device_bar_BDK_SLIX_MACX_INT_SUM_W1S(a,b) 0x0 /* PF_BAR0 */
5726 #define busnum_BDK_SLIX_MACX_INT_SUM_W1S(a,b) (a)
5727 #define arguments_BDK_SLIX_MACX_INT_SUM_W1S(a,b) (a),(b),-1,-1
5728
5729 /**
5730 * Register (PEXP) sli#_mac_number
5731 *
5732 * SLI MAC Number Register
5733 * When read from a MAC, this register returns the MAC's port number, otherwise returns zero.
5734 */
5735 union bdk_slix_mac_number
5736 {
5737 uint64_t u;
5738 struct bdk_slix_mac_number_s
5739 {
5740 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5741 uint64_t reserved_32_63 : 32;
5742 uint64_t chip_rev : 8; /**< [ 31: 24](RO/H) Chip revision. See MIO_FUS_DAT2[CHIP_ID]. */
5743 uint64_t reserved_20_23 : 4;
5744 uint64_t oci_id : 4; /**< [ 19: 16](RO) The CCPI node ID. */
5745 uint64_t reserved_9_15 : 7;
5746 uint64_t a_mode : 1; /**< [ 8: 8](RO/H) Trusted mode. See RST_BOOT[TRUSTED_MODE]. */
5747 uint64_t num : 8; /**< [ 7: 0](RO/H) MAC number. */
5748 #else /* Word 0 - Little Endian */
5749 uint64_t num : 8; /**< [ 7: 0](RO/H) MAC number. */
5750 uint64_t a_mode : 1; /**< [ 8: 8](RO/H) Trusted mode. See RST_BOOT[TRUSTED_MODE]. */
5751 uint64_t reserved_9_15 : 7;
5752 uint64_t oci_id : 4; /**< [ 19: 16](RO) The CCPI node ID. */
5753 uint64_t reserved_20_23 : 4;
5754 uint64_t chip_rev : 8; /**< [ 31: 24](RO/H) Chip revision. See MIO_FUS_DAT2[CHIP_ID]. */
5755 uint64_t reserved_32_63 : 32;
5756 #endif /* Word 0 - End */
5757 } s;
5758 /* struct bdk_slix_mac_number_s cn; */
5759 };
5760 typedef union bdk_slix_mac_number bdk_slix_mac_number_t;
5761
5762 static inline uint64_t BDK_SLIX_MAC_NUMBER(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SLIX_MAC_NUMBER(unsigned long a)5763 static inline uint64_t BDK_SLIX_MAC_NUMBER(unsigned long a)
5764 {
5765 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
5766 return 0x80ll + 0x10000000000ll * ((a) & 0x0);
5767 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
5768 return 0x80ll + 0x10000000000ll * ((a) & 0x1);
5769 __bdk_csr_fatal("SLIX_MAC_NUMBER", 1, a, 0, 0, 0);
5770 }
5771
5772 #define typedef_BDK_SLIX_MAC_NUMBER(a) bdk_slix_mac_number_t
5773 #define bustype_BDK_SLIX_MAC_NUMBER(a) BDK_CSR_TYPE_PEXP
5774 #define basename_BDK_SLIX_MAC_NUMBER(a) "SLIX_MAC_NUMBER"
5775 #define busnum_BDK_SLIX_MAC_NUMBER(a) (a)
5776 #define arguments_BDK_SLIX_MAC_NUMBER(a) (a),-1,-1,-1
5777
5778 /**
5779 * Register (PEXP) sli#_mac_number#
5780 *
5781 * SLI MAC Number Register
5782 * When read from a MAC, this register returns the MAC's port number; otherwise returns zero.
5783 */
5784 union bdk_slix_mac_numberx
5785 {
5786 uint64_t u;
5787 struct bdk_slix_mac_numberx_s
5788 {
5789 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5790 uint64_t reserved_32_63 : 32;
5791 uint64_t chip_rev : 8; /**< [ 31: 24](RO/H) Chip revision. See MIO_FUS_DAT2[CHIP_ID]. */
5792 uint64_t reserved_20_23 : 4;
5793 uint64_t oci_id : 4; /**< [ 19: 16](RO/H) The CCPI node ID. */
5794 uint64_t reserved_9_15 : 7;
5795 uint64_t a_mode : 1; /**< [ 8: 8](RO/H) Trusted mode. See RST_BOOT[TRUSTED_MODE]. */
5796 uint64_t num : 8; /**< [ 7: 0](RO/H) MAC number. */
5797 #else /* Word 0 - Little Endian */
5798 uint64_t num : 8; /**< [ 7: 0](RO/H) MAC number. */
5799 uint64_t a_mode : 1; /**< [ 8: 8](RO/H) Trusted mode. See RST_BOOT[TRUSTED_MODE]. */
5800 uint64_t reserved_9_15 : 7;
5801 uint64_t oci_id : 4; /**< [ 19: 16](RO/H) The CCPI node ID. */
5802 uint64_t reserved_20_23 : 4;
5803 uint64_t chip_rev : 8; /**< [ 31: 24](RO/H) Chip revision. See MIO_FUS_DAT2[CHIP_ID]. */
5804 uint64_t reserved_32_63 : 32;
5805 #endif /* Word 0 - End */
5806 } s;
5807 /* struct bdk_slix_mac_numberx_s cn; */
5808 };
5809 typedef union bdk_slix_mac_numberx bdk_slix_mac_numberx_t;
5810
5811 static inline uint64_t BDK_SLIX_MAC_NUMBERX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_MAC_NUMBERX(unsigned long a,unsigned long b)5812 static inline uint64_t BDK_SLIX_MAC_NUMBERX(unsigned long a, unsigned long b)
5813 {
5814 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=3)))
5815 return 0x2c050ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x3);
5816 __bdk_csr_fatal("SLIX_MAC_NUMBERX", 2, a, b, 0, 0);
5817 }
5818
5819 #define typedef_BDK_SLIX_MAC_NUMBERX(a,b) bdk_slix_mac_numberx_t
5820 #define bustype_BDK_SLIX_MAC_NUMBERX(a,b) BDK_CSR_TYPE_PEXP
5821 #define basename_BDK_SLIX_MAC_NUMBERX(a,b) "SLIX_MAC_NUMBERX"
5822 #define busnum_BDK_SLIX_MAC_NUMBERX(a,b) (a)
5823 #define arguments_BDK_SLIX_MAC_NUMBERX(a,b) (a),(b),-1,-1
5824
5825 /**
5826 * Register (NCB) sli#_mbe_int_ena_w1c
5827 *
5828 * SLI Interrupt Enable Clear Register
5829 * This register clears interrupt enable bits.
5830 */
5831 union bdk_slix_mbe_int_ena_w1c
5832 {
5833 uint64_t u;
5834 struct bdk_slix_mbe_int_ena_w1c_s
5835 {
5836 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5837 uint64_t reserved_0_63 : 64;
5838 #else /* Word 0 - Little Endian */
5839 uint64_t reserved_0_63 : 64;
5840 #endif /* Word 0 - End */
5841 } s;
5842 struct bdk_slix_mbe_int_ena_w1c_cn81xx
5843 {
5844 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5845 uint64_t reserved_54_63 : 10;
5846 uint64_t sed0_dbe : 22; /**< [ 53: 32](R/W1C/H) Reads or clears enable for SLI(0)_MBE_INT_SUM[SED0_DBE]. */
5847 uint64_t reserved_22_31 : 10;
5848 uint64_t sed0_sbe : 22; /**< [ 21: 0](R/W1C/H) Reads or clears enable for SLI(0)_MBE_INT_SUM[SED0_SBE]. */
5849 #else /* Word 0 - Little Endian */
5850 uint64_t sed0_sbe : 22; /**< [ 21: 0](R/W1C/H) Reads or clears enable for SLI(0)_MBE_INT_SUM[SED0_SBE]. */
5851 uint64_t reserved_22_31 : 10;
5852 uint64_t sed0_dbe : 22; /**< [ 53: 32](R/W1C/H) Reads or clears enable for SLI(0)_MBE_INT_SUM[SED0_DBE]. */
5853 uint64_t reserved_54_63 : 10;
5854 #endif /* Word 0 - End */
5855 } cn81xx;
5856 struct bdk_slix_mbe_int_ena_w1c_cn88xx
5857 {
5858 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5859 uint64_t reserved_54_63 : 10;
5860 uint64_t sed0_dbe : 22; /**< [ 53: 32](R/W1C/H) Reads or clears enable for SLI(0..1)_MBE_INT_SUM[SED0_DBE]. */
5861 uint64_t reserved_22_31 : 10;
5862 uint64_t sed0_sbe : 22; /**< [ 21: 0](R/W1C/H) Reads or clears enable for SLI(0..1)_MBE_INT_SUM[SED0_SBE]. */
5863 #else /* Word 0 - Little Endian */
5864 uint64_t sed0_sbe : 22; /**< [ 21: 0](R/W1C/H) Reads or clears enable for SLI(0..1)_MBE_INT_SUM[SED0_SBE]. */
5865 uint64_t reserved_22_31 : 10;
5866 uint64_t sed0_dbe : 22; /**< [ 53: 32](R/W1C/H) Reads or clears enable for SLI(0..1)_MBE_INT_SUM[SED0_DBE]. */
5867 uint64_t reserved_54_63 : 10;
5868 #endif /* Word 0 - End */
5869 } cn88xx;
5870 struct bdk_slix_mbe_int_ena_w1c_cn83xx
5871 {
5872 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5873 uint64_t dbe : 32; /**< [ 63: 32](R/W1C/H) Reads or clears enable for SLI(0)_MBE_INT_SUM[DBE]. */
5874 uint64_t sbe : 32; /**< [ 31: 0](R/W1C/H) Reads or clears enable for SLI(0)_MBE_INT_SUM[SBE]. */
5875 #else /* Word 0 - Little Endian */
5876 uint64_t sbe : 32; /**< [ 31: 0](R/W1C/H) Reads or clears enable for SLI(0)_MBE_INT_SUM[SBE]. */
5877 uint64_t dbe : 32; /**< [ 63: 32](R/W1C/H) Reads or clears enable for SLI(0)_MBE_INT_SUM[DBE]. */
5878 #endif /* Word 0 - End */
5879 } cn83xx;
5880 };
5881 typedef union bdk_slix_mbe_int_ena_w1c bdk_slix_mbe_int_ena_w1c_t;
5882
5883 static inline uint64_t BDK_SLIX_MBE_INT_ENA_W1C(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SLIX_MBE_INT_ENA_W1C(unsigned long a)5884 static inline uint64_t BDK_SLIX_MBE_INT_ENA_W1C(unsigned long a)
5885 {
5886 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
5887 return 0x874001002260ll + 0x1000000000ll * ((a) & 0x0);
5888 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a==0))
5889 return 0x874001002260ll + 0x1000000000ll * ((a) & 0x0);
5890 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
5891 return 0x874001002260ll + 0x1000000000ll * ((a) & 0x1);
5892 __bdk_csr_fatal("SLIX_MBE_INT_ENA_W1C", 1, a, 0, 0, 0);
5893 }
5894
5895 #define typedef_BDK_SLIX_MBE_INT_ENA_W1C(a) bdk_slix_mbe_int_ena_w1c_t
5896 #define bustype_BDK_SLIX_MBE_INT_ENA_W1C(a) BDK_CSR_TYPE_NCB
5897 #define basename_BDK_SLIX_MBE_INT_ENA_W1C(a) "SLIX_MBE_INT_ENA_W1C"
5898 #define device_bar_BDK_SLIX_MBE_INT_ENA_W1C(a) 0x0 /* PF_BAR0 */
5899 #define busnum_BDK_SLIX_MBE_INT_ENA_W1C(a) (a)
5900 #define arguments_BDK_SLIX_MBE_INT_ENA_W1C(a) (a),-1,-1,-1
5901
5902 /**
5903 * Register (NCB) sli#_mbe_int_ena_w1s
5904 *
5905 * SLI Interrupt Enable Set Register
5906 * This register sets interrupt enable bits.
5907 */
5908 union bdk_slix_mbe_int_ena_w1s
5909 {
5910 uint64_t u;
5911 struct bdk_slix_mbe_int_ena_w1s_s
5912 {
5913 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5914 uint64_t reserved_0_63 : 64;
5915 #else /* Word 0 - Little Endian */
5916 uint64_t reserved_0_63 : 64;
5917 #endif /* Word 0 - End */
5918 } s;
5919 struct bdk_slix_mbe_int_ena_w1s_cn81xx
5920 {
5921 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5922 uint64_t reserved_54_63 : 10;
5923 uint64_t sed0_dbe : 22; /**< [ 53: 32](R/W1S/H) Reads or sets enable for SLI(0)_MBE_INT_SUM[SED0_DBE]. */
5924 uint64_t reserved_22_31 : 10;
5925 uint64_t sed0_sbe : 22; /**< [ 21: 0](R/W1S/H) Reads or sets enable for SLI(0)_MBE_INT_SUM[SED0_SBE]. */
5926 #else /* Word 0 - Little Endian */
5927 uint64_t sed0_sbe : 22; /**< [ 21: 0](R/W1S/H) Reads or sets enable for SLI(0)_MBE_INT_SUM[SED0_SBE]. */
5928 uint64_t reserved_22_31 : 10;
5929 uint64_t sed0_dbe : 22; /**< [ 53: 32](R/W1S/H) Reads or sets enable for SLI(0)_MBE_INT_SUM[SED0_DBE]. */
5930 uint64_t reserved_54_63 : 10;
5931 #endif /* Word 0 - End */
5932 } cn81xx;
5933 struct bdk_slix_mbe_int_ena_w1s_cn88xx
5934 {
5935 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5936 uint64_t reserved_54_63 : 10;
5937 uint64_t sed0_dbe : 22; /**< [ 53: 32](R/W1S/H) Reads or sets enable for SLI(0..1)_MBE_INT_SUM[SED0_DBE]. */
5938 uint64_t reserved_22_31 : 10;
5939 uint64_t sed0_sbe : 22; /**< [ 21: 0](R/W1S/H) Reads or sets enable for SLI(0..1)_MBE_INT_SUM[SED0_SBE]. */
5940 #else /* Word 0 - Little Endian */
5941 uint64_t sed0_sbe : 22; /**< [ 21: 0](R/W1S/H) Reads or sets enable for SLI(0..1)_MBE_INT_SUM[SED0_SBE]. */
5942 uint64_t reserved_22_31 : 10;
5943 uint64_t sed0_dbe : 22; /**< [ 53: 32](R/W1S/H) Reads or sets enable for SLI(0..1)_MBE_INT_SUM[SED0_DBE]. */
5944 uint64_t reserved_54_63 : 10;
5945 #endif /* Word 0 - End */
5946 } cn88xx;
5947 struct bdk_slix_mbe_int_ena_w1s_cn83xx
5948 {
5949 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5950 uint64_t dbe : 32; /**< [ 63: 32](R/W1S/H) Reads or sets enable for SLI(0)_MBE_INT_SUM[DBE]. */
5951 uint64_t sbe : 32; /**< [ 31: 0](R/W1S/H) Reads or sets enable for SLI(0)_MBE_INT_SUM[SBE]. */
5952 #else /* Word 0 - Little Endian */
5953 uint64_t sbe : 32; /**< [ 31: 0](R/W1S/H) Reads or sets enable for SLI(0)_MBE_INT_SUM[SBE]. */
5954 uint64_t dbe : 32; /**< [ 63: 32](R/W1S/H) Reads or sets enable for SLI(0)_MBE_INT_SUM[DBE]. */
5955 #endif /* Word 0 - End */
5956 } cn83xx;
5957 };
5958 typedef union bdk_slix_mbe_int_ena_w1s bdk_slix_mbe_int_ena_w1s_t;
5959
5960 static inline uint64_t BDK_SLIX_MBE_INT_ENA_W1S(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SLIX_MBE_INT_ENA_W1S(unsigned long a)5961 static inline uint64_t BDK_SLIX_MBE_INT_ENA_W1S(unsigned long a)
5962 {
5963 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
5964 return 0x874001002280ll + 0x1000000000ll * ((a) & 0x0);
5965 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a==0))
5966 return 0x874001002280ll + 0x1000000000ll * ((a) & 0x0);
5967 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
5968 return 0x874001002280ll + 0x1000000000ll * ((a) & 0x1);
5969 __bdk_csr_fatal("SLIX_MBE_INT_ENA_W1S", 1, a, 0, 0, 0);
5970 }
5971
5972 #define typedef_BDK_SLIX_MBE_INT_ENA_W1S(a) bdk_slix_mbe_int_ena_w1s_t
5973 #define bustype_BDK_SLIX_MBE_INT_ENA_W1S(a) BDK_CSR_TYPE_NCB
5974 #define basename_BDK_SLIX_MBE_INT_ENA_W1S(a) "SLIX_MBE_INT_ENA_W1S"
5975 #define device_bar_BDK_SLIX_MBE_INT_ENA_W1S(a) 0x0 /* PF_BAR0 */
5976 #define busnum_BDK_SLIX_MBE_INT_ENA_W1S(a) (a)
5977 #define arguments_BDK_SLIX_MBE_INT_ENA_W1S(a) (a),-1,-1,-1
5978
5979 /**
5980 * Register (NCB) sli#_mbe_int_sum
5981 *
5982 * SLI MBE Interrupt Summary Register
5983 * This register contains the MBE interrupt-summary bits of the SLI.
5984 */
5985 union bdk_slix_mbe_int_sum
5986 {
5987 uint64_t u;
5988 struct bdk_slix_mbe_int_sum_s
5989 {
5990 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5991 uint64_t reserved_0_63 : 64;
5992 #else /* Word 0 - Little Endian */
5993 uint64_t reserved_0_63 : 64;
5994 #endif /* Word 0 - End */
5995 } s;
5996 struct bdk_slix_mbe_int_sum_cn81xx
5997 {
5998 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5999 uint64_t reserved_54_63 : 10;
6000 uint64_t sed0_dbe : 22; /**< [ 53: 32](R/W1C/H) SED0 double-bit error. When set, a SED0 double-bit error has occurred. */
6001 uint64_t reserved_22_31 : 10;
6002 uint64_t sed0_sbe : 22; /**< [ 21: 0](R/W1C/H) SED0 single-bit error. When set, a SED0 single-bit error has occurred. */
6003 #else /* Word 0 - Little Endian */
6004 uint64_t sed0_sbe : 22; /**< [ 21: 0](R/W1C/H) SED0 single-bit error. When set, a SED0 single-bit error has occurred. */
6005 uint64_t reserved_22_31 : 10;
6006 uint64_t sed0_dbe : 22; /**< [ 53: 32](R/W1C/H) SED0 double-bit error. When set, a SED0 double-bit error has occurred. */
6007 uint64_t reserved_54_63 : 10;
6008 #endif /* Word 0 - End */
6009 } cn81xx;
6010 /* struct bdk_slix_mbe_int_sum_cn81xx cn88xx; */
6011 struct bdk_slix_mbe_int_sum_cn83xx
6012 {
6013 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6014 uint64_t dbe : 32; /**< [ 63: 32](R/W1C/H) Double-bit error detected in internal RAM. One bit per memory, enumerated by
6015 SLI_RAMS_E. */
6016 uint64_t sbe : 32; /**< [ 31: 0](R/W1C/H) Single-bit error detected in internal RAM. One bit per memory, enumerated by
6017 SLI_RAMS_E. */
6018 #else /* Word 0 - Little Endian */
6019 uint64_t sbe : 32; /**< [ 31: 0](R/W1C/H) Single-bit error detected in internal RAM. One bit per memory, enumerated by
6020 SLI_RAMS_E. */
6021 uint64_t dbe : 32; /**< [ 63: 32](R/W1C/H) Double-bit error detected in internal RAM. One bit per memory, enumerated by
6022 SLI_RAMS_E. */
6023 #endif /* Word 0 - End */
6024 } cn83xx;
6025 };
6026 typedef union bdk_slix_mbe_int_sum bdk_slix_mbe_int_sum_t;
6027
6028 static inline uint64_t BDK_SLIX_MBE_INT_SUM(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SLIX_MBE_INT_SUM(unsigned long a)6029 static inline uint64_t BDK_SLIX_MBE_INT_SUM(unsigned long a)
6030 {
6031 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
6032 return 0x874001002220ll + 0x1000000000ll * ((a) & 0x0);
6033 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a==0))
6034 return 0x874001002220ll + 0x1000000000ll * ((a) & 0x0);
6035 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
6036 return 0x874001002220ll + 0x1000000000ll * ((a) & 0x1);
6037 __bdk_csr_fatal("SLIX_MBE_INT_SUM", 1, a, 0, 0, 0);
6038 }
6039
6040 #define typedef_BDK_SLIX_MBE_INT_SUM(a) bdk_slix_mbe_int_sum_t
6041 #define bustype_BDK_SLIX_MBE_INT_SUM(a) BDK_CSR_TYPE_NCB
6042 #define basename_BDK_SLIX_MBE_INT_SUM(a) "SLIX_MBE_INT_SUM"
6043 #define device_bar_BDK_SLIX_MBE_INT_SUM(a) 0x0 /* PF_BAR0 */
6044 #define busnum_BDK_SLIX_MBE_INT_SUM(a) (a)
6045 #define arguments_BDK_SLIX_MBE_INT_SUM(a) (a),-1,-1,-1
6046
6047 /**
6048 * Register (NCB) sli#_mbe_int_sum_w1s
6049 *
6050 * SLI Interrupt Set Register
6051 * This register sets interrupt bits.
6052 */
6053 union bdk_slix_mbe_int_sum_w1s
6054 {
6055 uint64_t u;
6056 struct bdk_slix_mbe_int_sum_w1s_s
6057 {
6058 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6059 uint64_t reserved_0_63 : 64;
6060 #else /* Word 0 - Little Endian */
6061 uint64_t reserved_0_63 : 64;
6062 #endif /* Word 0 - End */
6063 } s;
6064 struct bdk_slix_mbe_int_sum_w1s_cn81xx
6065 {
6066 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6067 uint64_t reserved_54_63 : 10;
6068 uint64_t sed0_dbe : 22; /**< [ 53: 32](R/W1S/H) Reads or sets SLI(0)_MBE_INT_SUM[SED0_DBE]. */
6069 uint64_t reserved_22_31 : 10;
6070 uint64_t sed0_sbe : 22; /**< [ 21: 0](R/W1S/H) Reads or sets SLI(0)_MBE_INT_SUM[SED0_SBE]. */
6071 #else /* Word 0 - Little Endian */
6072 uint64_t sed0_sbe : 22; /**< [ 21: 0](R/W1S/H) Reads or sets SLI(0)_MBE_INT_SUM[SED0_SBE]. */
6073 uint64_t reserved_22_31 : 10;
6074 uint64_t sed0_dbe : 22; /**< [ 53: 32](R/W1S/H) Reads or sets SLI(0)_MBE_INT_SUM[SED0_DBE]. */
6075 uint64_t reserved_54_63 : 10;
6076 #endif /* Word 0 - End */
6077 } cn81xx;
6078 struct bdk_slix_mbe_int_sum_w1s_cn88xx
6079 {
6080 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6081 uint64_t reserved_54_63 : 10;
6082 uint64_t sed0_dbe : 22; /**< [ 53: 32](R/W1S/H) Reads or sets SLI(0..1)_MBE_INT_SUM[SED0_DBE]. */
6083 uint64_t reserved_22_31 : 10;
6084 uint64_t sed0_sbe : 22; /**< [ 21: 0](R/W1S/H) Reads or sets SLI(0..1)_MBE_INT_SUM[SED0_SBE]. */
6085 #else /* Word 0 - Little Endian */
6086 uint64_t sed0_sbe : 22; /**< [ 21: 0](R/W1S/H) Reads or sets SLI(0..1)_MBE_INT_SUM[SED0_SBE]. */
6087 uint64_t reserved_22_31 : 10;
6088 uint64_t sed0_dbe : 22; /**< [ 53: 32](R/W1S/H) Reads or sets SLI(0..1)_MBE_INT_SUM[SED0_DBE]. */
6089 uint64_t reserved_54_63 : 10;
6090 #endif /* Word 0 - End */
6091 } cn88xx;
6092 struct bdk_slix_mbe_int_sum_w1s_cn83xx
6093 {
6094 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6095 uint64_t dbe : 32; /**< [ 63: 32](R/W1S/H) Reads or sets SLI(0)_MBE_INT_SUM[DBE]. */
6096 uint64_t sbe : 32; /**< [ 31: 0](R/W1S/H) Reads or sets SLI(0)_MBE_INT_SUM[SBE]. */
6097 #else /* Word 0 - Little Endian */
6098 uint64_t sbe : 32; /**< [ 31: 0](R/W1S/H) Reads or sets SLI(0)_MBE_INT_SUM[SBE]. */
6099 uint64_t dbe : 32; /**< [ 63: 32](R/W1S/H) Reads or sets SLI(0)_MBE_INT_SUM[DBE]. */
6100 #endif /* Word 0 - End */
6101 } cn83xx;
6102 };
6103 typedef union bdk_slix_mbe_int_sum_w1s bdk_slix_mbe_int_sum_w1s_t;
6104
6105 static inline uint64_t BDK_SLIX_MBE_INT_SUM_W1S(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SLIX_MBE_INT_SUM_W1S(unsigned long a)6106 static inline uint64_t BDK_SLIX_MBE_INT_SUM_W1S(unsigned long a)
6107 {
6108 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
6109 return 0x874001002240ll + 0x1000000000ll * ((a) & 0x0);
6110 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a==0))
6111 return 0x874001002240ll + 0x1000000000ll * ((a) & 0x0);
6112 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
6113 return 0x874001002240ll + 0x1000000000ll * ((a) & 0x1);
6114 __bdk_csr_fatal("SLIX_MBE_INT_SUM_W1S", 1, a, 0, 0, 0);
6115 }
6116
6117 #define typedef_BDK_SLIX_MBE_INT_SUM_W1S(a) bdk_slix_mbe_int_sum_w1s_t
6118 #define bustype_BDK_SLIX_MBE_INT_SUM_W1S(a) BDK_CSR_TYPE_NCB
6119 #define basename_BDK_SLIX_MBE_INT_SUM_W1S(a) "SLIX_MBE_INT_SUM_W1S"
6120 #define device_bar_BDK_SLIX_MBE_INT_SUM_W1S(a) 0x0 /* PF_BAR0 */
6121 #define busnum_BDK_SLIX_MBE_INT_SUM_W1S(a) (a)
6122 #define arguments_BDK_SLIX_MBE_INT_SUM_W1S(a) (a),-1,-1,-1
6123
6124 /**
6125 * Register (NCB) sli#_mem_ctl
6126 *
6127 * SLI Memory Control Register
6128 * This register controls the ECC of the SLI memories.
6129 */
6130 union bdk_slix_mem_ctl
6131 {
6132 uint64_t u;
6133 struct bdk_slix_mem_ctl_s
6134 {
6135 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6136 uint64_t reserved_0_63 : 64;
6137 #else /* Word 0 - Little Endian */
6138 uint64_t reserved_0_63 : 64;
6139 #endif /* Word 0 - End */
6140 } s;
6141 struct bdk_slix_mem_ctl_cn81xx
6142 {
6143 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6144 uint64_t reserved_30_63 : 34;
6145 uint64_t ctl : 30; /**< [ 29: 0](R/W) Control memory ECC functionality.
6146 \<29\> = Correction disable for csr_region_mem_csr_cor_dis.
6147 \<28:29\> = Flip syndrome for csr_region_mem_csr_flip_synd.
6148
6149 \<26\> = Correction disable for sndf\<h,l\>2_ffifo, sncf2_ffifo_csr_cor_dis.
6150 \<25:24\> = Flip syndrome for sndf\<h,l\>2_ffifo, sncf2_ffifo_csr_flip_synd.
6151 \<23\> = Correction disable for sndf\<h,l\>2_ffifo, sncf2_ffifo_csr_cor_dis.
6152 \<22:21\> = Flip syndrome for sndf\<h,l\>2_ffifo, sncf2_ffifo_csr_flip_synd.
6153 \<20\> = Correction disable for sndf\<h,l\>2_ffifo, sncf2_ffifo_csr_cor_dis.
6154 \<19:18\> = Flip syndrome for sndf\<h,l\>2_ffifo, sncf2_ffifo_csr_flip_synd.
6155
6156 \<17\> = Correction disable for cpl0_fifo_csr_cor_dis.
6157 \<16:15\> = Flip syndrome for cpl0_fifo_csr_flip_synd.
6158 \<14\> = Correction disable for cpl1_fifo_csr_cor_dis.
6159 \<13:12\> = Flip syndrome for cpl1_fifo_csr_flip_synd.
6160 \<11\> = Correction disable for cpl2_fifo_csr_cor_dis.
6161 \<10:9\> = Flip syndrome for cpl2_fifo_csr_flip_synd.
6162
6163 \<8\> = Correction disable for p2n0_tlp_\<p, n, cpl\>_fifo.
6164 \<7:6\> = Flip syndrome for p2n0_tlp_\<p,n,cpl\>_fifo.
6165 \<5\> = Correction disable for p2n1_tlp_\<p, n, cpl\>_fifo.
6166 \<4:3\> = Flip syndrome for p2n1_tlp_\<p,n,cpl\>_fifo.
6167 \<2\> = Correction disable for p2n2_tlp_\<p, n, cpl\>_fifo.
6168 \<1:0\> = Flip syndrome for p2n2_tlp_\<p,n,cpl\>_fifo. */
6169 #else /* Word 0 - Little Endian */
6170 uint64_t ctl : 30; /**< [ 29: 0](R/W) Control memory ECC functionality.
6171 \<29\> = Correction disable for csr_region_mem_csr_cor_dis.
6172 \<28:29\> = Flip syndrome for csr_region_mem_csr_flip_synd.
6173
6174 \<26\> = Correction disable for sndf\<h,l\>2_ffifo, sncf2_ffifo_csr_cor_dis.
6175 \<25:24\> = Flip syndrome for sndf\<h,l\>2_ffifo, sncf2_ffifo_csr_flip_synd.
6176 \<23\> = Correction disable for sndf\<h,l\>2_ffifo, sncf2_ffifo_csr_cor_dis.
6177 \<22:21\> = Flip syndrome for sndf\<h,l\>2_ffifo, sncf2_ffifo_csr_flip_synd.
6178 \<20\> = Correction disable for sndf\<h,l\>2_ffifo, sncf2_ffifo_csr_cor_dis.
6179 \<19:18\> = Flip syndrome for sndf\<h,l\>2_ffifo, sncf2_ffifo_csr_flip_synd.
6180
6181 \<17\> = Correction disable for cpl0_fifo_csr_cor_dis.
6182 \<16:15\> = Flip syndrome for cpl0_fifo_csr_flip_synd.
6183 \<14\> = Correction disable for cpl1_fifo_csr_cor_dis.
6184 \<13:12\> = Flip syndrome for cpl1_fifo_csr_flip_synd.
6185 \<11\> = Correction disable for cpl2_fifo_csr_cor_dis.
6186 \<10:9\> = Flip syndrome for cpl2_fifo_csr_flip_synd.
6187
6188 \<8\> = Correction disable for p2n0_tlp_\<p, n, cpl\>_fifo.
6189 \<7:6\> = Flip syndrome for p2n0_tlp_\<p,n,cpl\>_fifo.
6190 \<5\> = Correction disable for p2n1_tlp_\<p, n, cpl\>_fifo.
6191 \<4:3\> = Flip syndrome for p2n1_tlp_\<p,n,cpl\>_fifo.
6192 \<2\> = Correction disable for p2n2_tlp_\<p, n, cpl\>_fifo.
6193 \<1:0\> = Flip syndrome for p2n2_tlp_\<p,n,cpl\>_fifo. */
6194 uint64_t reserved_30_63 : 34;
6195 #endif /* Word 0 - End */
6196 } cn81xx;
6197 struct bdk_slix_mem_ctl_cn88xx
6198 {
6199 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6200 uint64_t reserved_30_63 : 34;
6201 uint64_t ctl : 30; /**< [ 29: 0](R/W) Control memory ECC functionality.
6202 \<29\> = Correction Disable for csr_region_mem_csr_cor_dis.
6203 \<28:29\> = Flip Syndrome for csr_region_mem_csr_flip_synd.
6204
6205 \<26\> = Correction Disable for sndf\<h,l\>2_ffifo, sncf2_ffifo_csr_cor_dis.
6206 \<25:24\> = Flip Syndrome for sndf\<h,l\>2_ffifo, sncf2_ffifo_csr_flip_synd.
6207 \<23\> = Correction Disable for sndf\<h,l\>2_ffifo, sncf2_ffifo_csr_cor_dis.
6208 \<22:21\> = Flip Syndrome for sndf\<h,l\>2_ffifo, sncf2_ffifo_csr_flip_synd.
6209 \<20\> = Correction Disable for sndf\<h,l\>2_ffifo, sncf2_ffifo_csr_cor_dis.
6210 \<19:18\> = Flip Syndrome for sndf\<h,l\>2_ffifo, sncf2_ffifo_csr_flip_synd.
6211
6212 \<17\> = Correction Disable for cpl0_fifo_csr_cor_dis.
6213 \<16:15\> = Flip Syndrome for cpl0_fifo_csr_flip_synd.
6214 \<14\> = Correction Disable for cpl1_fifo_csr_cor_dis.
6215 \<13:12\> = Flip Syndrome for cpl1_fifo_csr_flip_synd.
6216 \<11\> = Correction Disable for cpl2_fifo_csr_cor_dis.
6217 \<10:9\> = Flip Syndrome for cpl2_fifo_csr_flip_synd.
6218
6219 \<8\> = Correction Disable for p2n0_tlp_\<p, n, cpl\>_fifo.
6220 \<7:6\> = Flip Syndrome for p2n0_tlp_\<p,n,cpl\>_fifo.
6221 \<5\> = Correction Disable for p2n1_tlp_\<p, n, cpl\>_fifo.
6222 \<4:3\> = Flip Syndrome for p2n1_tlp_\<p,n,cpl\>_fifo.
6223 \<2\> = Correction Disable for p2n2_tlp_\<p, n, cpl\>_fifo.
6224 \<1:0\> = Flip Syndrome for p2n2_tlp_\<p,n,cpl\>_fifo. */
6225 #else /* Word 0 - Little Endian */
6226 uint64_t ctl : 30; /**< [ 29: 0](R/W) Control memory ECC functionality.
6227 \<29\> = Correction Disable for csr_region_mem_csr_cor_dis.
6228 \<28:29\> = Flip Syndrome for csr_region_mem_csr_flip_synd.
6229
6230 \<26\> = Correction Disable for sndf\<h,l\>2_ffifo, sncf2_ffifo_csr_cor_dis.
6231 \<25:24\> = Flip Syndrome for sndf\<h,l\>2_ffifo, sncf2_ffifo_csr_flip_synd.
6232 \<23\> = Correction Disable for sndf\<h,l\>2_ffifo, sncf2_ffifo_csr_cor_dis.
6233 \<22:21\> = Flip Syndrome for sndf\<h,l\>2_ffifo, sncf2_ffifo_csr_flip_synd.
6234 \<20\> = Correction Disable for sndf\<h,l\>2_ffifo, sncf2_ffifo_csr_cor_dis.
6235 \<19:18\> = Flip Syndrome for sndf\<h,l\>2_ffifo, sncf2_ffifo_csr_flip_synd.
6236
6237 \<17\> = Correction Disable for cpl0_fifo_csr_cor_dis.
6238 \<16:15\> = Flip Syndrome for cpl0_fifo_csr_flip_synd.
6239 \<14\> = Correction Disable for cpl1_fifo_csr_cor_dis.
6240 \<13:12\> = Flip Syndrome for cpl1_fifo_csr_flip_synd.
6241 \<11\> = Correction Disable for cpl2_fifo_csr_cor_dis.
6242 \<10:9\> = Flip Syndrome for cpl2_fifo_csr_flip_synd.
6243
6244 \<8\> = Correction Disable for p2n0_tlp_\<p, n, cpl\>_fifo.
6245 \<7:6\> = Flip Syndrome for p2n0_tlp_\<p,n,cpl\>_fifo.
6246 \<5\> = Correction Disable for p2n1_tlp_\<p, n, cpl\>_fifo.
6247 \<4:3\> = Flip Syndrome for p2n1_tlp_\<p,n,cpl\>_fifo.
6248 \<2\> = Correction Disable for p2n2_tlp_\<p, n, cpl\>_fifo.
6249 \<1:0\> = Flip Syndrome for p2n2_tlp_\<p,n,cpl\>_fifo. */
6250 uint64_t reserved_30_63 : 34;
6251 #endif /* Word 0 - End */
6252 } cn88xx;
6253 struct bdk_slix_mem_ctl_cn83xx
6254 {
6255 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6256 uint64_t reserved_32_63 : 32;
6257 uint64_t cdis : 32; /**< [ 31: 0](R/W) Disables ECC correction on each RAM. Bit positions enumerated with SLI_RAMS_E. */
6258 #else /* Word 0 - Little Endian */
6259 uint64_t cdis : 32; /**< [ 31: 0](R/W) Disables ECC correction on each RAM. Bit positions enumerated with SLI_RAMS_E. */
6260 uint64_t reserved_32_63 : 32;
6261 #endif /* Word 0 - End */
6262 } cn83xx;
6263 };
6264 typedef union bdk_slix_mem_ctl bdk_slix_mem_ctl_t;
6265
6266 static inline uint64_t BDK_SLIX_MEM_CTL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SLIX_MEM_CTL(unsigned long a)6267 static inline uint64_t BDK_SLIX_MEM_CTL(unsigned long a)
6268 {
6269 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
6270 return 0x874001002200ll + 0x1000000000ll * ((a) & 0x0);
6271 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a==0))
6272 return 0x874001002200ll + 0x1000000000ll * ((a) & 0x0);
6273 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
6274 return 0x874001002200ll + 0x1000000000ll * ((a) & 0x1);
6275 __bdk_csr_fatal("SLIX_MEM_CTL", 1, a, 0, 0, 0);
6276 }
6277
6278 #define typedef_BDK_SLIX_MEM_CTL(a) bdk_slix_mem_ctl_t
6279 #define bustype_BDK_SLIX_MEM_CTL(a) BDK_CSR_TYPE_NCB
6280 #define basename_BDK_SLIX_MEM_CTL(a) "SLIX_MEM_CTL"
6281 #define device_bar_BDK_SLIX_MEM_CTL(a) 0x0 /* PF_BAR0 */
6282 #define busnum_BDK_SLIX_MEM_CTL(a) (a)
6283 #define arguments_BDK_SLIX_MEM_CTL(a) (a),-1,-1,-1
6284
6285 /**
6286 * Register (NCB) sli#_mem_flip
6287 *
6288 * SLI ECC Control Register
6289 * This register controls the ECC of the SLI memories.
6290 */
6291 union bdk_slix_mem_flip
6292 {
6293 uint64_t u;
6294 struct bdk_slix_mem_flip_s
6295 {
6296 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6297 uint64_t flip1 : 32; /**< [ 63: 32](R/W) Flips syndrome bit 1 on writes. Bit positions enumerated with SLI_RAMS_E. */
6298 uint64_t flip0 : 32; /**< [ 31: 0](R/W) Flips syndrome bit 0 on writes. Bit positions enumerated with SLI_RAMS_E. */
6299 #else /* Word 0 - Little Endian */
6300 uint64_t flip0 : 32; /**< [ 31: 0](R/W) Flips syndrome bit 0 on writes. Bit positions enumerated with SLI_RAMS_E. */
6301 uint64_t flip1 : 32; /**< [ 63: 32](R/W) Flips syndrome bit 1 on writes. Bit positions enumerated with SLI_RAMS_E. */
6302 #endif /* Word 0 - End */
6303 } s;
6304 /* struct bdk_slix_mem_flip_s cn; */
6305 };
6306 typedef union bdk_slix_mem_flip bdk_slix_mem_flip_t;
6307
6308 static inline uint64_t BDK_SLIX_MEM_FLIP(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SLIX_MEM_FLIP(unsigned long a)6309 static inline uint64_t BDK_SLIX_MEM_FLIP(unsigned long a)
6310 {
6311 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a==0))
6312 return 0x874001002210ll + 0x1000000000ll * ((a) & 0x0);
6313 __bdk_csr_fatal("SLIX_MEM_FLIP", 1, a, 0, 0, 0);
6314 }
6315
6316 #define typedef_BDK_SLIX_MEM_FLIP(a) bdk_slix_mem_flip_t
6317 #define bustype_BDK_SLIX_MEM_FLIP(a) BDK_CSR_TYPE_NCB
6318 #define basename_BDK_SLIX_MEM_FLIP(a) "SLIX_MEM_FLIP"
6319 #define device_bar_BDK_SLIX_MEM_FLIP(a) 0x0 /* PF_BAR0 */
6320 #define busnum_BDK_SLIX_MEM_FLIP(a) (a)
6321 #define arguments_BDK_SLIX_MEM_FLIP(a) (a),-1,-1,-1
6322
6323 /**
6324 * Register (NCB) sli#_msix_pba#
6325 *
6326 * SLI MSI-X Pending Bit Array Registers
6327 * This register is the MSI-X PBA table; the bit number is indexed by the SLI_INT_VEC_E enumeration.
6328 */
6329 union bdk_slix_msix_pbax
6330 {
6331 uint64_t u;
6332 struct bdk_slix_msix_pbax_s
6333 {
6334 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6335 uint64_t pend : 64; /**< [ 63: 0](RO/H) Pending message for the associated SLI_MSIX_VEC()_CTL, enumerated by SLI_INT_VEC_E. Bits
6336 that have no associated SLI_INT_VEC_E are 0. */
6337 #else /* Word 0 - Little Endian */
6338 uint64_t pend : 64; /**< [ 63: 0](RO/H) Pending message for the associated SLI_MSIX_VEC()_CTL, enumerated by SLI_INT_VEC_E. Bits
6339 that have no associated SLI_INT_VEC_E are 0. */
6340 #endif /* Word 0 - End */
6341 } s;
6342 /* struct bdk_slix_msix_pbax_s cn; */
6343 };
6344 typedef union bdk_slix_msix_pbax bdk_slix_msix_pbax_t;
6345
6346 static inline uint64_t BDK_SLIX_MSIX_PBAX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_MSIX_PBAX(unsigned long a,unsigned long b)6347 static inline uint64_t BDK_SLIX_MSIX_PBAX(unsigned long a, unsigned long b)
6348 {
6349 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b==0)))
6350 return 0x8740100f0000ll + 0x1000000000ll * ((a) & 0x0) + 8ll * ((b) & 0x0);
6351 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b==0)))
6352 return 0x874c000f0000ll + 0x1000000000ll * ((a) & 0x0) + 8ll * ((b) & 0x0);
6353 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b==0)))
6354 return 0x8740100f0000ll + 0x1000000000ll * ((a) & 0x1) + 8ll * ((b) & 0x0);
6355 __bdk_csr_fatal("SLIX_MSIX_PBAX", 2, a, b, 0, 0);
6356 }
6357
6358 #define typedef_BDK_SLIX_MSIX_PBAX(a,b) bdk_slix_msix_pbax_t
6359 #define bustype_BDK_SLIX_MSIX_PBAX(a,b) BDK_CSR_TYPE_NCB
6360 #define basename_BDK_SLIX_MSIX_PBAX(a,b) "SLIX_MSIX_PBAX"
6361 #define device_bar_BDK_SLIX_MSIX_PBAX(a,b) 0x4 /* PF_BAR4 */
6362 #define busnum_BDK_SLIX_MSIX_PBAX(a,b) (a)
6363 #define arguments_BDK_SLIX_MSIX_PBAX(a,b) (a),(b),-1,-1
6364
6365 /**
6366 * Register (NCB) sli#_msix_vec#_addr
6367 *
6368 * SLI MSI-X Vector-Table Address Register
6369 * This register is the MSI-X vector table, indexed by the SLI_INT_VEC_E enumeration.
6370 */
6371 union bdk_slix_msix_vecx_addr
6372 {
6373 uint64_t u;
6374 struct bdk_slix_msix_vecx_addr_s
6375 {
6376 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6377 uint64_t reserved_49_63 : 15;
6378 uint64_t addr : 47; /**< [ 48: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
6379 uint64_t reserved_1 : 1;
6380 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
6381 0 = This vector may be read or written by either secure or nonsecure states.
6382 1 = This vector's SLI_MSIX_VEC()_ADDR, SLI_MSIX_VEC()_CTL, and corresponding
6383 bit of SLI_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
6384 by the nonsecure world.
6385
6386 If PCCPF_SLI_VSEC_SCTL[MSIX_SEC] (for documentation, see PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is
6387 set, all vectors are secure and function as if [SECVEC] was set. */
6388 #else /* Word 0 - Little Endian */
6389 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
6390 0 = This vector may be read or written by either secure or nonsecure states.
6391 1 = This vector's SLI_MSIX_VEC()_ADDR, SLI_MSIX_VEC()_CTL, and corresponding
6392 bit of SLI_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
6393 by the nonsecure world.
6394
6395 If PCCPF_SLI_VSEC_SCTL[MSIX_SEC] (for documentation, see PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is
6396 set, all vectors are secure and function as if [SECVEC] was set. */
6397 uint64_t reserved_1 : 1;
6398 uint64_t addr : 47; /**< [ 48: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
6399 uint64_t reserved_49_63 : 15;
6400 #endif /* Word 0 - End */
6401 } s;
6402 /* struct bdk_slix_msix_vecx_addr_s cn; */
6403 };
6404 typedef union bdk_slix_msix_vecx_addr bdk_slix_msix_vecx_addr_t;
6405
6406 static inline uint64_t BDK_SLIX_MSIX_VECX_ADDR(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_MSIX_VECX_ADDR(unsigned long a,unsigned long b)6407 static inline uint64_t BDK_SLIX_MSIX_VECX_ADDR(unsigned long a, unsigned long b)
6408 {
6409 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b<=3)))
6410 return 0x874010000000ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x3);
6411 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=16)))
6412 return 0x874c00000000ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x1f);
6413 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
6414 return 0x874010000000ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x3);
6415 __bdk_csr_fatal("SLIX_MSIX_VECX_ADDR", 2, a, b, 0, 0);
6416 }
6417
6418 #define typedef_BDK_SLIX_MSIX_VECX_ADDR(a,b) bdk_slix_msix_vecx_addr_t
6419 #define bustype_BDK_SLIX_MSIX_VECX_ADDR(a,b) BDK_CSR_TYPE_NCB
6420 #define basename_BDK_SLIX_MSIX_VECX_ADDR(a,b) "SLIX_MSIX_VECX_ADDR"
6421 #define device_bar_BDK_SLIX_MSIX_VECX_ADDR(a,b) 0x4 /* PF_BAR4 */
6422 #define busnum_BDK_SLIX_MSIX_VECX_ADDR(a,b) (a)
6423 #define arguments_BDK_SLIX_MSIX_VECX_ADDR(a,b) (a),(b),-1,-1
6424
6425 /**
6426 * Register (NCB) sli#_msix_vec#_ctl
6427 *
6428 * SLI MSI-X Vector-Table Control and Data Register
6429 * This register is the MSI-X vector table, indexed by the SLI_INT_VEC_E enumeration.
6430 */
6431 union bdk_slix_msix_vecx_ctl
6432 {
6433 uint64_t u;
6434 struct bdk_slix_msix_vecx_ctl_s
6435 {
6436 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6437 uint64_t reserved_33_63 : 31;
6438 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts are sent to this vector. */
6439 uint64_t reserved_20_31 : 12;
6440 uint64_t data : 20; /**< [ 19: 0](R/W) Data to use for MSI-X delivery of this vector. */
6441 #else /* Word 0 - Little Endian */
6442 uint64_t data : 20; /**< [ 19: 0](R/W) Data to use for MSI-X delivery of this vector. */
6443 uint64_t reserved_20_31 : 12;
6444 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts are sent to this vector. */
6445 uint64_t reserved_33_63 : 31;
6446 #endif /* Word 0 - End */
6447 } s;
6448 /* struct bdk_slix_msix_vecx_ctl_s cn; */
6449 };
6450 typedef union bdk_slix_msix_vecx_ctl bdk_slix_msix_vecx_ctl_t;
6451
6452 static inline uint64_t BDK_SLIX_MSIX_VECX_CTL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_MSIX_VECX_CTL(unsigned long a,unsigned long b)6453 static inline uint64_t BDK_SLIX_MSIX_VECX_CTL(unsigned long a, unsigned long b)
6454 {
6455 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b<=3)))
6456 return 0x874010000008ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x3);
6457 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=16)))
6458 return 0x874c00000008ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x1f);
6459 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
6460 return 0x874010000008ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x3);
6461 __bdk_csr_fatal("SLIX_MSIX_VECX_CTL", 2, a, b, 0, 0);
6462 }
6463
6464 #define typedef_BDK_SLIX_MSIX_VECX_CTL(a,b) bdk_slix_msix_vecx_ctl_t
6465 #define bustype_BDK_SLIX_MSIX_VECX_CTL(a,b) BDK_CSR_TYPE_NCB
6466 #define basename_BDK_SLIX_MSIX_VECX_CTL(a,b) "SLIX_MSIX_VECX_CTL"
6467 #define device_bar_BDK_SLIX_MSIX_VECX_CTL(a,b) 0x4 /* PF_BAR4 */
6468 #define busnum_BDK_SLIX_MSIX_VECX_CTL(a,b) (a)
6469 #define arguments_BDK_SLIX_MSIX_VECX_CTL(a,b) (a),(b),-1,-1
6470
6471 /**
6472 * Register (NCB) sli#_s2m_ctl
6473 *
6474 * SLI S2M Control Register
6475 * This register contains control functionality of the S2M attached to the SLI. This register
6476 * impacts all MACs attached to the S2M.
6477 */
6478 union bdk_slix_s2m_ctl
6479 {
6480 uint64_t u;
6481 struct bdk_slix_s2m_ctl_s
6482 {
6483 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6484 uint64_t reserved_15_63 : 49;
6485 uint64_t rd_flt : 1; /**< [ 14: 14](R/W) Read fault.
6486 0 = A PCIe non-config read which is terminated by PCIe with an error (UR, etc) will return
6487 to the NCB/cores all-ones and non-fault.
6488
6489 1 = A PCIe non-config read which is terminated by PCIe with an error (UR, etc) will return
6490 to the NCB/cores all-zeros and fault. In the case of a read by a core, this fault will
6491 cause an synchronous external abort in the core.
6492
6493 Config reads which are terminated by PCIe in with an error (UR, etc), or config reads when
6494 the PEM is disabled or link is down, will return to the NCB/cores all-ones and non-fault
6495 regardless of this bit. */
6496 uint64_t max_word : 4; /**< [ 13: 10](R/W) Maximum number of words. Specifies the maximum number of 8-byte words to merge into a
6497 single write operation from the cores to the MAC. Legal values are 1 to 8, with 0 treated
6498 as 16. */
6499 uint64_t timer : 10; /**< [ 9: 0](R/W) Merge timer. When the SLI starts a core-to-MAC write, TIMER specifies the maximum wait, in
6500 coprocessor-clock cycles, to merge additional write operations from the cores into one
6501 large write. The values for this field range from 1 to 1024, with 0 treated as 1024. */
6502 #else /* Word 0 - Little Endian */
6503 uint64_t timer : 10; /**< [ 9: 0](R/W) Merge timer. When the SLI starts a core-to-MAC write, TIMER specifies the maximum wait, in
6504 coprocessor-clock cycles, to merge additional write operations from the cores into one
6505 large write. The values for this field range from 1 to 1024, with 0 treated as 1024. */
6506 uint64_t max_word : 4; /**< [ 13: 10](R/W) Maximum number of words. Specifies the maximum number of 8-byte words to merge into a
6507 single write operation from the cores to the MAC. Legal values are 1 to 8, with 0 treated
6508 as 16. */
6509 uint64_t rd_flt : 1; /**< [ 14: 14](R/W) Read fault.
6510 0 = A PCIe non-config read which is terminated by PCIe with an error (UR, etc) will return
6511 to the NCB/cores all-ones and non-fault.
6512
6513 1 = A PCIe non-config read which is terminated by PCIe with an error (UR, etc) will return
6514 to the NCB/cores all-zeros and fault. In the case of a read by a core, this fault will
6515 cause an synchronous external abort in the core.
6516
6517 Config reads which are terminated by PCIe in with an error (UR, etc), or config reads when
6518 the PEM is disabled or link is down, will return to the NCB/cores all-ones and non-fault
6519 regardless of this bit. */
6520 uint64_t reserved_15_63 : 49;
6521 #endif /* Word 0 - End */
6522 } s;
6523 struct bdk_slix_s2m_ctl_cn88xxp1
6524 {
6525 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6526 uint64_t reserved_14_63 : 50;
6527 uint64_t max_word : 4; /**< [ 13: 10](R/W) Maximum number of words. Specifies the maximum number of 8-byte words to merge into a
6528 single write operation from the cores to the MAC. Legal values are 1 to 8, with 0 treated
6529 as 16. */
6530 uint64_t timer : 10; /**< [ 9: 0](R/W) Merge timer. When the SLI starts a core-to-MAC write, TIMER specifies the maximum wait, in
6531 coprocessor-clock cycles, to merge additional write operations from the cores into one
6532 large write. The values for this field range from 1 to 1024, with 0 treated as 1024. */
6533 #else /* Word 0 - Little Endian */
6534 uint64_t timer : 10; /**< [ 9: 0](R/W) Merge timer. When the SLI starts a core-to-MAC write, TIMER specifies the maximum wait, in
6535 coprocessor-clock cycles, to merge additional write operations from the cores into one
6536 large write. The values for this field range from 1 to 1024, with 0 treated as 1024. */
6537 uint64_t max_word : 4; /**< [ 13: 10](R/W) Maximum number of words. Specifies the maximum number of 8-byte words to merge into a
6538 single write operation from the cores to the MAC. Legal values are 1 to 8, with 0 treated
6539 as 16. */
6540 uint64_t reserved_14_63 : 50;
6541 #endif /* Word 0 - End */
6542 } cn88xxp1;
6543 /* struct bdk_slix_s2m_ctl_s cn81xx; */
6544 /* struct bdk_slix_s2m_ctl_s cn83xx; */
6545 struct bdk_slix_s2m_ctl_cn88xxp2
6546 {
6547 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6548 uint64_t reserved_15_63 : 49;
6549 uint64_t rd_flt : 1; /**< [ 14: 14](R/W) Read fault.
6550 0 = A PCIe non-config read which is terminated by PCIe with an error (UR, etc) will return
6551 to the NCB/cores all-ones and non-fault. This is compatible with CN88XX pass 1.0.
6552
6553 1 = A PCIe non-config read which is terminated by PCIe with an error (UR, etc) will return
6554 to the NCB/cores all-zeros and fault. In the case of a read by a core, this fault will
6555 cause an synchronous external abort in the core.
6556
6557 Config reads which are terminated by PCIe in with an error (UR, etc), or config reads when
6558 the PEM is disabled or link is down, will return to the NCB/cores all-ones and non-fault
6559 regardless of this bit. */
6560 uint64_t max_word : 4; /**< [ 13: 10](R/W) Maximum number of words. Specifies the maximum number of 8-byte words to merge into a
6561 single write operation from the cores to the MAC. Legal values are 1 to 8, with 0 treated
6562 as 16. */
6563 uint64_t timer : 10; /**< [ 9: 0](R/W) Merge timer. When the SLI starts a core-to-MAC write, TIMER specifies the maximum wait, in
6564 coprocessor-clock cycles, to merge additional write operations from the cores into one
6565 large write. The values for this field range from 1 to 1024, with 0 treated as 1024. */
6566 #else /* Word 0 - Little Endian */
6567 uint64_t timer : 10; /**< [ 9: 0](R/W) Merge timer. When the SLI starts a core-to-MAC write, TIMER specifies the maximum wait, in
6568 coprocessor-clock cycles, to merge additional write operations from the cores into one
6569 large write. The values for this field range from 1 to 1024, with 0 treated as 1024. */
6570 uint64_t max_word : 4; /**< [ 13: 10](R/W) Maximum number of words. Specifies the maximum number of 8-byte words to merge into a
6571 single write operation from the cores to the MAC. Legal values are 1 to 8, with 0 treated
6572 as 16. */
6573 uint64_t rd_flt : 1; /**< [ 14: 14](R/W) Read fault.
6574 0 = A PCIe non-config read which is terminated by PCIe with an error (UR, etc) will return
6575 to the NCB/cores all-ones and non-fault. This is compatible with CN88XX pass 1.0.
6576
6577 1 = A PCIe non-config read which is terminated by PCIe with an error (UR, etc) will return
6578 to the NCB/cores all-zeros and fault. In the case of a read by a core, this fault will
6579 cause an synchronous external abort in the core.
6580
6581 Config reads which are terminated by PCIe in with an error (UR, etc), or config reads when
6582 the PEM is disabled or link is down, will return to the NCB/cores all-ones and non-fault
6583 regardless of this bit. */
6584 uint64_t reserved_15_63 : 49;
6585 #endif /* Word 0 - End */
6586 } cn88xxp2;
6587 };
6588 typedef union bdk_slix_s2m_ctl bdk_slix_s2m_ctl_t;
6589
6590 static inline uint64_t BDK_SLIX_S2M_CTL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SLIX_S2M_CTL(unsigned long a)6591 static inline uint64_t BDK_SLIX_S2M_CTL(unsigned long a)
6592 {
6593 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
6594 return 0x874001002000ll + 0x1000000000ll * ((a) & 0x0);
6595 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a==0))
6596 return 0x874001002000ll + 0x1000000000ll * ((a) & 0x0);
6597 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
6598 return 0x874001002000ll + 0x1000000000ll * ((a) & 0x1);
6599 __bdk_csr_fatal("SLIX_S2M_CTL", 1, a, 0, 0, 0);
6600 }
6601
6602 #define typedef_BDK_SLIX_S2M_CTL(a) bdk_slix_s2m_ctl_t
6603 #define bustype_BDK_SLIX_S2M_CTL(a) BDK_CSR_TYPE_NCB
6604 #define basename_BDK_SLIX_S2M_CTL(a) "SLIX_S2M_CTL"
6605 #define device_bar_BDK_SLIX_S2M_CTL(a) 0x0 /* PF_BAR0 */
6606 #define busnum_BDK_SLIX_S2M_CTL(a) (a)
6607 #define arguments_BDK_SLIX_S2M_CTL(a) (a),-1,-1,-1
6608
6609 /**
6610 * Register (NCB) sli#_s2m_mac#_ctl
6611 *
6612 * SLI MAC Control Register
6613 * This register controls the functionality of the SLI's S2M in regards to a MAC.
6614 * Internal:
6615 * In 78xx was SLI()_CTL_STATUS and SLI()_MAC_CREDIT_CNT.
6616 */
6617 union bdk_slix_s2m_macx_ctl
6618 {
6619 uint64_t u;
6620 struct bdk_slix_s2m_macx_ctl_s
6621 {
6622 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6623 uint64_t reserved_32_63 : 32;
6624 uint64_t ccnt : 8; /**< [ 31: 24](R/W/H) CPL-TLP FIFO credits. Legal values are 0x25 to 0x80. For diagnostic use only. */
6625 uint64_t ncnt : 8; /**< [ 23: 16](R/W/H) NP-TLP FIFO credits. Legal values are 0x5 to 0x10. For diagnostic use only. */
6626 uint64_t pcnt : 8; /**< [ 15: 8](R/W/H) P-TLP FIFO credits. Legal values are 0x25 to 0x80. For diagnostic use only. */
6627 uint64_t tags : 8; /**< [ 7: 0](R/W/H) Number of tags available for MAC.
6628 One tag is needed for each outbound TLP that requires a CPL TLP.
6629 This field should only be written as part of a reset sequence and before issuing any read
6630 operations, CFGs, or I/O transactions from the core(s). For diagnostic use only.
6631 Legal values are 1 to 32. */
6632 #else /* Word 0 - Little Endian */
6633 uint64_t tags : 8; /**< [ 7: 0](R/W/H) Number of tags available for MAC.
6634 One tag is needed for each outbound TLP that requires a CPL TLP.
6635 This field should only be written as part of a reset sequence and before issuing any read
6636 operations, CFGs, or I/O transactions from the core(s). For diagnostic use only.
6637 Legal values are 1 to 32. */
6638 uint64_t pcnt : 8; /**< [ 15: 8](R/W/H) P-TLP FIFO credits. Legal values are 0x25 to 0x80. For diagnostic use only. */
6639 uint64_t ncnt : 8; /**< [ 23: 16](R/W/H) NP-TLP FIFO credits. Legal values are 0x5 to 0x10. For diagnostic use only. */
6640 uint64_t ccnt : 8; /**< [ 31: 24](R/W/H) CPL-TLP FIFO credits. Legal values are 0x25 to 0x80. For diagnostic use only. */
6641 uint64_t reserved_32_63 : 32;
6642 #endif /* Word 0 - End */
6643 } s;
6644 /* struct bdk_slix_s2m_macx_ctl_s cn81xx; */
6645 /* struct bdk_slix_s2m_macx_ctl_s cn88xx; */
6646 struct bdk_slix_s2m_macx_ctl_cn83xx
6647 {
6648 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6649 uint64_t reserved_32_63 : 32;
6650 uint64_t ccnt : 8; /**< [ 31: 24](R/W) CPL-TLP FIFO credits. Legal values are 0x25 to 0xF4. For diagnostic use only. */
6651 uint64_t ncnt : 8; /**< [ 23: 16](R/W) NP-TLP FIFO credits. Legal values are 0x5 to 0x20. For diagnostic use only. */
6652 uint64_t pcnt : 8; /**< [ 15: 8](R/W) P-TLP FIFO credits. Legal values are 0x25 to 0xF4. For diagnostic use only. */
6653 uint64_t tags : 8; /**< [ 7: 0](R/W) Number of tags available for MAC.
6654 One tag is needed for each outbound TLP that requires a CPL TLP.
6655 This field should only be written as part of a reset sequence and before issuing any read
6656 operations, CFGs, or I/O transactions from the core(s). For diagnostic use only.
6657 Legal values are 1 to 32. */
6658 #else /* Word 0 - Little Endian */
6659 uint64_t tags : 8; /**< [ 7: 0](R/W) Number of tags available for MAC.
6660 One tag is needed for each outbound TLP that requires a CPL TLP.
6661 This field should only be written as part of a reset sequence and before issuing any read
6662 operations, CFGs, or I/O transactions from the core(s). For diagnostic use only.
6663 Legal values are 1 to 32. */
6664 uint64_t pcnt : 8; /**< [ 15: 8](R/W) P-TLP FIFO credits. Legal values are 0x25 to 0xF4. For diagnostic use only. */
6665 uint64_t ncnt : 8; /**< [ 23: 16](R/W) NP-TLP FIFO credits. Legal values are 0x5 to 0x20. For diagnostic use only. */
6666 uint64_t ccnt : 8; /**< [ 31: 24](R/W) CPL-TLP FIFO credits. Legal values are 0x25 to 0xF4. For diagnostic use only. */
6667 uint64_t reserved_32_63 : 32;
6668 #endif /* Word 0 - End */
6669 } cn83xx;
6670 };
6671 typedef union bdk_slix_s2m_macx_ctl bdk_slix_s2m_macx_ctl_t;
6672
6673 static inline uint64_t BDK_SLIX_S2M_MACX_CTL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_S2M_MACX_CTL(unsigned long a,unsigned long b)6674 static inline uint64_t BDK_SLIX_S2M_MACX_CTL(unsigned long a, unsigned long b)
6675 {
6676 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b<=2)))
6677 return 0x874001002080ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x3);
6678 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=3)))
6679 return 0x874001002080ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x3);
6680 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=2)))
6681 return 0x874001002080ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x3);
6682 __bdk_csr_fatal("SLIX_S2M_MACX_CTL", 2, a, b, 0, 0);
6683 }
6684
6685 #define typedef_BDK_SLIX_S2M_MACX_CTL(a,b) bdk_slix_s2m_macx_ctl_t
6686 #define bustype_BDK_SLIX_S2M_MACX_CTL(a,b) BDK_CSR_TYPE_NCB
6687 #define basename_BDK_SLIX_S2M_MACX_CTL(a,b) "SLIX_S2M_MACX_CTL"
6688 #define device_bar_BDK_SLIX_S2M_MACX_CTL(a,b) 0x0 /* PF_BAR0 */
6689 #define busnum_BDK_SLIX_S2M_MACX_CTL(a,b) (a)
6690 #define arguments_BDK_SLIX_S2M_MACX_CTL(a,b) (a),(b),-1,-1
6691
6692 /**
6693 * Register (NCB) sli#_s2m_reg#_acc
6694 *
6695 * SLI Region Access Registers
6696 * These registers contains address index and control bits for access to memory from cores.
6697 * Indexed using {NCBO DST[3:0], NCBO Address[35:32]}.
6698 */
6699 union bdk_slix_s2m_regx_acc
6700 {
6701 uint64_t u;
6702 struct bdk_slix_s2m_regx_acc_s
6703 {
6704 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6705 uint64_t reserved_55_63 : 9;
6706 uint64_t ctype : 2; /**< [ 54: 53](R/W) The command type to be generated:
6707 0x0 = PCI memory.
6708 0x1 = PCI configuration (only 8, 16, 32-bit loads are supported). Note normally the ECAM
6709 would be used in place of this CTYPE.
6710 0x2 = PCI I/O (Only 8, 16, 32-bit loads are supported).
6711 0x3 = Reserved. */
6712 uint64_t zero : 1; /**< [ 52: 52](R/W) Causes all byte read operations to be zero-length read operations. Returns zeros to the
6713 EXEC for all read data. */
6714 uint64_t reserved_49_51 : 3;
6715 uint64_t nmerge : 1; /**< [ 48: 48](R/W) When set, no write merging is allowed in this window. */
6716 uint64_t esr : 2; /**< [ 47: 46](RO) Reserved. */
6717 uint64_t esw : 2; /**< [ 45: 44](RO) Reserved. */
6718 uint64_t wtype : 2; /**< [ 43: 42](R/W) Write type. ADDRTYPE\<1:0\> for write operations to this region.
6719 ADDRTYPE\<0\> is the relaxed-order attribute.
6720 ADDRTYPE\<1\> is the no-snoop attribute. */
6721 uint64_t rtype : 2; /**< [ 41: 40](R/W) Read type. ADDRTYPE\<1:0\> for read operations to this region.
6722 ADDRTYPE\<0\> is the relaxed-order attribute.
6723 ADDRTYPE\<1\> is the no-snoop attribute. */
6724 uint64_t reserved_32_39 : 8;
6725 uint64_t ba : 32; /**< [ 31: 0](R/W) Bus address. Address bits\<63:32\> for read/write operations that use this region. */
6726 #else /* Word 0 - Little Endian */
6727 uint64_t ba : 32; /**< [ 31: 0](R/W) Bus address. Address bits\<63:32\> for read/write operations that use this region. */
6728 uint64_t reserved_32_39 : 8;
6729 uint64_t rtype : 2; /**< [ 41: 40](R/W) Read type. ADDRTYPE\<1:0\> for read operations to this region.
6730 ADDRTYPE\<0\> is the relaxed-order attribute.
6731 ADDRTYPE\<1\> is the no-snoop attribute. */
6732 uint64_t wtype : 2; /**< [ 43: 42](R/W) Write type. ADDRTYPE\<1:0\> for write operations to this region.
6733 ADDRTYPE\<0\> is the relaxed-order attribute.
6734 ADDRTYPE\<1\> is the no-snoop attribute. */
6735 uint64_t esw : 2; /**< [ 45: 44](RO) Reserved. */
6736 uint64_t esr : 2; /**< [ 47: 46](RO) Reserved. */
6737 uint64_t nmerge : 1; /**< [ 48: 48](R/W) When set, no write merging is allowed in this window. */
6738 uint64_t reserved_49_51 : 3;
6739 uint64_t zero : 1; /**< [ 52: 52](R/W) Causes all byte read operations to be zero-length read operations. Returns zeros to the
6740 EXEC for all read data. */
6741 uint64_t ctype : 2; /**< [ 54: 53](R/W) The command type to be generated:
6742 0x0 = PCI memory.
6743 0x1 = PCI configuration (only 8, 16, 32-bit loads are supported). Note normally the ECAM
6744 would be used in place of this CTYPE.
6745 0x2 = PCI I/O (Only 8, 16, 32-bit loads are supported).
6746 0x3 = Reserved. */
6747 uint64_t reserved_55_63 : 9;
6748 #endif /* Word 0 - End */
6749 } s;
6750 struct bdk_slix_s2m_regx_acc_cn81xx
6751 {
6752 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6753 uint64_t reserved_55_63 : 9;
6754 uint64_t ctype : 2; /**< [ 54: 53](R/W) The command type to be generated:
6755 0x0 = PCI memory.
6756 0x1 = PCI configuration (only 8, 16, 32-bit loads are supported). Note normally the ECAM
6757 would be used in place of this CTYPE.
6758 0x2 = PCI I/O (Only 8, 16, 32-bit loads are supported).
6759 0x3 = Reserved. */
6760 uint64_t zero : 1; /**< [ 52: 52](R/W) Causes all byte read operations to be zero-length read operations. Returns zeros to the
6761 EXEC for all read data. */
6762 uint64_t mac : 3; /**< [ 51: 49](R/W) The MAC that reads/writes to this subid are sent. */
6763 uint64_t nmerge : 1; /**< [ 48: 48](R/W) When set, no write merging is allowed in this window. */
6764 uint64_t esr : 2; /**< [ 47: 46](RO) Reserved. */
6765 uint64_t esw : 2; /**< [ 45: 44](RO) Reserved. */
6766 uint64_t wtype : 2; /**< [ 43: 42](R/W) Write type. ADDRTYPE\<1:0\> for write operations to this region.
6767 ADDRTYPE\<0\> is the relaxed-order attribute.
6768 ADDRTYPE\<1\> is the no-snoop attribute. */
6769 uint64_t rtype : 2; /**< [ 41: 40](R/W) Read type. ADDRTYPE\<1:0\> for read operations to this region.
6770 ADDRTYPE\<0\> is the relaxed-order attribute.
6771 ADDRTYPE\<1\> is the no-snoop attribute. */
6772 uint64_t reserved_32_39 : 8;
6773 uint64_t ba : 32; /**< [ 31: 0](R/W) Bus address. Address bits\<63:32\> for read/write operations that use this region. */
6774 #else /* Word 0 - Little Endian */
6775 uint64_t ba : 32; /**< [ 31: 0](R/W) Bus address. Address bits\<63:32\> for read/write operations that use this region. */
6776 uint64_t reserved_32_39 : 8;
6777 uint64_t rtype : 2; /**< [ 41: 40](R/W) Read type. ADDRTYPE\<1:0\> for read operations to this region.
6778 ADDRTYPE\<0\> is the relaxed-order attribute.
6779 ADDRTYPE\<1\> is the no-snoop attribute. */
6780 uint64_t wtype : 2; /**< [ 43: 42](R/W) Write type. ADDRTYPE\<1:0\> for write operations to this region.
6781 ADDRTYPE\<0\> is the relaxed-order attribute.
6782 ADDRTYPE\<1\> is the no-snoop attribute. */
6783 uint64_t esw : 2; /**< [ 45: 44](RO) Reserved. */
6784 uint64_t esr : 2; /**< [ 47: 46](RO) Reserved. */
6785 uint64_t nmerge : 1; /**< [ 48: 48](R/W) When set, no write merging is allowed in this window. */
6786 uint64_t mac : 3; /**< [ 51: 49](R/W) The MAC that reads/writes to this subid are sent. */
6787 uint64_t zero : 1; /**< [ 52: 52](R/W) Causes all byte read operations to be zero-length read operations. Returns zeros to the
6788 EXEC for all read data. */
6789 uint64_t ctype : 2; /**< [ 54: 53](R/W) The command type to be generated:
6790 0x0 = PCI memory.
6791 0x1 = PCI configuration (only 8, 16, 32-bit loads are supported). Note normally the ECAM
6792 would be used in place of this CTYPE.
6793 0x2 = PCI I/O (Only 8, 16, 32-bit loads are supported).
6794 0x3 = Reserved. */
6795 uint64_t reserved_55_63 : 9;
6796 #endif /* Word 0 - End */
6797 } cn81xx;
6798 /* struct bdk_slix_s2m_regx_acc_cn81xx cn88xx; */
6799 struct bdk_slix_s2m_regx_acc_cn83xx
6800 {
6801 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6802 uint64_t reserved_55_63 : 9;
6803 uint64_t ctype : 2; /**< [ 54: 53](R/W) The command type to be generated:
6804 0x0 = PCI memory.
6805 0x1 = PCI configuration (only 8, 16, 32-bit loads are supported). Note normally the ECAM
6806 would be used in place of this CTYPE.
6807 0x2 = PCI I/O (Only 8, 16, 32-bit loads are supported).
6808 0x3 = Reserved. */
6809 uint64_t zero : 1; /**< [ 52: 52](R/W) Causes all byte read operations to be zero-length read operations. Returns zeros to the
6810 EXEC for all read data. */
6811 uint64_t epf : 3; /**< [ 51: 49](R/W) The EPF that reads/writes to this subid are sent. */
6812 uint64_t nmerge : 1; /**< [ 48: 48](R/W) When set, no write merging is allowed in this window. */
6813 uint64_t esr : 2; /**< [ 47: 46](RO) Reserved. */
6814 uint64_t esw : 2; /**< [ 45: 44](RO) Reserved. */
6815 uint64_t wtype : 2; /**< [ 43: 42](R/W) Write type. ADDRTYPE\<1:0\> for write operations to this region.
6816 ADDRTYPE\<0\> is the relaxed-order attribute.
6817 ADDRTYPE\<1\> is the no-snoop attribute. */
6818 uint64_t rtype : 2; /**< [ 41: 40](R/W) Read type. ADDRTYPE\<1:0\> for read operations to this region.
6819 ADDRTYPE\<0\> is the relaxed-order attribute.
6820 ADDRTYPE\<1\> is the no-snoop attribute. */
6821 uint64_t reserved_32_39 : 8;
6822 uint64_t ba : 32; /**< [ 31: 0](R/W) Bus address. Address bits\<63:32\> for read/write operations that use this region. */
6823 #else /* Word 0 - Little Endian */
6824 uint64_t ba : 32; /**< [ 31: 0](R/W) Bus address. Address bits\<63:32\> for read/write operations that use this region. */
6825 uint64_t reserved_32_39 : 8;
6826 uint64_t rtype : 2; /**< [ 41: 40](R/W) Read type. ADDRTYPE\<1:0\> for read operations to this region.
6827 ADDRTYPE\<0\> is the relaxed-order attribute.
6828 ADDRTYPE\<1\> is the no-snoop attribute. */
6829 uint64_t wtype : 2; /**< [ 43: 42](R/W) Write type. ADDRTYPE\<1:0\> for write operations to this region.
6830 ADDRTYPE\<0\> is the relaxed-order attribute.
6831 ADDRTYPE\<1\> is the no-snoop attribute. */
6832 uint64_t esw : 2; /**< [ 45: 44](RO) Reserved. */
6833 uint64_t esr : 2; /**< [ 47: 46](RO) Reserved. */
6834 uint64_t nmerge : 1; /**< [ 48: 48](R/W) When set, no write merging is allowed in this window. */
6835 uint64_t epf : 3; /**< [ 51: 49](R/W) The EPF that reads/writes to this subid are sent. */
6836 uint64_t zero : 1; /**< [ 52: 52](R/W) Causes all byte read operations to be zero-length read operations. Returns zeros to the
6837 EXEC for all read data. */
6838 uint64_t ctype : 2; /**< [ 54: 53](R/W) The command type to be generated:
6839 0x0 = PCI memory.
6840 0x1 = PCI configuration (only 8, 16, 32-bit loads are supported). Note normally the ECAM
6841 would be used in place of this CTYPE.
6842 0x2 = PCI I/O (Only 8, 16, 32-bit loads are supported).
6843 0x3 = Reserved. */
6844 uint64_t reserved_55_63 : 9;
6845 #endif /* Word 0 - End */
6846 } cn83xx;
6847 };
6848 typedef union bdk_slix_s2m_regx_acc bdk_slix_s2m_regx_acc_t;
6849
6850 static inline uint64_t BDK_SLIX_S2M_REGX_ACC(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_S2M_REGX_ACC(unsigned long a,unsigned long b)6851 static inline uint64_t BDK_SLIX_S2M_REGX_ACC(unsigned long a, unsigned long b)
6852 {
6853 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b<=255)))
6854 return 0x874001000000ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0xff);
6855 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=255)))
6856 return 0x874001000000ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0xff);
6857 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=255)))
6858 return 0x874001000000ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0xff);
6859 __bdk_csr_fatal("SLIX_S2M_REGX_ACC", 2, a, b, 0, 0);
6860 }
6861
6862 #define typedef_BDK_SLIX_S2M_REGX_ACC(a,b) bdk_slix_s2m_regx_acc_t
6863 #define bustype_BDK_SLIX_S2M_REGX_ACC(a,b) BDK_CSR_TYPE_NCB
6864 #define basename_BDK_SLIX_S2M_REGX_ACC(a,b) "SLIX_S2M_REGX_ACC"
6865 #define device_bar_BDK_SLIX_S2M_REGX_ACC(a,b) 0x0 /* PF_BAR0 */
6866 #define busnum_BDK_SLIX_S2M_REGX_ACC(a,b) (a)
6867 #define arguments_BDK_SLIX_S2M_REGX_ACC(a,b) (a),(b),-1,-1
6868
6869 /**
6870 * Register (NCB) sli#_s2m_reg#_acc2
6871 *
6872 * SLI Region Access 2 Registers
6873 * See SLI()_LMAC_CONST0().
6874 */
6875 union bdk_slix_s2m_regx_acc2
6876 {
6877 uint64_t u;
6878 struct bdk_slix_s2m_regx_acc2_s
6879 {
6880 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6881 uint64_t reserved_16_63 : 48;
6882 uint64_t vf_rsvd : 9; /**< [ 15: 7](RO) For expansion of the [VF] field for compatibility with other chips with larger
6883 SLI()_LMAC_CONST1()[VFS]. */
6884 uint64_t pvf : 7; /**< [ 6: 0](R/W) The PF/VF number. 0x0=PF, 0x1-0x40 is VF number (i.e 0x1=VF1).
6885 Must be less than SLI()_LMAC_CONST1()[VFS]. */
6886 #else /* Word 0 - Little Endian */
6887 uint64_t pvf : 7; /**< [ 6: 0](R/W) The PF/VF number. 0x0=PF, 0x1-0x40 is VF number (i.e 0x1=VF1).
6888 Must be less than SLI()_LMAC_CONST1()[VFS]. */
6889 uint64_t vf_rsvd : 9; /**< [ 15: 7](RO) For expansion of the [VF] field for compatibility with other chips with larger
6890 SLI()_LMAC_CONST1()[VFS]. */
6891 uint64_t reserved_16_63 : 48;
6892 #endif /* Word 0 - End */
6893 } s;
6894 /* struct bdk_slix_s2m_regx_acc2_s cn; */
6895 };
6896 typedef union bdk_slix_s2m_regx_acc2 bdk_slix_s2m_regx_acc2_t;
6897
6898 static inline uint64_t BDK_SLIX_S2M_REGX_ACC2(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_S2M_REGX_ACC2(unsigned long a,unsigned long b)6899 static inline uint64_t BDK_SLIX_S2M_REGX_ACC2(unsigned long a, unsigned long b)
6900 {
6901 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=255)))
6902 return 0x874001005000ll + 0x1000000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0xff);
6903 __bdk_csr_fatal("SLIX_S2M_REGX_ACC2", 2, a, b, 0, 0);
6904 }
6905
6906 #define typedef_BDK_SLIX_S2M_REGX_ACC2(a,b) bdk_slix_s2m_regx_acc2_t
6907 #define bustype_BDK_SLIX_S2M_REGX_ACC2(a,b) BDK_CSR_TYPE_NCB
6908 #define basename_BDK_SLIX_S2M_REGX_ACC2(a,b) "SLIX_S2M_REGX_ACC2"
6909 #define device_bar_BDK_SLIX_S2M_REGX_ACC2(a,b) 0x0 /* PF_BAR0 */
6910 #define busnum_BDK_SLIX_S2M_REGX_ACC2(a,b) (a)
6911 #define arguments_BDK_SLIX_S2M_REGX_ACC2(a,b) (a),(b),-1,-1
6912
6913 /**
6914 * Register (PEXP_NCB) sli#_scratch_1
6915 *
6916 * SLI Scratch 1 Register
6917 * These registers are general purpose 64-bit scratch registers for software use.
6918 */
6919 union bdk_slix_scratch_1
6920 {
6921 uint64_t u;
6922 struct bdk_slix_scratch_1_s
6923 {
6924 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6925 uint64_t data : 64; /**< [ 63: 0](R/W) The value in this register is totally software defined. */
6926 #else /* Word 0 - Little Endian */
6927 uint64_t data : 64; /**< [ 63: 0](R/W) The value in this register is totally software defined. */
6928 #endif /* Word 0 - End */
6929 } s;
6930 /* struct bdk_slix_scratch_1_s cn; */
6931 };
6932 typedef union bdk_slix_scratch_1 bdk_slix_scratch_1_t;
6933
6934 static inline uint64_t BDK_SLIX_SCRATCH_1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SLIX_SCRATCH_1(unsigned long a)6935 static inline uint64_t BDK_SLIX_SCRATCH_1(unsigned long a)
6936 {
6937 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
6938 return 0x874000001000ll + 0x1000000000ll * ((a) & 0x0);
6939 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a==0))
6940 return 0x874000001000ll + 0x1000000000ll * ((a) & 0x0);
6941 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
6942 return 0x874000001000ll + 0x1000000000ll * ((a) & 0x1);
6943 __bdk_csr_fatal("SLIX_SCRATCH_1", 1, a, 0, 0, 0);
6944 }
6945
6946 #define typedef_BDK_SLIX_SCRATCH_1(a) bdk_slix_scratch_1_t
6947 #define bustype_BDK_SLIX_SCRATCH_1(a) BDK_CSR_TYPE_PEXP_NCB
6948 #define basename_BDK_SLIX_SCRATCH_1(a) "SLIX_SCRATCH_1"
6949 #define device_bar_BDK_SLIX_SCRATCH_1(a) 0x0 /* PF_BAR0 */
6950 #define busnum_BDK_SLIX_SCRATCH_1(a) (a)
6951 #define arguments_BDK_SLIX_SCRATCH_1(a) (a),-1,-1,-1
6952
6953 /**
6954 * Register (PEXP_NCB) sli#_scratch_2
6955 *
6956 * SLI Scratch 2 Register
6957 * These registers are general purpose 64-bit scratch registers for software use.
6958 */
6959 union bdk_slix_scratch_2
6960 {
6961 uint64_t u;
6962 struct bdk_slix_scratch_2_s
6963 {
6964 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6965 uint64_t data : 64; /**< [ 63: 0](R/W) The value in this register is totally software defined. */
6966 #else /* Word 0 - Little Endian */
6967 uint64_t data : 64; /**< [ 63: 0](R/W) The value in this register is totally software defined. */
6968 #endif /* Word 0 - End */
6969 } s;
6970 /* struct bdk_slix_scratch_2_s cn; */
6971 };
6972 typedef union bdk_slix_scratch_2 bdk_slix_scratch_2_t;
6973
6974 static inline uint64_t BDK_SLIX_SCRATCH_2(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SLIX_SCRATCH_2(unsigned long a)6975 static inline uint64_t BDK_SLIX_SCRATCH_2(unsigned long a)
6976 {
6977 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
6978 return 0x874000001010ll + 0x1000000000ll * ((a) & 0x0);
6979 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a==0))
6980 return 0x874000001010ll + 0x1000000000ll * ((a) & 0x0);
6981 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
6982 return 0x874000001010ll + 0x1000000000ll * ((a) & 0x1);
6983 __bdk_csr_fatal("SLIX_SCRATCH_2", 1, a, 0, 0, 0);
6984 }
6985
6986 #define typedef_BDK_SLIX_SCRATCH_2(a) bdk_slix_scratch_2_t
6987 #define bustype_BDK_SLIX_SCRATCH_2(a) BDK_CSR_TYPE_PEXP_NCB
6988 #define basename_BDK_SLIX_SCRATCH_2(a) "SLIX_SCRATCH_2"
6989 #define device_bar_BDK_SLIX_SCRATCH_2(a) 0x0 /* PF_BAR0 */
6990 #define busnum_BDK_SLIX_SCRATCH_2(a) (a)
6991 #define arguments_BDK_SLIX_SCRATCH_2(a) (a),-1,-1,-1
6992
6993 /**
6994 * Register (NCB) sli#_sctl
6995 *
6996 * SLI Secure Control Register
6997 */
6998 union bdk_slix_sctl
6999 {
7000 uint64_t u;
7001 struct bdk_slix_sctl_s
7002 {
7003 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7004 uint64_t reserved_1_63 : 63;
7005 uint64_t scen : 1; /**< [ 0: 0](SR/W) Allow SLI window transactions to request secure-world accesses.
7006
7007 0 = SLI()_WIN_RD_ADDR[SECEN], SLI()_WIN_WR_ADDR[SECEN] are ignored and treated
7008 as if zero. Window transactions onto NCB are nonsecure, though the SMMU may
7009 later promote them to secure.
7010
7011 1 = SLI()_WIN_RD_ADDR[SECEN], SLI()_WIN_WR_ADDR[SECEN] are honored. Window
7012 transactions may request nonsecure or secure world. This bit should not be set
7013 in trusted-mode.
7014
7015 Resets to 0 when in trusted-mode (RST_BOOT[TRUSTED_MODE]), else resets to 1. */
7016 #else /* Word 0 - Little Endian */
7017 uint64_t scen : 1; /**< [ 0: 0](SR/W) Allow SLI window transactions to request secure-world accesses.
7018
7019 0 = SLI()_WIN_RD_ADDR[SECEN], SLI()_WIN_WR_ADDR[SECEN] are ignored and treated
7020 as if zero. Window transactions onto NCB are nonsecure, though the SMMU may
7021 later promote them to secure.
7022
7023 1 = SLI()_WIN_RD_ADDR[SECEN], SLI()_WIN_WR_ADDR[SECEN] are honored. Window
7024 transactions may request nonsecure or secure world. This bit should not be set
7025 in trusted-mode.
7026
7027 Resets to 0 when in trusted-mode (RST_BOOT[TRUSTED_MODE]), else resets to 1. */
7028 uint64_t reserved_1_63 : 63;
7029 #endif /* Word 0 - End */
7030 } s;
7031 struct bdk_slix_sctl_cn81xx
7032 {
7033 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7034 uint64_t reserved_1_63 : 63;
7035 uint64_t scen : 1; /**< [ 0: 0](SR/W) Allow SLI window transactions to request secure-world accesses.
7036
7037 0 = SLI()_WIN_RD_ADDR[RD_SEC], SLI()_WIN_WR_ADDR[WR_SEC] are ignored and treated
7038 as if zero. Window transactions onto NCB are nonsecure, though the SMMU may
7039 later promote them to secure.
7040
7041 1 = SLI()_WIN_RD_ADDR[RD_SEC], SLI()_WIN_WR_ADDR[WR_SEC] are honored. Window
7042 transactions may request nonsecure or secure world. This bit should not be set
7043 in trusted-mode.
7044
7045 Resets to 0 when in trusted-mode (RST_BOOT[TRUSTED_MODE]), else resets to 1. */
7046 #else /* Word 0 - Little Endian */
7047 uint64_t scen : 1; /**< [ 0: 0](SR/W) Allow SLI window transactions to request secure-world accesses.
7048
7049 0 = SLI()_WIN_RD_ADDR[RD_SEC], SLI()_WIN_WR_ADDR[WR_SEC] are ignored and treated
7050 as if zero. Window transactions onto NCB are nonsecure, though the SMMU may
7051 later promote them to secure.
7052
7053 1 = SLI()_WIN_RD_ADDR[RD_SEC], SLI()_WIN_WR_ADDR[WR_SEC] are honored. Window
7054 transactions may request nonsecure or secure world. This bit should not be set
7055 in trusted-mode.
7056
7057 Resets to 0 when in trusted-mode (RST_BOOT[TRUSTED_MODE]), else resets to 1. */
7058 uint64_t reserved_1_63 : 63;
7059 #endif /* Word 0 - End */
7060 } cn81xx;
7061 /* struct bdk_slix_sctl_cn81xx cn88xx; */
7062 /* struct bdk_slix_sctl_s cn83xx; */
7063 };
7064 typedef union bdk_slix_sctl bdk_slix_sctl_t;
7065
7066 static inline uint64_t BDK_SLIX_SCTL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SLIX_SCTL(unsigned long a)7067 static inline uint64_t BDK_SLIX_SCTL(unsigned long a)
7068 {
7069 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
7070 return 0x874001002010ll + 0x1000000000ll * ((a) & 0x0);
7071 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a==0))
7072 return 0x874001002010ll + 0x1000000000ll * ((a) & 0x0);
7073 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX_PASS2_X) && (a<=1))
7074 return 0x874001002010ll + 0x1000000000ll * ((a) & 0x1);
7075 __bdk_csr_fatal("SLIX_SCTL", 1, a, 0, 0, 0);
7076 }
7077
7078 #define typedef_BDK_SLIX_SCTL(a) bdk_slix_sctl_t
7079 #define bustype_BDK_SLIX_SCTL(a) BDK_CSR_TYPE_NCB
7080 #define basename_BDK_SLIX_SCTL(a) "SLIX_SCTL"
7081 #define device_bar_BDK_SLIX_SCTL(a) 0x0 /* PF_BAR0 */
7082 #define busnum_BDK_SLIX_SCTL(a) (a)
7083 #define arguments_BDK_SLIX_SCTL(a) (a),-1,-1,-1
7084
7085 /**
7086 * Register (PEXP) sli#_win_rd_addr
7087 *
7088 * SLI Window Read Address Register
7089 * This register contains the address to be read when SLI()_WIN_RD_DATA is read.
7090 * Writing this register causes a read operation to take place.
7091 * This register should not be used to read SLI_* registers.
7092 */
7093 union bdk_slix_win_rd_addr
7094 {
7095 uint64_t u;
7096 struct bdk_slix_win_rd_addr_s
7097 {
7098 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7099 uint64_t secen : 1; /**< [ 63: 63](R/W) This request is a secure-world transaction. This is intended to be set only for
7100 transactions during early boot when the SMMU is in bypass mode; after SMMU
7101 initialization SMMU()_SDDR() may be used to control which SLI streams are secure.
7102
7103 If SLI()_SCTL[SECEN] = 0, this bit is ignored and transactions are always nonsecure
7104 onto the NCB, though the SMMU may later promote them to secure. */
7105 uint64_t reserved_51_62 : 12;
7106 uint64_t ld_cmd : 2; /**< [ 50: 49](R/W) The load command size.
7107 0x3 = Load 8 bytes.
7108 0x2 = Load 4 bytes.
7109 0x1 = Load 2 bytes.
7110 0x0 = Load 1 bytes. */
7111 uint64_t rd_addr : 49; /**< [ 48: 0](R/W) The IOVA sent to the NCB for this load request. */
7112 #else /* Word 0 - Little Endian */
7113 uint64_t rd_addr : 49; /**< [ 48: 0](R/W) The IOVA sent to the NCB for this load request. */
7114 uint64_t ld_cmd : 2; /**< [ 50: 49](R/W) The load command size.
7115 0x3 = Load 8 bytes.
7116 0x2 = Load 4 bytes.
7117 0x1 = Load 2 bytes.
7118 0x0 = Load 1 bytes. */
7119 uint64_t reserved_51_62 : 12;
7120 uint64_t secen : 1; /**< [ 63: 63](R/W) This request is a secure-world transaction. This is intended to be set only for
7121 transactions during early boot when the SMMU is in bypass mode; after SMMU
7122 initialization SMMU()_SDDR() may be used to control which SLI streams are secure.
7123
7124 If SLI()_SCTL[SECEN] = 0, this bit is ignored and transactions are always nonsecure
7125 onto the NCB, though the SMMU may later promote them to secure. */
7126 #endif /* Word 0 - End */
7127 } s;
7128 struct bdk_slix_win_rd_addr_cn88xxp1
7129 {
7130 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7131 uint64_t reserved_51_63 : 13;
7132 uint64_t ld_cmd : 2; /**< [ 50: 49](R/W) The load command size.
7133 0x3 = Load 8 bytes.
7134 0x2 = Load 4 bytes.
7135 0x1 = Load 2 bytes.
7136 0x0 = Load 1 bytes. */
7137 uint64_t rd_addr : 49; /**< [ 48: 0](R/W) The IOVA sent to the NCB for this load request. */
7138 #else /* Word 0 - Little Endian */
7139 uint64_t rd_addr : 49; /**< [ 48: 0](R/W) The IOVA sent to the NCB for this load request. */
7140 uint64_t ld_cmd : 2; /**< [ 50: 49](R/W) The load command size.
7141 0x3 = Load 8 bytes.
7142 0x2 = Load 4 bytes.
7143 0x1 = Load 2 bytes.
7144 0x0 = Load 1 bytes. */
7145 uint64_t reserved_51_63 : 13;
7146 #endif /* Word 0 - End */
7147 } cn88xxp1;
7148 /* struct bdk_slix_win_rd_addr_s cn81xx; */
7149 /* struct bdk_slix_win_rd_addr_s cn88xxp2; */
7150 };
7151 typedef union bdk_slix_win_rd_addr bdk_slix_win_rd_addr_t;
7152
7153 static inline uint64_t BDK_SLIX_WIN_RD_ADDR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SLIX_WIN_RD_ADDR(unsigned long a)7154 static inline uint64_t BDK_SLIX_WIN_RD_ADDR(unsigned long a)
7155 {
7156 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
7157 return 0x10ll + 0x10000000000ll * ((a) & 0x0);
7158 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
7159 return 0x10ll + 0x10000000000ll * ((a) & 0x1);
7160 __bdk_csr_fatal("SLIX_WIN_RD_ADDR", 1, a, 0, 0, 0);
7161 }
7162
7163 #define typedef_BDK_SLIX_WIN_RD_ADDR(a) bdk_slix_win_rd_addr_t
7164 #define bustype_BDK_SLIX_WIN_RD_ADDR(a) BDK_CSR_TYPE_PEXP
7165 #define basename_BDK_SLIX_WIN_RD_ADDR(a) "SLIX_WIN_RD_ADDR"
7166 #define busnum_BDK_SLIX_WIN_RD_ADDR(a) (a)
7167 #define arguments_BDK_SLIX_WIN_RD_ADDR(a) (a),-1,-1,-1
7168
7169 /**
7170 * Register (PEXP) sli#_win_rd_addr#
7171 *
7172 * SLI Window Read Address Register
7173 * This register contains the address to be read when SLI()_WIN_RD_DATA() is read.
7174 * Writing this register causes a read operation to take place.
7175 * This register should not be used to read SLI_* registers.
7176 */
7177 union bdk_slix_win_rd_addrx
7178 {
7179 uint64_t u;
7180 struct bdk_slix_win_rd_addrx_s
7181 {
7182 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7183 uint64_t secen : 1; /**< [ 63: 63](R/W) This request is a secure-world transaction. This is intended to be set only for
7184 transactions during early boot when the SMMU is in bypass mode; after SMMU
7185 initialization SMMU()_SSDR() may be used to control which SLI streams are secure.
7186
7187 If SLI()_SCTL[SCEN] = 0, this bit is ignored and transactions are always nonsecure
7188 onto the NCB, though the SMMU may later promote them to secure. */
7189 uint64_t reserved_51_62 : 12;
7190 uint64_t ld_cmd : 2; /**< [ 50: 49](R/W) The load command size.
7191 0x3 = Load 8 bytes.
7192 0x2 = Load 4 bytes.
7193 0x1 = Load 2 bytes.
7194 0x0 = Load 1 bytes. */
7195 uint64_t rd_addr : 49; /**< [ 48: 0](R/W) The IOVA sent to the NCB for this load request. */
7196 #else /* Word 0 - Little Endian */
7197 uint64_t rd_addr : 49; /**< [ 48: 0](R/W) The IOVA sent to the NCB for this load request. */
7198 uint64_t ld_cmd : 2; /**< [ 50: 49](R/W) The load command size.
7199 0x3 = Load 8 bytes.
7200 0x2 = Load 4 bytes.
7201 0x1 = Load 2 bytes.
7202 0x0 = Load 1 bytes. */
7203 uint64_t reserved_51_62 : 12;
7204 uint64_t secen : 1; /**< [ 63: 63](R/W) This request is a secure-world transaction. This is intended to be set only for
7205 transactions during early boot when the SMMU is in bypass mode; after SMMU
7206 initialization SMMU()_SSDR() may be used to control which SLI streams are secure.
7207
7208 If SLI()_SCTL[SCEN] = 0, this bit is ignored and transactions are always nonsecure
7209 onto the NCB, though the SMMU may later promote them to secure. */
7210 #endif /* Word 0 - End */
7211 } s;
7212 /* struct bdk_slix_win_rd_addrx_s cn; */
7213 };
7214 typedef union bdk_slix_win_rd_addrx bdk_slix_win_rd_addrx_t;
7215
7216 static inline uint64_t BDK_SLIX_WIN_RD_ADDRX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_WIN_RD_ADDRX(unsigned long a,unsigned long b)7217 static inline uint64_t BDK_SLIX_WIN_RD_ADDRX(unsigned long a, unsigned long b)
7218 {
7219 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=3)))
7220 return 0x2c010ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x3);
7221 __bdk_csr_fatal("SLIX_WIN_RD_ADDRX", 2, a, b, 0, 0);
7222 }
7223
7224 #define typedef_BDK_SLIX_WIN_RD_ADDRX(a,b) bdk_slix_win_rd_addrx_t
7225 #define bustype_BDK_SLIX_WIN_RD_ADDRX(a,b) BDK_CSR_TYPE_PEXP
7226 #define basename_BDK_SLIX_WIN_RD_ADDRX(a,b) "SLIX_WIN_RD_ADDRX"
7227 #define busnum_BDK_SLIX_WIN_RD_ADDRX(a,b) (a)
7228 #define arguments_BDK_SLIX_WIN_RD_ADDRX(a,b) (a),(b),-1,-1
7229
7230 /**
7231 * Register (PEXP) sli#_win_rd_data
7232 *
7233 * SLI Window Read Data Register
7234 * This register contains the address to be read when SLI()_WIN_RD_DATA is read.
7235 */
7236 union bdk_slix_win_rd_data
7237 {
7238 uint64_t u;
7239 struct bdk_slix_win_rd_data_s
7240 {
7241 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7242 uint64_t rd_data : 64; /**< [ 63: 0](RO/H) The read data. */
7243 #else /* Word 0 - Little Endian */
7244 uint64_t rd_data : 64; /**< [ 63: 0](RO/H) The read data. */
7245 #endif /* Word 0 - End */
7246 } s;
7247 /* struct bdk_slix_win_rd_data_s cn; */
7248 };
7249 typedef union bdk_slix_win_rd_data bdk_slix_win_rd_data_t;
7250
7251 static inline uint64_t BDK_SLIX_WIN_RD_DATA(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SLIX_WIN_RD_DATA(unsigned long a)7252 static inline uint64_t BDK_SLIX_WIN_RD_DATA(unsigned long a)
7253 {
7254 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
7255 return 0x40ll + 0x10000000000ll * ((a) & 0x0);
7256 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
7257 return 0x40ll + 0x10000000000ll * ((a) & 0x1);
7258 __bdk_csr_fatal("SLIX_WIN_RD_DATA", 1, a, 0, 0, 0);
7259 }
7260
7261 #define typedef_BDK_SLIX_WIN_RD_DATA(a) bdk_slix_win_rd_data_t
7262 #define bustype_BDK_SLIX_WIN_RD_DATA(a) BDK_CSR_TYPE_PEXP
7263 #define basename_BDK_SLIX_WIN_RD_DATA(a) "SLIX_WIN_RD_DATA"
7264 #define busnum_BDK_SLIX_WIN_RD_DATA(a) (a)
7265 #define arguments_BDK_SLIX_WIN_RD_DATA(a) (a),-1,-1,-1
7266
7267 /**
7268 * Register (PEXP) sli#_win_rd_data#
7269 *
7270 * SLI Window Read Data Register
7271 * This register contains the address to be read when SLI()_WIN_RD_DATA() is read.
7272 */
7273 union bdk_slix_win_rd_datax
7274 {
7275 uint64_t u;
7276 struct bdk_slix_win_rd_datax_s
7277 {
7278 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7279 uint64_t rd_data : 64; /**< [ 63: 0](RO/H) The read data. */
7280 #else /* Word 0 - Little Endian */
7281 uint64_t rd_data : 64; /**< [ 63: 0](RO/H) The read data. */
7282 #endif /* Word 0 - End */
7283 } s;
7284 /* struct bdk_slix_win_rd_datax_s cn; */
7285 };
7286 typedef union bdk_slix_win_rd_datax bdk_slix_win_rd_datax_t;
7287
7288 static inline uint64_t BDK_SLIX_WIN_RD_DATAX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_WIN_RD_DATAX(unsigned long a,unsigned long b)7289 static inline uint64_t BDK_SLIX_WIN_RD_DATAX(unsigned long a, unsigned long b)
7290 {
7291 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=3)))
7292 return 0x2c040ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x3);
7293 __bdk_csr_fatal("SLIX_WIN_RD_DATAX", 2, a, b, 0, 0);
7294 }
7295
7296 #define typedef_BDK_SLIX_WIN_RD_DATAX(a,b) bdk_slix_win_rd_datax_t
7297 #define bustype_BDK_SLIX_WIN_RD_DATAX(a,b) BDK_CSR_TYPE_PEXP
7298 #define basename_BDK_SLIX_WIN_RD_DATAX(a,b) "SLIX_WIN_RD_DATAX"
7299 #define busnum_BDK_SLIX_WIN_RD_DATAX(a,b) (a)
7300 #define arguments_BDK_SLIX_WIN_RD_DATAX(a,b) (a),(b),-1,-1
7301
7302 /**
7303 * Register (PEXP) sli#_win_wr_addr
7304 *
7305 * SLI Window Write Address Register
7306 * Contains the address to be writen to when a write operation is started by writing
7307 * SLI()_WIN_WR_DATA.
7308 * This register should not be used to write SLI_* registers.
7309 */
7310 union bdk_slix_win_wr_addr
7311 {
7312 uint64_t u;
7313 struct bdk_slix_win_wr_addr_s
7314 {
7315 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7316 uint64_t secen : 1; /**< [ 63: 63](R/W) This request is a secure-world transaction. This is intended to be set only for
7317 transactions during early boot when the SMMU is in bypass mode; after SMMU
7318 initialization SMMU()_SDDR() may be used to control which SLI streams are secure.
7319
7320 If SLI()_SCTL[SECEN] = 0, this bit is ignored and transactions are always nonsecure
7321 onto the NCB, though the SMMU may later promote them to secure. */
7322 uint64_t reserved_49_62 : 14;
7323 uint64_t wr_addr : 46; /**< [ 48: 3](R/W) The IOVA sent to the NCB for this store request. */
7324 uint64_t reserved_0_2 : 3;
7325 #else /* Word 0 - Little Endian */
7326 uint64_t reserved_0_2 : 3;
7327 uint64_t wr_addr : 46; /**< [ 48: 3](R/W) The IOVA sent to the NCB for this store request. */
7328 uint64_t reserved_49_62 : 14;
7329 uint64_t secen : 1; /**< [ 63: 63](R/W) This request is a secure-world transaction. This is intended to be set only for
7330 transactions during early boot when the SMMU is in bypass mode; after SMMU
7331 initialization SMMU()_SDDR() may be used to control which SLI streams are secure.
7332
7333 If SLI()_SCTL[SECEN] = 0, this bit is ignored and transactions are always nonsecure
7334 onto the NCB, though the SMMU may later promote them to secure. */
7335 #endif /* Word 0 - End */
7336 } s;
7337 struct bdk_slix_win_wr_addr_cn88xxp1
7338 {
7339 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7340 uint64_t reserved_49_63 : 15;
7341 uint64_t wr_addr : 46; /**< [ 48: 3](R/W) The IOVA sent to the NCB for this store request. */
7342 uint64_t reserved_0_2 : 3;
7343 #else /* Word 0 - Little Endian */
7344 uint64_t reserved_0_2 : 3;
7345 uint64_t wr_addr : 46; /**< [ 48: 3](R/W) The IOVA sent to the NCB for this store request. */
7346 uint64_t reserved_49_63 : 15;
7347 #endif /* Word 0 - End */
7348 } cn88xxp1;
7349 /* struct bdk_slix_win_wr_addr_s cn81xx; */
7350 /* struct bdk_slix_win_wr_addr_s cn88xxp2; */
7351 };
7352 typedef union bdk_slix_win_wr_addr bdk_slix_win_wr_addr_t;
7353
7354 static inline uint64_t BDK_SLIX_WIN_WR_ADDR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SLIX_WIN_WR_ADDR(unsigned long a)7355 static inline uint64_t BDK_SLIX_WIN_WR_ADDR(unsigned long a)
7356 {
7357 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
7358 return 0ll + 0x10000000000ll * ((a) & 0x0);
7359 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
7360 return 0ll + 0x10000000000ll * ((a) & 0x1);
7361 __bdk_csr_fatal("SLIX_WIN_WR_ADDR", 1, a, 0, 0, 0);
7362 }
7363
7364 #define typedef_BDK_SLIX_WIN_WR_ADDR(a) bdk_slix_win_wr_addr_t
7365 #define bustype_BDK_SLIX_WIN_WR_ADDR(a) BDK_CSR_TYPE_PEXP
7366 #define basename_BDK_SLIX_WIN_WR_ADDR(a) "SLIX_WIN_WR_ADDR"
7367 #define busnum_BDK_SLIX_WIN_WR_ADDR(a) (a)
7368 #define arguments_BDK_SLIX_WIN_WR_ADDR(a) (a),-1,-1,-1
7369
7370 /**
7371 * Register (PEXP) sli#_win_wr_addr#
7372 *
7373 * SLI Window Write Address Register
7374 * Contains the address to be written to when a write operation is started by writing
7375 * SLI()_WIN_WR_DATA().
7376 * This register should not be used to write SLI_* registers.
7377 */
7378 union bdk_slix_win_wr_addrx
7379 {
7380 uint64_t u;
7381 struct bdk_slix_win_wr_addrx_s
7382 {
7383 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7384 uint64_t secen : 1; /**< [ 63: 63](R/W) This request is a secure-world transaction. This is intended to be set only for
7385 transactions during early boot when the SMMU is in bypass mode; after SMMU
7386 initialization SMMU()_SSDR() may be used to control which SLI streams are secure.
7387
7388 If SLI()_SCTL[SCEN] = 0, this bit is ignored and transactions are always nonsecure
7389 onto the NCB, though the SMMU may later promote them to secure. */
7390 uint64_t reserved_49_62 : 14;
7391 uint64_t wr_addr : 46; /**< [ 48: 3](R/W) The IOVA sent to the NCB for this store request. */
7392 uint64_t reserved_0_2 : 3;
7393 #else /* Word 0 - Little Endian */
7394 uint64_t reserved_0_2 : 3;
7395 uint64_t wr_addr : 46; /**< [ 48: 3](R/W) The IOVA sent to the NCB for this store request. */
7396 uint64_t reserved_49_62 : 14;
7397 uint64_t secen : 1; /**< [ 63: 63](R/W) This request is a secure-world transaction. This is intended to be set only for
7398 transactions during early boot when the SMMU is in bypass mode; after SMMU
7399 initialization SMMU()_SSDR() may be used to control which SLI streams are secure.
7400
7401 If SLI()_SCTL[SCEN] = 0, this bit is ignored and transactions are always nonsecure
7402 onto the NCB, though the SMMU may later promote them to secure. */
7403 #endif /* Word 0 - End */
7404 } s;
7405 /* struct bdk_slix_win_wr_addrx_s cn; */
7406 };
7407 typedef union bdk_slix_win_wr_addrx bdk_slix_win_wr_addrx_t;
7408
7409 static inline uint64_t BDK_SLIX_WIN_WR_ADDRX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_WIN_WR_ADDRX(unsigned long a,unsigned long b)7410 static inline uint64_t BDK_SLIX_WIN_WR_ADDRX(unsigned long a, unsigned long b)
7411 {
7412 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=3)))
7413 return 0x2c000ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x3);
7414 __bdk_csr_fatal("SLIX_WIN_WR_ADDRX", 2, a, b, 0, 0);
7415 }
7416
7417 #define typedef_BDK_SLIX_WIN_WR_ADDRX(a,b) bdk_slix_win_wr_addrx_t
7418 #define bustype_BDK_SLIX_WIN_WR_ADDRX(a,b) BDK_CSR_TYPE_PEXP
7419 #define basename_BDK_SLIX_WIN_WR_ADDRX(a,b) "SLIX_WIN_WR_ADDRX"
7420 #define busnum_BDK_SLIX_WIN_WR_ADDRX(a,b) (a)
7421 #define arguments_BDK_SLIX_WIN_WR_ADDRX(a,b) (a),(b),-1,-1
7422
7423 /**
7424 * Register (PEXP) sli#_win_wr_data
7425 *
7426 * SLI Window Write Data Register
7427 * This register contains the data to write to the address located in SLI()_WIN_WR_ADDR.
7428 * Writing this register causes a write operation to take place.
7429 */
7430 union bdk_slix_win_wr_data
7431 {
7432 uint64_t u;
7433 struct bdk_slix_win_wr_data_s
7434 {
7435 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7436 uint64_t wr_data : 64; /**< [ 63: 0](R/W) The data to be written. */
7437 #else /* Word 0 - Little Endian */
7438 uint64_t wr_data : 64; /**< [ 63: 0](R/W) The data to be written. */
7439 #endif /* Word 0 - End */
7440 } s;
7441 /* struct bdk_slix_win_wr_data_s cn; */
7442 };
7443 typedef union bdk_slix_win_wr_data bdk_slix_win_wr_data_t;
7444
7445 static inline uint64_t BDK_SLIX_WIN_WR_DATA(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SLIX_WIN_WR_DATA(unsigned long a)7446 static inline uint64_t BDK_SLIX_WIN_WR_DATA(unsigned long a)
7447 {
7448 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
7449 return 0x20ll + 0x10000000000ll * ((a) & 0x0);
7450 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
7451 return 0x20ll + 0x10000000000ll * ((a) & 0x1);
7452 __bdk_csr_fatal("SLIX_WIN_WR_DATA", 1, a, 0, 0, 0);
7453 }
7454
7455 #define typedef_BDK_SLIX_WIN_WR_DATA(a) bdk_slix_win_wr_data_t
7456 #define bustype_BDK_SLIX_WIN_WR_DATA(a) BDK_CSR_TYPE_PEXP
7457 #define basename_BDK_SLIX_WIN_WR_DATA(a) "SLIX_WIN_WR_DATA"
7458 #define busnum_BDK_SLIX_WIN_WR_DATA(a) (a)
7459 #define arguments_BDK_SLIX_WIN_WR_DATA(a) (a),-1,-1,-1
7460
7461 /**
7462 * Register (PEXP) sli#_win_wr_data#
7463 *
7464 * SLI Window Write Data Register
7465 * This register contains the data to write to the address located in SLI()_WIN_WR_ADDR().
7466 * Writing this register causes a write operation to take place.
7467 */
7468 union bdk_slix_win_wr_datax
7469 {
7470 uint64_t u;
7471 struct bdk_slix_win_wr_datax_s
7472 {
7473 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7474 uint64_t wr_data : 64; /**< [ 63: 0](R/W) The data to be written. */
7475 #else /* Word 0 - Little Endian */
7476 uint64_t wr_data : 64; /**< [ 63: 0](R/W) The data to be written. */
7477 #endif /* Word 0 - End */
7478 } s;
7479 /* struct bdk_slix_win_wr_datax_s cn; */
7480 };
7481 typedef union bdk_slix_win_wr_datax bdk_slix_win_wr_datax_t;
7482
7483 static inline uint64_t BDK_SLIX_WIN_WR_DATAX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_WIN_WR_DATAX(unsigned long a,unsigned long b)7484 static inline uint64_t BDK_SLIX_WIN_WR_DATAX(unsigned long a, unsigned long b)
7485 {
7486 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=3)))
7487 return 0x2c020ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x3);
7488 __bdk_csr_fatal("SLIX_WIN_WR_DATAX", 2, a, b, 0, 0);
7489 }
7490
7491 #define typedef_BDK_SLIX_WIN_WR_DATAX(a,b) bdk_slix_win_wr_datax_t
7492 #define bustype_BDK_SLIX_WIN_WR_DATAX(a,b) BDK_CSR_TYPE_PEXP
7493 #define basename_BDK_SLIX_WIN_WR_DATAX(a,b) "SLIX_WIN_WR_DATAX"
7494 #define busnum_BDK_SLIX_WIN_WR_DATAX(a,b) (a)
7495 #define arguments_BDK_SLIX_WIN_WR_DATAX(a,b) (a),(b),-1,-1
7496
7497 /**
7498 * Register (PEXP) sli#_win_wr_mask
7499 *
7500 * SLI Window Write Mask Register
7501 * This register contains the mask for the data in SLI()_WIN_WR_DATA.
7502 */
7503 union bdk_slix_win_wr_mask
7504 {
7505 uint64_t u;
7506 struct bdk_slix_win_wr_mask_s
7507 {
7508 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7509 uint64_t reserved_8_63 : 56;
7510 uint64_t wr_mask : 8; /**< [ 7: 0](R/W) The byte enables sent to the NCB for this store request. */
7511 #else /* Word 0 - Little Endian */
7512 uint64_t wr_mask : 8; /**< [ 7: 0](R/W) The byte enables sent to the NCB for this store request. */
7513 uint64_t reserved_8_63 : 56;
7514 #endif /* Word 0 - End */
7515 } s;
7516 /* struct bdk_slix_win_wr_mask_s cn; */
7517 };
7518 typedef union bdk_slix_win_wr_mask bdk_slix_win_wr_mask_t;
7519
7520 static inline uint64_t BDK_SLIX_WIN_WR_MASK(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SLIX_WIN_WR_MASK(unsigned long a)7521 static inline uint64_t BDK_SLIX_WIN_WR_MASK(unsigned long a)
7522 {
7523 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
7524 return 0x30ll + 0x10000000000ll * ((a) & 0x0);
7525 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
7526 return 0x30ll + 0x10000000000ll * ((a) & 0x1);
7527 __bdk_csr_fatal("SLIX_WIN_WR_MASK", 1, a, 0, 0, 0);
7528 }
7529
7530 #define typedef_BDK_SLIX_WIN_WR_MASK(a) bdk_slix_win_wr_mask_t
7531 #define bustype_BDK_SLIX_WIN_WR_MASK(a) BDK_CSR_TYPE_PEXP
7532 #define basename_BDK_SLIX_WIN_WR_MASK(a) "SLIX_WIN_WR_MASK"
7533 #define busnum_BDK_SLIX_WIN_WR_MASK(a) (a)
7534 #define arguments_BDK_SLIX_WIN_WR_MASK(a) (a),-1,-1,-1
7535
7536 /**
7537 * Register (PEXP) sli#_win_wr_mask#
7538 *
7539 * SLI Window Write Mask Register
7540 * This register contains the mask for the data in SLI()_WIN_WR_DATA().
7541 */
7542 union bdk_slix_win_wr_maskx
7543 {
7544 uint64_t u;
7545 struct bdk_slix_win_wr_maskx_s
7546 {
7547 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7548 uint64_t reserved_8_63 : 56;
7549 uint64_t wr_mask : 8; /**< [ 7: 0](R/W) The byte enables sent to the NCB for this store request. */
7550 #else /* Word 0 - Little Endian */
7551 uint64_t wr_mask : 8; /**< [ 7: 0](R/W) The byte enables sent to the NCB for this store request. */
7552 uint64_t reserved_8_63 : 56;
7553 #endif /* Word 0 - End */
7554 } s;
7555 /* struct bdk_slix_win_wr_maskx_s cn; */
7556 };
7557 typedef union bdk_slix_win_wr_maskx bdk_slix_win_wr_maskx_t;
7558
7559 static inline uint64_t BDK_SLIX_WIN_WR_MASKX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SLIX_WIN_WR_MASKX(unsigned long a,unsigned long b)7560 static inline uint64_t BDK_SLIX_WIN_WR_MASKX(unsigned long a, unsigned long b)
7561 {
7562 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a==0) && (b<=3)))
7563 return 0x2c030ll + 0x1000000000ll * ((a) & 0x0) + 0x800000ll * ((b) & 0x3);
7564 __bdk_csr_fatal("SLIX_WIN_WR_MASKX", 2, a, b, 0, 0);
7565 }
7566
7567 #define typedef_BDK_SLIX_WIN_WR_MASKX(a,b) bdk_slix_win_wr_maskx_t
7568 #define bustype_BDK_SLIX_WIN_WR_MASKX(a,b) BDK_CSR_TYPE_PEXP
7569 #define basename_BDK_SLIX_WIN_WR_MASKX(a,b) "SLIX_WIN_WR_MASKX"
7570 #define busnum_BDK_SLIX_WIN_WR_MASKX(a,b) (a)
7571 #define arguments_BDK_SLIX_WIN_WR_MASKX(a,b) (a),(b),-1,-1
7572
7573 #endif /* __BDK_CSRS_SLI_H__ */
7574