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Searched refs:MSR_IA32_MISC_ENABLE (Results 1 – 8 of 8) sorted by relevance

/aosp_15_r20/external/crosvm/x86_64/src/
H A Dregs.rs153 crate::msr_index::MSR_IA32_MISC_ENABLE, in set_default_msrs()
174 crate::msr_index::MSR_IA32_MISC_ENABLE, in set_long_mode_msrs()
H A Dmsr_index.rs334 pub const MSR_IA32_MISC_ENABLE: ::std::os::raw::c_uint = 0x000001a0; constant
/aosp_15_r20/external/linux-kselftest/tools/testing/selftests/kvm/x86_64/
H A Dmonitor_mwait_test.c124 vcpu_set_msr(vcpu, MSR_IA32_MISC_ENABLE, in main()
/aosp_15_r20/prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.17-4.8/sysroot/usr/include/x86_64-linux-gnu/asm/
Dmsr-index.h317 #define MSR_IA32_MISC_ENABLE 0x000001a0 macro
/aosp_15_r20/prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.17-4.8/sysroot/usr/include/i386-linux-gnu/asm/
Dmsr-index.h317 #define MSR_IA32_MISC_ENABLE 0x000001a0 macro
/aosp_15_r20/external/coreboot/src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Register/Intel/
H A DArchitecturalMsr.h1439 #define MSR_IA32_MISC_ENABLE 0x000001A0 macro
/aosp_15_r20/external/coreboot/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Register/Intel/
H A DArchitecturalMsr.h1411 #define MSR_IA32_MISC_ENABLE 0x000001A0 macro
/aosp_15_r20/external/coreboot/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/
H A DArchitecturalMsr.h1439 #define MSR_IA32_MISC_ENABLE 0x000001A0 macro