Searched refs:MISC1_CFG_BASE (Results 1 – 14 of 14) sorted by relevance
27 #define MISC1_CFG_BASE (MCU_BIU_BASE + 0xE040) macro28 #define DFD_INTERNAL_CTL (MISC1_CFG_BASE + 0x00)29 #define DFD_INTERNAL_PWR_ON (MISC1_CFG_BASE + 0x08)30 #define DFD_CHAIN_LENGTH0 (MISC1_CFG_BASE + 0x0C)31 #define DFD_INTERNAL_SHIFT_CLK_RATIO (MISC1_CFG_BASE + 0x10)32 #define DFD_CHAIN_LENGTH1 (MISC1_CFG_BASE + 0x1C)33 #define DFD_CHAIN_LENGTH2 (MISC1_CFG_BASE + 0x20)34 #define DFD_CHAIN_LENGTH3 (MISC1_CFG_BASE + 0x24)35 #define DFD_INTERNAL_TEST_SO_0 (MISC1_CFG_BASE + 0x28)36 #define DFD_INTERNAL_NUM_OF_TEST_SO_GROUP (MISC1_CFG_BASE + 0x30)[all …]
30 #define MISC1_CFG_BASE (MCU_BIU_BASE + 0xE040) macro31 #define DFD_INTERNAL_CTL (MISC1_CFG_BASE + 0x00)32 #define DFD_INTERNAL_PWR_ON (MISC1_CFG_BASE + 0x08)33 #define DFD_CHAIN_LENGTH0 (MISC1_CFG_BASE + 0x0C)34 #define DFD_INTERNAL_SHIFT_CLK_RATIO (MISC1_CFG_BASE + 0x10)35 #define DFD_CHAIN_LENGTH1 (MISC1_CFG_BASE + 0x1C)36 #define DFD_CHAIN_LENGTH2 (MISC1_CFG_BASE + 0x20)37 #define DFD_CHAIN_LENGTH3 (MISC1_CFG_BASE + 0x24)38 #define DFD_INTERNAL_TEST_SO_0 (MISC1_CFG_BASE + 0x28)39 #define DFD_INTERNAL_NUM_OF_TEST_SO_GROUP (MISC1_CFG_BASE + 0x30)[all …]
141 ret = mmio_read_32(MISC1_CFG_BASE + arg1); in dfd_smc_dispatcher()147 sync_writel(MISC1_CFG_BASE + arg1, arg2); in dfd_smc_dispatcher()
23 #define MISC1_CFG_BASE (MCU_BIU_BASE + 0xE040) macro24 #define DFD_INTERNAL_CTL (MISC1_CFG_BASE + 0x00)25 #define DFD_INTERNAL_PWR_ON (MISC1_CFG_BASE + 0x08)26 #define DFD_CHAIN_LENGTH0 (MISC1_CFG_BASE + 0x0C)27 #define DFD_INTERNAL_SHIFT_CLK_RATIO (MISC1_CFG_BASE + 0x10)28 #define DFD_CHAIN_LENGTH1 (MISC1_CFG_BASE + 0x1C)29 #define DFD_CHAIN_LENGTH2 (MISC1_CFG_BASE + 0x20)30 #define DFD_CHAIN_LENGTH3 (MISC1_CFG_BASE + 0x24)31 #define DFD_INTERNAL_TEST_SO_0 (MISC1_CFG_BASE + 0x28)32 #define DFD_INTERNAL_NUM_OF_TEST_SO_GROUP (MISC1_CFG_BASE + 0x30)[all …]
124 ret = mmio_read_32(MISC1_CFG_BASE + arg1); in dfd_smc_dispatcher()130 sync_writel(MISC1_CFG_BASE + arg1, arg2); in dfd_smc_dispatcher()
23 #define MISC1_CFG_BASE (MCU_BIU_BASE + 0xA040) macro25 #define DFD_INTERNAL_CTL (MISC1_CFG_BASE + 0x00)26 #define DFD_INTERNAL_PWR_ON (MISC1_CFG_BASE + 0x08)27 #define DFD_CHAIN_LENGTH0 (MISC1_CFG_BASE + 0x0C)28 #define DFD_INTERNAL_SHIFT_CLK_RATIO (MISC1_CFG_BASE + 0x10)29 #define DFD_INTERNAL_TEST_SO_0 (MISC1_CFG_BASE + 0x28)30 #define DFD_INTERNAL_NUM_OF_TEST_SO_GROUP (MISC1_CFG_BASE + 0x30)31 #define DFD_V30_CTL (MISC1_CFG_BASE + 0x48)32 #define DFD_V30_BASE_ADDR (MISC1_CFG_BASE + 0x4C)33 #define DFD_TEST_SI_0 (MISC1_CFG_BASE + 0x58)[all …]
83 ret = mmio_read_32(MISC1_CFG_BASE + arg1); in dfd_smc_dispatcher()89 sync_writel(MISC1_CFG_BASE + arg1, arg2); in dfd_smc_dispatcher()
14 #define MISC1_CFG_BASE 0xb00 macro16 #define DFD_INTERNAL_CTL (MCU_BIU_BASE + MISC1_CFG_BASE + 0x00)
27 ret = mmio_read_32(MISC1_CFG_BASE + arg1); in dfd_smc_dispatcher()33 sync_writel(MISC1_CFG_BASE + arg1, arg2); in dfd_smc_dispatcher()