Searched refs:LogicOpcode (Results 1 – 5 of 5) sorted by relevance
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 1529 unsigned LogicOpcode = LogicMI->getOpcode(); in matchShiftOfShiftedLogic() local
1530 if (LogicOpcode != TargetOpcode::G_AND && LogicOpcode != TargetOpcode::G_OR && in matchShiftOfShiftedLogic()
1531 LogicOpcode != TargetOpcode::G_XOR) in matchShiftOfShiftedLogic()
2722 unsigned LogicOpcode = MI.getOpcode(); in matchHoistLogicOpWithSameOpcodeHands() local
2723 assert(LogicOpcode == TargetOpcode::G_AND || in matchHoistLogicOpWithSameOpcodeHands()
2724 LogicOpcode == TargetOpcode::G_OR || in matchHoistLogicOpWithSameOpcodeHands()
2725 LogicOpcode == TargetOpcode::G_XOR); in matchHoistLogicOpWithSameOpcodeHands()
2755 if (!isLegalOrBeforeLegalizer({LogicOpcode, {XTy, YTy}})) in matchHoistLogicOpWithSameOpcodeHands()
2790 InstructionBuildSteps LogicSteps(LogicOpcode, LogicBuildSteps); in matchHoistLogicOpWithSameOpcodeHands()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 5313 unsigned LogicOpcode = N->getOpcode(); in hoistLogicOpWithSameOpcodeHands() local
5315 assert((LogicOpcode == ISD::AND || LogicOpcode == ISD::OR || in hoistLogicOpWithSameOpcodeHands()
5316 LogicOpcode == ISD::XOR) && "Expected logic opcode"); in hoistLogicOpWithSameOpcodeHands()
5343 !TLI.isOperationLegalOrCustom(LogicOpcode, XVT)) in hoistLogicOpWithSameOpcodeHands()
5348 !TLI.isTypeDesirableForOp(LogicOpcode, XVT)) in hoistLogicOpWithSameOpcodeHands()
5351 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y); in hoistLogicOpWithSameOpcodeHands()
5365 if (LegalOperations && !TLI.isOperationLegal(LogicOpcode, XVT)) in hoistLogicOpWithSameOpcodeHands()
5373 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y); in hoistLogicOpWithSameOpcodeHands()
5385 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y); in hoistLogicOpWithSameOpcodeHands()
5394 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y); in hoistLogicOpWithSameOpcodeHands()
[all …]
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| H A D | TargetLowering.cpp | 4086 unsigned LogicOpcode = Cond == ISD::SETEQ ? ISD::AND : ISD::OR; in simplifySetCCWithCTPOP() local
4087 return DAG.getNode(LogicOpcode, dl, VT, LHS, RHS); in simplifySetCCWithCTPOP()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 4363 unsigned LogicOpcode = N->getOpcode(); in hoistLogicOpWithSameOpcodeHands() local
4365 assert((LogicOpcode == ISD::AND || LogicOpcode == ISD::OR || in hoistLogicOpWithSameOpcodeHands()
4366 LogicOpcode == ISD::XOR) && "Expected logic opcode"); in hoistLogicOpWithSameOpcodeHands()
4393 !TLI.isOperationLegalOrCustom(LogicOpcode, XVT)) in hoistLogicOpWithSameOpcodeHands()
4398 !TLI.isTypeDesirableForOp(LogicOpcode, XVT)) in hoistLogicOpWithSameOpcodeHands()
4401 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y); in hoistLogicOpWithSameOpcodeHands()
4415 if (LegalOperations && !TLI.isOperationLegal(LogicOpcode, XVT)) in hoistLogicOpWithSameOpcodeHands()
4423 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y); in hoistLogicOpWithSameOpcodeHands()
4435 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y); in hoistLogicOpWithSameOpcodeHands()
4444 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y); in hoistLogicOpWithSameOpcodeHands()
[all …]
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| H A D | TargetLowering.cpp | 3210 unsigned LogicOpcode = Cond == ISD::SETEQ ? ISD::AND : ISD::OR; in SimplifySetCC() local
3211 return DAG.getNode(LogicOpcode, dl, VT, LHS, RHS); in SimplifySetCC()
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