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/XiangShan/src/main/scala/xiangshan/cache/dcache/
H A DDCacheWrapper.scala990 …val prefetchArray = Module(new L1PrefetchSourceArray(readPorts = PrefetchArrayReadPort, writePorts… constant
1127 …meta_read_ports.takeRight(backendParams.HyuCnt)).zip(prefetchArray.io.read).foreach { case (p, r) …
1136 extra_meta_resp_ports.zip(prefetchArray.io.resp).foreach { case (p, r) => {
1152 prefetchArray.io.read.last.valid := mainPipe.io.prefetch_flag_write.valid
1153 prefetchArray.io.read.last.bits.idx := mainPipe.io.prefetch_flag_write.bits.idx
1154 prefetchArray.io.read.last.bits.way_en := mainPipe.io.prefetch_flag_write.bits.way_en
1162 val extra_flag_prefetch = Mux1H(extra_flag_way_en, prefetchArray.io.resp.last)
1180 prefetch_flag_write_ports.zip(prefetchArray.io.write).foreach { case (p, w) => w <> p }