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Searched refs:pf_source (Results 1 – 12 of 12) sorted by relevance

/XiangShan/src/main/scala/xiangshan/mem/prefetch/
H A DL1PrefetchInterface.scala58 val pf_source = new L1PrefetchSource constant
H A DL1PrefetchComponent.scala714 l1_pf_req_arb.io.in(i).bits.req.pf_source := l1_array(i).source
792 …en = l1_pf_req_arb.io.out.fire && (l1_pf_req_arb.io.out.bits.req.pf_source.value === L1_HW_PREFETC…
H A DSMSPrefetcher.scala1337 io.l1_req.bits.pf_source.value := L1_HW_PREFETCH_NULL
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/
H A DMainPipe.scala71 val pf_source = UInt(L1PfSourceBits.W) constant
790 miss_req.pf_source := L1_HW_PREFETCH_NULL
864 io.prefetch_flag_write.bits.source := s3_req.pf_source
867 …iss && !isFromL1Prefetch(s2_repl_pf) && s2_repl_coh.isValid() && isFromL1Prefetch(s2_req.pf_source)
870 io.bloom_filter_query.clr.valid := s3_fire && isFromL1Prefetch(s3_req.pf_source)
H A DMissQueue.scala49 val pf_source = UInt(L1PfSourceBits.W) constant
819 io.main_pipe_req.bits.pf_source := req.pf_source
1161 …prefetch := alloc && io.req.valid && !io.req.bits.cancel && isFromL1Prefetch(io.req.bits.pf_source)
/XiangShan/src/main/scala/xiangshan/cache/dcache/storepipe/
H A DStorePipe.scala177 io.miss_req.bits.pf_source := L1_HW_PREFETCH_STORE
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/
H A DLoadPipe.scala423 io.miss_req.bits.pf_source := RegNext(RegNext(io.lsu.pf_source)) // TODO: clock gate
/XiangShan/src/main/scala/xiangshan/mem/
H A DMemBlock.scala624 …outer.l2_pf_sender_opt.get.out.head._1.pf_source := Mux(l1_pf_to_l2.valid, l1_pf_to_l2.bits.source…
875 dcache.io.lsu.load(0).pf_source := vSegmentUnit.io.rdcache.pf_source
887 dcache.io.lsu.load(0).pf_source := loadUnits(0).io.dcache.pf_source
/XiangShan/src/main/scala/xiangshan/mem/pipeline/
H A DHybridUnit.scala294 …io.ldu_io.dcache.pf_source := Mux(s0_hw_prf_select, io.ldu_io.prefetch_req.bits.pf_sou…
H A DLoadUnit.scala418 …io.dcache.pf_source := Mux(s0_hw_prf_select, io.prefetch_req.bits.pf_source.value, L1_…
/XiangShan/src/main/scala/xiangshan/mem/vector/
H A DVSegmentUnit.scala677 io.rdcache.pf_source := LOAD_SOURCE.U
/XiangShan/src/main/scala/xiangshan/cache/dcache/
H A DDCacheWrapper.scala628 val pf_source = Output(UInt(L1PfSourceBits.W)) constant