1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #include <acpi/acpi.h> 4 #include <amdblocks/cpu.h> 5 #include <cpu/amd/msr.h> 6 #include <cpu/cpu.h> 7 #include <cpu/x86/msr.h> 8 #include <stdint.h> 9 10 asmlinkage void bootblock_resume_entry(void); 11 write_resume_eip(void)12void write_resume_eip(void) 13 { 14 msr_t s3_resume_entry = { 15 .raw = (uintptr_t)bootblock_resume_entry, 16 }; 17 18 /* 19 * Writing to the EIP register can only be done once, otherwise a fault is triggered. 20 * When this register is written, it will trigger the microcode to stash the CPU state 21 * (crX , mtrrs, registers, etc) into the CC6 save area. On resume, the state will be 22 * restored and execution will continue at the EIP. 23 */ 24 if (!acpi_is_wakeup_s3()) 25 wrmsr(S3_RESUME_EIP_MSR, s3_resume_entry); 26 } 27