1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <bootstate.h>
4 #include <console/console.h>
5 #include <cpu/cpu.h>
6 #include <device/mmio.h>
7 #include <device/pci_ops.h>
8 #include <fsp/util.h>
9 #include <intelblocks/systemagent.h>
10 #include <intelblocks/vtd.h>
11 #include <lib.h>
12 #include <soc/iomap.h>
13 #include <soc/pci_devs.h>
14
15 /* FSP 2.x VT-d HOB from edk2-platforms */
16 static const uint8_t vtd_pmr_info_data_hob_guid[16] = {
17 0x45, 0x16, 0xb6, 0x6f, 0x68, 0xf1, 0xbe, 0x46,
18 0x80, 0xec, 0xb5, 0x02, 0x38, 0x5e, 0xe7, 0xe7
19 };
20
21 struct vtd_pmr_info_hob {
22 uint32_t protected_low_base;
23 uint32_t protected_low_limit;
24 uint64_t protected_high_base;
25 uint64_t protected_high_limit;
26 } __packed;
27
28 static struct vtd_pmr_info_hob *pmr_hob;
29
is_vtd_enabled(uintptr_t vtd_base)30 static bool is_vtd_enabled(uintptr_t vtd_base)
31 {
32 uint32_t version = vtd_read32(vtd_base, VER_REG);
33
34 if (version == 0 || version == UINT32_MAX) {
35 printk(BIOS_WARNING, "No VT-d @ 0x%08lx\n", vtd_base);
36 return false;
37 }
38
39 printk(BIOS_DEBUG, "VT-d @ 0x%08lx, version %x.%x\n",
40 vtd_base, (version & 0xf0) >> 4, version & 0xf);
41
42 return true;
43 }
44
vtd_get_pmr_alignment_lo(uintptr_t vtd_base)45 static uint32_t vtd_get_pmr_alignment_lo(uintptr_t vtd_base)
46 {
47 uint32_t value;
48
49 vtd_write32(vtd_base, PLMLIMIT_REG, 0xffffffff);
50 value = vtd_read32(vtd_base, PLMLIMIT_REG);
51 value = ~value + 1;
52
53 return value;
54 }
55
vtd_get_pmr_alignment_hi(uintptr_t vtd_base)56 static uint64_t vtd_get_pmr_alignment_hi(uintptr_t vtd_base)
57 {
58 uint64_t value;
59
60 vtd_write64(vtd_base, PHMLIMIT_REG, 0xffffffffffffffffULL);
61 value = vtd_read64(vtd_base, PHMLIMIT_REG);
62 value = ~value + 1ULL;
63 value = value & ((1ULL << (uint32_t)cpu_phys_address_size()) - 1ULL);
64
65 /* The host address width can be different than the sizing of the register.
66 * Simply find the least significant bit set and use it as alignment;
67 */
68 return __ffs64(value);
69 }
70
vtd_set_pmr_low(uintptr_t vtd_base)71 static void vtd_set_pmr_low(uintptr_t vtd_base)
72 {
73 uint32_t pmr_lo_align;
74 uint32_t pmr_lo_limit;
75 /*
76 * Typical PMR alignment is 1MB so we should be good but check just in
77 * case.
78 */
79 pmr_lo_align = vtd_get_pmr_alignment_lo(vtd_base);
80 pmr_lo_limit = pmr_hob->protected_low_limit;
81
82 if (!IS_ALIGNED(pmr_lo_limit, pmr_lo_align)) {
83 pmr_lo_limit = ALIGN_DOWN(pmr_lo_limit, pmr_lo_align);
84 printk(BIOS_WARNING, "PMR limit low not properly aligned, aligning down to %08x\n",
85 pmr_lo_limit);
86 }
87
88 printk(BIOS_INFO, "Setting DMA protection [0x0 - 0x%08x]\n", pmr_lo_limit);
89 vtd_write32(vtd_base, PLMBASE_REG, 0);
90 vtd_write32(vtd_base, PLMLIMIT_REG, pmr_lo_limit - 1);
91 }
92
vtd_set_pmr_high(uintptr_t vtd_base)93 static void vtd_set_pmr_high(uintptr_t vtd_base)
94 {
95 uint64_t pmr_hi_align;
96 uint64_t pmr_hi_limit;
97 /*
98 * Typical PMR alignment is 1MB so we should be good with above 4G
99 * memory but check just in case.
100 */
101 pmr_hi_align = vtd_get_pmr_alignment_hi(vtd_base);
102 pmr_hi_limit = pmr_hob->protected_high_limit;
103
104 /* No memory above 4G? Skip PMR high programming */
105 if (pmr_hi_limit == 0 || pmr_hi_limit < 4ULL * GiB)
106 return;
107
108 if (!IS_ALIGNED(pmr_hi_limit, pmr_hi_align)) {
109 pmr_hi_limit = ALIGN_DOWN(pmr_hi_limit, pmr_hi_align);
110 printk(BIOS_WARNING, "PMR High limit not properly aligned, "
111 "aligning down to %016llx\n",
112 pmr_hi_limit);
113 }
114
115 printk(BIOS_INFO, "Setting DMA protection [0x100000000 - 0x%016llx]\n", pmr_hi_limit);
116 vtd_write64(vtd_base, PHMBASE_REG, 4ULL * GiB);
117 vtd_write64(vtd_base, PHMLIMIT_REG, pmr_hi_limit - 1ULL);
118 }
119
disable_pmr_protection(uintptr_t vtd_base)120 static bool disable_pmr_protection(uintptr_t vtd_base)
121 {
122 if (vtd_read32(vtd_base, PMEN_REG) & PMEN_PRS) {
123 vtd_write32(vtd_base, PMEN_REG, vtd_read32(vtd_base, PMEN_REG) & ~PMEN_EPM);
124 if (vtd_read32(vtd_base, PMEN_REG) & PMEN_PRS) {
125 printk(BIOS_ERR, "Failed to disable existing DMA protection\n");
126 return false;
127 }
128 }
129
130 return true;
131 }
132
enable_pmr_protection(uintptr_t vtd_base)133 static bool enable_pmr_protection(uintptr_t vtd_base)
134 {
135 vtd_write32(vtd_base, PMEN_REG, vtd_read32(vtd_base, PMEN_REG) | PMEN_EPM);
136 if (vtd_read32(vtd_base, PMEN_REG) & PMEN_PRS)
137 return true;
138
139 return false;
140 }
141
locate_pmr_info_hob(void)142 static const void *locate_pmr_info_hob(void)
143 {
144 size_t size;
145 const void *hob;
146
147 if (pmr_hob)
148 return (void *)pmr_hob;
149
150 hob = fsp_find_extension_hob_by_guid(vtd_pmr_info_data_hob_guid, &size);
151
152 if (hob) {
153 pmr_hob = (struct vtd_pmr_info_hob *)hob;
154 printk(BIOS_SPEW, "PMR info HOB:\n"
155 " protected_low_base: %08x\n"
156 " protected_low_limit: %08x\n"
157 " protected_high_base: %016llx\n"
158 " protected_high_limit: %016llx\n",
159 pmr_hob->protected_low_base, pmr_hob->protected_low_limit,
160 pmr_hob->protected_high_base, pmr_hob->protected_high_limit);
161 }
162
163 return hob;
164 }
165
vtd_engine_enable_dma_protection(uintptr_t vtd_base)166 static void vtd_engine_enable_dma_protection(uintptr_t vtd_base)
167 {
168 if (!is_vtd_enabled(vtd_base)) {
169 printk(BIOS_ERR, "Not enabling DMA protection, VT-d not found\n");
170 return;
171 }
172
173 /* At minimum PMR Low must be supported, coreboot executes in 32bit space (for now) */
174 if (!(vtd_read32(vtd_base, CAP_REG) & CAP_PMR_LO)) {
175 printk(BIOS_ERR, "Not enabling DMA protection, PMR registers not supported\n");
176 return;
177 }
178
179 if (!locate_pmr_info_hob()) {
180 printk(BIOS_ERR, "VT-d PMR HOB not found, not enabling DMA protection\n");
181 return;
182 }
183
184 /* If protection is enabled, disable it first */
185 if (!disable_pmr_protection(vtd_base)) {
186 printk(BIOS_ERR, "Not setting DMA protection\n");
187 return;
188 }
189
190 vtd_set_pmr_low(vtd_base);
191
192 if (vtd_read32(vtd_base, CAP_REG) & CAP_PMR_HI)
193 vtd_set_pmr_high(vtd_base);
194
195 if (enable_pmr_protection(vtd_base))
196 printk(BIOS_INFO, "Successfully enabled VT-d PMR DMA protection\n");
197 else
198 printk(BIOS_ERR, "Enabling VT-d PMR DMA protection failed\n");
199 }
200
find_resource_hob_by_addr(const uint64_t addr)201 static const struct hob_resource *find_resource_hob_by_addr(const uint64_t addr)
202 {
203 const struct hob_header *hob_iterator;
204 const struct hob_resource *res;
205
206 if (fsp_hob_iterator_init(&hob_iterator) != CB_SUCCESS) {
207 printk(BIOS_ERR, "Failed to find HOB list\n");
208 return NULL;
209 }
210
211 while (fsp_hob_iterator_get_next_resource(&hob_iterator, &res) == CB_SUCCESS) {
212 if ((res->type == EFI_RESOURCE_MEMORY_RESERVED) && (res->addr == addr))
213 return res;
214 }
215
216 return NULL;
217 }
218
vtd_get_dma_buffer(size_t * size)219 void *vtd_get_dma_buffer(size_t *size)
220 {
221 const struct hob_resource *res;
222
223 if (!CONFIG(ENABLE_EARLY_DMA_PROTECTION))
224 goto no_dma_buffer;
225
226 if (!locate_pmr_info_hob()) {
227 printk(BIOS_ERR, "FSP PMR info HOB not found\n");
228 goto no_dma_buffer;
229 }
230
231 /* PMR low limit will be the DMA buffer base reserved by FSP */
232 res = find_resource_hob_by_addr((uint64_t)pmr_hob->protected_low_limit);
233 if (!res) {
234 printk(BIOS_ERR, "FSP PMR resource HOB not found\n");
235 goto no_dma_buffer;
236 }
237
238 if (size)
239 *size = res->length;
240
241 return (void *)(uintptr_t)res->addr;
242
243 no_dma_buffer:
244 if (size)
245 *size = 0;
246 return NULL;
247 }
248
vtd_enable_dma_protection(void)249 void vtd_enable_dma_protection(void)
250 {
251 if (!CONFIG(ENABLE_EARLY_DMA_PROTECTION))
252 return;
253
254 vtd_engine_enable_dma_protection(VTVC0_BASE_ADDRESS);
255 /*
256 * FIXME: GFX VT-d will fail to set PMR (tested on ADL-S).
257 * Should we program PMRs on all VT-d engines?
258 * vtd_engine_enable_dma_protection(GFXVT_BASE_ADDRESS);
259 * vtd_engine_enable_dma_protection(IPUVT_BASE_ADDRESS);
260 */
261 }
262
vtd_disable_pmr_on_resume(void * unused)263 static void vtd_disable_pmr_on_resume(void *unused)
264 {
265 /* At minimum PMR Low must be supported */
266 if (!(vtd_read32(VTVC0_BASE_ADDRESS, CAP_REG) & CAP_PMR_LO))
267 return;
268
269 if (disable_pmr_protection(VTVC0_BASE_ADDRESS)) {
270 vtd_write32(VTVC0_BASE_ADDRESS, PLMBASE_REG, 0);
271 vtd_write32(VTVC0_BASE_ADDRESS, PLMLIMIT_REG, 0);
272 if (vtd_read32(VTVC0_BASE_ADDRESS, CAP_REG) & CAP_PMR_HI) {
273 vtd_write64(VTVC0_BASE_ADDRESS, PHMBASE_REG, 0);
274 vtd_write64(VTVC0_BASE_ADDRESS, PHMLIMIT_REG, 0);
275 }
276 }
277 }
278
279 BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, vtd_disable_pmr_on_resume, NULL);
280