1 /* 2 * Copyright (c) 2018-2022, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #ifndef __VP_VEBOX_COMMON_H__ 23 #define __VP_VEBOX_COMMON_H__ 24 25 #include "mhw_vebox.h" 26 #include "vp_common.h" 27 #include "vp_filter.h" 28 29 typedef class MhwVeboxInterface *PMHW_VEBOX_INTERFACE; 30 31 typedef struct _VP_VEBOX_SURFACE_STATE_CMD_PARAMS 32 { 33 PVP_SURFACE pSurfInput; 34 PVP_SURFACE pSurfOutput; 35 PVP_SURFACE pSurfSTMM; 36 PVP_SURFACE pSurfDNOutput; 37 PVP_SURFACE pSurfSkinScoreOutput; 38 bool bDIEnable; 39 bool b3DlutEnable; 40 } VP_VEBOX_SURFACE_STATE_CMD_PARAMS, *PVP_VEBOX_SURFACE_STATE_CMD_PARAMS; 41 42 enum GFX_MEDIA_VEBOX_DI_OUTPUT_MODE 43 { 44 MEDIA_VEBOX_DI_OUTPUT_BOTH = 0, 45 MEDIA_VEBOX_DI_OUTPUT_PREVIOUS = 1, 46 MEDIA_VEBOX_DI_OUTPUT_CURRENT = 2 47 }; 48 49 enum MEDIASTATE_GCC_BASIC_MODE_SELECTION 50 { 51 MEDIASTATE_GCC_DEFAULT = 0, 52 MEDIASTATE_GCC_SCALING_FACTOR, 53 MEDIASTATE_GCC_SINGLE_AXIS_GAMMA_CORRECTION, 54 MEDIASTATE_GCC_SCALING_FACTOR_WITH_FIXED_LUMA 55 }; 56 57 class VpVeboxRenderData 58 { 59 public: ~VpVeboxRenderData()60 virtual ~VpVeboxRenderData() 61 { 62 if (pAceCacheData) 63 { 64 MOS_FreeMemAndSetNull(pAceCacheData); 65 } 66 } 67 Init()68 virtual MOS_STATUS Init() 69 { 70 MHW_ACE_PARAMS aceParams = {}; 71 PerfTag = VPHAL_NONE; 72 73 DN.value = 0; 74 DI.value = 0; 75 IECP.STE.value = 0; 76 IECP.ACE.value = 0; 77 IECP.TCC.value = 0; 78 IECP.PROCAMP.value = 0; 79 IECP.LACE.value = 0; 80 IECP.CGC.value = 0; 81 82 VP_PUBLIC_CHK_STATUS_RETURN(MOS_SecureMemcpy(&aceParams, 83 sizeof(MHW_ACE_PARAMS), 84 &m_veboxIecpParams.AceParams, 85 sizeof(MHW_ACE_PARAMS))); 86 87 MOS_ZeroMemory(&m_veboxDNDIParams, sizeof(MHW_VEBOX_DNDI_PARAMS)); 88 MOS_ZeroMemory(&m_veboxIecpParams, sizeof(MHW_VEBOX_IECP_PARAMS)); 89 MOS_ZeroMemory(&m_veboxGamutParams, sizeof(MHW_VEBOX_GAMUT_PARAMS)); 90 MOS_ZeroMemory(&m_HvsParams, sizeof(VPHAL_HVSDENOISE_PARAMS)); 91 MOS_ZeroMemory(&HDR3DLUT, sizeof(HDR3DLUT)); 92 93 VP_PUBLIC_CHK_STATUS_RETURN(MOS_SecureMemcpy(&m_veboxIecpParams.AceParams, 94 sizeof(MHW_ACE_PARAMS), 95 &aceParams, 96 sizeof(MHW_ACE_PARAMS))); 97 98 VP_PUBLIC_CHK_STATUS_RETURN(InitChromaSampling()); 99 100 return MOS_STATUS_SUCCESS; 101 } 102 GetHVSParams()103 virtual VPHAL_HVSDENOISE_PARAMS &GetHVSParams() 104 { 105 return m_HvsParams; 106 } 107 GetDNDIParams()108 virtual MHW_VEBOX_DNDI_PARAMS &GetDNDIParams() 109 { 110 return m_veboxDNDIParams; 111 } 112 GetIECPParams()113 virtual MHW_VEBOX_IECP_PARAMS &GetIECPParams() 114 { 115 return m_veboxIecpParams; 116 } 117 GetChromaSubSamplingParams()118 virtual MHW_VEBOX_CHROMA_SAMPLING &GetChromaSubSamplingParams() 119 { 120 return m_chromaSampling; 121 } 122 GetGamutParams()123 virtual MHW_VEBOX_GAMUT_PARAMS &GetGamutParams() 124 { 125 return m_veboxGamutParams; 126 } 127 IsDiEnabled()128 bool IsDiEnabled() 129 { 130 return DI.bDeinterlace || DI.bQueryVariance; 131 } 132 133 union 134 { 135 struct 136 { 137 uint32_t bDnEnabled : 1; // DN enabled; 138 uint32_t bAutoDetect : 1; // Auto DN enabled 139 uint32_t bChromaDnEnabled : 1; // Chroma DN Enabled 140 uint32_t bHvsDnEnabled : 1; // HVS DN Enabled 141 }; 142 uint32_t value = 0; 143 } DN; 144 145 union 146 { 147 struct 148 { 149 uint32_t bDeinterlace : 1; // DN enabled; 150 uint32_t bQueryVariance : 1; // DN enabled; 151 uint32_t bFmdEnabled : 1; // FMD enabled; 152 uint32_t bTFF : 1; 153 }; 154 uint32_t value = 0; 155 } DI; 156 157 union 158 { 159 struct 160 { 161 bool bHdr3DLut; //!< Enable 3DLut to process HDR 162 bool bUseVEHdrSfc; //!< Use SFC to perform CSC/Scaling for HDR content 163 bool is3DLutTableFilled; //!< 3DLut is filled by kernel/ 164 bool is3DLutTableUpdatedByKernel; //!< 3DLut is updated by kernel/ 165 bool isExternal3DLutTable; //!< 3DLut is updated by API/ 166 uint32_t uiMaxDisplayLum; //!< Maximum Display Luminance 167 uint32_t uiMaxContentLevelLum; //!< Maximum Content Level Luminance 168 VPHAL_HDR_MODE hdrMode; 169 uint32_t uiLutSize; 170 MOS_RESOURCE external3DLutSurfResource; 171 }; 172 } HDR3DLUT; 173 struct 174 { 175 union 176 { 177 struct 178 { 179 uint32_t bProcampEnabled : 1; // STE enabled; 180 }; 181 uint32_t value = 0; 182 } PROCAMP; 183 184 union 185 { 186 struct 187 { 188 uint32_t bSteEnabled : 1; // STE enabled; 189 uint32_t bStdEnabled : 1; // STD enabled; This flag is for vebox std alone case. 190 }; 191 uint32_t value = 0; 192 } STE; 193 194 union 195 { 196 struct 197 { 198 uint32_t bTccEnabled : 1; // TCC enabled; 199 }; 200 uint32_t value = 0; 201 } TCC; 202 203 union 204 { 205 struct 206 { 207 uint32_t bAceEnabled : 1; // ACE enabled; 208 uint32_t bAceHistogramEnabled : 1; // ACE histogram enabled, should be set to 1 when bAceEnabled == 1; 209 }; 210 uint32_t value = 0; 211 } ACE; 212 213 union 214 { 215 struct 216 { 217 uint32_t bLaceEnabled : 1; // DN enabled; 218 }; 219 uint32_t value = 0; 220 } LACE; 221 222 union 223 { 224 struct 225 { 226 uint32_t bBeCSCEnabled : 1; // Back end CSC enabled; 227 }; 228 uint32_t value = 0; 229 }BeCSC; 230 231 union 232 { 233 struct 234 { 235 uint32_t bCGCEnabled : 1; // Color Gamut Compression enabled; 236 }; 237 uint32_t value = 0; 238 }CGC; 239 IsIecpEnabled__anon4715132d0708240 bool IsIecpEnabled() 241 { 242 return ACE.bAceEnabled || LACE.bLaceEnabled || 243 BeCSC.bBeCSCEnabled || TCC.bTccEnabled || 244 STE.bSteEnabled || PROCAMP.bProcampEnabled || STE.bStdEnabled || CGC.bCGCEnabled; 245 } 246 } IECP; 247 248 249 // Perf 250 VPHAL_PERFTAG PerfTag = VPHAL_NONE; 251 252 uint32_t *pAceCacheData = nullptr; 253 InitChromaSampling()254 virtual MOS_STATUS InitChromaSampling() 255 { 256 MOS_ZeroMemory(&m_chromaSampling, sizeof(MHW_VEBOX_CHROMA_SAMPLING)); 257 m_chromaSampling.BypassChromaUpsampling = 1; 258 m_chromaSampling.ChromaUpsamplingCoSitedHorizontalOffset = 0; 259 m_chromaSampling.ChromaUpsamplingCoSitedVerticalOffset = 0; 260 m_chromaSampling.BypassChromaDownsampling = 1; 261 m_chromaSampling.ChromaDownsamplingCoSitedHorizontalOffset = 0; 262 m_chromaSampling.ChromaDownsamplingCoSitedVerticalOffset = 0; 263 return MOS_STATUS_SUCCESS; 264 } 265 protected: 266 VPHAL_HVSDENOISE_PARAMS m_HvsParams = {}; 267 MHW_VEBOX_DNDI_PARAMS m_veboxDNDIParams = {}; 268 MHW_VEBOX_IECP_PARAMS m_veboxIecpParams = {}; 269 MHW_VEBOX_CHROMA_SAMPLING m_chromaSampling = {}; 270 MHW_VEBOX_GAMUT_PARAMS m_veboxGamutParams = {}; 271 272 MEDIA_CLASS_DEFINE_END(VpVeboxRenderData) 273 }; 274 275 using PVpVeboxRenderData = VpVeboxRenderData*; 276 277 #endif // !__VP_VEBOX_COMMON_H__