1 /*
2 * Copyright (c) 2022, Xilinx, Inc. All rights reserved.
3 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /*
9 * Versal NET IPI agent registers access management
10 */
11
12 #include <lib/utils_def.h>
13 #include <ipi.h>
14 #include <plat_ipi.h>
15
16 /* versal_net ipi configuration table */
17 static const struct ipi_config versal_net_ipi_table[IPI_ID_MAX] = {
18 /* A72 IPI */
19 [IPI_ID_APU] = {
20 .ipi_bit_mask = IPI0_TRIG_BIT,
21 .ipi_reg_base = IPI0_REG_BASE,
22 .secure_only = 0,
23 },
24
25 /* PMC IPI */
26 [IPI_ID_PMC] = {
27 .ipi_bit_mask = PMC_IPI_TRIG_BIT,
28 .ipi_reg_base = IPI0_REG_BASE,
29 .secure_only = IPI_SECURE_MASK,
30 },
31
32 /* RPU0 IPI */
33 [IPI_ID_RPU0] = {
34 .ipi_bit_mask = IPI1_TRIG_BIT,
35 .ipi_reg_base = IPI1_REG_BASE,
36 .secure_only = 0,
37 },
38
39 /* RPU1 IPI */
40 [IPI_ID_RPU1] = {
41 .ipi_bit_mask = IPI2_TRIG_BIT,
42 .ipi_reg_base = IPI2_REG_BASE,
43 .secure_only = 0,
44 },
45
46 /* IPI3 IPI */
47 [IPI_ID_3] = {
48 .ipi_bit_mask = IPI3_TRIG_BIT,
49 .ipi_reg_base = IPI3_REG_BASE,
50 .secure_only = 0,
51 },
52
53 /* IPI4 IPI */
54 [IPI_ID_4] = {
55 .ipi_bit_mask = IPI4_TRIG_BIT,
56 .ipi_reg_base = IPI4_REG_BASE,
57 .secure_only = 0,
58 },
59
60 /* IPI5 IPI */
61 [IPI_ID_5] = {
62 .ipi_bit_mask = IPI5_TRIG_BIT,
63 .ipi_reg_base = IPI5_REG_BASE,
64 .secure_only = 0,
65 },
66
67 /* PMC_NOBUF IPI */
68 [IPI_ID_PMC_NOBUF] = {
69 .ipi_bit_mask = PMC_NOBUF_TRIG_BIT,
70 .ipi_reg_base = PMC_NOBUF_REG_BASE,
71 .secure_only = IPI_SECURE_MASK,
72 },
73
74 /* IPI6 IPI */
75 [IPI_ID_6_NOBUF_95] = {
76 .ipi_bit_mask = IPI6_NOBUF_95_TRIG_BIT,
77 .ipi_reg_base = IPI6_NOBUF_95_REG_BASE,
78 .secure_only = 0,
79 },
80
81 /* IPI1 NO BUF IPI */
82 [IPI_ID_1_NOBUF] = {
83 .ipi_bit_mask = IPI1_NOBUF_TRIG_BIT,
84 .ipi_reg_base = IPI1_NOBUF_REG_BASE,
85 .secure_only = 0,
86 },
87
88 /* IPI2 NO BUF IPI */
89 [IPI_ID_2_NOBUF] = {
90 .ipi_bit_mask = IPI2_NOBUF_TRIG_BIT,
91 .ipi_reg_base = IPI2_NOBUF_REG_BASE,
92 .secure_only = 0,
93 },
94
95 /* IPI3 NO BUF IPI */
96 [IPI_ID_3_NOBUF] = {
97 .ipi_bit_mask = IPI3_NOBUF_TRIG_BIT,
98 .ipi_reg_base = IPI3_NOBUF_REG_BASE,
99 .secure_only = 0,
100 },
101
102 /* IPI4 NO BUF IPI */
103 [IPI_ID_4_NOBUF] = {
104 .ipi_bit_mask = IPI4_NOBUF_TRIG_BIT,
105 .ipi_reg_base = IPI4_NOBUF_REG_BASE,
106 .secure_only = 0,
107 },
108
109 /* IPI5 NO BUF IPI */
110 [IPI_ID_5_NOBUF] = {
111 .ipi_bit_mask = IPI5_NOBUF_TRIG_BIT,
112 .ipi_reg_base = IPI5_NOBUF_REG_BASE,
113 .secure_only = 0,
114 },
115
116 /* IPI6 NO BUF IPI */
117 [IPI_ID_6_NOBUF_101] = {
118 .ipi_bit_mask = IPI6_NOBUF_101_TRIG_BIT,
119 .ipi_reg_base = IPI6_NOBUF_101_REG_BASE,
120 .secure_only = 0,
121 },
122 };
123
124 /* versal_net_ipi_config_table_init() - Initialize versal_net IPI configuration
125 * data.
126 * @ipi_config_table: IPI configuration table.
127 * @ipi_total: Total number of IPI available.
128 *
129 */
versal_net_ipi_config_table_init(void)130 void versal_net_ipi_config_table_init(void)
131 {
132 ipi_config_table_init(versal_net_ipi_table, ARRAY_SIZE(versal_net_ipi_table));
133 }
134