1 /** @file 2 3 Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR> 4 5 Redistribution and use in source and binary forms, with or without modification, 6 are permitted provided that the following conditions are met: 7 8 * Redistributions of source code must retain the above copyright notice, this 9 list of conditions and the following disclaimer. 10 * Redistributions in binary form must reproduce the above copyright notice, this 11 list of conditions and the following disclaimer in the documentation and/or 12 other materials provided with the distribution. 13 * Neither the name of Intel Corporation nor the names of its contributors may 14 be used to endorse or promote products derived from this software without 15 specific prior written permission. 16 17 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 21 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 THE POSSIBILITY OF SUCH DAMAGE. 28 29 **/ 30 31 #ifndef _MEMORY_MAP_DATA_HOB_H_ 32 #define _MEMORY_MAP_DATA_HOB_H_ 33 34 #define MEMORY_MAP_HOB_GUID \ 35 { \ 36 0xf8870015,0x6994,0x4b98,0x95,0xa2,0xbd,0x56,0xda,0x91,0xc0,0x7f \ 37 } 38 39 #ifndef MAX_SOCKET 40 #define MAX_SOCKET 4 41 #endif 42 43 #ifndef MAX_IMC 44 #define MAX_IMC 4 // Maximum memory controllers per socket 45 #endif 46 47 #ifndef MAX_MC_CH 48 #define MAX_MC_CH 2 // Max number of channels per MC (3 for EP) 49 #endif 50 51 #ifndef MAX_CH 52 #define MAX_CH ((MAX_IMC)*(MAX_MC_CH)) // Max channels per socket (worst case EP * EX combination = 16) 53 #endif 54 55 #define MAX_CXL_AMT 0 56 57 #ifndef MAX_UNIQUE_NGN_DIMM_INTERLEAVE 58 #define MAX_UNIQUE_NGN_DIMM_INTERLEAVE 2 // Max number of unique interleaves for NGN DIMM 59 #endif 60 61 #ifndef MAX_SPARE_RANK 62 #define MAX_SPARE_RANK 2 // Max number of spare ranks in a channel 63 #endif 64 65 #ifndef MAX_HBM_IO 66 #define MAX_HBM_IO 4 67 #endif 68 69 #ifndef MAX_DIMM 70 #define MAX_DIMM 2 // Max DIMM per channel 71 #endif 72 73 #ifndef MAX_RANK_DIMM 74 #define MAX_RANK_DIMM 2 75 #endif 76 77 #ifndef MAX_DRAM_CLUSTERS 78 #define MAX_DRAM_CLUSTERS 4 79 #endif 80 81 #ifndef MAX_SAD_RULES 82 #define MAX_SAD_RULES 16 83 #endif 84 85 #ifndef MAX_FPGA_REMOTE_SAD_RULES 86 #define MAX_FPGA_REMOTE_SAD_RULES 2 // Maximum FPGA sockets exists on ICX platform 87 #endif 88 89 #define MAX_SI_SOCKET 8 // Maximum silicon supported socket number 90 91 #define MAX_AMT (MAX_IMC+MAX_CXL_AMT) // Max abstract memory target per socket 92 #define AMT_MAX_NODE ((MAX_AMT)*(MAX_SOCKET)) // Max abstract memory target for all sockets 93 94 // NGN 95 #define NGN_MAX_SERIALNUMBER_STRLEN 4 96 #define NGN_MAX_PARTNUMBER_STRLEN 30 97 #define NGN_FW_VER_LEN 4 98 #define NGN_LOG_TYPE_NUM 2 99 #define NGN_LOG_LEVEL_NUM 2 100 101 /** 102 * Memory channel index conversion macros. 103 * 104 * We got two types of memory channel indexes: 105 * - socket channel - indexes 0..MAX_CH, used in [socket][channel] indexing 106 * - IMC channel - indexes 0..MAX_MC_CH, used in [socket][IMC][channel] indexing 107 * The below defined macros convert one channel index to the other one. 108 */ 109 #define MEM_SKTCH_TO_IMC(SktCh) ((SktCh) / MAX_MC_CH) 110 #define MEM_SKTCH_TO_IMCCH(SktCh) ((SktCh) % MAX_MC_CH) 111 #define MEM_IMCCH_TO_SKTCH(Imc, Ch) ((Imc) * MAX_MC_CH + (Ch)) 112 113 #define MEM_64MB_TO_BYTES(Size64M) ((UINT64)(Size64M) << 26) 114 #define MEM_64MB_TO_KBYTES(Size64M) ((UINT64)(Size64M) << 16) 115 #define MEM_64MB_TO_MBYTES(Size64M) ((UINT64)(Size64M) << 6) 116 #define MEM_64MB_TO_GBYTES(Size64M) ((Size64M) >> 4) 117 #define MEM_BYTES_TO_64MB(SizeB) ((SizeB) >> 26) 118 #define MEM_KBYTES_TO_64MB(SizeKB) ((SizeKB) >> 16) 119 #define MEM_MBYTES_TO_64MB(SizeMB) ((SizeMB) >> 6) 120 121 typedef UINT8 CXL_INTLV_SET_KEY; 122 123 #define FSP_RESERVED1_LEN 77 124 #define FSP_RESERVED2_LEN 2174 125 #define FSP_RESERVED3_LEN 21 126 #define FSP_RESERVED4_LEN 130 127 #define FSP_RESERVED5_LEN 10 128 #define FSP_RESERVED6_LEN 800 129 #pragma pack(1) 130 131 typedef enum { 132 DIMM_RANK_MAP_OUT_UNKNOWN = 0, 133 DIMM_RANK_MAP_OUT_MEM_DECODE, 134 DIMM_RANK_MAP_OUT_POP_POR_VIOLATION, 135 DIMM_RANK_MAP_OUT_RANK_DISABLED, 136 DIMM_RANK_MAP_OUT_ADVMEMTEST_FAILURE, 137 DIMM_RANK_MAP_OUT_MAX 138 } DIMM_RANK_MAP_OUT_REASON; 139 140 struct RankDevice { 141 UINT8 enabled; // 0 = disabled, 1 = enabled 142 UINT8 logicalRank; // Logical Rank number (0 - 7) 143 UINT16 rankSize; // Units of 64 MB 144 }; 145 146 struct PersisentDpaMap 147 { 148 UINT32 perRegionDPAOffset; 149 UINT32 SPALimit; 150 }; 151 152 typedef struct firmwareRev { 153 UINT8 majorVersion; 154 UINT8 minorVersion; 155 UINT8 hotfixVersion; 156 UINT16 buildVersion; 157 } FIRMWARE_REV; 158 159 typedef struct DimmDevice { 160 UINT8 Present; 161 BOOLEAN Enabled; 162 UINT8 DcpmmPresent; // 1 - This is a DCPMM 163 UINT8 X4Present; 164 UINT8 DramIoWidth; // Actual DRAM IO Width (4, 8, 16) 165 UINT8 NumRanks; 166 UINT8 keyByte; 167 UINT8 actKeyByte2; // Actual module type reported by SPD 168 UINT8 actSPDModuleOrg; // Actual number of DRAM ranks and device width 169 UINT8 dimmTs; // Thermal sensor data. 170 UINT16 VolCap; // Volatile capacity (AEP DIMM only) 171 UINT16 nonVolCap; // Non-volatile capacity (AEP DIMM only) 172 UINT16 DimmSize; 173 UINT32 NVmemSize; 174 UINT16 SPDMMfgId; // Module Mfg Id from SPD 175 UINT16 VendorID; 176 UINT16 DeviceID; 177 UINT16 RevisionID; 178 UINT32 perRegionDPA; // DPA of PMEM that Nfit needs 179 struct PersisentDpaMap perDPAMap[MAX_UNIQUE_NGN_DIMM_INTERLEAVE]; // DPA map 180 UINT8 serialNumber[NGN_MAX_SERIALNUMBER_STRLEN]; // Serial Number 181 UINT8 PartNumber[NGN_MAX_PARTNUMBER_STRLEN]; // Part Number 182 UINT8 FirmwareVersionStr[NGN_FW_VER_LEN]; // Used to update the SMBIOS TYPE 17 183 struct firmwareRev FirmwareVersion; // Firmware revision 184 struct RankDevice rankList[MAX_RANK_DIMM]; 185 UINT16 InterfaceFormatCode; 186 UINT16 SubsystemVendorID; 187 UINT16 SubsystemDeviceID; 188 UINT16 SubsystemRevisionID; 189 UINT16 FisVersion; // Firmware Interface Specification version 190 UINT8 DimmSku; // Dimm SKU info 191 UINT8 manufacturingLocation; // Manufacturing location for the NVDIMM 192 UINT16 manufacturingDate; // Date the NVDIMM was manufactured 193 INT32 commonTck; 194 UINT8 EnergyType; // 0: 12V aux power; 1: dedicated backup energy source; 2: no backup energy source 195 BOOLEAN NvDimmNPresent; // JEDEC NVDIMM-N Type Memory Present 196 UINT8 CidBitMap; // SubRankPer CS for DIMM device 197 UINT16 SPDRegVen; // Register Vendor ID in SPD 198 DIMM_RANK_MAP_OUT_REASON MapOutReason; 199 } MEMMAP_DIMM_DEVICE_INFO_STRUCT; 200 201 struct ChannelDevice { 202 UINT8 Enabled; // 0 = channel disabled, 1 = channel enabled 203 UINT8 Features; // Bit mask of features to enable or disable 204 UINT8 MaxDimm; // Number of DIMM 205 UINT8 NumRanks; // Number of ranks on this channel 206 UINT8 chFailed; 207 UINT8 ngnChFailed; 208 UINT8 Is9x4DimmPresent; // 9x4 dimm present indicator 209 UINT8 SpareLogicalRank[MAX_SPARE_RANK]; // Logical rank, selected as Spare 210 UINT8 SparePhysicalRank[MAX_SPARE_RANK]; // Physical rank, selected as spare 211 UINT16 SpareRankSize[MAX_SPARE_RANK]; // spare rank size 212 UINT8 EnabledLogicalRanks; // Bitmap of Logical ranks that are enabled 213 UINT8 DdrPopulationMap; // Bitmap to indicate location of DDR DIMMs within the channel memory slots (BIT0: Ch.D0, BIT1: CH.D1) 214 UINT8 PmemPopulationMap; // Bitmap to indicate location of PMem modules within the channel memory slots (BIT0: Ch.D0, BIT1: CH.D1) 215 MEMMAP_DIMM_DEVICE_INFO_STRUCT DimmInfo[MAX_DIMM]; 216 }; 217 218 struct memcontroller { 219 UINT32 MemSize; 220 }; 221 222 typedef enum { 223 MemTypeNone = 0, 224 MemType1lmDdr, 225 MemType1lmAppDirect, 226 MemType1lmAppDirectReserved, 227 MemType1lmCtrl, 228 MemType1lmHbm, 229 MemTypeNxm, 230 MemType2lmDdrCacheMemoryMode, 231 MemType2lmDdrWbCacheAppDirect, 232 MemType2lmHbmCacheDdr, 233 MemType2lmHbmCacheMemoryMode, 234 MemTypeCxlAccVolatileMem, 235 MemTypeCxlAccPersistentMem, 236 MemTypeFpga, 237 MemTypeCxlExpVolatileMem, 238 MemTypeCxlExpPersistentMem, 239 MemTypeCxl2lmDdrCacheMem, 240 MemTypeCxlHetero, 241 MemTypeMax 242 } MEM_TYPE; 243 244 typedef struct SADTable { 245 UINT8 Enable; // Rule enable 246 MEM_TYPE type; // Bit map of memory region types, See defines 'MEM_TYPE_???' above for bit definitions of the ranges. 247 UINT8 granularity; // Interleave granularities for current SAD entry. Possible interleave granularity options depend on the SAD entry type. Note that SAD entry type BLK Window and CSR/Mailbox/Ctrl region do not support any granularity options 248 UINT32 Base; // Base of the current SAD entry 249 UINT32 Limit; // Limit of the current SAD entry 250 UINT8 ways; // Interleave ways for SAD 251 UINT8 channelInterBitmap[MAX_AMT]; //Bit map to denote which DDR4/NM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved 252 UINT8 FMchannelInterBitmap[MAX_AMT]; //Bit map to denote which FM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved 253 UINT8 NmChWays; // Channel Interleave ways for SAD. Represents channelInterBitmap ways for DDR4/NM. 254 UINT8 FmChWays; // Channel Interleave ways for SAD. Represents FMchannelInterBitmap ways for DDRT. 255 UINT16 imcInterBitmap; // Bit map to denote which IMCs are interleaved from this socket. 256 UINT16 NmImcInterBitmap; // Bit map to denote which IMCs are interleaved from this socket as NM. 257 BOOLEAN local; // 0 - Remote 1- Local 258 UINT8 IotEnabled; // To indicate if IOT is enabled 259 UINT8 mirrored; // To Indicate the SAD is mirrored while enabling partial mirroring 260 UINT8 Attr; 261 UINT8 tgtGranularity; // Interleave mode for target list 262 UINT8 Cluster; // SNC cluster, hemisphere, or quadrant index. 263 UINT8 HostBridgeGran; // Host bridge interleaving granularity. 264 UINT32 HotPlugPadSize; // Memory size padded for CXL hot plug. 0 if it is not a CXL hot plug SAD. 265 CXL_INTLV_SET_KEY CxlIntlvSetKey; // The unique key of CXL interleave set. (7nm) 266 } SAD_TABLE; 267 268 typedef struct socket { 269 UINT8 SocketEnabled; 270 UINT32 IioStackBitmap; 271 BOOLEAN HbmIoEn[MAX_HBM_IO]; // Flag indicates if HBM IO is enabled. TRUE: HBM IO is Enabled, FALSE: HBM IO is disabled. 272 UINT8 imcEnabled[MAX_IMC]; 273 UINT8 SadIntList[MAX_DRAM_CLUSTERS * MAX_SAD_RULES][AMT_MAX_NODE]; // SAD interleave list 274 UINT32 SktTotMemMapSPA; // Total memory mapped to SPA 275 UINT32 SktMemSize2LM; // Total memory excluded from Limit 276 SAD_TABLE SAD[MAX_DRAM_CLUSTERS * MAX_SAD_RULES]; // SAD table 277 struct memcontroller imc[MAX_IMC]; 278 struct ChannelDevice ChannelInfo[MAX_CH]; 279 } MEMMAP_SOCKET; 280 281 typedef struct { 282 UINT8 Enabled; // Indicates if this EDC is enabled 283 UINT32 MemAsCache; // Memory used as Cache, in 64MB units 284 UINT32 MemAsFlat; // Memory used as Flat memory, in 64MB units 285 } EDC_INFO; 286 287 typedef struct SystemMemoryMapElement { 288 UINT16 Type; // Type of this memory element; Bit0: 1LM Bit1: 2LM Bit2: PMEM Bit3: PMEM-cache Bit4: BLK Window Bit5: CSR/Mailbox/Ctrl region 289 UINT8 NodeId; // Node ID of the HA Owning the memory 290 UINT8 SocketId; // Socket Id of socket that has his memory - ONLY IN NUMA 291 UINT8 SktInterBitmap; // Socket interleave bitmap, if more that on socket then ImcInterBitmap and ChInterBitmap are identical in all sockets 292 UINT16 ImcInterBitmap; // IMC interleave bitmap for this memory 293 UINT8 ChInterBitmap[MAX_IMC];//Bit map to denote which channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved 294 UINT32 BaseAddress; // Base Address of the element in 64MB chunks 295 UINT32 ElementSize; // Size of this memory element in 64MB chunks 296 } SYSTEM_MEMORY_MAP_ELEMENT; 297 298 typedef struct SystemMemoryMapHob { 299 // 300 // Total Clusters. In SNC2 mode there are 2 clusters and SNC4 mode has 4 clusters. 301 // All2All/Quad/Hemi modes can be considered as having only one cluster (i.e SNC1). 302 // 303 UINT8 TotalClusters; 304 305 UINT8 reserved1[FSP_RESERVED1_LEN]; // MEMORY_MAP_BLOCK_DECODER_DATA BlockDecoderData; // block decoder data structure 306 UINT32 lowMemBase; // Mem base in 64MB units for below 4GB mem. 307 UINT32 lowMemSize; // Mem size in 64MB units for below 4GB mem. 308 UINT32 highMemBase; // Mem base in 64MB units for above 4GB mem. 309 UINT32 highMemSize; // Mem size in 64MB units for above 4GB mem. 310 UINT32 memSize; // Total physical memory size 311 UINT16 memFreq; // Mem Frequency 312 UINT16 HbmFreq; // HBM Frequency in MHz. 313 UINT8 memMode; // 0 - Independent, 1 - Lockstep 314 UINT8 volMemMode; // 0 - 1LM, 1 - 2LM 315 UINT8 CacheMemType; // 0 - DDR$DDRT, 1 - HBM$DDR. Only valid if volMemMode is 2LM 316 UINT16 DramType; 317 UINT8 DdrVoltage; 318 BOOLEAN SupportedPMemPresent; // TRUE if at least one PMem is present and supported by BIOS 319 BOOLEAN EkvPresent; // Set if EKV controller on system 320 BOOLEAN BwvPresent; // Set if BWV controller on system 321 BOOLEAN CwvPresent; // Set if CWV controller on system 322 UINT8 XMPProfilesSup; 323 UINT8 XMPCapability; 324 // 325 // HBM Specific Info. 326 // 327 UINT16 HbmInstances[MAX_SOCKET]; // Total HBM instances 328 UINT32 HbmFlatMemSize; // Total HBM memory size in 64MB units, if HBM used as Flat memory 329 UINT32 HbmCacheMemSize; // Total HBM memory used as cache, if HBM used as Cache memory 330 UINT16 HbmSpeed; // Configured HBM (i.e OPIO channel) speed in MT/s. 331 UINT16 MaxHbmSpeed; // Max HBM (i.e OPIO channel) speed in MT/s. 332 UINT8 SystemRasType; 333 UINT8 RasModesEnabled; // RAS modes that are enabled 334 UINT16 ExRasModesEnabled; // Extended RAS modes that are enabled 335 UINT8 sncEnabled; // 0 - SNC disabled for this configuration, 1 - SNC enabled for this configuration 336 UINT8 NumOfCluster; 337 UINT8 NumChPerMC; 338 UINT8 numberEntries; // Number of Memory Map Elements 339 SYSTEM_MEMORY_MAP_ELEMENT Element[(MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES) + MAX_FPGA_REMOTE_SAD_RULES]; 340 UINT8 reserved2[FSP_RESERVED2_LEN]; // struct memSetup MemSetup; 341 UINT8 reserved3[FSP_RESERVED3_LEN]; // MEM_DFXMEMVARS DfxMemVar; 342 MEMMAP_SOCKET Socket[MAX_SOCKET]; 343 UINT8 reserved4[FSP_RESERVED4_LEN]; // struct memTiming profileMemTime[XMP_MAX_PROFILES]; 344 345 UINT8 reserved5[FSP_RESERVED5_LEN]; // RASMEMORYINFO RasMeminfo; 346 UINT8 LatchSystemShutdownState; 347 BOOLEAN IsWpqFlushSupported; 348 UINT8 EadrSupport; 349 UINT8 EadrCacheFlushMode; 350 UINT8 SetSecureEraseSktChHob[MAX_SOCKET][MAX_CH]; //MAX_CH * MAX_SOCKET * MAX_DCPMM_CH 351 UINT8 reserved6[FSP_RESERVED6_LEN]; // HOST_DDRT_DIMM_DEVICE_INFO_STRUCT HostDdrtDimmInfo[MAX_SOCKET][MAX_CH]; 352 UINT32 DdrCacheSize[MAX_SOCKET][MAX_CH]; // Size of DDR memory reserved for 2LM cache (64MB granularity) 353 BOOLEAN AdrStateForPmemModule[MAX_SOCKET][MAX_CH]; // ADR state for Intel PMEM Modules 354 UINT16 BiosFisVersion; // Firmware Interface Specification version currently supported by BIOS 355 UINT16 MaxAveragePowerLimit; // Max Power limit in mW used for averaged power ( Valid range ends at 15000mW) 356 UINT16 MinAveragePowerLimit; // Min Power limit in mW used for averaged power ( Valid range starts from 10000mW) 357 UINT16 CurrAveragePowerLimit; // Current Power limit in mW used for average power 358 UINT16 MaxMbbPowerLimit; // Max MBB power limit ( Valid range ends at 18000mW). 359 UINT16 MinMbbPowerLimit; // Min MBB power limit ( Valid range starts from 15000mW). 360 UINT16 CurrMbbPowerLimit; // Current Power limit in mW used for MBB power 361 UINT32 MaxMbbAveragePowerTimeConstant; // Max MBB Average Power Time Constant 362 UINT32 MinMbbAveragePowerTimeConstant; // Min MBB Average Power Time Constant 363 UINT32 CurrMbbAveragePowerTimeConstant; // Current MBB Average Power Time Constant 364 UINT32 MmiohBase; // MMIOH base in 64MB granularity 365 UINT8 MaxSadRules; // Maximum SAD entries supported by silicon (24 for 14nm silicon, 16 for 10nm silicon) 366 UINT8 NumberofChaDramClusters; // Number of CHA DRAM decoder clusters 367 BOOLEAN VirtualNumaEnable; // Enable or Disable Virtual NUMA 368 UINT8 VirtualNumOfCluster; // Number of Virtual NUMA nodes in each physical NUMA node (Socket or SNC cluster) 369 } SYSTEM_MEMORY_MAP_HOB; 370 371 #pragma pack() 372 373 #endif // _MEMORY_MAP_DATA_H_ 374