1 /*
2 *
3 * Copyright (C) 2015 Rockchip Electronics
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15 #include <libpayload.h>
16 #include <assert.h>
17 #include <limits.h>
18
19 #include <udc/dwc2_udc.h>
20 #include "dwc2_priv.h"
21
get_mps(dwc2_ep_t * ep)22 static int get_mps(dwc2_ep_t *ep)
23 {
24 dwc2_ep_reg_t *ep_reg = ep->ep_regs;
25 depctl_t depctl;
26 uint16_t mps = 0;
27
28 depctl.d32 = readl(&ep_reg->depctl);
29 if (ep->ep_num == 0) {
30 switch (depctl.mps) {
31 case D0EPCTL_MPS_64:
32 mps = 64;
33 break;
34 case D0EPCTL_MPS_32:
35 mps = 32;
36 break;
37 case D0EPCTL_MPS_16:
38 mps = 16;
39 break;
40 case D0EPCTL_MPS_8:
41 mps = 8;
42 break;
43 default:
44 usb_debug("get mps error\n");
45 }
46 } else {
47 mps = depctl.mps;
48 }
49
50 return mps;
51 }
52
dwc2_process_ep(dwc2_ep_t * ep,int len,void * buf)53 static void dwc2_process_ep(dwc2_ep_t *ep, int len, void *buf)
54 {
55 depctl_t depctl;
56 depsiz_t depsiz;
57 uint16_t pkt_cnt;
58 uint16_t mps;
59 int max_transfer_size;
60 dwc2_ep_reg_t *ep_reg = ep->ep_regs;
61
62 if (ep->ep_num == 0)
63 max_transfer_size = EP0_MAXLEN;
64 else
65 max_transfer_size = EP_MAXLEN;
66 assert(len <= max_transfer_size);
67
68 mps = get_mps(ep);
69
70 pkt_cnt = ALIGN_UP(len, mps) / mps;
71 if (pkt_cnt == 0)
72 pkt_cnt = 1;
73
74 depsiz.pktcnt = pkt_cnt;
75 depsiz.xfersize = len;
76 writel(depsiz.d32, &ep_reg->deptsiz);
77
78 writel((uint32_t)buf, &ep_reg->depdma);
79
80 depctl.d32 = readl(&ep_reg->depctl);
81
82 if (ep->ep_num != 0) {
83 if (depctl.dpid == 0)
84 depctl.setd0pid = 1;
85 else
86 depctl.setd1pid = 1;
87 }
88 depctl.cnak = 1;
89 depctl.epena = 1;
90 writel(depctl.d32, &ep_reg->depctl);
91
92 }
93
dwc2_write_ep(dwc2_ep_t * ep,int len,void * buf)94 static void dwc2_write_ep(dwc2_ep_t *ep, int len, void *buf)
95 {
96 dwc2_process_ep(ep, len, buf);
97 }
98
dwc2_read_ep(dwc2_ep_t * ep,int len,void * buf)99 static void dwc2_read_ep(dwc2_ep_t *ep, int len, void *buf)
100 {
101 dwc2_process_ep(ep, len, buf);
102 }
103
dwc2_connect(struct usbdev_ctrl * this,int connect)104 static void dwc2_connect(struct usbdev_ctrl *this, int connect)
105 {
106 /* Turn on the USB connection by enabling the pullup resistor */
107 dwc2_pdata_t *p = DWC2_PDATA(this);
108 dctl_t dctl;
109
110 usb_debug("DwcUdcConnect\n");
111
112 dctl.d32 = readl(&p->regs->device.dctl);
113
114 if (connect)
115 /* Connect */
116 dctl.sftdiscon = 0;
117 else
118 /* Disconnect */
119 dctl.sftdiscon = 1;
120
121 writel(dctl.d32, &p->regs->device.dctl);
122 }
123
dwc2_bus_reset(struct usbdev_ctrl * this)124 static void dwc2_bus_reset(struct usbdev_ctrl *this)
125 {
126 dwc2_pdata_t *p = DWC2_PDATA(this);
127 dcfg_t dcfg;
128 dctl_t dctl;
129
130 if (this->initialized)
131 this->initialized = 0;
132
133 /* Reset device addr */
134 dcfg.d32 = readl(&p->regs->device.dcfg);
135 dcfg.devaddr = 0;
136 writel(dcfg.d32, &p->regs->device.dcfg);
137
138 dctl.d32 = readl(&p->regs->device.dctl);
139 dctl.rmtwkupsig = 0;
140 writel(dctl.d32, &p->regs->device.dctl);
141 }
142
dwc2_enum_done(struct usbdev_ctrl * this)143 static void dwc2_enum_done(struct usbdev_ctrl *this)
144 {
145 dwc2_pdata_t *p = DWC2_PDATA(this);
146
147 dctl_t dctl;
148 dsts_t dsts;
149
150 usb_debug("dwc2_enum_done\n");
151
152 dsts.d32 = readl(&p->regs->device.dsts);
153
154 switch (dsts.enumspd) {
155 case 0:
156 this->ep_mps[0][0] = 64;
157 this->ep_mps[0][1] = 64;
158 usb_debug("HighSpeed Enum Done\n");
159 break;
160 default:
161 usb_debug("EnumSpeed Error\n");
162 return;
163 }
164
165 /* Clear global IN Nak */
166 dctl.d32 = readl(&p->regs->device.dctl);
167 dctl.cgnpinnak = 1;
168 writel(dctl.d32, &p->regs->device.dctl);
169 }
170
dwc2_tx_fifo_flush(struct usbdev_ctrl * this,unsigned int idx)171 static void dwc2_tx_fifo_flush(struct usbdev_ctrl *this, unsigned int idx)
172 {
173 dwc2_pdata_t *p = DWC2_PDATA(this);
174 grstctl_t grstctl;
175 int timeout = 100;
176
177 grstctl.d32 = readl(&p->regs->core.grstctl);
178 grstctl.txfflsh = 1;
179 grstctl.txfnum = idx;
180 writel(grstctl.d32, &p->regs->core.grstctl);
181
182 /* wait until the fifo is flushed */
183 do {
184 udelay(1);
185 grstctl.d32 = readl(&p->regs->core.grstctl);
186
187 if (--timeout < 0) {
188 usb_debug("timeout flushing Tx fifo %x\n", idx);
189 break;
190 }
191 } while (grstctl.txfflsh);
192 }
193
dwc2_rx_fifo_flush(struct usbdev_ctrl * this,unsigned int idx)194 static void dwc2_rx_fifo_flush(struct usbdev_ctrl *this, unsigned int idx)
195 {
196 dwc2_pdata_t *p = DWC2_PDATA(this);
197 grstctl_t grstctl;
198 int timeout = 100;
199
200 grstctl.d32 = readl(&p->regs->core.grstctl);
201 grstctl.rxfflsh = 1;
202 writel(grstctl.d32, &p->regs->core.grstctl);
203
204 /* wait until the fifo is flushed */
205 do {
206 udelay(1);
207 grstctl.d32 = readl(&p->regs->core.grstctl);
208
209 if (--timeout < 0) {
210 usb_debug("timeout flushing Rx fifo %x\n", idx);
211 break;
212 }
213 } while (grstctl.rxfflsh);
214 }
215
dwc2_disable_ep(dwc2_ep_reg_t * ep_reg)216 static void dwc2_disable_ep(dwc2_ep_reg_t *ep_reg)
217 {
218 depctl_t depctl;
219 depint_t depint;
220
221 /* Disable the required IN/OUT endpoint */
222 depctl.d32 = readl(&ep_reg->depctl);
223
224 /* Already disabled */
225 if (depctl.epena == 0)
226 return;
227 depctl.epdis = 1;
228 depctl.snak = 1;
229 writel(depctl.d32, &ep_reg->depctl);
230
231 /* Wait for the DEPINTn.EPDisabled interrupt */
232 do {
233 depint.d32 = readl(&ep_reg->depint);
234 } while (!depint.epdisbld);
235
236 /* Clear DEPINTn.EPDisabled */
237 writel(depint.d32, &ep_reg->depint);
238
239 depctl.d32 = readl(&ep_reg->depctl);
240 depctl.epena = 0;
241 depctl.epdis = 0;
242 writel(depctl.d32, &ep_reg->depctl);
243 }
244
dwc2_halt_ep(struct usbdev_ctrl * this,int ep,int in_dir)245 static void dwc2_halt_ep(struct usbdev_ctrl *this, int ep, int in_dir)
246 {
247 dwc2_pdata_t *p = DWC2_PDATA(this);
248 dwc2_ep_reg_t *ep_reg = p->eps[ep][in_dir].ep_regs;
249 depctl_t depctl;
250 dctl_t dctl;
251 gintsts_t gintsts;
252
253 usb_debug("dwc2_halt_ep ep %d-%d\n", ep, in_dir);
254 depctl.d32 = readl(&ep_reg->depctl);
255 /* Already disabled */
256 if (!depctl.epena)
257 return;
258 /* First step: disable EP */
259 if (in_dir) {
260 /* Only support Non-Periodic IN Endpoints */
261 dctl.d32 = readl(&p->regs->device.dctl);
262 dctl.sgnpinnak = 1;
263 writel(dctl.d32, &p->regs->device.dctl);
264
265 /* Wait for the GINTSTS.Global IN NP NAK Effective interrupt */
266 do {
267 gintsts.d32 = readl(&p->regs->core.gintsts);
268 } while (!gintsts.ginnakeff);
269
270 /* Clear GINTSTS.Global IN NP NAK Effective interrupt */
271 writel(gintsts.d32, &p->regs->core.gintsts);
272 dwc2_disable_ep(ep_reg);
273
274 /* Flush Tx Fifo */
275 dwc2_tx_fifo_flush(this, p->eps[ep][in_dir].txfifo);
276
277 } else {
278 /* Enable Global OUT NAK mode */
279 dctl.d32 = readl(&p->regs->device.dctl);
280 dctl.sgoutnak = 1;
281 writel(dctl.d32, &p->regs->device.dctl);
282
283 /* Wait for the GINTSTS.GOUTNakEff interrupt */
284 do {
285 gintsts.d32 = readl(&p->regs->core.gintsts);
286 } while (!gintsts.goutnakeff);
287
288 /* Clear GINTSTS.GOUTNakEff */
289 writel(gintsts.d32, &p->regs->core.gintsts);
290
291 dwc2_disable_ep(ep_reg);
292
293 dctl.d32 = readl(&p->regs->device.dctl);
294 dctl.cgoutnak = 1;
295 dctl.sgoutnak = 0;
296 writel(dctl.d32, &p->regs->device.dctl);
297 }
298
299 /* Second step: clear job queue */
300 while (!SIMPLEQ_EMPTY(&p->eps[ep][in_dir].job_queue)) {
301 struct job *job = SIMPLEQ_FIRST(&p->eps[ep][in_dir].job_queue);
302
303 if (job->autofree)
304 free(job->data);
305
306 SIMPLEQ_REMOVE_HEAD(&p->eps[ep][in_dir].job_queue, queue);
307 }
308 }
309
find_tx_fifo(struct usbdev_ctrl * this,uint32_t mps)310 static int find_tx_fifo(struct usbdev_ctrl *this, uint32_t mps)
311 {
312 dwc2_pdata_t *p = DWC2_PDATA(this);
313 uint32_t fifo_index = 0;
314 uint32_t fifo_size = UINT_MAX;
315 gtxfsiz_t gtxfsiz;
316 int i, val;
317
318 for (i = 1; i < MAX_EPS_CHANNELS - 1; i++) {
319 if (p->fifo_map & (1 << i))
320 continue;
321 gtxfsiz.d32 = readl(&p->regs->core.dptxfsiz_dieptxf[i]);
322 val = gtxfsiz.txfdep * 4;
323
324 if (val < mps)
325 continue;
326 /* Search for smallest acceptable fifo */
327 if (val < fifo_size) {
328 fifo_size = val;
329 fifo_index = i;
330 }
331 }
332
333 if (!fifo_index)
334 fatal("find_tx_fifo no suitable fifo found\n");
335
336 p->fifo_map |= 1 << fifo_index;
337
338 return fifo_index;
339
340 }
341
dwc2_start_ep0(struct usbdev_ctrl * this)342 static void dwc2_start_ep0(struct usbdev_ctrl *this)
343 {
344 dwc2_pdata_t *p = DWC2_PDATA(this);
345 depctl_t depctl = { .d32 = 0 };
346 depint_t depint = { .d32 = 0xff };
347
348 usb_debug("dwc2_start_ep0\n");
349
350 /* Enable endpoint, reset data toggle */
351 depctl.mps = 0;
352 depctl.usbactep = 1;
353 depctl.snak = 1;
354 depctl.epdis = 1;
355
356 writel(depctl.d32, &p->regs->device.inep[0].depctl);
357 writel(depint.d32, &p->regs->device.inep[0].depint);
358 writel(depctl.d32, &p->regs->device.outep[0].depctl);
359 writel(depint.d32, &p->regs->device.outep[0].depint);
360
361 p->eps[0][0].busy = 0;
362 p->eps[0][1].busy = 0;
363 this->ep_mps[0][0] = 64;
364 this->ep_mps[0][1] = 64;
365 }
366
dwc2_start_ep(struct usbdev_ctrl * this,int ep,int in_dir,int ep_type,int mps)367 static void dwc2_start_ep(struct usbdev_ctrl *this,
368 int ep, int in_dir, int ep_type, int mps)
369 {
370 dwc2_pdata_t *p = DWC2_PDATA(this);
371 dwc2_ep_reg_t *ep_reg = p->eps[ep][in_dir].ep_regs;
372 depctl_t depctl = { .d32 = 0 };
373
374 assert((ep < 16) && (ep > 0));
375 usb_debug("dwc2_start_ep %d-%d (type %d)\n", ep, in_dir, ep_type);
376
377 in_dir = in_dir ? 1 : 0;
378
379 /* Enable endpoint, reset data toggle */
380 depctl.setd0pid = 1;
381 depctl.mps = mps & 0x3ff;
382 depctl.usbactep = 1;
383
384 /* ep type 0:ctrl 1:isoc 2:bulk 3:intr */
385 depctl.eptype = ep_type;
386 depctl.snak = 1;
387 if (in_dir) {
388 /* Allocate Tx FIFO */
389 p->eps[ep][in_dir].txfifo = find_tx_fifo(this, mps);
390 }
391 writel(depctl.d32, &ep_reg->depctl);
392
393 p->eps[ep][in_dir].busy = 0;
394 this->ep_mps[ep][in_dir] = mps;
395 }
396
continue_ep_transfer(dwc2_pdata_t * p,int endpoint,int in_dir)397 static void continue_ep_transfer(dwc2_pdata_t *p,
398 int endpoint, int in_dir)
399 {
400 int max_transfer_size = (endpoint == 0) ? EP0_MAXLEN : EP_MAXLEN;
401 int mps;
402 uint32_t remind_length;
403 void *data_buf;
404
405 if (SIMPLEQ_EMPTY(&p->eps[endpoint][in_dir].job_queue))
406 return;
407
408 struct job *job = SIMPLEQ_FIRST(&p->eps[endpoint][in_dir].job_queue);
409
410 remind_length = job->length - job->xfered_length;
411
412 job->xfer_length = (remind_length > max_transfer_size) ?
413 max_transfer_size : remind_length;
414 data_buf = job->data + job->xfered_length;
415
416 if ((((uint32_t)data_buf & 3) != 0) && (job->xfer_length > 0))
417 usb_debug("Un-aligned buffer address\n");
418
419 if (in_dir) {
420 dwc2_write_ep(&p->eps[endpoint][in_dir],
421 job->xfer_length, data_buf);
422 } else {
423 mps = get_mps(&p->eps[endpoint][in_dir]);
424 job->xfer_length = ALIGN_UP(job->xfer_length, mps);
425 dwc2_read_ep(&p->eps[endpoint][0], job->xfer_length, data_buf);
426 }
427 }
428
start_ep_transfer(dwc2_pdata_t * p,int endpoint,int in_dir)429 static void start_ep_transfer(dwc2_pdata_t *p,
430 int endpoint, int in_dir)
431 {
432 int max_transfer_size = (endpoint == 0) ? EP0_MAXLEN : EP_MAXLEN;
433 int mps;
434
435 if (p->eps[endpoint][in_dir].busy) {
436 usb_debug("ep %d-%d busy\n", endpoint, in_dir);
437 return;
438 }
439
440 if (SIMPLEQ_EMPTY(&p->eps[endpoint][in_dir].job_queue)) {
441 usb_debug("ep %d-%d empty\n", endpoint, in_dir);
442 return;
443 }
444
445 struct job *job = SIMPLEQ_FIRST(&p->eps[endpoint][in_dir].job_queue);
446
447 job->xfer_length = (job->length > max_transfer_size) ?
448 max_transfer_size : job->length;
449
450 if (in_dir) {
451 dwc2_write_ep(&p->eps[endpoint][1], job->xfer_length, job->data);
452 } else {
453 mps = get_mps(&p->eps[endpoint][0]);
454 job->xfer_length = ALIGN_UP(job->xfer_length, mps);
455 /* BUG */
456 if ((endpoint == 0) && (job->length == 0))
457 job->data = p->setup_buf;
458 dwc2_read_ep(&p->eps[endpoint][0], job->xfer_length, job->data);
459 }
460
461 usb_debug("start EP %d-%d with %zx bytes starting at %p\n", endpoint,
462 in_dir, job->length, job->data);
463
464 p->eps[endpoint][in_dir].busy = 1;
465 }
466
dwc2_enqueue_packet(struct usbdev_ctrl * this,int endpoint,int in_dir,void * data,int len,int zlp,int autofree)467 static void dwc2_enqueue_packet(struct usbdev_ctrl *this, int endpoint,
468 int in_dir, void *data, int len, int zlp, int autofree)
469 {
470 dwc2_pdata_t *p = DWC2_PDATA(this);
471 struct job *job = xzalloc(sizeof(*job));
472
473 job->data = data;
474 job->length = len;
475 job->zlp = zlp;
476 job->autofree = autofree;
477
478 usb_debug("adding job %d bytes to EP %d-%d\n", len, endpoint, in_dir);
479 SIMPLEQ_INSERT_TAIL(&p->eps[endpoint][in_dir].job_queue, job, queue);
480
481 if ((endpoint == 0) || (this->initialized))
482 start_ep_transfer(p, endpoint, in_dir);
483 }
484
complete_ep_transfer(struct usbdev_ctrl * this,int endpoint,int in_dir,int xfer_result)485 static void complete_ep_transfer(struct usbdev_ctrl *this, int endpoint,
486 int in_dir, int xfer_result)
487 {
488 dwc2_pdata_t *p = DWC2_PDATA(this);
489 struct job *job = SIMPLEQ_FIRST(&p->eps[endpoint][in_dir].job_queue);
490 int mps = this->ep_mps[endpoint][in_dir];
491
492 if (in_dir) {
493 job->xfered_length += job->xfer_length - xfer_result;
494 if (job->xfered_length < job->length ||
495 (job->xfered_length == job->length &&
496 job->xfered_length % mps == 0 && job->xfer_length)) {
497 continue_ep_transfer(p, endpoint, in_dir);
498 return;
499 }
500 } else {
501 job->xfered_length += job->xfer_length - xfer_result;
502 }
503 SIMPLEQ_REMOVE_HEAD(&p->eps[endpoint][in_dir].job_queue, queue);
504
505 usb_debug("%d-%d: scheduled %zd, now %zd bytes\n", endpoint, in_dir,
506 job->length, job->xfered_length);
507
508 if (this->current_config &&
509 this->current_config->interfaces[0].handle_packet)
510 this->current_config->interfaces[0].handle_packet(this,
511 endpoint, in_dir, job->data, job->xfered_length);
512
513 if (job->autofree)
514 free(job->data);
515 free(job);
516
517 p->eps[endpoint][in_dir].busy = 0;
518
519 if (endpoint == 0 && job->xfered_length == 0)
520 dwc2_enqueue_packet(this, 0, 0, p->setup_buf, 8, 0, 0);
521 else
522 start_ep_transfer(p, endpoint, in_dir);
523 }
524
dwc2_outep_intr(struct usbdev_ctrl * this,dwc2_ep_t * ep)525 static void dwc2_outep_intr(struct usbdev_ctrl *this, dwc2_ep_t *ep)
526 {
527 dwc2_pdata_t *p = DWC2_PDATA(this);
528 depint_t depint;
529 depsiz_t depsiz;
530
531 depint.d32 = readl(&ep->ep_regs->depint) &
532 readl(&p->regs->device.doepmsk);
533
534 /* Don't process XferCompl interrupt if it is a setup packet */
535 if ((ep->ep_num == 0) && (depint.setup || depint.stuppktrcvd))
536 depint.xfercompl = 0;
537
538 /* Transfer completed */
539 if (depint.xfercompl) {
540 usb_debug("DOEPINT_XFERCOMPL\n");
541 writel(DXEPINT_XFERCOMPL, &ep->ep_regs->depint);
542 depsiz.d32 = readl(&ep->ep_regs->deptsiz);
543
544 if (ep->ep_num == 0)
545 depsiz.xfersize &= 0x7f;
546
547 complete_ep_transfer(this, ep->ep_num, 0, depsiz.xfersize);
548 }
549 /* Endpoint disable */
550 if (depint.epdisbld) {
551 usb_debug("DEPINT_EPDISBLD\n");
552 writel(DXEPINT_EPDISBLD, &ep->ep_regs->depint);
553 }
554 /* AHB Error */
555 if (depint.ahberr) {
556 usb_debug("DEPINT_AHBERR\n");
557 writel(DXEPINT_AHBERR, &ep->ep_regs->depint);
558 }
559
560 /* Handle Setup Phase Done (Control Ep) */
561 if (depint.setup) {
562 usb_debug("DEPINT_SETUP\n");
563 writel(DXEPINT_SETUP, &ep->ep_regs->depint);
564 #ifdef USB_DEBUG
565 hexdump(p->setup_buf, sizeof(dev_req_t));
566 #endif
567 SIMPLEQ_REMOVE_HEAD(&p->eps[0][0].job_queue, queue);
568 p->eps[0][0].busy = 0;
569
570 udc_handle_setup(this, ep->ep_num, (dev_req_t *)p->setup_buf);
571 }
572 }
573
dwc2_inep_intr(struct usbdev_ctrl * this,dwc2_ep_t * ep)574 static void dwc2_inep_intr(struct usbdev_ctrl *this, dwc2_ep_t *ep)
575 {
576 dwc2_pdata_t *p = DWC2_PDATA(this);
577 depint_t depint;
578 depsiz_t depsiz;
579
580 depint.d32 = readl(&ep->ep_regs->depint) &
581 readl(&p->regs->device.doepmsk);
582
583 /* Don't process XferCompl interrupt if it is a setup packet */
584 if ((ep->ep_num == 0) && (depint.setup)) {
585 usb_debug("IN ep timeout\n");
586 writel(DXEPINT_TIMEOUT, &ep->ep_regs->depint);
587 }
588
589 /* Transfer completed */
590 if (depint.xfercompl) {
591 usb_debug("DIEPINT_XFERCOMPL\n");
592 writel(DXEPINT_XFERCOMPL, &ep->ep_regs->depint);
593 depsiz.d32 = readl(&ep->ep_regs->deptsiz);
594
595 if (ep->ep_num == 0)
596 depsiz.xfersize &= 0x7f;
597
598 complete_ep_transfer(this, ep->ep_num, 1, depsiz.xfersize);
599 }
600 /* Endpoint disable */
601 if (depint.epdisbld) {
602 usb_debug("DEPINT_EPDISBLD\n");
603 writel(DXEPINT_EPDISBLD, &ep->ep_regs->depint);
604 }
605 /* AHB Error */
606 if (depint.ahberr) {
607 usb_debug("DEPINT_AHBERR\n");
608 writel(DXEPINT_AHBERR, &ep->ep_regs->depint);
609 }
610 }
611
dwc2_check_irq(struct usbdev_ctrl * this)612 static int dwc2_check_irq(struct usbdev_ctrl *this)
613 {
614 dwc2_pdata_t *p = DWC2_PDATA(this);
615 gintsts_t gintsts;
616 uint32_t daint, daint_out, daint_in, ep;
617
618 gintsts.d32 = readl(&p->regs->core.gintsts) &
619 readl(&p->regs->core.gintmsk);
620
621 if (gintsts.d32 == 0)
622 return 1;
623
624 /* EP INTR */
625 if (gintsts.oepint || gintsts.iepint) {
626
627 daint = readl(&p->regs->device.daint) &
628 readl(&p->regs->device.daintmsk);
629
630 daint_out = daint >> DAINT_OUTEP_SHIFT;
631 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
632
633 for (ep = 0; ep < MAX_EPS_CHANNELS; ep++, daint_in >>= 1) {
634 if (daint_in & 1)
635 dwc2_inep_intr(this, &p->eps[ep][1]);
636 }
637
638 for (ep = 0; ep < MAX_EPS_CHANNELS; ep++, daint_out >>= 1) {
639 if (daint_out & 1)
640 dwc2_outep_intr(this, &p->eps[ep][0]);
641 }
642 }
643
644 /* USB Bus Suspend */
645 if (gintsts.usbsusp) {
646 usb_debug("GINTSTS_ERLYSUSP\n");
647 writel(GINTSTS_USBSUSP, &p->regs->core.gintsts);
648 }
649 /* USB Bus Reset */
650 if (gintsts.usbrst) {
651 usb_debug("GINTSTS_USBRST\n");
652 dwc2_bus_reset(this);
653 writel(GINTSTS_USBRST, &p->regs->core.gintsts);
654 }
655 /* Enumeration done */
656 if (gintsts.enumdone) {
657 usb_debug("GINTSTS_ENUMDONE\n");
658 dwc2_enum_done(this);
659 writel(GINTSTS_ENUMDONE, &p->regs->core.gintsts);
660 }
661 if (gintsts.sessreqint) {
662 usb_debug("GINTSTS_SESSREQINT\n");
663 writel(GINTSTS_SESSREQINT, &p->regs->core.gintsts);
664 }
665 if (gintsts.wkupint) {
666 usb_debug("GINTSTS_WKUPINT\n");
667 writel(GINTSTS_WKUPINT, &p->regs->core.gintsts);
668 }
669
670 return 1;
671 }
672
dwc2_force_shutdown(struct usbdev_ctrl * this)673 static void dwc2_force_shutdown(struct usbdev_ctrl *this)
674 {
675 gusbcfg_t gusbcfg;
676 dwc2_pdata_t *p = DWC2_PDATA(this);
677
678 /* Disconnect */
679 dwc2_connect(this, 0);
680
681 /* Back to normal otg mode */
682 gusbcfg.d32 = readl(&p->regs->core.gusbcfg);
683 gusbcfg.forcehstmode = 0;
684 gusbcfg.forcedevmode = 0;
685 writel(gusbcfg.d32, &p->regs->core.gusbcfg);
686
687 free(p);
688 free(this);
689 }
690
dwc2_shutdown(struct usbdev_ctrl * this)691 static void dwc2_shutdown(struct usbdev_ctrl *this)
692 {
693 dwc2_pdata_t *p = DWC2_PDATA(this);
694 int i, j;
695 int is_empty = 0;
696
697 uint64_t shutdown_timer_us = timer_us(0);
698 /* Wait up to 3 seconds for packets to be flushed out. */
699 uint64_t shutdown_timeout_us = 3 * 1000 * 1000UL;
700
701 while ((!is_empty) &&
702 (timer_us(shutdown_timer_us) < shutdown_timeout_us)) {
703 is_empty = 1;
704 this->poll(this);
705 for (i = 0; i < 16; i++)
706 for (j = 0; j < 2; j++) {
707 /*
708 * EP0-OUT needs to always have an active packet
709 * for proper operation of control packet
710 * flow. Thus, ignore if only 1 packet is
711 * present in EP0-OUT.
712 */
713 if ((i == 0) && (j == 0) &&
714 SIMPLEQ_SINGLETON(&p->eps[0][0].job_queue,
715 queue))
716 continue;
717
718 if (!SIMPLEQ_EMPTY(&p->eps[i][j].job_queue))
719 is_empty = 0;
720 }
721 }
722
723 if (timer_us(shutdown_timer_us) >= shutdown_timeout_us)
724 usb_debug("Error: Failed to empty queues.. timeout\n");
725
726 dwc2_force_shutdown(this);
727 }
728
dwc2_set_address(struct usbdev_ctrl * this,int address)729 static void dwc2_set_address(struct usbdev_ctrl *this, int address)
730 {
731 dwc2_pdata_t *p = DWC2_PDATA(this);
732 dcfg_t dcfg;
733
734 dcfg.d32 = readl(&p->regs->device.dcfg);
735 dcfg.devaddr = address;
736 writel(dcfg.d32, &p->regs->device.dcfg);
737 }
738
dwc2_stall(struct usbdev_ctrl * this,uint8_t ep,int in_dir,int set)739 static void dwc2_stall(struct usbdev_ctrl *this,
740 uint8_t ep, int in_dir, int set)
741 {
742 dwc2_pdata_t *p = DWC2_PDATA(this);
743 dwc2_ep_reg_t *ep_reg = p->eps[ep][in_dir].ep_regs;
744 depctl_t depctl;
745
746 usb_debug("dwc2_stall\n");
747 depctl.d32 = readl(&ep_reg->depctl);
748
749 in_dir = in_dir ? 1 : 0;
750
751 if (set) {
752 depctl.stall = 1;
753 depctl.setd0pid = 1;
754 writel(depctl.d32, &ep_reg->depctl);
755 } else {
756 /* STALL bit will be clear by core */
757 }
758 this->ep_halted[ep][in_dir] = set;
759 }
760
dwc2_malloc(size_t size)761 static void *dwc2_malloc(size_t size)
762 {
763 return dma_memalign(4096, size);
764 }
765
dwc2_free(void * ptr)766 static void dwc2_free(void *ptr)
767 {
768 free(ptr);
769 }
770
dwc2_reinit_udc(struct usbdev_ctrl * this,void * _opreg,const device_descriptor_t * dd)771 static int dwc2_reinit_udc(struct usbdev_ctrl *this, void *_opreg,
772 const device_descriptor_t *dd)
773 {
774 grstctl_t grstctl = { .d32 = 0 };
775 gintmsk_t gintmsk = { .d32 = 0 };
776 gahbcfg_t gahbcfg = { .d32 = 0 };
777 gusbcfg_t gusbcfg = { .d32 = 0 };
778 grxfsiz_t grxfsiz = { .d32 = 0 };
779 dtxfsiz_t dtxfsiz0 = { .d32 = 0 };
780 dtxfsiz_t dtxfsiz1 = { .d32 = 0 };
781 dtxfsiz_t dtxfsiz2 = { .d32 = 0 };
782 depint_t depint_msk = { .d32 = 0 };
783 dcfg_t dcfg = { .d32 = 0 };
784 dwc2_reg_t *regs = (dwc2_reg_t *)_opreg;
785 dwc2_pdata_t *p = DWC2_PDATA(this);
786 const int timeout = 10000;
787 int i;
788
789 p->regs = phys_to_virt(regs);
790 p->fifo_map = 0;
791 p->setup_buf = dma_memalign(4, 64);
792
793 for (i = 0; i < MAX_EPS_CHANNELS; i++) {
794 /* Init OUT EPs */
795 p->eps[i][0].ep_num = i;
796 p->eps[i][0].ep_regs = ®s->device.outep[i];
797 SIMPLEQ_INIT(&p->eps[i][0].job_queue);
798
799 /* Init IN EPs */
800 p->eps[i][1].ep_num = i;
801 p->eps[i][1].ep_regs = ®s->device.inep[i];
802 SIMPLEQ_INIT(&p->eps[i][1].job_queue);
803 }
804
805 usb_debug("dwc2_hw_init\n");
806
807 /* Wait for AHB idle */
808 for (i = 0; i < timeout; i++) {
809 udelay(1);
810 grstctl.d32 = readl(®s->core.grstctl);
811 if (grstctl.ahbidle)
812 break;
813 }
814 if (i == timeout) {
815 usb_debug("DWC2 Init error AHB Idle\n");
816 return 0;
817 }
818
819 /* Restart the Phy Clock */
820 /* Core soft reset */
821 grstctl.csftrst = 1;
822 writel(grstctl.d32, ®s->core.grstctl);
823 for (i = 0; i <= timeout; i++) {
824 udelay(1);
825 grstctl.d32 = readl(®s->core.grstctl);
826 if (!grstctl.csftrst)
827 break;
828
829 if (i == timeout) {
830 usb_debug("DWC2 Init error reset fail\n");
831 return 0;
832 }
833 }
834
835 /* Restart the Phy Clock */
836 writel(0x0, ®s->pcgr.pcgcctl);
837
838 /* Set 16bit PHY if & Force host mode */
839 gusbcfg.d32 = readl(®s->core.gusbcfg);
840 gusbcfg.phyif = 1;
841 gusbcfg.forcehstmode = 0;
842 gusbcfg.forcedevmode = 1;
843 writel(gusbcfg.d32, ®s->core.gusbcfg);
844
845 dcfg.d32 = readl(®s->device.dcfg);
846 /* reset device addr */
847 dcfg.devaddr = 0;
848 /* enable HS */
849 dcfg.devspd = 0;
850 writel(dcfg.d32, ®s->device.dcfg);
851
852 dwc2_tx_fifo_flush(this, 0x10);
853 dwc2_rx_fifo_flush(this, 0);
854
855 grxfsiz.rxfdep = RX_FIFO_SIZE;
856 writel(grxfsiz.d32, ®s->core.grxfsiz);
857
858 dtxfsiz0.dtxfdep = DTX_FIFO_SIZE_0;
859 dtxfsiz0.dtxfstaddr = DTX_FIFO_SIZE_0_OFFSET;
860 writel(dtxfsiz0.d32, ®s->core.gnptxfsiz);
861
862 dtxfsiz1.dtxfdep = DTX_FIFO_SIZE_1;
863 dtxfsiz1.dtxfstaddr = DTX_FIFO_SIZE_1_OFFSET;
864 writel(dtxfsiz1.d32, ®s->core.dptxfsiz_dieptxf[0]);
865
866 dtxfsiz2.dtxfdep = DTX_FIFO_SIZE_2;
867 dtxfsiz2.dtxfstaddr = DTX_FIFO_SIZE_2_OFFSET;
868 writel(dtxfsiz2.d32, ®s->core.dptxfsiz_dieptxf[1]);
869
870 /* Config Ep0 */
871 dwc2_start_ep0(this);
872
873 dwc2_enqueue_packet(this, 0, 0, p->setup_buf, 8, 0, 0);
874
875 depint_msk.xfercompl = 1;
876 depint_msk.epdisbld = 1;
877 depint_msk.ahberr = 1;
878 depint_msk.setup = 1;
879
880 /* device IN interrupt mask */
881 writel(depint_msk.d32, ®s->device.diepmsk);
882 /* device OUT interrupt mask */
883 writel(depint_msk.d32, ®s->device.doepmsk);
884
885 /* Clear all pending interrupt */
886 writel(0xffffffff, ®s->device.daint);
887
888 /* Config core interface regs */
889 writel(0xffffffff, ®s->core.gintsts);
890 writel(0xffffffff, ®s->core.gotgint);
891
892 /* Enable device endpoint interrupt */
893 writel(0xffffffff, ®s->device.daintmsk);
894
895 gintmsk.usbsusp = 1;
896 gintmsk.usbrst = 1;
897 gintmsk.enumdone = 1;
898 gintmsk.sessreqint = 1;
899 gintmsk.iepint = 1;
900 gintmsk.oepint = 1;
901 writel(gintmsk.d32, ®s->core.gintmsk);
902
903 gahbcfg.d32 = readl(®s->core.gahbcfg);
904 gahbcfg.dmaen = 1;
905 gahbcfg.glblintrmsk = 1;
906 gahbcfg.hbstlen = DMA_BURST_INCR16;
907 writel(gahbcfg.d32, ®s->core.gahbcfg);
908
909 dwc2_connect(this, 1);
910
911 return 1;
912
913 }
914
dwc2_udc_init(device_descriptor_t * dd)915 struct usbdev_ctrl *dwc2_udc_init(device_descriptor_t *dd)
916 {
917 struct usbdev_ctrl *ctrl = calloc(1, sizeof(*ctrl));
918 int i;
919
920 usb_debug("dwc2_udc_init\n");
921 if (ctrl == NULL)
922 return NULL;
923
924 ctrl->pdata = calloc(1, sizeof(dwc2_pdata_t));
925 if (ctrl->pdata == NULL) {
926 free(ctrl);
927 return NULL;
928 }
929 memcpy(&ctrl->device_descriptor, dd, sizeof(*dd));
930 SLIST_INIT(&ctrl->configs);
931
932 ctrl->poll = dwc2_check_irq;
933 ctrl->add_gadget = udc_add_gadget;
934 ctrl->add_strings = udc_add_strings;
935 ctrl->enqueue_packet = dwc2_enqueue_packet;
936 ctrl->force_shutdown = dwc2_force_shutdown;
937 ctrl->shutdown = dwc2_shutdown;
938 ctrl->set_address = dwc2_set_address;
939 ctrl->stall = dwc2_stall;
940 ctrl->halt_ep = dwc2_halt_ep;
941 ctrl->start_ep = dwc2_start_ep;
942 ctrl->alloc_data = dwc2_malloc;
943 ctrl->free_data = dwc2_free;
944 ctrl->initialized = 0;
945
946 ctrl->ep_mps[0][0] = 64;
947 ctrl->ep_mps[0][1] = 64;
948 for (i = 1; i < 16; i++) {
949 ctrl->ep_mps[i][0] = 512;
950 ctrl->ep_mps[i][1] = 512;
951 }
952
953 if (!dwc2_reinit_udc(ctrl, (void *)0xff580000, dd)) {
954 free(ctrl->pdata);
955 free(ctrl);
956 return NULL;
957 }
958
959 return ctrl;
960 }
961